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// High Level Design Compiler for Intel(R) FPGAs Version 24.2 (Release Build #99.1)
// 
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// SystemVerilog created from i_sfc_logic_s_c1_in_for_body_c_compmm_ms_c1_enter923_c_compmm_m0
// Created for function/kernel c_compMM_m
// SystemVerilog created on Wed Mar 26 11:59:07 2025


(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 113007; -name MESSAGE_DISABLE 10958" *)
module c_compMM_m_i_sfc_logic_s_c1_in_for_body_0000enter923_c_compmm_m0 (
    output wire [0:0] out_c1_exi2926_0_tpl,
    output wire [63:0] out_c1_exi2926_1_tpl,
    output wire [15:0] out_c1_exi2926_2_tpl,
    output wire [15:0] out_c1_exi2926_3_tpl,
    output wire [0:0] out_o_valid,
    output wire [0:0] out_unnamed_c_compMM_m4,
    input wire [0:0] in_c1_eni5_0_tpl,
    input wire [15:0] in_c1_eni5_1_tpl,
    input wire [15:0] in_c1_eni5_2_tpl,
    input wire [15:0] in_c1_eni5_3_tpl,
    input wire [15:0] in_c1_eni5_4_tpl,
    input wire [15:0] in_c1_eni5_5_tpl,
    input wire [15:0] in_c1_eni5_6_tpl,
    input wire [15:0] in_c1_eni5_7_tpl,
    input wire [15:0] in_c1_eni5_8_tpl,
    input wire [15:0] in_c1_eni5_9_tpl,
    input wire [15:0] in_c1_eni5_10_tpl,
    input wire [15:0] in_c1_eni5_11_tpl,
    input wire [15:0] in_c1_eni5_12_tpl,
    input wire [15:0] in_c1_eni5_13_tpl,
    input wire [15:0] in_c1_eni5_14_tpl,
    input wire [15:0] in_c1_eni5_15_tpl,
    input wire [15:0] in_c1_eni5_16_tpl,
    input wire [15:0] in_c1_eni5_17_tpl,
    input wire [15:0] in_c1_eni5_18_tpl,
    input wire [15:0] in_c1_eni5_19_tpl,
    input wire [15:0] in_c1_eni5_20_tpl,
    input wire [15:0] in_c1_eni5_21_tpl,
    input wire [15:0] in_c1_eni5_22_tpl,
    input wire [15:0] in_c1_eni5_23_tpl,
    input wire [15:0] in_c1_eni5_24_tpl,
    input wire [15:0] in_c1_eni5_25_tpl,
    input wire [15:0] in_c1_eni5_26_tpl,
    input wire [15:0] in_c1_eni5_27_tpl,
    input wire [15:0] in_c1_eni5_28_tpl,
    input wire [15:0] in_c1_eni5_29_tpl,
    input wire [15:0] in_c1_eni5_30_tpl,
    input wire [15:0] in_c1_eni5_31_tpl,
    input wire [15:0] in_c1_eni5_32_tpl,
    input wire [15:0] in_c1_eni5_33_tpl,
    input wire [15:0] in_c1_eni5_34_tpl,
    input wire [15:0] in_c1_eni5_35_tpl,
    input wire [15:0] in_c1_eni5_36_tpl,
    input wire [15:0] in_c1_eni5_37_tpl,
    input wire [15:0] in_c1_eni5_38_tpl,
    input wire [15:0] in_c1_eni5_39_tpl,
    input wire [15:0] in_c1_eni5_40_tpl,
    input wire [15:0] in_c1_eni5_41_tpl,
    input wire [15:0] in_c1_eni5_42_tpl,
    input wire [15:0] in_c1_eni5_43_tpl,
    input wire [15:0] in_c1_eni5_44_tpl,
    input wire [15:0] in_c1_eni5_45_tpl,
    input wire [15:0] in_c1_eni5_46_tpl,
    input wire [15:0] in_c1_eni5_47_tpl,
    input wire [15:0] in_c1_eni5_48_tpl,
    input wire [15:0] in_c1_eni5_49_tpl,
    input wire [15:0] in_c1_eni5_50_tpl,
    input wire [15:0] in_c1_eni5_51_tpl,
    input wire [15:0] in_c1_eni5_52_tpl,
    input wire [15:0] in_c1_eni5_53_tpl,
    input wire [15:0] in_c1_eni5_54_tpl,
    input wire [15:0] in_c1_eni5_55_tpl,
    input wire [15:0] in_c1_eni5_56_tpl,
    input wire [15:0] in_c1_eni5_57_tpl,
    input wire [15:0] in_c1_eni5_58_tpl,
    input wire [15:0] in_c1_eni5_59_tpl,
    input wire [15:0] in_c1_eni5_60_tpl,
    input wire [15:0] in_c1_eni5_61_tpl,
    input wire [15:0] in_c1_eni5_62_tpl,
    input wire [15:0] in_c1_eni5_63_tpl,
    input wire [15:0] in_c1_eni5_64_tpl,
    input wire [15:0] in_c1_eni5_65_tpl,
    input wire [15:0] in_c1_eni5_66_tpl,
    input wire [15:0] in_c1_eni5_67_tpl,
    input wire [15:0] in_c1_eni5_68_tpl,
    input wire [15:0] in_c1_eni5_69_tpl,
    input wire [15:0] in_c1_eni5_70_tpl,
    input wire [15:0] in_c1_eni5_71_tpl,
    input wire [15:0] in_c1_eni5_72_tpl,
    input wire [15:0] in_c1_eni5_73_tpl,
    input wire [15:0] in_c1_eni5_74_tpl,
    input wire [15:0] in_c1_eni5_75_tpl,
    input wire [15:0] in_c1_eni5_76_tpl,
    input wire [15:0] in_c1_eni5_77_tpl,
    input wire [15:0] in_c1_eni5_78_tpl,
    input wire [15:0] in_c1_eni5_79_tpl,
    input wire [15:0] in_c1_eni5_80_tpl,
    input wire [15:0] in_c1_eni5_81_tpl,
    input wire [15:0] in_c1_eni5_82_tpl,
    input wire [15:0] in_c1_eni5_83_tpl,
    input wire [15:0] in_c1_eni5_84_tpl,
    input wire [15:0] in_c1_eni5_85_tpl,
    input wire [15:0] in_c1_eni5_86_tpl,
    input wire [15:0] in_c1_eni5_87_tpl,
    input wire [15:0] in_c1_eni5_88_tpl,
    input wire [15:0] in_c1_eni5_89_tpl,
    input wire [15:0] in_c1_eni5_90_tpl,
    input wire [15:0] in_c1_eni5_91_tpl,
    input wire [15:0] in_c1_eni5_92_tpl,
    input wire [15:0] in_c1_eni5_93_tpl,
    input wire [15:0] in_c1_eni5_94_tpl,
    input wire [15:0] in_c1_eni5_95_tpl,
    input wire [15:0] in_c1_eni5_96_tpl,
    input wire [15:0] in_c1_eni5_97_tpl,
    input wire [15:0] in_c1_eni5_98_tpl,
    input wire [15:0] in_c1_eni5_99_tpl,
    input wire [15:0] in_c1_eni5_100_tpl,
    input wire [15:0] in_c1_eni5_101_tpl,
    input wire [15:0] in_c1_eni5_102_tpl,
    input wire [15:0] in_c1_eni5_103_tpl,
    input wire [15:0] in_c1_eni5_104_tpl,
    input wire [15:0] in_c1_eni5_105_tpl,
    input wire [15:0] in_c1_eni5_106_tpl,
    input wire [15:0] in_c1_eni5_107_tpl,
    input wire [15:0] in_c1_eni5_108_tpl,
    input wire [15:0] in_c1_eni5_109_tpl,
    input wire [15:0] in_c1_eni5_110_tpl,
    input wire [15:0] in_c1_eni5_111_tpl,
    input wire [15:0] in_c1_eni5_112_tpl,
    input wire [15:0] in_c1_eni5_113_tpl,
    input wire [15:0] in_c1_eni5_114_tpl,
    input wire [15:0] in_c1_eni5_115_tpl,
    input wire [15:0] in_c1_eni5_116_tpl,
    input wire [15:0] in_c1_eni5_117_tpl,
    input wire [15:0] in_c1_eni5_118_tpl,
    input wire [15:0] in_c1_eni5_119_tpl,
    input wire [15:0] in_c1_eni5_120_tpl,
    input wire [15:0] in_c1_eni5_121_tpl,
    input wire [15:0] in_c1_eni5_122_tpl,
    input wire [15:0] in_c1_eni5_123_tpl,
    input wire [15:0] in_c1_eni5_124_tpl,
    input wire [15:0] in_c1_eni5_125_tpl,
    input wire [15:0] in_c1_eni5_126_tpl,
    input wire [15:0] in_c1_eni5_127_tpl,
    input wire [15:0] in_c1_eni5_128_tpl,
    input wire [15:0] in_c1_eni5_129_tpl,
    input wire [15:0] in_c1_eni5_130_tpl,
    input wire [15:0] in_c1_eni5_131_tpl,
    input wire [15:0] in_c1_eni5_132_tpl,
    input wire [15:0] in_c1_eni5_133_tpl,
    input wire [15:0] in_c1_eni5_134_tpl,
    input wire [15:0] in_c1_eni5_135_tpl,
    input wire [15:0] in_c1_eni5_136_tpl,
    input wire [15:0] in_c1_eni5_137_tpl,
    input wire [15:0] in_c1_eni5_138_tpl,
    input wire [15:0] in_c1_eni5_139_tpl,
    input wire [15:0] in_c1_eni5_140_tpl,
    input wire [15:0] in_c1_eni5_141_tpl,
    input wire [15:0] in_c1_eni5_142_tpl,
    input wire [15:0] in_c1_eni5_143_tpl,
    input wire [15:0] in_c1_eni5_144_tpl,
    input wire [15:0] in_c1_eni5_145_tpl,
    input wire [15:0] in_c1_eni5_146_tpl,
    input wire [15:0] in_c1_eni5_147_tpl,
    input wire [15:0] in_c1_eni5_148_tpl,
    input wire [15:0] in_c1_eni5_149_tpl,
    input wire [15:0] in_c1_eni5_150_tpl,
    input wire [15:0] in_c1_eni5_151_tpl,
    input wire [15:0] in_c1_eni5_152_tpl,
    input wire [15:0] in_c1_eni5_153_tpl,
    input wire [15:0] in_c1_eni5_154_tpl,
    input wire [15:0] in_c1_eni5_155_tpl,
    input wire [15:0] in_c1_eni5_156_tpl,
    input wire [15:0] in_c1_eni5_157_tpl,
    input wire [15:0] in_c1_eni5_158_tpl,
    input wire [15:0] in_c1_eni5_159_tpl,
    input wire [15:0] in_c1_eni5_160_tpl,
    input wire [15:0] in_c1_eni5_161_tpl,
    input wire [15:0] in_c1_eni5_162_tpl,
    input wire [15:0] in_c1_eni5_163_tpl,
    input wire [15:0] in_c1_eni5_164_tpl,
    input wire [15:0] in_c1_eni5_165_tpl,
    input wire [15:0] in_c1_eni5_166_tpl,
    input wire [15:0] in_c1_eni5_167_tpl,
    input wire [15:0] in_c1_eni5_168_tpl,
    input wire [15:0] in_c1_eni5_169_tpl,
    input wire [15:0] in_c1_eni5_170_tpl,
    input wire [15:0] in_c1_eni5_171_tpl,
    input wire [15:0] in_c1_eni5_172_tpl,
    input wire [15:0] in_c1_eni5_173_tpl,
    input wire [15:0] in_c1_eni5_174_tpl,
    input wire [15:0] in_c1_eni5_175_tpl,
    input wire [15:0] in_c1_eni5_176_tpl,
    input wire [15:0] in_c1_eni5_177_tpl,
    input wire [15:0] in_c1_eni5_178_tpl,
    input wire [15:0] in_c1_eni5_179_tpl,
    input wire [15:0] in_c1_eni5_180_tpl,
    input wire [15:0] in_c1_eni5_181_tpl,
    input wire [15:0] in_c1_eni5_182_tpl,
    input wire [15:0] in_c1_eni5_183_tpl,
    input wire [15:0] in_c1_eni5_184_tpl,
    input wire [15:0] in_c1_eni5_185_tpl,
    input wire [15:0] in_c1_eni5_186_tpl,
    input wire [15:0] in_c1_eni5_187_tpl,
    input wire [15:0] in_c1_eni5_188_tpl,
    input wire [15:0] in_c1_eni5_189_tpl,
    input wire [15:0] in_c1_eni5_190_tpl,
    input wire [15:0] in_c1_eni5_191_tpl,
    input wire [15:0] in_c1_eni5_192_tpl,
    input wire [15:0] in_c1_eni5_193_tpl,
    input wire [15:0] in_c1_eni5_194_tpl,
    input wire [15:0] in_c1_eni5_195_tpl,
    input wire [15:0] in_c1_eni5_196_tpl,
    input wire [15:0] in_c1_eni5_197_tpl,
    input wire [15:0] in_c1_eni5_198_tpl,
    input wire [15:0] in_c1_eni5_199_tpl,
    input wire [15:0] in_c1_eni5_200_tpl,
    input wire [15:0] in_c1_eni5_201_tpl,
    input wire [15:0] in_c1_eni5_202_tpl,
    input wire [15:0] in_c1_eni5_203_tpl,
    input wire [15:0] in_c1_eni5_204_tpl,
    input wire [15:0] in_c1_eni5_205_tpl,
    input wire [15:0] in_c1_eni5_206_tpl,
    input wire [15:0] in_c1_eni5_207_tpl,
    input wire [15:0] in_c1_eni5_208_tpl,
    input wire [15:0] in_c1_eni5_209_tpl,
    input wire [15:0] in_c1_eni5_210_tpl,
    input wire [15:0] in_c1_eni5_211_tpl,
    input wire [15:0] in_c1_eni5_212_tpl,
    input wire [15:0] in_c1_eni5_213_tpl,
    input wire [15:0] in_c1_eni5_214_tpl,
    input wire [15:0] in_c1_eni5_215_tpl,
    input wire [15:0] in_c1_eni5_216_tpl,
    input wire [15:0] in_c1_eni5_217_tpl,
    input wire [15:0] in_c1_eni5_218_tpl,
    input wire [15:0] in_c1_eni5_219_tpl,
    input wire [15:0] in_c1_eni5_220_tpl,
    input wire [15:0] in_c1_eni5_221_tpl,
    input wire [15:0] in_c1_eni5_222_tpl,
    input wire [15:0] in_c1_eni5_223_tpl,
    input wire [15:0] in_c1_eni5_224_tpl,
    input wire [15:0] in_c1_eni5_225_tpl,
    input wire [15:0] in_c1_eni5_226_tpl,
    input wire [15:0] in_c1_eni5_227_tpl,
    input wire [15:0] in_c1_eni5_228_tpl,
    input wire [15:0] in_c1_eni5_229_tpl,
    input wire [15:0] in_c1_eni5_230_tpl,
    input wire [15:0] in_c1_eni5_231_tpl,
    input wire [15:0] in_c1_eni5_232_tpl,
    input wire [15:0] in_c1_eni5_233_tpl,
    input wire [15:0] in_c1_eni5_234_tpl,
    input wire [15:0] in_c1_eni5_235_tpl,
    input wire [15:0] in_c1_eni5_236_tpl,
    input wire [15:0] in_c1_eni5_237_tpl,
    input wire [15:0] in_c1_eni5_238_tpl,
    input wire [15:0] in_c1_eni5_239_tpl,
    input wire [15:0] in_c1_eni5_240_tpl,
    input wire [15:0] in_c1_eni5_241_tpl,
    input wire [15:0] in_c1_eni5_242_tpl,
    input wire [15:0] in_c1_eni5_243_tpl,
    input wire [15:0] in_c1_eni5_244_tpl,
    input wire [15:0] in_c1_eni5_245_tpl,
    input wire [15:0] in_c1_eni5_246_tpl,
    input wire [15:0] in_c1_eni5_247_tpl,
    input wire [15:0] in_c1_eni5_248_tpl,
    input wire [15:0] in_c1_eni5_249_tpl,
    input wire [15:0] in_c1_eni5_250_tpl,
    input wire [15:0] in_c1_eni5_251_tpl,
    input wire [15:0] in_c1_eni5_252_tpl,
    input wire [15:0] in_c1_eni5_253_tpl,
    input wire [15:0] in_c1_eni5_254_tpl,
    input wire [15:0] in_c1_eni5_255_tpl,
    input wire [15:0] in_c1_eni5_256_tpl,
    input wire [63:0] in_c1_eni5_257_tpl,
    input wire [0:0] in_i_valid,
    input wire [15:0] in_intel_reserved_ffwd_100_0,
    input wire [15:0] in_intel_reserved_ffwd_101_0,
    input wire [15:0] in_intel_reserved_ffwd_102_0,
    input wire [15:0] in_intel_reserved_ffwd_103_0,
    input wire [15:0] in_intel_reserved_ffwd_104_0,
    input wire [15:0] in_intel_reserved_ffwd_105_0,
    input wire [15:0] in_intel_reserved_ffwd_106_0,
    input wire [15:0] in_intel_reserved_ffwd_107_0,
    input wire [15:0] in_intel_reserved_ffwd_108_0,
    input wire [15:0] in_intel_reserved_ffwd_109_0,
    input wire [15:0] in_intel_reserved_ffwd_10_0,
    input wire [15:0] in_intel_reserved_ffwd_110_0,
    input wire [15:0] in_intel_reserved_ffwd_111_0,
    input wire [15:0] in_intel_reserved_ffwd_112_0,
    input wire [15:0] in_intel_reserved_ffwd_113_0,
    input wire [15:0] in_intel_reserved_ffwd_114_0,
    input wire [15:0] in_intel_reserved_ffwd_115_0,
    input wire [15:0] in_intel_reserved_ffwd_116_0,
    input wire [15:0] in_intel_reserved_ffwd_117_0,
    input wire [15:0] in_intel_reserved_ffwd_118_0,
    input wire [15:0] in_intel_reserved_ffwd_119_0,
    input wire [15:0] in_intel_reserved_ffwd_11_0,
    input wire [15:0] in_intel_reserved_ffwd_120_0,
    input wire [15:0] in_intel_reserved_ffwd_121_0,
    input wire [15:0] in_intel_reserved_ffwd_122_0,
    input wire [15:0] in_intel_reserved_ffwd_123_0,
    input wire [15:0] in_intel_reserved_ffwd_124_0,
    input wire [15:0] in_intel_reserved_ffwd_125_0,
    input wire [15:0] in_intel_reserved_ffwd_126_0,
    input wire [15:0] in_intel_reserved_ffwd_127_0,
    input wire [15:0] in_intel_reserved_ffwd_128_0,
    input wire [15:0] in_intel_reserved_ffwd_129_0,
    input wire [15:0] in_intel_reserved_ffwd_12_0,
    input wire [15:0] in_intel_reserved_ffwd_130_0,
    input wire [15:0] in_intel_reserved_ffwd_131_0,
    input wire [15:0] in_intel_reserved_ffwd_132_0,
    input wire [15:0] in_intel_reserved_ffwd_133_0,
    input wire [15:0] in_intel_reserved_ffwd_134_0,
    input wire [15:0] in_intel_reserved_ffwd_135_0,
    input wire [15:0] in_intel_reserved_ffwd_136_0,
    input wire [15:0] in_intel_reserved_ffwd_137_0,
    input wire [15:0] in_intel_reserved_ffwd_138_0,
    input wire [15:0] in_intel_reserved_ffwd_139_0,
    input wire [15:0] in_intel_reserved_ffwd_13_0,
    input wire [15:0] in_intel_reserved_ffwd_140_0,
    input wire [15:0] in_intel_reserved_ffwd_141_0,
    input wire [15:0] in_intel_reserved_ffwd_142_0,
    input wire [15:0] in_intel_reserved_ffwd_143_0,
    input wire [15:0] in_intel_reserved_ffwd_144_0,
    input wire [15:0] in_intel_reserved_ffwd_145_0,
    input wire [15:0] in_intel_reserved_ffwd_146_0,
    input wire [15:0] in_intel_reserved_ffwd_147_0,
    input wire [15:0] in_intel_reserved_ffwd_148_0,
    input wire [15:0] in_intel_reserved_ffwd_149_0,
    input wire [15:0] in_intel_reserved_ffwd_14_0,
    input wire [15:0] in_intel_reserved_ffwd_150_0,
    input wire [15:0] in_intel_reserved_ffwd_151_0,
    input wire [15:0] in_intel_reserved_ffwd_152_0,
    input wire [15:0] in_intel_reserved_ffwd_153_0,
    input wire [15:0] in_intel_reserved_ffwd_154_0,
    input wire [15:0] in_intel_reserved_ffwd_155_0,
    input wire [15:0] in_intel_reserved_ffwd_156_0,
    input wire [15:0] in_intel_reserved_ffwd_157_0,
    input wire [15:0] in_intel_reserved_ffwd_158_0,
    input wire [15:0] in_intel_reserved_ffwd_159_0,
    input wire [15:0] in_intel_reserved_ffwd_15_0,
    input wire [15:0] in_intel_reserved_ffwd_160_0,
    input wire [15:0] in_intel_reserved_ffwd_161_0,
    input wire [15:0] in_intel_reserved_ffwd_162_0,
    input wire [15:0] in_intel_reserved_ffwd_163_0,
    input wire [15:0] in_intel_reserved_ffwd_164_0,
    input wire [15:0] in_intel_reserved_ffwd_165_0,
    input wire [15:0] in_intel_reserved_ffwd_166_0,
    input wire [15:0] in_intel_reserved_ffwd_167_0,
    input wire [15:0] in_intel_reserved_ffwd_168_0,
    input wire [15:0] in_intel_reserved_ffwd_169_0,
    input wire [15:0] in_intel_reserved_ffwd_16_0,
    input wire [15:0] in_intel_reserved_ffwd_170_0,
    input wire [15:0] in_intel_reserved_ffwd_171_0,
    input wire [15:0] in_intel_reserved_ffwd_172_0,
    input wire [15:0] in_intel_reserved_ffwd_173_0,
    input wire [15:0] in_intel_reserved_ffwd_174_0,
    input wire [15:0] in_intel_reserved_ffwd_175_0,
    input wire [15:0] in_intel_reserved_ffwd_176_0,
    input wire [15:0] in_intel_reserved_ffwd_177_0,
    input wire [15:0] in_intel_reserved_ffwd_178_0,
    input wire [15:0] in_intel_reserved_ffwd_179_0,
    input wire [15:0] in_intel_reserved_ffwd_17_0,
    input wire [15:0] in_intel_reserved_ffwd_180_0,
    input wire [15:0] in_intel_reserved_ffwd_181_0,
    input wire [15:0] in_intel_reserved_ffwd_182_0,
    input wire [15:0] in_intel_reserved_ffwd_183_0,
    input wire [15:0] in_intel_reserved_ffwd_184_0,
    input wire [15:0] in_intel_reserved_ffwd_185_0,
    input wire [15:0] in_intel_reserved_ffwd_186_0,
    input wire [15:0] in_intel_reserved_ffwd_187_0,
    input wire [15:0] in_intel_reserved_ffwd_188_0,
    input wire [15:0] in_intel_reserved_ffwd_189_0,
    input wire [15:0] in_intel_reserved_ffwd_18_0,
    input wire [15:0] in_intel_reserved_ffwd_190_0,
    input wire [15:0] in_intel_reserved_ffwd_191_0,
    input wire [15:0] in_intel_reserved_ffwd_192_0,
    input wire [15:0] in_intel_reserved_ffwd_193_0,
    input wire [15:0] in_intel_reserved_ffwd_194_0,
    input wire [15:0] in_intel_reserved_ffwd_195_0,
    input wire [15:0] in_intel_reserved_ffwd_196_0,
    input wire [15:0] in_intel_reserved_ffwd_197_0,
    input wire [15:0] in_intel_reserved_ffwd_198_0,
    input wire [15:0] in_intel_reserved_ffwd_199_0,
    input wire [15:0] in_intel_reserved_ffwd_19_0,
    input wire [15:0] in_intel_reserved_ffwd_1_0,
    input wire [15:0] in_intel_reserved_ffwd_200_0,
    input wire [15:0] in_intel_reserved_ffwd_201_0,
    input wire [15:0] in_intel_reserved_ffwd_202_0,
    input wire [15:0] in_intel_reserved_ffwd_203_0,
    input wire [15:0] in_intel_reserved_ffwd_204_0,
    input wire [15:0] in_intel_reserved_ffwd_205_0,
    input wire [15:0] in_intel_reserved_ffwd_206_0,
    input wire [15:0] in_intel_reserved_ffwd_207_0,
    input wire [15:0] in_intel_reserved_ffwd_208_0,
    input wire [15:0] in_intel_reserved_ffwd_209_0,
    input wire [15:0] in_intel_reserved_ffwd_20_0,
    input wire [15:0] in_intel_reserved_ffwd_210_0,
    input wire [15:0] in_intel_reserved_ffwd_211_0,
    input wire [15:0] in_intel_reserved_ffwd_212_0,
    input wire [15:0] in_intel_reserved_ffwd_213_0,
    input wire [15:0] in_intel_reserved_ffwd_214_0,
    input wire [15:0] in_intel_reserved_ffwd_215_0,
    input wire [15:0] in_intel_reserved_ffwd_216_0,
    input wire [15:0] in_intel_reserved_ffwd_217_0,
    input wire [15:0] in_intel_reserved_ffwd_218_0,
    input wire [15:0] in_intel_reserved_ffwd_219_0,
    input wire [15:0] in_intel_reserved_ffwd_21_0,
    input wire [15:0] in_intel_reserved_ffwd_220_0,
    input wire [15:0] in_intel_reserved_ffwd_221_0,
    input wire [15:0] in_intel_reserved_ffwd_222_0,
    input wire [15:0] in_intel_reserved_ffwd_223_0,
    input wire [15:0] in_intel_reserved_ffwd_224_0,
    input wire [15:0] in_intel_reserved_ffwd_225_0,
    input wire [15:0] in_intel_reserved_ffwd_226_0,
    input wire [15:0] in_intel_reserved_ffwd_227_0,
    input wire [15:0] in_intel_reserved_ffwd_228_0,
    input wire [15:0] in_intel_reserved_ffwd_229_0,
    input wire [15:0] in_intel_reserved_ffwd_22_0,
    input wire [15:0] in_intel_reserved_ffwd_230_0,
    input wire [15:0] in_intel_reserved_ffwd_231_0,
    input wire [15:0] in_intel_reserved_ffwd_232_0,
    input wire [15:0] in_intel_reserved_ffwd_233_0,
    input wire [15:0] in_intel_reserved_ffwd_234_0,
    input wire [15:0] in_intel_reserved_ffwd_235_0,
    input wire [15:0] in_intel_reserved_ffwd_236_0,
    input wire [15:0] in_intel_reserved_ffwd_237_0,
    input wire [15:0] in_intel_reserved_ffwd_238_0,
    input wire [15:0] in_intel_reserved_ffwd_239_0,
    input wire [15:0] in_intel_reserved_ffwd_23_0,
    input wire [15:0] in_intel_reserved_ffwd_240_0,
    input wire [15:0] in_intel_reserved_ffwd_241_0,
    input wire [15:0] in_intel_reserved_ffwd_242_0,
    input wire [15:0] in_intel_reserved_ffwd_243_0,
    input wire [15:0] in_intel_reserved_ffwd_244_0,
    input wire [15:0] in_intel_reserved_ffwd_245_0,
    input wire [15:0] in_intel_reserved_ffwd_246_0,
    input wire [15:0] in_intel_reserved_ffwd_247_0,
    input wire [15:0] in_intel_reserved_ffwd_248_0,
    input wire [15:0] in_intel_reserved_ffwd_249_0,
    input wire [15:0] in_intel_reserved_ffwd_24_0,
    input wire [15:0] in_intel_reserved_ffwd_250_0,
    input wire [15:0] in_intel_reserved_ffwd_251_0,
    input wire [15:0] in_intel_reserved_ffwd_252_0,
    input wire [15:0] in_intel_reserved_ffwd_253_0,
    input wire [15:0] in_intel_reserved_ffwd_254_0,
    input wire [15:0] in_intel_reserved_ffwd_255_0,
    input wire [15:0] in_intel_reserved_ffwd_256_0,
    input wire [15:0] in_intel_reserved_ffwd_25_0,
    input wire [15:0] in_intel_reserved_ffwd_26_0,
    input wire [15:0] in_intel_reserved_ffwd_27_0,
    input wire [15:0] in_intel_reserved_ffwd_28_0,
    input wire [15:0] in_intel_reserved_ffwd_29_0,
    input wire [15:0] in_intel_reserved_ffwd_2_0,
    input wire [15:0] in_intel_reserved_ffwd_30_0,
    input wire [15:0] in_intel_reserved_ffwd_31_0,
    input wire [15:0] in_intel_reserved_ffwd_32_0,
    input wire [15:0] in_intel_reserved_ffwd_33_0,
    input wire [15:0] in_intel_reserved_ffwd_34_0,
    input wire [15:0] in_intel_reserved_ffwd_35_0,
    input wire [15:0] in_intel_reserved_ffwd_36_0,
    input wire [15:0] in_intel_reserved_ffwd_37_0,
    input wire [15:0] in_intel_reserved_ffwd_38_0,
    input wire [15:0] in_intel_reserved_ffwd_39_0,
    input wire [15:0] in_intel_reserved_ffwd_3_0,
    input wire [15:0] in_intel_reserved_ffwd_40_0,
    input wire [15:0] in_intel_reserved_ffwd_41_0,
    input wire [15:0] in_intel_reserved_ffwd_42_0,
    input wire [15:0] in_intel_reserved_ffwd_43_0,
    input wire [15:0] in_intel_reserved_ffwd_44_0,
    input wire [15:0] in_intel_reserved_ffwd_45_0,
    input wire [15:0] in_intel_reserved_ffwd_46_0,
    input wire [15:0] in_intel_reserved_ffwd_47_0,
    input wire [15:0] in_intel_reserved_ffwd_48_0,
    input wire [15:0] in_intel_reserved_ffwd_49_0,
    input wire [15:0] in_intel_reserved_ffwd_4_0,
    input wire [15:0] in_intel_reserved_ffwd_50_0,
    input wire [15:0] in_intel_reserved_ffwd_51_0,
    input wire [15:0] in_intel_reserved_ffwd_52_0,
    input wire [15:0] in_intel_reserved_ffwd_53_0,
    input wire [15:0] in_intel_reserved_ffwd_54_0,
    input wire [15:0] in_intel_reserved_ffwd_55_0,
    input wire [15:0] in_intel_reserved_ffwd_56_0,
    input wire [15:0] in_intel_reserved_ffwd_57_0,
    input wire [15:0] in_intel_reserved_ffwd_58_0,
    input wire [15:0] in_intel_reserved_ffwd_59_0,
    input wire [15:0] in_intel_reserved_ffwd_5_0,
    input wire [15:0] in_intel_reserved_ffwd_60_0,
    input wire [15:0] in_intel_reserved_ffwd_61_0,
    input wire [15:0] in_intel_reserved_ffwd_62_0,
    input wire [15:0] in_intel_reserved_ffwd_63_0,
    input wire [15:0] in_intel_reserved_ffwd_64_0,
    input wire [15:0] in_intel_reserved_ffwd_65_0,
    input wire [15:0] in_intel_reserved_ffwd_66_0,
    input wire [15:0] in_intel_reserved_ffwd_67_0,
    input wire [15:0] in_intel_reserved_ffwd_68_0,
    input wire [15:0] in_intel_reserved_ffwd_69_0,
    input wire [15:0] in_intel_reserved_ffwd_6_0,
    input wire [15:0] in_intel_reserved_ffwd_70_0,
    input wire [15:0] in_intel_reserved_ffwd_71_0,
    input wire [15:0] in_intel_reserved_ffwd_72_0,
    input wire [15:0] in_intel_reserved_ffwd_73_0,
    input wire [15:0] in_intel_reserved_ffwd_74_0,
    input wire [15:0] in_intel_reserved_ffwd_75_0,
    input wire [15:0] in_intel_reserved_ffwd_76_0,
    input wire [15:0] in_intel_reserved_ffwd_77_0,
    input wire [15:0] in_intel_reserved_ffwd_78_0,
    input wire [15:0] in_intel_reserved_ffwd_79_0,
    input wire [15:0] in_intel_reserved_ffwd_7_0,
    input wire [15:0] in_intel_reserved_ffwd_80_0,
    input wire [15:0] in_intel_reserved_ffwd_81_0,
    input wire [15:0] in_intel_reserved_ffwd_82_0,
    input wire [15:0] in_intel_reserved_ffwd_83_0,
    input wire [15:0] in_intel_reserved_ffwd_84_0,
    input wire [15:0] in_intel_reserved_ffwd_85_0,
    input wire [15:0] in_intel_reserved_ffwd_86_0,
    input wire [15:0] in_intel_reserved_ffwd_87_0,
    input wire [15:0] in_intel_reserved_ffwd_88_0,
    input wire [15:0] in_intel_reserved_ffwd_89_0,
    input wire [15:0] in_intel_reserved_ffwd_8_0,
    input wire [15:0] in_intel_reserved_ffwd_90_0,
    input wire [15:0] in_intel_reserved_ffwd_91_0,
    input wire [15:0] in_intel_reserved_ffwd_92_0,
    input wire [15:0] in_intel_reserved_ffwd_93_0,
    input wire [15:0] in_intel_reserved_ffwd_94_0,
    input wire [15:0] in_intel_reserved_ffwd_95_0,
    input wire [15:0] in_intel_reserved_ffwd_96_0,
    input wire [15:0] in_intel_reserved_ffwd_97_0,
    input wire [15:0] in_intel_reserved_ffwd_98_0,
    input wire [15:0] in_intel_reserved_ffwd_99_0,
    input wire [15:0] in_intel_reserved_ffwd_9_0,
    input wire clock,
    input wire resetn
    );

    wire [0:0] GND_q;
    wire [0:0] VCC_q;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_100_c_compmm_m3069_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_101_c_compmm_m3097_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_102_c_compmm_m3125_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_103_c_compmm_m3153_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_104_c_compmm_m3181_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_105_c_compmm_m3209_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_106_c_compmm_m3237_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_107_c_compmm_m3265_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_108_c_compmm_m3293_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_109_c_compmm_m3321_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_10_c_compmm_m546_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_110_c_compmm_m3349_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_111_c_compmm_m3377_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_112_c_compmm_m3405_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_113_c_compmm_m3433_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_114_c_compmm_m3461_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_115_c_compmm_m3489_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_116_c_compmm_m3517_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_117_c_compmm_m3545_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_118_c_compmm_m3573_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_119_c_compmm_m3601_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_11_c_compmm_m574_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_120_c_compmm_m3629_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_121_c_compmm_m3657_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_122_c_compmm_m3685_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_123_c_compmm_m3713_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_124_c_compmm_m3741_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_125_c_compmm_m3769_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_126_c_compmm_m3797_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_127_c_compmm_m3825_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_12_c_compmm_m602_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_13_c_compmm_m630_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_14_c_compmm_m658_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_15_c_compmm_m686_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_16_c_compmm_m714_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_17_c_compmm_m742_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_18_c_compmm_m770_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_19_c_compmm_m798_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_1_c_compmm_m294_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_20_c_compmm_m826_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_21_c_compmm_m854_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_22_c_compmm_m882_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_23_c_compmm_m910_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_24_c_compmm_m938_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_25_c_compmm_m966_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_26_c_compmm_m994_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_27_c_compmm_m1022_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_28_c_compmm_m1050_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_29_c_compmm_m1078_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_2_c_compmm_m322_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_30_c_compmm_m1106_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_31_c_compmm_m1134_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_32_c_compmm_m1163_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_33_c_compmm_m1191_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_34_c_compmm_m1219_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_35_c_compmm_m1247_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_36_c_compmm_m1275_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_37_c_compmm_m1303_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_38_c_compmm_m1331_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_39_c_compmm_m1359_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_3_c_compmm_m350_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_40_c_compmm_m1387_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_41_c_compmm_m1415_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_42_c_compmm_m1443_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_43_c_compmm_m1471_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_44_c_compmm_m1499_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_45_c_compmm_m1527_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_46_c_compmm_m1555_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_47_c_compmm_m1583_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_48_c_compmm_m1611_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_49_c_compmm_m1639_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_4_c_compmm_m378_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_50_c_compmm_m1667_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_51_c_compmm_m1695_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_52_c_compmm_m1723_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_53_c_compmm_m1751_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_54_c_compmm_m1779_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_55_c_compmm_m1807_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_56_c_compmm_m1835_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_57_c_compmm_m1863_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_58_c_compmm_m1891_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_59_c_compmm_m1919_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_5_c_compmm_m406_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_60_c_compmm_m1947_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_61_c_compmm_m1975_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_62_c_compmm_m2003_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_63_c_compmm_m2031_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_64_c_compmm_m2060_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_65_c_compmm_m2088_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_66_c_compmm_m2116_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_67_c_compmm_m2144_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_68_c_compmm_m2172_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_69_c_compmm_m2200_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_6_c_compmm_m434_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_70_c_compmm_m2228_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_71_c_compmm_m2256_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_72_c_compmm_m2284_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_73_c_compmm_m2312_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_74_c_compmm_m2340_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_75_c_compmm_m2368_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_76_c_compmm_m2396_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_77_c_compmm_m2424_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_78_c_compmm_m2452_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_79_c_compmm_m2480_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_7_c_compmm_m462_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_80_c_compmm_m2508_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_81_c_compmm_m2536_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_82_c_compmm_m2564_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_83_c_compmm_m2592_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_84_c_compmm_m2620_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_85_c_compmm_m2648_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_86_c_compmm_m2676_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_87_c_compmm_m2704_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_88_c_compmm_m2732_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_89_c_compmm_m2760_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_8_c_compmm_m490_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_90_c_compmm_m2788_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_91_c_compmm_m2816_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_92_c_compmm_m2844_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_93_c_compmm_m2872_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_94_c_compmm_m2900_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_95_c_compmm_m2928_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_96_c_compmm_m2957_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_97_c_compmm_m2985_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_98_c_compmm_m3013_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_99_c_compmm_m3041_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_9_c_compmm_m518_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i126_i_c_compmm_m268_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_100_c_compmm_m3085_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_104_c_compmm_m3197_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_105_c_compmm_m3225_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_106_c_compmm_m3253_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_107_c_compmm_m3281_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_108_c_compmm_m3309_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_109_c_compmm_m3337_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_10_c_compmm_m562_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_110_c_compmm_m3365_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_111_c_compmm_m3393_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_112_c_compmm_m3421_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_113_c_compmm_m3449_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_114_c_compmm_m3477_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_115_c_compmm_m3505_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_116_c_compmm_m3533_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_117_c_compmm_m3561_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_118_c_compmm_m3589_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_119_c_compmm_m3617_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_11_c_compmm_m590_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_120_c_compmm_m3645_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_121_c_compmm_m3673_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_122_c_compmm_m3701_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_123_c_compmm_m3729_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_124_c_compmm_m3757_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_125_c_compmm_m3785_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_126_c_compmm_m3813_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_127_c_compmm_m3841_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_12_c_compmm_m618_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_13_c_compmm_m646_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_14_c_compmm_m674_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_15_c_compmm_m702_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_16_c_compmm_m730_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_17_c_compmm_m758_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_18_c_compmm_m786_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_19_c_compmm_m814_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_20_c_compmm_m842_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_21_c_compmm_m870_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_22_c_compmm_m898_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_23_c_compmm_m926_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_24_c_compmm_m954_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_25_c_compmm_m982_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_26_c_compmm_m1010_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_27_c_compmm_m1038_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_28_c_compmm_m1066_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_29_c_compmm_m1094_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_2_c_compmm_m338_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_30_c_compmm_m1122_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_31_c_compmm_m1150_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_32_c_compmm_m1179_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_33_c_compmm_m1207_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_34_c_compmm_m1235_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_35_c_compmm_m1263_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_36_c_compmm_m1291_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_37_c_compmm_m1319_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_38_c_compmm_m1347_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_39_c_compmm_m1375_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_3_c_compmm_m366_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_40_c_compmm_m1403_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_41_c_compmm_m1431_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_42_c_compmm_m1459_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_43_c_compmm_m1487_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_44_c_compmm_m1515_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_45_c_compmm_m1543_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_46_c_compmm_m1571_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_47_c_compmm_m1599_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_48_c_compmm_m1627_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_49_c_compmm_m1655_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_4_c_compmm_m394_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_50_c_compmm_m1683_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_51_c_compmm_m1711_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_52_c_compmm_m1739_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_53_c_compmm_m1767_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_54_c_compmm_m1795_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_55_c_compmm_m1823_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_56_c_compmm_m1851_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_57_c_compmm_m1879_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_58_c_compmm_m1907_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_59_c_compmm_m1935_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_5_c_compmm_m422_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_60_c_compmm_m1963_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_61_c_compmm_m1991_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_62_c_compmm_m2019_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_63_c_compmm_m2047_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_64_c_compmm_m2076_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_65_c_compmm_m2104_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_66_c_compmm_m2132_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_67_c_compmm_m2160_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_68_c_compmm_m2188_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_69_c_compmm_m2216_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_6_c_compmm_m450_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_70_c_compmm_m2244_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_71_c_compmm_m2272_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_72_c_compmm_m2300_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_73_c_compmm_m2328_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_74_c_compmm_m2356_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_75_c_compmm_m2384_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_76_c_compmm_m2412_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_77_c_compmm_m2440_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_78_c_compmm_m2468_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_79_c_compmm_m2496_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_7_c_compmm_m478_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_80_c_compmm_m2524_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_81_c_compmm_m2552_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_82_c_compmm_m2580_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_83_c_compmm_m2608_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_84_c_compmm_m2636_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_85_c_compmm_m2664_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_86_c_compmm_m2692_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_87_c_compmm_m2720_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_88_c_compmm_m2748_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_89_c_compmm_m2776_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_8_c_compmm_m506_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_90_c_compmm_m2804_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_91_c_compmm_m2832_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_92_c_compmm_m2860_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_93_c_compmm_m2888_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_94_c_compmm_m2916_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_95_c_compmm_m2944_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_96_c_compmm_m2973_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_97_c_compmm_m3001_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_99_c_compmm_m3057_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x_b;
    wire [15:0] bgTrunc_i_add_i_i_i_i_i_i_c_compmm_m282_sel_x_b;
    wire [33:0] i_conv_i_i_i84_i_c_compmm_m262_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x_b;
    wire [15:0] i_conv_i_i_i_i97_i_c_compmm_m264_sel_x_b;
    wire [33:0] i_conv_i_i_i_i_c_compmm_m276_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x_b;
    wire [15:0] i_conv_i_i_i_i_i_c_compmm_m278_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_10_c_compmm_m554_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_11_c_compmm_m582_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_12_c_compmm_m610_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_13_c_compmm_m638_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_14_c_compmm_m666_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_15_c_compmm_m694_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_16_c_compmm_m722_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_17_c_compmm_m750_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_18_c_compmm_m778_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_19_c_compmm_m806_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_1_c_compmm_m302_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_20_c_compmm_m834_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_21_c_compmm_m862_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_22_c_compmm_m890_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_23_c_compmm_m918_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_24_c_compmm_m946_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_25_c_compmm_m974_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_2_c_compmm_m330_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_3_c_compmm_m358_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_4_c_compmm_m386_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_5_c_compmm_m414_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_6_c_compmm_m442_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_7_c_compmm_m470_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_8_c_compmm_m498_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_sel_x_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_9_c_compmm_m526_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1008_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1020_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1036_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1048_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1064_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1076_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1092_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1104_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1120_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1132_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1148_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1161_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1177_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1189_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1205_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1217_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1233_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1245_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1261_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1273_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1289_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1301_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1317_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1329_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1345_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1357_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1373_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1385_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1401_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1413_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1429_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1441_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1457_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1469_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1485_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1497_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1513_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1525_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1541_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1553_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1569_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1581_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1597_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1609_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1625_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1637_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1653_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1665_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1681_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1693_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1709_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1721_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1737_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1749_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1765_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1777_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1793_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1805_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1821_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1833_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1849_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1861_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1877_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1889_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1905_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1917_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1933_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1945_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1961_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1973_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m1989_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2001_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2017_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2029_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2045_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2058_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2074_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2086_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2102_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2114_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2130_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2142_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2158_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2170_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2186_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2198_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2214_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2226_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2242_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2254_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2270_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2282_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2298_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2310_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2326_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2338_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2354_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2366_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2382_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2394_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2410_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2422_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2438_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2450_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2466_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2478_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2494_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2506_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2522_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2534_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2550_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2562_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2578_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2590_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2606_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2618_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2634_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2646_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m266_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2662_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2674_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2690_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2702_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2718_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2730_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2746_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2758_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2774_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2786_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m280_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2802_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2814_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2830_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2842_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2858_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2870_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2886_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2898_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2914_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m292_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2926_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2942_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2955_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2971_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2983_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m2999_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3011_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3027_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3039_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3055_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3067_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m308_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3083_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3095_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3111_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3123_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3139_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3151_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3167_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3179_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3195_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m320_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3207_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3223_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3235_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3251_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3263_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3279_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3291_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3307_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3319_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3335_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3347_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m336_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3363_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3375_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3391_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3403_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3419_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3431_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3447_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3459_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3475_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m348_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3487_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3503_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3515_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3531_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3543_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3559_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3571_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3587_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3599_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3615_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3627_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m364_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3643_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3655_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3671_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3683_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3699_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3711_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3727_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3739_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3755_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m376_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3767_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3783_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3795_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3811_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3823_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m3839_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m392_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m404_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m420_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m432_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m448_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m460_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m476_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m488_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m504_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m516_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m532_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m544_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m560_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m572_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m588_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m600_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m616_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m628_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m644_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m656_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m672_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m684_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m700_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m712_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m728_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m740_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m756_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m768_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m784_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m796_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m812_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m824_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m840_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m852_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m868_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m880_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m896_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m908_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m924_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m936_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m952_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m964_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m980_sel_x_b;
    wire [15:0] i_unnamed_c_compmm_m992_sel_x_b;
    wire [16:0] i_add_i_i_i_i_i126_i_100_c_compmm_m3069_a;
    wire [16:0] i_add_i_i_i_i_i126_i_100_c_compmm_m3069_b;
    logic [16:0] i_add_i_i_i_i_i126_i_100_c_compmm_m3069_o;
    wire [16:0] i_add_i_i_i_i_i126_i_100_c_compmm_m3069_q;
    wire [16:0] i_add_i_i_i_i_i126_i_101_c_compmm_m3097_a;
    wire [16:0] i_add_i_i_i_i_i126_i_101_c_compmm_m3097_b;
    logic [16:0] i_add_i_i_i_i_i126_i_101_c_compmm_m3097_o;
    wire [16:0] i_add_i_i_i_i_i126_i_101_c_compmm_m3097_q;
    wire [16:0] i_add_i_i_i_i_i126_i_102_c_compmm_m3125_a;
    wire [16:0] i_add_i_i_i_i_i126_i_102_c_compmm_m3125_b;
    logic [16:0] i_add_i_i_i_i_i126_i_102_c_compmm_m3125_o;
    wire [16:0] i_add_i_i_i_i_i126_i_102_c_compmm_m3125_q;
    wire [16:0] i_add_i_i_i_i_i126_i_103_c_compmm_m3153_a;
    wire [16:0] i_add_i_i_i_i_i126_i_103_c_compmm_m3153_b;
    logic [16:0] i_add_i_i_i_i_i126_i_103_c_compmm_m3153_o;
    wire [16:0] i_add_i_i_i_i_i126_i_103_c_compmm_m3153_q;
    wire [16:0] i_add_i_i_i_i_i126_i_104_c_compmm_m3181_a;
    wire [16:0] i_add_i_i_i_i_i126_i_104_c_compmm_m3181_b;
    logic [16:0] i_add_i_i_i_i_i126_i_104_c_compmm_m3181_o;
    wire [16:0] i_add_i_i_i_i_i126_i_104_c_compmm_m3181_q;
    wire [16:0] i_add_i_i_i_i_i126_i_105_c_compmm_m3209_a;
    wire [16:0] i_add_i_i_i_i_i126_i_105_c_compmm_m3209_b;
    logic [16:0] i_add_i_i_i_i_i126_i_105_c_compmm_m3209_o;
    wire [16:0] i_add_i_i_i_i_i126_i_105_c_compmm_m3209_q;
    wire [16:0] i_add_i_i_i_i_i126_i_106_c_compmm_m3237_a;
    wire [16:0] i_add_i_i_i_i_i126_i_106_c_compmm_m3237_b;
    logic [16:0] i_add_i_i_i_i_i126_i_106_c_compmm_m3237_o;
    wire [16:0] i_add_i_i_i_i_i126_i_106_c_compmm_m3237_q;
    wire [16:0] i_add_i_i_i_i_i126_i_107_c_compmm_m3265_a;
    wire [16:0] i_add_i_i_i_i_i126_i_107_c_compmm_m3265_b;
    logic [16:0] i_add_i_i_i_i_i126_i_107_c_compmm_m3265_o;
    wire [16:0] i_add_i_i_i_i_i126_i_107_c_compmm_m3265_q;
    wire [16:0] i_add_i_i_i_i_i126_i_108_c_compmm_m3293_a;
    wire [16:0] i_add_i_i_i_i_i126_i_108_c_compmm_m3293_b;
    logic [16:0] i_add_i_i_i_i_i126_i_108_c_compmm_m3293_o;
    wire [16:0] i_add_i_i_i_i_i126_i_108_c_compmm_m3293_q;
    wire [16:0] i_add_i_i_i_i_i126_i_109_c_compmm_m3321_a;
    wire [16:0] i_add_i_i_i_i_i126_i_109_c_compmm_m3321_b;
    logic [16:0] i_add_i_i_i_i_i126_i_109_c_compmm_m3321_o;
    wire [16:0] i_add_i_i_i_i_i126_i_109_c_compmm_m3321_q;
    wire [16:0] i_add_i_i_i_i_i126_i_10_c_compmm_m546_a;
    wire [16:0] i_add_i_i_i_i_i126_i_10_c_compmm_m546_b;
    logic [16:0] i_add_i_i_i_i_i126_i_10_c_compmm_m546_o;
    wire [16:0] i_add_i_i_i_i_i126_i_10_c_compmm_m546_q;
    wire [16:0] i_add_i_i_i_i_i126_i_110_c_compmm_m3349_a;
    wire [16:0] i_add_i_i_i_i_i126_i_110_c_compmm_m3349_b;
    logic [16:0] i_add_i_i_i_i_i126_i_110_c_compmm_m3349_o;
    wire [16:0] i_add_i_i_i_i_i126_i_110_c_compmm_m3349_q;
    wire [16:0] i_add_i_i_i_i_i126_i_111_c_compmm_m3377_a;
    wire [16:0] i_add_i_i_i_i_i126_i_111_c_compmm_m3377_b;
    logic [16:0] i_add_i_i_i_i_i126_i_111_c_compmm_m3377_o;
    wire [16:0] i_add_i_i_i_i_i126_i_111_c_compmm_m3377_q;
    wire [16:0] i_add_i_i_i_i_i126_i_112_c_compmm_m3405_a;
    wire [16:0] i_add_i_i_i_i_i126_i_112_c_compmm_m3405_b;
    logic [16:0] i_add_i_i_i_i_i126_i_112_c_compmm_m3405_o;
    wire [16:0] i_add_i_i_i_i_i126_i_112_c_compmm_m3405_q;
    wire [16:0] i_add_i_i_i_i_i126_i_113_c_compmm_m3433_a;
    wire [16:0] i_add_i_i_i_i_i126_i_113_c_compmm_m3433_b;
    logic [16:0] i_add_i_i_i_i_i126_i_113_c_compmm_m3433_o;
    wire [16:0] i_add_i_i_i_i_i126_i_113_c_compmm_m3433_q;
    wire [16:0] i_add_i_i_i_i_i126_i_114_c_compmm_m3461_a;
    wire [16:0] i_add_i_i_i_i_i126_i_114_c_compmm_m3461_b;
    logic [16:0] i_add_i_i_i_i_i126_i_114_c_compmm_m3461_o;
    wire [16:0] i_add_i_i_i_i_i126_i_114_c_compmm_m3461_q;
    wire [16:0] i_add_i_i_i_i_i126_i_115_c_compmm_m3489_a;
    wire [16:0] i_add_i_i_i_i_i126_i_115_c_compmm_m3489_b;
    logic [16:0] i_add_i_i_i_i_i126_i_115_c_compmm_m3489_o;
    wire [16:0] i_add_i_i_i_i_i126_i_115_c_compmm_m3489_q;
    wire [16:0] i_add_i_i_i_i_i126_i_116_c_compmm_m3517_a;
    wire [16:0] i_add_i_i_i_i_i126_i_116_c_compmm_m3517_b;
    logic [16:0] i_add_i_i_i_i_i126_i_116_c_compmm_m3517_o;
    wire [16:0] i_add_i_i_i_i_i126_i_116_c_compmm_m3517_q;
    wire [16:0] i_add_i_i_i_i_i126_i_117_c_compmm_m3545_a;
    wire [16:0] i_add_i_i_i_i_i126_i_117_c_compmm_m3545_b;
    logic [16:0] i_add_i_i_i_i_i126_i_117_c_compmm_m3545_o;
    wire [16:0] i_add_i_i_i_i_i126_i_117_c_compmm_m3545_q;
    wire [16:0] i_add_i_i_i_i_i126_i_118_c_compmm_m3573_a;
    wire [16:0] i_add_i_i_i_i_i126_i_118_c_compmm_m3573_b;
    logic [16:0] i_add_i_i_i_i_i126_i_118_c_compmm_m3573_o;
    wire [16:0] i_add_i_i_i_i_i126_i_118_c_compmm_m3573_q;
    wire [16:0] i_add_i_i_i_i_i126_i_119_c_compmm_m3601_a;
    wire [16:0] i_add_i_i_i_i_i126_i_119_c_compmm_m3601_b;
    logic [16:0] i_add_i_i_i_i_i126_i_119_c_compmm_m3601_o;
    wire [16:0] i_add_i_i_i_i_i126_i_119_c_compmm_m3601_q;
    wire [16:0] i_add_i_i_i_i_i126_i_11_c_compmm_m574_a;
    wire [16:0] i_add_i_i_i_i_i126_i_11_c_compmm_m574_b;
    logic [16:0] i_add_i_i_i_i_i126_i_11_c_compmm_m574_o;
    wire [16:0] i_add_i_i_i_i_i126_i_11_c_compmm_m574_q;
    wire [16:0] i_add_i_i_i_i_i126_i_120_c_compmm_m3629_a;
    wire [16:0] i_add_i_i_i_i_i126_i_120_c_compmm_m3629_b;
    logic [16:0] i_add_i_i_i_i_i126_i_120_c_compmm_m3629_o;
    wire [16:0] i_add_i_i_i_i_i126_i_120_c_compmm_m3629_q;
    wire [16:0] i_add_i_i_i_i_i126_i_121_c_compmm_m3657_a;
    wire [16:0] i_add_i_i_i_i_i126_i_121_c_compmm_m3657_b;
    logic [16:0] i_add_i_i_i_i_i126_i_121_c_compmm_m3657_o;
    wire [16:0] i_add_i_i_i_i_i126_i_121_c_compmm_m3657_q;
    wire [16:0] i_add_i_i_i_i_i126_i_122_c_compmm_m3685_a;
    wire [16:0] i_add_i_i_i_i_i126_i_122_c_compmm_m3685_b;
    logic [16:0] i_add_i_i_i_i_i126_i_122_c_compmm_m3685_o;
    wire [16:0] i_add_i_i_i_i_i126_i_122_c_compmm_m3685_q;
    wire [16:0] i_add_i_i_i_i_i126_i_123_c_compmm_m3713_a;
    wire [16:0] i_add_i_i_i_i_i126_i_123_c_compmm_m3713_b;
    logic [16:0] i_add_i_i_i_i_i126_i_123_c_compmm_m3713_o;
    wire [16:0] i_add_i_i_i_i_i126_i_123_c_compmm_m3713_q;
    wire [16:0] i_add_i_i_i_i_i126_i_124_c_compmm_m3741_a;
    wire [16:0] i_add_i_i_i_i_i126_i_124_c_compmm_m3741_b;
    logic [16:0] i_add_i_i_i_i_i126_i_124_c_compmm_m3741_o;
    wire [16:0] i_add_i_i_i_i_i126_i_124_c_compmm_m3741_q;
    wire [16:0] i_add_i_i_i_i_i126_i_125_c_compmm_m3769_a;
    wire [16:0] i_add_i_i_i_i_i126_i_125_c_compmm_m3769_b;
    logic [16:0] i_add_i_i_i_i_i126_i_125_c_compmm_m3769_o;
    wire [16:0] i_add_i_i_i_i_i126_i_125_c_compmm_m3769_q;
    wire [16:0] i_add_i_i_i_i_i126_i_126_c_compmm_m3797_a;
    wire [16:0] i_add_i_i_i_i_i126_i_126_c_compmm_m3797_b;
    logic [16:0] i_add_i_i_i_i_i126_i_126_c_compmm_m3797_o;
    wire [16:0] i_add_i_i_i_i_i126_i_126_c_compmm_m3797_q;
    wire [16:0] i_add_i_i_i_i_i126_i_127_c_compmm_m3825_a;
    wire [16:0] i_add_i_i_i_i_i126_i_127_c_compmm_m3825_b;
    logic [16:0] i_add_i_i_i_i_i126_i_127_c_compmm_m3825_o;
    wire [16:0] i_add_i_i_i_i_i126_i_127_c_compmm_m3825_q;
    wire [16:0] i_add_i_i_i_i_i126_i_12_c_compmm_m602_a;
    wire [16:0] i_add_i_i_i_i_i126_i_12_c_compmm_m602_b;
    logic [16:0] i_add_i_i_i_i_i126_i_12_c_compmm_m602_o;
    wire [16:0] i_add_i_i_i_i_i126_i_12_c_compmm_m602_q;
    wire [16:0] i_add_i_i_i_i_i126_i_13_c_compmm_m630_a;
    wire [16:0] i_add_i_i_i_i_i126_i_13_c_compmm_m630_b;
    logic [16:0] i_add_i_i_i_i_i126_i_13_c_compmm_m630_o;
    wire [16:0] i_add_i_i_i_i_i126_i_13_c_compmm_m630_q;
    wire [16:0] i_add_i_i_i_i_i126_i_14_c_compmm_m658_a;
    wire [16:0] i_add_i_i_i_i_i126_i_14_c_compmm_m658_b;
    logic [16:0] i_add_i_i_i_i_i126_i_14_c_compmm_m658_o;
    wire [16:0] i_add_i_i_i_i_i126_i_14_c_compmm_m658_q;
    wire [16:0] i_add_i_i_i_i_i126_i_15_c_compmm_m686_a;
    wire [16:0] i_add_i_i_i_i_i126_i_15_c_compmm_m686_b;
    logic [16:0] i_add_i_i_i_i_i126_i_15_c_compmm_m686_o;
    wire [16:0] i_add_i_i_i_i_i126_i_15_c_compmm_m686_q;
    wire [16:0] i_add_i_i_i_i_i126_i_16_c_compmm_m714_a;
    wire [16:0] i_add_i_i_i_i_i126_i_16_c_compmm_m714_b;
    logic [16:0] i_add_i_i_i_i_i126_i_16_c_compmm_m714_o;
    wire [16:0] i_add_i_i_i_i_i126_i_16_c_compmm_m714_q;
    wire [16:0] i_add_i_i_i_i_i126_i_17_c_compmm_m742_a;
    wire [16:0] i_add_i_i_i_i_i126_i_17_c_compmm_m742_b;
    logic [16:0] i_add_i_i_i_i_i126_i_17_c_compmm_m742_o;
    wire [16:0] i_add_i_i_i_i_i126_i_17_c_compmm_m742_q;
    wire [16:0] i_add_i_i_i_i_i126_i_18_c_compmm_m770_a;
    wire [16:0] i_add_i_i_i_i_i126_i_18_c_compmm_m770_b;
    logic [16:0] i_add_i_i_i_i_i126_i_18_c_compmm_m770_o;
    wire [16:0] i_add_i_i_i_i_i126_i_18_c_compmm_m770_q;
    wire [16:0] i_add_i_i_i_i_i126_i_19_c_compmm_m798_a;
    wire [16:0] i_add_i_i_i_i_i126_i_19_c_compmm_m798_b;
    logic [16:0] i_add_i_i_i_i_i126_i_19_c_compmm_m798_o;
    wire [16:0] i_add_i_i_i_i_i126_i_19_c_compmm_m798_q;
    wire [16:0] i_add_i_i_i_i_i126_i_1_c_compmm_m294_a;
    wire [16:0] i_add_i_i_i_i_i126_i_1_c_compmm_m294_b;
    logic [16:0] i_add_i_i_i_i_i126_i_1_c_compmm_m294_o;
    wire [16:0] i_add_i_i_i_i_i126_i_1_c_compmm_m294_q;
    wire [16:0] i_add_i_i_i_i_i126_i_20_c_compmm_m826_a;
    wire [16:0] i_add_i_i_i_i_i126_i_20_c_compmm_m826_b;
    logic [16:0] i_add_i_i_i_i_i126_i_20_c_compmm_m826_o;
    wire [16:0] i_add_i_i_i_i_i126_i_20_c_compmm_m826_q;
    wire [16:0] i_add_i_i_i_i_i126_i_21_c_compmm_m854_a;
    wire [16:0] i_add_i_i_i_i_i126_i_21_c_compmm_m854_b;
    logic [16:0] i_add_i_i_i_i_i126_i_21_c_compmm_m854_o;
    wire [16:0] i_add_i_i_i_i_i126_i_21_c_compmm_m854_q;
    wire [16:0] i_add_i_i_i_i_i126_i_22_c_compmm_m882_a;
    wire [16:0] i_add_i_i_i_i_i126_i_22_c_compmm_m882_b;
    logic [16:0] i_add_i_i_i_i_i126_i_22_c_compmm_m882_o;
    wire [16:0] i_add_i_i_i_i_i126_i_22_c_compmm_m882_q;
    wire [16:0] i_add_i_i_i_i_i126_i_23_c_compmm_m910_a;
    wire [16:0] i_add_i_i_i_i_i126_i_23_c_compmm_m910_b;
    logic [16:0] i_add_i_i_i_i_i126_i_23_c_compmm_m910_o;
    wire [16:0] i_add_i_i_i_i_i126_i_23_c_compmm_m910_q;
    wire [16:0] i_add_i_i_i_i_i126_i_24_c_compmm_m938_a;
    wire [16:0] i_add_i_i_i_i_i126_i_24_c_compmm_m938_b;
    logic [16:0] i_add_i_i_i_i_i126_i_24_c_compmm_m938_o;
    wire [16:0] i_add_i_i_i_i_i126_i_24_c_compmm_m938_q;
    wire [16:0] i_add_i_i_i_i_i126_i_25_c_compmm_m966_a;
    wire [16:0] i_add_i_i_i_i_i126_i_25_c_compmm_m966_b;
    logic [16:0] i_add_i_i_i_i_i126_i_25_c_compmm_m966_o;
    wire [16:0] i_add_i_i_i_i_i126_i_25_c_compmm_m966_q;
    wire [16:0] i_add_i_i_i_i_i126_i_26_c_compmm_m994_a;
    wire [16:0] i_add_i_i_i_i_i126_i_26_c_compmm_m994_b;
    logic [16:0] i_add_i_i_i_i_i126_i_26_c_compmm_m994_o;
    wire [16:0] i_add_i_i_i_i_i126_i_26_c_compmm_m994_q;
    wire [16:0] i_add_i_i_i_i_i126_i_27_c_compmm_m1022_a;
    wire [16:0] i_add_i_i_i_i_i126_i_27_c_compmm_m1022_b;
    logic [16:0] i_add_i_i_i_i_i126_i_27_c_compmm_m1022_o;
    wire [16:0] i_add_i_i_i_i_i126_i_27_c_compmm_m1022_q;
    wire [16:0] i_add_i_i_i_i_i126_i_28_c_compmm_m1050_a;
    wire [16:0] i_add_i_i_i_i_i126_i_28_c_compmm_m1050_b;
    logic [16:0] i_add_i_i_i_i_i126_i_28_c_compmm_m1050_o;
    wire [16:0] i_add_i_i_i_i_i126_i_28_c_compmm_m1050_q;
    wire [16:0] i_add_i_i_i_i_i126_i_29_c_compmm_m1078_a;
    wire [16:0] i_add_i_i_i_i_i126_i_29_c_compmm_m1078_b;
    logic [16:0] i_add_i_i_i_i_i126_i_29_c_compmm_m1078_o;
    wire [16:0] i_add_i_i_i_i_i126_i_29_c_compmm_m1078_q;
    wire [16:0] i_add_i_i_i_i_i126_i_2_c_compmm_m322_a;
    wire [16:0] i_add_i_i_i_i_i126_i_2_c_compmm_m322_b;
    logic [16:0] i_add_i_i_i_i_i126_i_2_c_compmm_m322_o;
    wire [16:0] i_add_i_i_i_i_i126_i_2_c_compmm_m322_q;
    wire [16:0] i_add_i_i_i_i_i126_i_30_c_compmm_m1106_a;
    wire [16:0] i_add_i_i_i_i_i126_i_30_c_compmm_m1106_b;
    logic [16:0] i_add_i_i_i_i_i126_i_30_c_compmm_m1106_o;
    wire [16:0] i_add_i_i_i_i_i126_i_30_c_compmm_m1106_q;
    wire [16:0] i_add_i_i_i_i_i126_i_31_c_compmm_m1134_a;
    wire [16:0] i_add_i_i_i_i_i126_i_31_c_compmm_m1134_b;
    logic [16:0] i_add_i_i_i_i_i126_i_31_c_compmm_m1134_o;
    wire [16:0] i_add_i_i_i_i_i126_i_31_c_compmm_m1134_q;
    wire [16:0] i_add_i_i_i_i_i126_i_32_c_compmm_m1163_a;
    wire [16:0] i_add_i_i_i_i_i126_i_32_c_compmm_m1163_b;
    logic [16:0] i_add_i_i_i_i_i126_i_32_c_compmm_m1163_o;
    wire [16:0] i_add_i_i_i_i_i126_i_32_c_compmm_m1163_q;
    wire [16:0] i_add_i_i_i_i_i126_i_33_c_compmm_m1191_a;
    wire [16:0] i_add_i_i_i_i_i126_i_33_c_compmm_m1191_b;
    logic [16:0] i_add_i_i_i_i_i126_i_33_c_compmm_m1191_o;
    wire [16:0] i_add_i_i_i_i_i126_i_33_c_compmm_m1191_q;
    wire [16:0] i_add_i_i_i_i_i126_i_34_c_compmm_m1219_a;
    wire [16:0] i_add_i_i_i_i_i126_i_34_c_compmm_m1219_b;
    logic [16:0] i_add_i_i_i_i_i126_i_34_c_compmm_m1219_o;
    wire [16:0] i_add_i_i_i_i_i126_i_34_c_compmm_m1219_q;
    wire [16:0] i_add_i_i_i_i_i126_i_35_c_compmm_m1247_a;
    wire [16:0] i_add_i_i_i_i_i126_i_35_c_compmm_m1247_b;
    logic [16:0] i_add_i_i_i_i_i126_i_35_c_compmm_m1247_o;
    wire [16:0] i_add_i_i_i_i_i126_i_35_c_compmm_m1247_q;
    wire [16:0] i_add_i_i_i_i_i126_i_36_c_compmm_m1275_a;
    wire [16:0] i_add_i_i_i_i_i126_i_36_c_compmm_m1275_b;
    logic [16:0] i_add_i_i_i_i_i126_i_36_c_compmm_m1275_o;
    wire [16:0] i_add_i_i_i_i_i126_i_36_c_compmm_m1275_q;
    wire [16:0] i_add_i_i_i_i_i126_i_37_c_compmm_m1303_a;
    wire [16:0] i_add_i_i_i_i_i126_i_37_c_compmm_m1303_b;
    logic [16:0] i_add_i_i_i_i_i126_i_37_c_compmm_m1303_o;
    wire [16:0] i_add_i_i_i_i_i126_i_37_c_compmm_m1303_q;
    wire [16:0] i_add_i_i_i_i_i126_i_38_c_compmm_m1331_a;
    wire [16:0] i_add_i_i_i_i_i126_i_38_c_compmm_m1331_b;
    logic [16:0] i_add_i_i_i_i_i126_i_38_c_compmm_m1331_o;
    wire [16:0] i_add_i_i_i_i_i126_i_38_c_compmm_m1331_q;
    wire [16:0] i_add_i_i_i_i_i126_i_39_c_compmm_m1359_a;
    wire [16:0] i_add_i_i_i_i_i126_i_39_c_compmm_m1359_b;
    logic [16:0] i_add_i_i_i_i_i126_i_39_c_compmm_m1359_o;
    wire [16:0] i_add_i_i_i_i_i126_i_39_c_compmm_m1359_q;
    wire [16:0] i_add_i_i_i_i_i126_i_3_c_compmm_m350_a;
    wire [16:0] i_add_i_i_i_i_i126_i_3_c_compmm_m350_b;
    logic [16:0] i_add_i_i_i_i_i126_i_3_c_compmm_m350_o;
    wire [16:0] i_add_i_i_i_i_i126_i_3_c_compmm_m350_q;
    wire [16:0] i_add_i_i_i_i_i126_i_40_c_compmm_m1387_a;
    wire [16:0] i_add_i_i_i_i_i126_i_40_c_compmm_m1387_b;
    logic [16:0] i_add_i_i_i_i_i126_i_40_c_compmm_m1387_o;
    wire [16:0] i_add_i_i_i_i_i126_i_40_c_compmm_m1387_q;
    wire [16:0] i_add_i_i_i_i_i126_i_41_c_compmm_m1415_a;
    wire [16:0] i_add_i_i_i_i_i126_i_41_c_compmm_m1415_b;
    logic [16:0] i_add_i_i_i_i_i126_i_41_c_compmm_m1415_o;
    wire [16:0] i_add_i_i_i_i_i126_i_41_c_compmm_m1415_q;
    wire [16:0] i_add_i_i_i_i_i126_i_42_c_compmm_m1443_a;
    wire [16:0] i_add_i_i_i_i_i126_i_42_c_compmm_m1443_b;
    logic [16:0] i_add_i_i_i_i_i126_i_42_c_compmm_m1443_o;
    wire [16:0] i_add_i_i_i_i_i126_i_42_c_compmm_m1443_q;
    wire [16:0] i_add_i_i_i_i_i126_i_43_c_compmm_m1471_a;
    wire [16:0] i_add_i_i_i_i_i126_i_43_c_compmm_m1471_b;
    logic [16:0] i_add_i_i_i_i_i126_i_43_c_compmm_m1471_o;
    wire [16:0] i_add_i_i_i_i_i126_i_43_c_compmm_m1471_q;
    wire [16:0] i_add_i_i_i_i_i126_i_44_c_compmm_m1499_a;
    wire [16:0] i_add_i_i_i_i_i126_i_44_c_compmm_m1499_b;
    logic [16:0] i_add_i_i_i_i_i126_i_44_c_compmm_m1499_o;
    wire [16:0] i_add_i_i_i_i_i126_i_44_c_compmm_m1499_q;
    wire [16:0] i_add_i_i_i_i_i126_i_45_c_compmm_m1527_a;
    wire [16:0] i_add_i_i_i_i_i126_i_45_c_compmm_m1527_b;
    logic [16:0] i_add_i_i_i_i_i126_i_45_c_compmm_m1527_o;
    wire [16:0] i_add_i_i_i_i_i126_i_45_c_compmm_m1527_q;
    wire [16:0] i_add_i_i_i_i_i126_i_46_c_compmm_m1555_a;
    wire [16:0] i_add_i_i_i_i_i126_i_46_c_compmm_m1555_b;
    logic [16:0] i_add_i_i_i_i_i126_i_46_c_compmm_m1555_o;
    wire [16:0] i_add_i_i_i_i_i126_i_46_c_compmm_m1555_q;
    wire [16:0] i_add_i_i_i_i_i126_i_47_c_compmm_m1583_a;
    wire [16:0] i_add_i_i_i_i_i126_i_47_c_compmm_m1583_b;
    logic [16:0] i_add_i_i_i_i_i126_i_47_c_compmm_m1583_o;
    wire [16:0] i_add_i_i_i_i_i126_i_47_c_compmm_m1583_q;
    wire [16:0] i_add_i_i_i_i_i126_i_48_c_compmm_m1611_a;
    wire [16:0] i_add_i_i_i_i_i126_i_48_c_compmm_m1611_b;
    logic [16:0] i_add_i_i_i_i_i126_i_48_c_compmm_m1611_o;
    wire [16:0] i_add_i_i_i_i_i126_i_48_c_compmm_m1611_q;
    wire [16:0] i_add_i_i_i_i_i126_i_49_c_compmm_m1639_a;
    wire [16:0] i_add_i_i_i_i_i126_i_49_c_compmm_m1639_b;
    logic [16:0] i_add_i_i_i_i_i126_i_49_c_compmm_m1639_o;
    wire [16:0] i_add_i_i_i_i_i126_i_49_c_compmm_m1639_q;
    wire [16:0] i_add_i_i_i_i_i126_i_4_c_compmm_m378_a;
    wire [16:0] i_add_i_i_i_i_i126_i_4_c_compmm_m378_b;
    logic [16:0] i_add_i_i_i_i_i126_i_4_c_compmm_m378_o;
    wire [16:0] i_add_i_i_i_i_i126_i_4_c_compmm_m378_q;
    wire [16:0] i_add_i_i_i_i_i126_i_50_c_compmm_m1667_a;
    wire [16:0] i_add_i_i_i_i_i126_i_50_c_compmm_m1667_b;
    logic [16:0] i_add_i_i_i_i_i126_i_50_c_compmm_m1667_o;
    wire [16:0] i_add_i_i_i_i_i126_i_50_c_compmm_m1667_q;
    wire [16:0] i_add_i_i_i_i_i126_i_51_c_compmm_m1695_a;
    wire [16:0] i_add_i_i_i_i_i126_i_51_c_compmm_m1695_b;
    logic [16:0] i_add_i_i_i_i_i126_i_51_c_compmm_m1695_o;
    wire [16:0] i_add_i_i_i_i_i126_i_51_c_compmm_m1695_q;
    wire [16:0] i_add_i_i_i_i_i126_i_52_c_compmm_m1723_a;
    wire [16:0] i_add_i_i_i_i_i126_i_52_c_compmm_m1723_b;
    logic [16:0] i_add_i_i_i_i_i126_i_52_c_compmm_m1723_o;
    wire [16:0] i_add_i_i_i_i_i126_i_52_c_compmm_m1723_q;
    wire [16:0] i_add_i_i_i_i_i126_i_53_c_compmm_m1751_a;
    wire [16:0] i_add_i_i_i_i_i126_i_53_c_compmm_m1751_b;
    logic [16:0] i_add_i_i_i_i_i126_i_53_c_compmm_m1751_o;
    wire [16:0] i_add_i_i_i_i_i126_i_53_c_compmm_m1751_q;
    wire [16:0] i_add_i_i_i_i_i126_i_54_c_compmm_m1779_a;
    wire [16:0] i_add_i_i_i_i_i126_i_54_c_compmm_m1779_b;
    logic [16:0] i_add_i_i_i_i_i126_i_54_c_compmm_m1779_o;
    wire [16:0] i_add_i_i_i_i_i126_i_54_c_compmm_m1779_q;
    wire [16:0] i_add_i_i_i_i_i126_i_55_c_compmm_m1807_a;
    wire [16:0] i_add_i_i_i_i_i126_i_55_c_compmm_m1807_b;
    logic [16:0] i_add_i_i_i_i_i126_i_55_c_compmm_m1807_o;
    wire [16:0] i_add_i_i_i_i_i126_i_55_c_compmm_m1807_q;
    wire [16:0] i_add_i_i_i_i_i126_i_56_c_compmm_m1835_a;
    wire [16:0] i_add_i_i_i_i_i126_i_56_c_compmm_m1835_b;
    logic [16:0] i_add_i_i_i_i_i126_i_56_c_compmm_m1835_o;
    wire [16:0] i_add_i_i_i_i_i126_i_56_c_compmm_m1835_q;
    wire [16:0] i_add_i_i_i_i_i126_i_57_c_compmm_m1863_a;
    wire [16:0] i_add_i_i_i_i_i126_i_57_c_compmm_m1863_b;
    logic [16:0] i_add_i_i_i_i_i126_i_57_c_compmm_m1863_o;
    wire [16:0] i_add_i_i_i_i_i126_i_57_c_compmm_m1863_q;
    wire [16:0] i_add_i_i_i_i_i126_i_58_c_compmm_m1891_a;
    wire [16:0] i_add_i_i_i_i_i126_i_58_c_compmm_m1891_b;
    logic [16:0] i_add_i_i_i_i_i126_i_58_c_compmm_m1891_o;
    wire [16:0] i_add_i_i_i_i_i126_i_58_c_compmm_m1891_q;
    wire [16:0] i_add_i_i_i_i_i126_i_59_c_compmm_m1919_a;
    wire [16:0] i_add_i_i_i_i_i126_i_59_c_compmm_m1919_b;
    logic [16:0] i_add_i_i_i_i_i126_i_59_c_compmm_m1919_o;
    wire [16:0] i_add_i_i_i_i_i126_i_59_c_compmm_m1919_q;
    wire [16:0] i_add_i_i_i_i_i126_i_5_c_compmm_m406_a;
    wire [16:0] i_add_i_i_i_i_i126_i_5_c_compmm_m406_b;
    logic [16:0] i_add_i_i_i_i_i126_i_5_c_compmm_m406_o;
    wire [16:0] i_add_i_i_i_i_i126_i_5_c_compmm_m406_q;
    wire [16:0] i_add_i_i_i_i_i126_i_60_c_compmm_m1947_a;
    wire [16:0] i_add_i_i_i_i_i126_i_60_c_compmm_m1947_b;
    logic [16:0] i_add_i_i_i_i_i126_i_60_c_compmm_m1947_o;
    wire [16:0] i_add_i_i_i_i_i126_i_60_c_compmm_m1947_q;
    wire [16:0] i_add_i_i_i_i_i126_i_61_c_compmm_m1975_a;
    wire [16:0] i_add_i_i_i_i_i126_i_61_c_compmm_m1975_b;
    logic [16:0] i_add_i_i_i_i_i126_i_61_c_compmm_m1975_o;
    wire [16:0] i_add_i_i_i_i_i126_i_61_c_compmm_m1975_q;
    wire [16:0] i_add_i_i_i_i_i126_i_62_c_compmm_m2003_a;
    wire [16:0] i_add_i_i_i_i_i126_i_62_c_compmm_m2003_b;
    logic [16:0] i_add_i_i_i_i_i126_i_62_c_compmm_m2003_o;
    wire [16:0] i_add_i_i_i_i_i126_i_62_c_compmm_m2003_q;
    wire [16:0] i_add_i_i_i_i_i126_i_63_c_compmm_m2031_a;
    wire [16:0] i_add_i_i_i_i_i126_i_63_c_compmm_m2031_b;
    logic [16:0] i_add_i_i_i_i_i126_i_63_c_compmm_m2031_o;
    wire [16:0] i_add_i_i_i_i_i126_i_63_c_compmm_m2031_q;
    wire [16:0] i_add_i_i_i_i_i126_i_64_c_compmm_m2060_a;
    wire [16:0] i_add_i_i_i_i_i126_i_64_c_compmm_m2060_b;
    logic [16:0] i_add_i_i_i_i_i126_i_64_c_compmm_m2060_o;
    wire [16:0] i_add_i_i_i_i_i126_i_64_c_compmm_m2060_q;
    wire [16:0] i_add_i_i_i_i_i126_i_65_c_compmm_m2088_a;
    wire [16:0] i_add_i_i_i_i_i126_i_65_c_compmm_m2088_b;
    logic [16:0] i_add_i_i_i_i_i126_i_65_c_compmm_m2088_o;
    wire [16:0] i_add_i_i_i_i_i126_i_65_c_compmm_m2088_q;
    wire [16:0] i_add_i_i_i_i_i126_i_66_c_compmm_m2116_a;
    wire [16:0] i_add_i_i_i_i_i126_i_66_c_compmm_m2116_b;
    logic [16:0] i_add_i_i_i_i_i126_i_66_c_compmm_m2116_o;
    wire [16:0] i_add_i_i_i_i_i126_i_66_c_compmm_m2116_q;
    wire [16:0] i_add_i_i_i_i_i126_i_67_c_compmm_m2144_a;
    wire [16:0] i_add_i_i_i_i_i126_i_67_c_compmm_m2144_b;
    logic [16:0] i_add_i_i_i_i_i126_i_67_c_compmm_m2144_o;
    wire [16:0] i_add_i_i_i_i_i126_i_67_c_compmm_m2144_q;
    wire [16:0] i_add_i_i_i_i_i126_i_68_c_compmm_m2172_a;
    wire [16:0] i_add_i_i_i_i_i126_i_68_c_compmm_m2172_b;
    logic [16:0] i_add_i_i_i_i_i126_i_68_c_compmm_m2172_o;
    wire [16:0] i_add_i_i_i_i_i126_i_68_c_compmm_m2172_q;
    wire [16:0] i_add_i_i_i_i_i126_i_69_c_compmm_m2200_a;
    wire [16:0] i_add_i_i_i_i_i126_i_69_c_compmm_m2200_b;
    logic [16:0] i_add_i_i_i_i_i126_i_69_c_compmm_m2200_o;
    wire [16:0] i_add_i_i_i_i_i126_i_69_c_compmm_m2200_q;
    wire [16:0] i_add_i_i_i_i_i126_i_6_c_compmm_m434_a;
    wire [16:0] i_add_i_i_i_i_i126_i_6_c_compmm_m434_b;
    logic [16:0] i_add_i_i_i_i_i126_i_6_c_compmm_m434_o;
    wire [16:0] i_add_i_i_i_i_i126_i_6_c_compmm_m434_q;
    wire [16:0] i_add_i_i_i_i_i126_i_70_c_compmm_m2228_a;
    wire [16:0] i_add_i_i_i_i_i126_i_70_c_compmm_m2228_b;
    logic [16:0] i_add_i_i_i_i_i126_i_70_c_compmm_m2228_o;
    wire [16:0] i_add_i_i_i_i_i126_i_70_c_compmm_m2228_q;
    wire [16:0] i_add_i_i_i_i_i126_i_71_c_compmm_m2256_a;
    wire [16:0] i_add_i_i_i_i_i126_i_71_c_compmm_m2256_b;
    logic [16:0] i_add_i_i_i_i_i126_i_71_c_compmm_m2256_o;
    wire [16:0] i_add_i_i_i_i_i126_i_71_c_compmm_m2256_q;
    wire [16:0] i_add_i_i_i_i_i126_i_72_c_compmm_m2284_a;
    wire [16:0] i_add_i_i_i_i_i126_i_72_c_compmm_m2284_b;
    logic [16:0] i_add_i_i_i_i_i126_i_72_c_compmm_m2284_o;
    wire [16:0] i_add_i_i_i_i_i126_i_72_c_compmm_m2284_q;
    wire [16:0] i_add_i_i_i_i_i126_i_73_c_compmm_m2312_a;
    wire [16:0] i_add_i_i_i_i_i126_i_73_c_compmm_m2312_b;
    logic [16:0] i_add_i_i_i_i_i126_i_73_c_compmm_m2312_o;
    wire [16:0] i_add_i_i_i_i_i126_i_73_c_compmm_m2312_q;
    wire [16:0] i_add_i_i_i_i_i126_i_74_c_compmm_m2340_a;
    wire [16:0] i_add_i_i_i_i_i126_i_74_c_compmm_m2340_b;
    logic [16:0] i_add_i_i_i_i_i126_i_74_c_compmm_m2340_o;
    wire [16:0] i_add_i_i_i_i_i126_i_74_c_compmm_m2340_q;
    wire [16:0] i_add_i_i_i_i_i126_i_75_c_compmm_m2368_a;
    wire [16:0] i_add_i_i_i_i_i126_i_75_c_compmm_m2368_b;
    logic [16:0] i_add_i_i_i_i_i126_i_75_c_compmm_m2368_o;
    wire [16:0] i_add_i_i_i_i_i126_i_75_c_compmm_m2368_q;
    wire [16:0] i_add_i_i_i_i_i126_i_76_c_compmm_m2396_a;
    wire [16:0] i_add_i_i_i_i_i126_i_76_c_compmm_m2396_b;
    logic [16:0] i_add_i_i_i_i_i126_i_76_c_compmm_m2396_o;
    wire [16:0] i_add_i_i_i_i_i126_i_76_c_compmm_m2396_q;
    wire [16:0] i_add_i_i_i_i_i126_i_77_c_compmm_m2424_a;
    wire [16:0] i_add_i_i_i_i_i126_i_77_c_compmm_m2424_b;
    logic [16:0] i_add_i_i_i_i_i126_i_77_c_compmm_m2424_o;
    wire [16:0] i_add_i_i_i_i_i126_i_77_c_compmm_m2424_q;
    wire [16:0] i_add_i_i_i_i_i126_i_78_c_compmm_m2452_a;
    wire [16:0] i_add_i_i_i_i_i126_i_78_c_compmm_m2452_b;
    logic [16:0] i_add_i_i_i_i_i126_i_78_c_compmm_m2452_o;
    wire [16:0] i_add_i_i_i_i_i126_i_78_c_compmm_m2452_q;
    wire [16:0] i_add_i_i_i_i_i126_i_79_c_compmm_m2480_a;
    wire [16:0] i_add_i_i_i_i_i126_i_79_c_compmm_m2480_b;
    logic [16:0] i_add_i_i_i_i_i126_i_79_c_compmm_m2480_o;
    wire [16:0] i_add_i_i_i_i_i126_i_79_c_compmm_m2480_q;
    wire [16:0] i_add_i_i_i_i_i126_i_7_c_compmm_m462_a;
    wire [16:0] i_add_i_i_i_i_i126_i_7_c_compmm_m462_b;
    logic [16:0] i_add_i_i_i_i_i126_i_7_c_compmm_m462_o;
    wire [16:0] i_add_i_i_i_i_i126_i_7_c_compmm_m462_q;
    wire [16:0] i_add_i_i_i_i_i126_i_80_c_compmm_m2508_a;
    wire [16:0] i_add_i_i_i_i_i126_i_80_c_compmm_m2508_b;
    logic [16:0] i_add_i_i_i_i_i126_i_80_c_compmm_m2508_o;
    wire [16:0] i_add_i_i_i_i_i126_i_80_c_compmm_m2508_q;
    wire [16:0] i_add_i_i_i_i_i126_i_81_c_compmm_m2536_a;
    wire [16:0] i_add_i_i_i_i_i126_i_81_c_compmm_m2536_b;
    logic [16:0] i_add_i_i_i_i_i126_i_81_c_compmm_m2536_o;
    wire [16:0] i_add_i_i_i_i_i126_i_81_c_compmm_m2536_q;
    wire [16:0] i_add_i_i_i_i_i126_i_82_c_compmm_m2564_a;
    wire [16:0] i_add_i_i_i_i_i126_i_82_c_compmm_m2564_b;
    logic [16:0] i_add_i_i_i_i_i126_i_82_c_compmm_m2564_o;
    wire [16:0] i_add_i_i_i_i_i126_i_82_c_compmm_m2564_q;
    wire [16:0] i_add_i_i_i_i_i126_i_83_c_compmm_m2592_a;
    wire [16:0] i_add_i_i_i_i_i126_i_83_c_compmm_m2592_b;
    logic [16:0] i_add_i_i_i_i_i126_i_83_c_compmm_m2592_o;
    wire [16:0] i_add_i_i_i_i_i126_i_83_c_compmm_m2592_q;
    wire [16:0] i_add_i_i_i_i_i126_i_84_c_compmm_m2620_a;
    wire [16:0] i_add_i_i_i_i_i126_i_84_c_compmm_m2620_b;
    logic [16:0] i_add_i_i_i_i_i126_i_84_c_compmm_m2620_o;
    wire [16:0] i_add_i_i_i_i_i126_i_84_c_compmm_m2620_q;
    wire [16:0] i_add_i_i_i_i_i126_i_85_c_compmm_m2648_a;
    wire [16:0] i_add_i_i_i_i_i126_i_85_c_compmm_m2648_b;
    logic [16:0] i_add_i_i_i_i_i126_i_85_c_compmm_m2648_o;
    wire [16:0] i_add_i_i_i_i_i126_i_85_c_compmm_m2648_q;
    wire [16:0] i_add_i_i_i_i_i126_i_86_c_compmm_m2676_a;
    wire [16:0] i_add_i_i_i_i_i126_i_86_c_compmm_m2676_b;
    logic [16:0] i_add_i_i_i_i_i126_i_86_c_compmm_m2676_o;
    wire [16:0] i_add_i_i_i_i_i126_i_86_c_compmm_m2676_q;
    wire [16:0] i_add_i_i_i_i_i126_i_87_c_compmm_m2704_a;
    wire [16:0] i_add_i_i_i_i_i126_i_87_c_compmm_m2704_b;
    logic [16:0] i_add_i_i_i_i_i126_i_87_c_compmm_m2704_o;
    wire [16:0] i_add_i_i_i_i_i126_i_87_c_compmm_m2704_q;
    wire [16:0] i_add_i_i_i_i_i126_i_88_c_compmm_m2732_a;
    wire [16:0] i_add_i_i_i_i_i126_i_88_c_compmm_m2732_b;
    logic [16:0] i_add_i_i_i_i_i126_i_88_c_compmm_m2732_o;
    wire [16:0] i_add_i_i_i_i_i126_i_88_c_compmm_m2732_q;
    wire [16:0] i_add_i_i_i_i_i126_i_89_c_compmm_m2760_a;
    wire [16:0] i_add_i_i_i_i_i126_i_89_c_compmm_m2760_b;
    logic [16:0] i_add_i_i_i_i_i126_i_89_c_compmm_m2760_o;
    wire [16:0] i_add_i_i_i_i_i126_i_89_c_compmm_m2760_q;
    wire [16:0] i_add_i_i_i_i_i126_i_8_c_compmm_m490_a;
    wire [16:0] i_add_i_i_i_i_i126_i_8_c_compmm_m490_b;
    logic [16:0] i_add_i_i_i_i_i126_i_8_c_compmm_m490_o;
    wire [16:0] i_add_i_i_i_i_i126_i_8_c_compmm_m490_q;
    wire [16:0] i_add_i_i_i_i_i126_i_90_c_compmm_m2788_a;
    wire [16:0] i_add_i_i_i_i_i126_i_90_c_compmm_m2788_b;
    logic [16:0] i_add_i_i_i_i_i126_i_90_c_compmm_m2788_o;
    wire [16:0] i_add_i_i_i_i_i126_i_90_c_compmm_m2788_q;
    wire [16:0] i_add_i_i_i_i_i126_i_91_c_compmm_m2816_a;
    wire [16:0] i_add_i_i_i_i_i126_i_91_c_compmm_m2816_b;
    logic [16:0] i_add_i_i_i_i_i126_i_91_c_compmm_m2816_o;
    wire [16:0] i_add_i_i_i_i_i126_i_91_c_compmm_m2816_q;
    wire [16:0] i_add_i_i_i_i_i126_i_92_c_compmm_m2844_a;
    wire [16:0] i_add_i_i_i_i_i126_i_92_c_compmm_m2844_b;
    logic [16:0] i_add_i_i_i_i_i126_i_92_c_compmm_m2844_o;
    wire [16:0] i_add_i_i_i_i_i126_i_92_c_compmm_m2844_q;
    wire [16:0] i_add_i_i_i_i_i126_i_93_c_compmm_m2872_a;
    wire [16:0] i_add_i_i_i_i_i126_i_93_c_compmm_m2872_b;
    logic [16:0] i_add_i_i_i_i_i126_i_93_c_compmm_m2872_o;
    wire [16:0] i_add_i_i_i_i_i126_i_93_c_compmm_m2872_q;
    wire [16:0] i_add_i_i_i_i_i126_i_94_c_compmm_m2900_a;
    wire [16:0] i_add_i_i_i_i_i126_i_94_c_compmm_m2900_b;
    logic [16:0] i_add_i_i_i_i_i126_i_94_c_compmm_m2900_o;
    wire [16:0] i_add_i_i_i_i_i126_i_94_c_compmm_m2900_q;
    wire [16:0] i_add_i_i_i_i_i126_i_95_c_compmm_m2928_a;
    wire [16:0] i_add_i_i_i_i_i126_i_95_c_compmm_m2928_b;
    logic [16:0] i_add_i_i_i_i_i126_i_95_c_compmm_m2928_o;
    wire [16:0] i_add_i_i_i_i_i126_i_95_c_compmm_m2928_q;
    wire [16:0] i_add_i_i_i_i_i126_i_96_c_compmm_m2957_a;
    wire [16:0] i_add_i_i_i_i_i126_i_96_c_compmm_m2957_b;
    logic [16:0] i_add_i_i_i_i_i126_i_96_c_compmm_m2957_o;
    wire [16:0] i_add_i_i_i_i_i126_i_96_c_compmm_m2957_q;
    wire [16:0] i_add_i_i_i_i_i126_i_97_c_compmm_m2985_a;
    wire [16:0] i_add_i_i_i_i_i126_i_97_c_compmm_m2985_b;
    logic [16:0] i_add_i_i_i_i_i126_i_97_c_compmm_m2985_o;
    wire [16:0] i_add_i_i_i_i_i126_i_97_c_compmm_m2985_q;
    wire [16:0] i_add_i_i_i_i_i126_i_98_c_compmm_m3013_a;
    wire [16:0] i_add_i_i_i_i_i126_i_98_c_compmm_m3013_b;
    logic [16:0] i_add_i_i_i_i_i126_i_98_c_compmm_m3013_o;
    wire [16:0] i_add_i_i_i_i_i126_i_98_c_compmm_m3013_q;
    wire [16:0] i_add_i_i_i_i_i126_i_99_c_compmm_m3041_a;
    wire [16:0] i_add_i_i_i_i_i126_i_99_c_compmm_m3041_b;
    logic [16:0] i_add_i_i_i_i_i126_i_99_c_compmm_m3041_o;
    wire [16:0] i_add_i_i_i_i_i126_i_99_c_compmm_m3041_q;
    wire [16:0] i_add_i_i_i_i_i126_i_9_c_compmm_m518_a;
    wire [16:0] i_add_i_i_i_i_i126_i_9_c_compmm_m518_b;
    logic [16:0] i_add_i_i_i_i_i126_i_9_c_compmm_m518_o;
    wire [16:0] i_add_i_i_i_i_i126_i_9_c_compmm_m518_q;
    wire [16:0] i_add_i_i_i_i_i126_i_c_compmm_m268_a;
    wire [16:0] i_add_i_i_i_i_i126_i_c_compmm_m268_b;
    logic [16:0] i_add_i_i_i_i_i126_i_c_compmm_m268_o;
    wire [16:0] i_add_i_i_i_i_i126_i_c_compmm_m268_q;
    wire [16:0] i_add_i_i_i_i_i_i_100_c_compmm_m3085_a;
    wire [16:0] i_add_i_i_i_i_i_i_100_c_compmm_m3085_b;
    logic [16:0] i_add_i_i_i_i_i_i_100_c_compmm_m3085_o;
    wire [16:0] i_add_i_i_i_i_i_i_100_c_compmm_m3085_q;
    wire [16:0] i_add_i_i_i_i_i_i_101_c_compmm_m3113_a;
    wire [16:0] i_add_i_i_i_i_i_i_101_c_compmm_m3113_b;
    logic [16:0] i_add_i_i_i_i_i_i_101_c_compmm_m3113_o;
    wire [16:0] i_add_i_i_i_i_i_i_101_c_compmm_m3113_q;
    wire [16:0] i_add_i_i_i_i_i_i_102_c_compmm_m3141_a;
    wire [16:0] i_add_i_i_i_i_i_i_102_c_compmm_m3141_b;
    logic [16:0] i_add_i_i_i_i_i_i_102_c_compmm_m3141_o;
    wire [16:0] i_add_i_i_i_i_i_i_102_c_compmm_m3141_q;
    wire [16:0] i_add_i_i_i_i_i_i_103_c_compmm_m3169_a;
    wire [16:0] i_add_i_i_i_i_i_i_103_c_compmm_m3169_b;
    logic [16:0] i_add_i_i_i_i_i_i_103_c_compmm_m3169_o;
    wire [16:0] i_add_i_i_i_i_i_i_103_c_compmm_m3169_q;
    wire [16:0] i_add_i_i_i_i_i_i_104_c_compmm_m3197_a;
    wire [16:0] i_add_i_i_i_i_i_i_104_c_compmm_m3197_b;
    logic [16:0] i_add_i_i_i_i_i_i_104_c_compmm_m3197_o;
    wire [16:0] i_add_i_i_i_i_i_i_104_c_compmm_m3197_q;
    wire [16:0] i_add_i_i_i_i_i_i_105_c_compmm_m3225_a;
    wire [16:0] i_add_i_i_i_i_i_i_105_c_compmm_m3225_b;
    logic [16:0] i_add_i_i_i_i_i_i_105_c_compmm_m3225_o;
    wire [16:0] i_add_i_i_i_i_i_i_105_c_compmm_m3225_q;
    wire [16:0] i_add_i_i_i_i_i_i_106_c_compmm_m3253_a;
    wire [16:0] i_add_i_i_i_i_i_i_106_c_compmm_m3253_b;
    logic [16:0] i_add_i_i_i_i_i_i_106_c_compmm_m3253_o;
    wire [16:0] i_add_i_i_i_i_i_i_106_c_compmm_m3253_q;
    wire [16:0] i_add_i_i_i_i_i_i_107_c_compmm_m3281_a;
    wire [16:0] i_add_i_i_i_i_i_i_107_c_compmm_m3281_b;
    logic [16:0] i_add_i_i_i_i_i_i_107_c_compmm_m3281_o;
    wire [16:0] i_add_i_i_i_i_i_i_107_c_compmm_m3281_q;
    wire [16:0] i_add_i_i_i_i_i_i_108_c_compmm_m3309_a;
    wire [16:0] i_add_i_i_i_i_i_i_108_c_compmm_m3309_b;
    logic [16:0] i_add_i_i_i_i_i_i_108_c_compmm_m3309_o;
    wire [16:0] i_add_i_i_i_i_i_i_108_c_compmm_m3309_q;
    wire [16:0] i_add_i_i_i_i_i_i_109_c_compmm_m3337_a;
    wire [16:0] i_add_i_i_i_i_i_i_109_c_compmm_m3337_b;
    logic [16:0] i_add_i_i_i_i_i_i_109_c_compmm_m3337_o;
    wire [16:0] i_add_i_i_i_i_i_i_109_c_compmm_m3337_q;
    wire [16:0] i_add_i_i_i_i_i_i_10_c_compmm_m562_a;
    wire [16:0] i_add_i_i_i_i_i_i_10_c_compmm_m562_b;
    logic [16:0] i_add_i_i_i_i_i_i_10_c_compmm_m562_o;
    wire [16:0] i_add_i_i_i_i_i_i_10_c_compmm_m562_q;
    wire [16:0] i_add_i_i_i_i_i_i_110_c_compmm_m3365_a;
    wire [16:0] i_add_i_i_i_i_i_i_110_c_compmm_m3365_b;
    logic [16:0] i_add_i_i_i_i_i_i_110_c_compmm_m3365_o;
    wire [16:0] i_add_i_i_i_i_i_i_110_c_compmm_m3365_q;
    wire [16:0] i_add_i_i_i_i_i_i_111_c_compmm_m3393_a;
    wire [16:0] i_add_i_i_i_i_i_i_111_c_compmm_m3393_b;
    logic [16:0] i_add_i_i_i_i_i_i_111_c_compmm_m3393_o;
    wire [16:0] i_add_i_i_i_i_i_i_111_c_compmm_m3393_q;
    wire [16:0] i_add_i_i_i_i_i_i_112_c_compmm_m3421_a;
    wire [16:0] i_add_i_i_i_i_i_i_112_c_compmm_m3421_b;
    logic [16:0] i_add_i_i_i_i_i_i_112_c_compmm_m3421_o;
    wire [16:0] i_add_i_i_i_i_i_i_112_c_compmm_m3421_q;
    wire [16:0] i_add_i_i_i_i_i_i_113_c_compmm_m3449_a;
    wire [16:0] i_add_i_i_i_i_i_i_113_c_compmm_m3449_b;
    logic [16:0] i_add_i_i_i_i_i_i_113_c_compmm_m3449_o;
    wire [16:0] i_add_i_i_i_i_i_i_113_c_compmm_m3449_q;
    wire [16:0] i_add_i_i_i_i_i_i_114_c_compmm_m3477_a;
    wire [16:0] i_add_i_i_i_i_i_i_114_c_compmm_m3477_b;
    logic [16:0] i_add_i_i_i_i_i_i_114_c_compmm_m3477_o;
    wire [16:0] i_add_i_i_i_i_i_i_114_c_compmm_m3477_q;
    wire [16:0] i_add_i_i_i_i_i_i_115_c_compmm_m3505_a;
    wire [16:0] i_add_i_i_i_i_i_i_115_c_compmm_m3505_b;
    logic [16:0] i_add_i_i_i_i_i_i_115_c_compmm_m3505_o;
    wire [16:0] i_add_i_i_i_i_i_i_115_c_compmm_m3505_q;
    wire [16:0] i_add_i_i_i_i_i_i_116_c_compmm_m3533_a;
    wire [16:0] i_add_i_i_i_i_i_i_116_c_compmm_m3533_b;
    logic [16:0] i_add_i_i_i_i_i_i_116_c_compmm_m3533_o;
    wire [16:0] i_add_i_i_i_i_i_i_116_c_compmm_m3533_q;
    wire [16:0] i_add_i_i_i_i_i_i_117_c_compmm_m3561_a;
    wire [16:0] i_add_i_i_i_i_i_i_117_c_compmm_m3561_b;
    logic [16:0] i_add_i_i_i_i_i_i_117_c_compmm_m3561_o;
    wire [16:0] i_add_i_i_i_i_i_i_117_c_compmm_m3561_q;
    wire [16:0] i_add_i_i_i_i_i_i_118_c_compmm_m3589_a;
    wire [16:0] i_add_i_i_i_i_i_i_118_c_compmm_m3589_b;
    logic [16:0] i_add_i_i_i_i_i_i_118_c_compmm_m3589_o;
    wire [16:0] i_add_i_i_i_i_i_i_118_c_compmm_m3589_q;
    wire [16:0] i_add_i_i_i_i_i_i_119_c_compmm_m3617_a;
    wire [16:0] i_add_i_i_i_i_i_i_119_c_compmm_m3617_b;
    logic [16:0] i_add_i_i_i_i_i_i_119_c_compmm_m3617_o;
    wire [16:0] i_add_i_i_i_i_i_i_119_c_compmm_m3617_q;
    wire [16:0] i_add_i_i_i_i_i_i_11_c_compmm_m590_a;
    wire [16:0] i_add_i_i_i_i_i_i_11_c_compmm_m590_b;
    logic [16:0] i_add_i_i_i_i_i_i_11_c_compmm_m590_o;
    wire [16:0] i_add_i_i_i_i_i_i_11_c_compmm_m590_q;
    wire [16:0] i_add_i_i_i_i_i_i_120_c_compmm_m3645_a;
    wire [16:0] i_add_i_i_i_i_i_i_120_c_compmm_m3645_b;
    logic [16:0] i_add_i_i_i_i_i_i_120_c_compmm_m3645_o;
    wire [16:0] i_add_i_i_i_i_i_i_120_c_compmm_m3645_q;
    wire [16:0] i_add_i_i_i_i_i_i_121_c_compmm_m3673_a;
    wire [16:0] i_add_i_i_i_i_i_i_121_c_compmm_m3673_b;
    logic [16:0] i_add_i_i_i_i_i_i_121_c_compmm_m3673_o;
    wire [16:0] i_add_i_i_i_i_i_i_121_c_compmm_m3673_q;
    wire [16:0] i_add_i_i_i_i_i_i_122_c_compmm_m3701_a;
    wire [16:0] i_add_i_i_i_i_i_i_122_c_compmm_m3701_b;
    logic [16:0] i_add_i_i_i_i_i_i_122_c_compmm_m3701_o;
    wire [16:0] i_add_i_i_i_i_i_i_122_c_compmm_m3701_q;
    wire [16:0] i_add_i_i_i_i_i_i_123_c_compmm_m3729_a;
    wire [16:0] i_add_i_i_i_i_i_i_123_c_compmm_m3729_b;
    logic [16:0] i_add_i_i_i_i_i_i_123_c_compmm_m3729_o;
    wire [16:0] i_add_i_i_i_i_i_i_123_c_compmm_m3729_q;
    wire [16:0] i_add_i_i_i_i_i_i_124_c_compmm_m3757_a;
    wire [16:0] i_add_i_i_i_i_i_i_124_c_compmm_m3757_b;
    logic [16:0] i_add_i_i_i_i_i_i_124_c_compmm_m3757_o;
    wire [16:0] i_add_i_i_i_i_i_i_124_c_compmm_m3757_q;
    wire [16:0] i_add_i_i_i_i_i_i_125_c_compmm_m3785_a;
    wire [16:0] i_add_i_i_i_i_i_i_125_c_compmm_m3785_b;
    logic [16:0] i_add_i_i_i_i_i_i_125_c_compmm_m3785_o;
    wire [16:0] i_add_i_i_i_i_i_i_125_c_compmm_m3785_q;
    wire [16:0] i_add_i_i_i_i_i_i_126_c_compmm_m3813_a;
    wire [16:0] i_add_i_i_i_i_i_i_126_c_compmm_m3813_b;
    logic [16:0] i_add_i_i_i_i_i_i_126_c_compmm_m3813_o;
    wire [16:0] i_add_i_i_i_i_i_i_126_c_compmm_m3813_q;
    wire [16:0] i_add_i_i_i_i_i_i_127_c_compmm_m3841_a;
    wire [16:0] i_add_i_i_i_i_i_i_127_c_compmm_m3841_b;
    logic [16:0] i_add_i_i_i_i_i_i_127_c_compmm_m3841_o;
    wire [16:0] i_add_i_i_i_i_i_i_127_c_compmm_m3841_q;
    wire [16:0] i_add_i_i_i_i_i_i_12_c_compmm_m618_a;
    wire [16:0] i_add_i_i_i_i_i_i_12_c_compmm_m618_b;
    logic [16:0] i_add_i_i_i_i_i_i_12_c_compmm_m618_o;
    wire [16:0] i_add_i_i_i_i_i_i_12_c_compmm_m618_q;
    wire [16:0] i_add_i_i_i_i_i_i_13_c_compmm_m646_a;
    wire [16:0] i_add_i_i_i_i_i_i_13_c_compmm_m646_b;
    logic [16:0] i_add_i_i_i_i_i_i_13_c_compmm_m646_o;
    wire [16:0] i_add_i_i_i_i_i_i_13_c_compmm_m646_q;
    wire [16:0] i_add_i_i_i_i_i_i_14_c_compmm_m674_a;
    wire [16:0] i_add_i_i_i_i_i_i_14_c_compmm_m674_b;
    logic [16:0] i_add_i_i_i_i_i_i_14_c_compmm_m674_o;
    wire [16:0] i_add_i_i_i_i_i_i_14_c_compmm_m674_q;
    wire [16:0] i_add_i_i_i_i_i_i_15_c_compmm_m702_a;
    wire [16:0] i_add_i_i_i_i_i_i_15_c_compmm_m702_b;
    logic [16:0] i_add_i_i_i_i_i_i_15_c_compmm_m702_o;
    wire [16:0] i_add_i_i_i_i_i_i_15_c_compmm_m702_q;
    wire [16:0] i_add_i_i_i_i_i_i_16_c_compmm_m730_a;
    wire [16:0] i_add_i_i_i_i_i_i_16_c_compmm_m730_b;
    logic [16:0] i_add_i_i_i_i_i_i_16_c_compmm_m730_o;
    wire [16:0] i_add_i_i_i_i_i_i_16_c_compmm_m730_q;
    wire [16:0] i_add_i_i_i_i_i_i_17_c_compmm_m758_a;
    wire [16:0] i_add_i_i_i_i_i_i_17_c_compmm_m758_b;
    logic [16:0] i_add_i_i_i_i_i_i_17_c_compmm_m758_o;
    wire [16:0] i_add_i_i_i_i_i_i_17_c_compmm_m758_q;
    wire [16:0] i_add_i_i_i_i_i_i_18_c_compmm_m786_a;
    wire [16:0] i_add_i_i_i_i_i_i_18_c_compmm_m786_b;
    logic [16:0] i_add_i_i_i_i_i_i_18_c_compmm_m786_o;
    wire [16:0] i_add_i_i_i_i_i_i_18_c_compmm_m786_q;
    wire [16:0] i_add_i_i_i_i_i_i_19_c_compmm_m814_a;
    wire [16:0] i_add_i_i_i_i_i_i_19_c_compmm_m814_b;
    logic [16:0] i_add_i_i_i_i_i_i_19_c_compmm_m814_o;
    wire [16:0] i_add_i_i_i_i_i_i_19_c_compmm_m814_q;
    wire [16:0] i_add_i_i_i_i_i_i_1_c_compmm_m310_a;
    wire [16:0] i_add_i_i_i_i_i_i_1_c_compmm_m310_b;
    logic [16:0] i_add_i_i_i_i_i_i_1_c_compmm_m310_o;
    wire [16:0] i_add_i_i_i_i_i_i_1_c_compmm_m310_q;
    wire [16:0] i_add_i_i_i_i_i_i_20_c_compmm_m842_a;
    wire [16:0] i_add_i_i_i_i_i_i_20_c_compmm_m842_b;
    logic [16:0] i_add_i_i_i_i_i_i_20_c_compmm_m842_o;
    wire [16:0] i_add_i_i_i_i_i_i_20_c_compmm_m842_q;
    wire [16:0] i_add_i_i_i_i_i_i_21_c_compmm_m870_a;
    wire [16:0] i_add_i_i_i_i_i_i_21_c_compmm_m870_b;
    logic [16:0] i_add_i_i_i_i_i_i_21_c_compmm_m870_o;
    wire [16:0] i_add_i_i_i_i_i_i_21_c_compmm_m870_q;
    wire [16:0] i_add_i_i_i_i_i_i_22_c_compmm_m898_a;
    wire [16:0] i_add_i_i_i_i_i_i_22_c_compmm_m898_b;
    logic [16:0] i_add_i_i_i_i_i_i_22_c_compmm_m898_o;
    wire [16:0] i_add_i_i_i_i_i_i_22_c_compmm_m898_q;
    wire [16:0] i_add_i_i_i_i_i_i_23_c_compmm_m926_a;
    wire [16:0] i_add_i_i_i_i_i_i_23_c_compmm_m926_b;
    logic [16:0] i_add_i_i_i_i_i_i_23_c_compmm_m926_o;
    wire [16:0] i_add_i_i_i_i_i_i_23_c_compmm_m926_q;
    wire [16:0] i_add_i_i_i_i_i_i_24_c_compmm_m954_a;
    wire [16:0] i_add_i_i_i_i_i_i_24_c_compmm_m954_b;
    logic [16:0] i_add_i_i_i_i_i_i_24_c_compmm_m954_o;
    wire [16:0] i_add_i_i_i_i_i_i_24_c_compmm_m954_q;
    wire [16:0] i_add_i_i_i_i_i_i_25_c_compmm_m982_a;
    wire [16:0] i_add_i_i_i_i_i_i_25_c_compmm_m982_b;
    logic [16:0] i_add_i_i_i_i_i_i_25_c_compmm_m982_o;
    wire [16:0] i_add_i_i_i_i_i_i_25_c_compmm_m982_q;
    wire [16:0] i_add_i_i_i_i_i_i_26_c_compmm_m1010_a;
    wire [16:0] i_add_i_i_i_i_i_i_26_c_compmm_m1010_b;
    logic [16:0] i_add_i_i_i_i_i_i_26_c_compmm_m1010_o;
    wire [16:0] i_add_i_i_i_i_i_i_26_c_compmm_m1010_q;
    wire [16:0] i_add_i_i_i_i_i_i_27_c_compmm_m1038_a;
    wire [16:0] i_add_i_i_i_i_i_i_27_c_compmm_m1038_b;
    logic [16:0] i_add_i_i_i_i_i_i_27_c_compmm_m1038_o;
    wire [16:0] i_add_i_i_i_i_i_i_27_c_compmm_m1038_q;
    wire [16:0] i_add_i_i_i_i_i_i_28_c_compmm_m1066_a;
    wire [16:0] i_add_i_i_i_i_i_i_28_c_compmm_m1066_b;
    logic [16:0] i_add_i_i_i_i_i_i_28_c_compmm_m1066_o;
    wire [16:0] i_add_i_i_i_i_i_i_28_c_compmm_m1066_q;
    wire [16:0] i_add_i_i_i_i_i_i_29_c_compmm_m1094_a;
    wire [16:0] i_add_i_i_i_i_i_i_29_c_compmm_m1094_b;
    logic [16:0] i_add_i_i_i_i_i_i_29_c_compmm_m1094_o;
    wire [16:0] i_add_i_i_i_i_i_i_29_c_compmm_m1094_q;
    wire [16:0] i_add_i_i_i_i_i_i_2_c_compmm_m338_a;
    wire [16:0] i_add_i_i_i_i_i_i_2_c_compmm_m338_b;
    logic [16:0] i_add_i_i_i_i_i_i_2_c_compmm_m338_o;
    wire [16:0] i_add_i_i_i_i_i_i_2_c_compmm_m338_q;
    wire [16:0] i_add_i_i_i_i_i_i_30_c_compmm_m1122_a;
    wire [16:0] i_add_i_i_i_i_i_i_30_c_compmm_m1122_b;
    logic [16:0] i_add_i_i_i_i_i_i_30_c_compmm_m1122_o;
    wire [16:0] i_add_i_i_i_i_i_i_30_c_compmm_m1122_q;
    wire [16:0] i_add_i_i_i_i_i_i_31_c_compmm_m1150_a;
    wire [16:0] i_add_i_i_i_i_i_i_31_c_compmm_m1150_b;
    logic [16:0] i_add_i_i_i_i_i_i_31_c_compmm_m1150_o;
    wire [16:0] i_add_i_i_i_i_i_i_31_c_compmm_m1150_q;
    wire [16:0] i_add_i_i_i_i_i_i_32_c_compmm_m1179_a;
    wire [16:0] i_add_i_i_i_i_i_i_32_c_compmm_m1179_b;
    logic [16:0] i_add_i_i_i_i_i_i_32_c_compmm_m1179_o;
    wire [16:0] i_add_i_i_i_i_i_i_32_c_compmm_m1179_q;
    wire [16:0] i_add_i_i_i_i_i_i_33_c_compmm_m1207_a;
    wire [16:0] i_add_i_i_i_i_i_i_33_c_compmm_m1207_b;
    logic [16:0] i_add_i_i_i_i_i_i_33_c_compmm_m1207_o;
    wire [16:0] i_add_i_i_i_i_i_i_33_c_compmm_m1207_q;
    wire [16:0] i_add_i_i_i_i_i_i_34_c_compmm_m1235_a;
    wire [16:0] i_add_i_i_i_i_i_i_34_c_compmm_m1235_b;
    logic [16:0] i_add_i_i_i_i_i_i_34_c_compmm_m1235_o;
    wire [16:0] i_add_i_i_i_i_i_i_34_c_compmm_m1235_q;
    wire [16:0] i_add_i_i_i_i_i_i_35_c_compmm_m1263_a;
    wire [16:0] i_add_i_i_i_i_i_i_35_c_compmm_m1263_b;
    logic [16:0] i_add_i_i_i_i_i_i_35_c_compmm_m1263_o;
    wire [16:0] i_add_i_i_i_i_i_i_35_c_compmm_m1263_q;
    wire [16:0] i_add_i_i_i_i_i_i_36_c_compmm_m1291_a;
    wire [16:0] i_add_i_i_i_i_i_i_36_c_compmm_m1291_b;
    logic [16:0] i_add_i_i_i_i_i_i_36_c_compmm_m1291_o;
    wire [16:0] i_add_i_i_i_i_i_i_36_c_compmm_m1291_q;
    wire [16:0] i_add_i_i_i_i_i_i_37_c_compmm_m1319_a;
    wire [16:0] i_add_i_i_i_i_i_i_37_c_compmm_m1319_b;
    logic [16:0] i_add_i_i_i_i_i_i_37_c_compmm_m1319_o;
    wire [16:0] i_add_i_i_i_i_i_i_37_c_compmm_m1319_q;
    wire [16:0] i_add_i_i_i_i_i_i_38_c_compmm_m1347_a;
    wire [16:0] i_add_i_i_i_i_i_i_38_c_compmm_m1347_b;
    logic [16:0] i_add_i_i_i_i_i_i_38_c_compmm_m1347_o;
    wire [16:0] i_add_i_i_i_i_i_i_38_c_compmm_m1347_q;
    wire [16:0] i_add_i_i_i_i_i_i_39_c_compmm_m1375_a;
    wire [16:0] i_add_i_i_i_i_i_i_39_c_compmm_m1375_b;
    logic [16:0] i_add_i_i_i_i_i_i_39_c_compmm_m1375_o;
    wire [16:0] i_add_i_i_i_i_i_i_39_c_compmm_m1375_q;
    wire [16:0] i_add_i_i_i_i_i_i_3_c_compmm_m366_a;
    wire [16:0] i_add_i_i_i_i_i_i_3_c_compmm_m366_b;
    logic [16:0] i_add_i_i_i_i_i_i_3_c_compmm_m366_o;
    wire [16:0] i_add_i_i_i_i_i_i_3_c_compmm_m366_q;
    wire [16:0] i_add_i_i_i_i_i_i_40_c_compmm_m1403_a;
    wire [16:0] i_add_i_i_i_i_i_i_40_c_compmm_m1403_b;
    logic [16:0] i_add_i_i_i_i_i_i_40_c_compmm_m1403_o;
    wire [16:0] i_add_i_i_i_i_i_i_40_c_compmm_m1403_q;
    wire [16:0] i_add_i_i_i_i_i_i_41_c_compmm_m1431_a;
    wire [16:0] i_add_i_i_i_i_i_i_41_c_compmm_m1431_b;
    logic [16:0] i_add_i_i_i_i_i_i_41_c_compmm_m1431_o;
    wire [16:0] i_add_i_i_i_i_i_i_41_c_compmm_m1431_q;
    wire [16:0] i_add_i_i_i_i_i_i_42_c_compmm_m1459_a;
    wire [16:0] i_add_i_i_i_i_i_i_42_c_compmm_m1459_b;
    logic [16:0] i_add_i_i_i_i_i_i_42_c_compmm_m1459_o;
    wire [16:0] i_add_i_i_i_i_i_i_42_c_compmm_m1459_q;
    wire [16:0] i_add_i_i_i_i_i_i_43_c_compmm_m1487_a;
    wire [16:0] i_add_i_i_i_i_i_i_43_c_compmm_m1487_b;
    logic [16:0] i_add_i_i_i_i_i_i_43_c_compmm_m1487_o;
    wire [16:0] i_add_i_i_i_i_i_i_43_c_compmm_m1487_q;
    wire [16:0] i_add_i_i_i_i_i_i_44_c_compmm_m1515_a;
    wire [16:0] i_add_i_i_i_i_i_i_44_c_compmm_m1515_b;
    logic [16:0] i_add_i_i_i_i_i_i_44_c_compmm_m1515_o;
    wire [16:0] i_add_i_i_i_i_i_i_44_c_compmm_m1515_q;
    wire [16:0] i_add_i_i_i_i_i_i_45_c_compmm_m1543_a;
    wire [16:0] i_add_i_i_i_i_i_i_45_c_compmm_m1543_b;
    logic [16:0] i_add_i_i_i_i_i_i_45_c_compmm_m1543_o;
    wire [16:0] i_add_i_i_i_i_i_i_45_c_compmm_m1543_q;
    wire [16:0] i_add_i_i_i_i_i_i_46_c_compmm_m1571_a;
    wire [16:0] i_add_i_i_i_i_i_i_46_c_compmm_m1571_b;
    logic [16:0] i_add_i_i_i_i_i_i_46_c_compmm_m1571_o;
    wire [16:0] i_add_i_i_i_i_i_i_46_c_compmm_m1571_q;
    wire [16:0] i_add_i_i_i_i_i_i_47_c_compmm_m1599_a;
    wire [16:0] i_add_i_i_i_i_i_i_47_c_compmm_m1599_b;
    logic [16:0] i_add_i_i_i_i_i_i_47_c_compmm_m1599_o;
    wire [16:0] i_add_i_i_i_i_i_i_47_c_compmm_m1599_q;
    wire [16:0] i_add_i_i_i_i_i_i_48_c_compmm_m1627_a;
    wire [16:0] i_add_i_i_i_i_i_i_48_c_compmm_m1627_b;
    logic [16:0] i_add_i_i_i_i_i_i_48_c_compmm_m1627_o;
    wire [16:0] i_add_i_i_i_i_i_i_48_c_compmm_m1627_q;
    wire [16:0] i_add_i_i_i_i_i_i_49_c_compmm_m1655_a;
    wire [16:0] i_add_i_i_i_i_i_i_49_c_compmm_m1655_b;
    logic [16:0] i_add_i_i_i_i_i_i_49_c_compmm_m1655_o;
    wire [16:0] i_add_i_i_i_i_i_i_49_c_compmm_m1655_q;
    wire [16:0] i_add_i_i_i_i_i_i_4_c_compmm_m394_a;
    wire [16:0] i_add_i_i_i_i_i_i_4_c_compmm_m394_b;
    logic [16:0] i_add_i_i_i_i_i_i_4_c_compmm_m394_o;
    wire [16:0] i_add_i_i_i_i_i_i_4_c_compmm_m394_q;
    wire [16:0] i_add_i_i_i_i_i_i_50_c_compmm_m1683_a;
    wire [16:0] i_add_i_i_i_i_i_i_50_c_compmm_m1683_b;
    logic [16:0] i_add_i_i_i_i_i_i_50_c_compmm_m1683_o;
    wire [16:0] i_add_i_i_i_i_i_i_50_c_compmm_m1683_q;
    wire [16:0] i_add_i_i_i_i_i_i_51_c_compmm_m1711_a;
    wire [16:0] i_add_i_i_i_i_i_i_51_c_compmm_m1711_b;
    logic [16:0] i_add_i_i_i_i_i_i_51_c_compmm_m1711_o;
    wire [16:0] i_add_i_i_i_i_i_i_51_c_compmm_m1711_q;
    wire [16:0] i_add_i_i_i_i_i_i_52_c_compmm_m1739_a;
    wire [16:0] i_add_i_i_i_i_i_i_52_c_compmm_m1739_b;
    logic [16:0] i_add_i_i_i_i_i_i_52_c_compmm_m1739_o;
    wire [16:0] i_add_i_i_i_i_i_i_52_c_compmm_m1739_q;
    wire [16:0] i_add_i_i_i_i_i_i_53_c_compmm_m1767_a;
    wire [16:0] i_add_i_i_i_i_i_i_53_c_compmm_m1767_b;
    logic [16:0] i_add_i_i_i_i_i_i_53_c_compmm_m1767_o;
    wire [16:0] i_add_i_i_i_i_i_i_53_c_compmm_m1767_q;
    wire [16:0] i_add_i_i_i_i_i_i_54_c_compmm_m1795_a;
    wire [16:0] i_add_i_i_i_i_i_i_54_c_compmm_m1795_b;
    logic [16:0] i_add_i_i_i_i_i_i_54_c_compmm_m1795_o;
    wire [16:0] i_add_i_i_i_i_i_i_54_c_compmm_m1795_q;
    wire [16:0] i_add_i_i_i_i_i_i_55_c_compmm_m1823_a;
    wire [16:0] i_add_i_i_i_i_i_i_55_c_compmm_m1823_b;
    logic [16:0] i_add_i_i_i_i_i_i_55_c_compmm_m1823_o;
    wire [16:0] i_add_i_i_i_i_i_i_55_c_compmm_m1823_q;
    wire [16:0] i_add_i_i_i_i_i_i_56_c_compmm_m1851_a;
    wire [16:0] i_add_i_i_i_i_i_i_56_c_compmm_m1851_b;
    logic [16:0] i_add_i_i_i_i_i_i_56_c_compmm_m1851_o;
    wire [16:0] i_add_i_i_i_i_i_i_56_c_compmm_m1851_q;
    wire [16:0] i_add_i_i_i_i_i_i_57_c_compmm_m1879_a;
    wire [16:0] i_add_i_i_i_i_i_i_57_c_compmm_m1879_b;
    logic [16:0] i_add_i_i_i_i_i_i_57_c_compmm_m1879_o;
    wire [16:0] i_add_i_i_i_i_i_i_57_c_compmm_m1879_q;
    wire [16:0] i_add_i_i_i_i_i_i_58_c_compmm_m1907_a;
    wire [16:0] i_add_i_i_i_i_i_i_58_c_compmm_m1907_b;
    logic [16:0] i_add_i_i_i_i_i_i_58_c_compmm_m1907_o;
    wire [16:0] i_add_i_i_i_i_i_i_58_c_compmm_m1907_q;
    wire [16:0] i_add_i_i_i_i_i_i_59_c_compmm_m1935_a;
    wire [16:0] i_add_i_i_i_i_i_i_59_c_compmm_m1935_b;
    logic [16:0] i_add_i_i_i_i_i_i_59_c_compmm_m1935_o;
    wire [16:0] i_add_i_i_i_i_i_i_59_c_compmm_m1935_q;
    wire [16:0] i_add_i_i_i_i_i_i_5_c_compmm_m422_a;
    wire [16:0] i_add_i_i_i_i_i_i_5_c_compmm_m422_b;
    logic [16:0] i_add_i_i_i_i_i_i_5_c_compmm_m422_o;
    wire [16:0] i_add_i_i_i_i_i_i_5_c_compmm_m422_q;
    wire [16:0] i_add_i_i_i_i_i_i_60_c_compmm_m1963_a;
    wire [16:0] i_add_i_i_i_i_i_i_60_c_compmm_m1963_b;
    logic [16:0] i_add_i_i_i_i_i_i_60_c_compmm_m1963_o;
    wire [16:0] i_add_i_i_i_i_i_i_60_c_compmm_m1963_q;
    wire [16:0] i_add_i_i_i_i_i_i_61_c_compmm_m1991_a;
    wire [16:0] i_add_i_i_i_i_i_i_61_c_compmm_m1991_b;
    logic [16:0] i_add_i_i_i_i_i_i_61_c_compmm_m1991_o;
    wire [16:0] i_add_i_i_i_i_i_i_61_c_compmm_m1991_q;
    wire [16:0] i_add_i_i_i_i_i_i_62_c_compmm_m2019_a;
    wire [16:0] i_add_i_i_i_i_i_i_62_c_compmm_m2019_b;
    logic [16:0] i_add_i_i_i_i_i_i_62_c_compmm_m2019_o;
    wire [16:0] i_add_i_i_i_i_i_i_62_c_compmm_m2019_q;
    wire [16:0] i_add_i_i_i_i_i_i_63_c_compmm_m2047_a;
    wire [16:0] i_add_i_i_i_i_i_i_63_c_compmm_m2047_b;
    logic [16:0] i_add_i_i_i_i_i_i_63_c_compmm_m2047_o;
    wire [16:0] i_add_i_i_i_i_i_i_63_c_compmm_m2047_q;
    wire [16:0] i_add_i_i_i_i_i_i_64_c_compmm_m2076_a;
    wire [16:0] i_add_i_i_i_i_i_i_64_c_compmm_m2076_b;
    logic [16:0] i_add_i_i_i_i_i_i_64_c_compmm_m2076_o;
    wire [16:0] i_add_i_i_i_i_i_i_64_c_compmm_m2076_q;
    wire [16:0] i_add_i_i_i_i_i_i_65_c_compmm_m2104_a;
    wire [16:0] i_add_i_i_i_i_i_i_65_c_compmm_m2104_b;
    logic [16:0] i_add_i_i_i_i_i_i_65_c_compmm_m2104_o;
    wire [16:0] i_add_i_i_i_i_i_i_65_c_compmm_m2104_q;
    wire [16:0] i_add_i_i_i_i_i_i_66_c_compmm_m2132_a;
    wire [16:0] i_add_i_i_i_i_i_i_66_c_compmm_m2132_b;
    logic [16:0] i_add_i_i_i_i_i_i_66_c_compmm_m2132_o;
    wire [16:0] i_add_i_i_i_i_i_i_66_c_compmm_m2132_q;
    wire [16:0] i_add_i_i_i_i_i_i_67_c_compmm_m2160_a;
    wire [16:0] i_add_i_i_i_i_i_i_67_c_compmm_m2160_b;
    logic [16:0] i_add_i_i_i_i_i_i_67_c_compmm_m2160_o;
    wire [16:0] i_add_i_i_i_i_i_i_67_c_compmm_m2160_q;
    wire [16:0] i_add_i_i_i_i_i_i_68_c_compmm_m2188_a;
    wire [16:0] i_add_i_i_i_i_i_i_68_c_compmm_m2188_b;
    logic [16:0] i_add_i_i_i_i_i_i_68_c_compmm_m2188_o;
    wire [16:0] i_add_i_i_i_i_i_i_68_c_compmm_m2188_q;
    wire [16:0] i_add_i_i_i_i_i_i_69_c_compmm_m2216_a;
    wire [16:0] i_add_i_i_i_i_i_i_69_c_compmm_m2216_b;
    logic [16:0] i_add_i_i_i_i_i_i_69_c_compmm_m2216_o;
    wire [16:0] i_add_i_i_i_i_i_i_69_c_compmm_m2216_q;
    wire [16:0] i_add_i_i_i_i_i_i_6_c_compmm_m450_a;
    wire [16:0] i_add_i_i_i_i_i_i_6_c_compmm_m450_b;
    logic [16:0] i_add_i_i_i_i_i_i_6_c_compmm_m450_o;
    wire [16:0] i_add_i_i_i_i_i_i_6_c_compmm_m450_q;
    wire [16:0] i_add_i_i_i_i_i_i_70_c_compmm_m2244_a;
    wire [16:0] i_add_i_i_i_i_i_i_70_c_compmm_m2244_b;
    logic [16:0] i_add_i_i_i_i_i_i_70_c_compmm_m2244_o;
    wire [16:0] i_add_i_i_i_i_i_i_70_c_compmm_m2244_q;
    wire [16:0] i_add_i_i_i_i_i_i_71_c_compmm_m2272_a;
    wire [16:0] i_add_i_i_i_i_i_i_71_c_compmm_m2272_b;
    logic [16:0] i_add_i_i_i_i_i_i_71_c_compmm_m2272_o;
    wire [16:0] i_add_i_i_i_i_i_i_71_c_compmm_m2272_q;
    wire [16:0] i_add_i_i_i_i_i_i_72_c_compmm_m2300_a;
    wire [16:0] i_add_i_i_i_i_i_i_72_c_compmm_m2300_b;
    logic [16:0] i_add_i_i_i_i_i_i_72_c_compmm_m2300_o;
    wire [16:0] i_add_i_i_i_i_i_i_72_c_compmm_m2300_q;
    wire [16:0] i_add_i_i_i_i_i_i_73_c_compmm_m2328_a;
    wire [16:0] i_add_i_i_i_i_i_i_73_c_compmm_m2328_b;
    logic [16:0] i_add_i_i_i_i_i_i_73_c_compmm_m2328_o;
    wire [16:0] i_add_i_i_i_i_i_i_73_c_compmm_m2328_q;
    wire [16:0] i_add_i_i_i_i_i_i_74_c_compmm_m2356_a;
    wire [16:0] i_add_i_i_i_i_i_i_74_c_compmm_m2356_b;
    logic [16:0] i_add_i_i_i_i_i_i_74_c_compmm_m2356_o;
    wire [16:0] i_add_i_i_i_i_i_i_74_c_compmm_m2356_q;
    wire [16:0] i_add_i_i_i_i_i_i_75_c_compmm_m2384_a;
    wire [16:0] i_add_i_i_i_i_i_i_75_c_compmm_m2384_b;
    logic [16:0] i_add_i_i_i_i_i_i_75_c_compmm_m2384_o;
    wire [16:0] i_add_i_i_i_i_i_i_75_c_compmm_m2384_q;
    wire [16:0] i_add_i_i_i_i_i_i_76_c_compmm_m2412_a;
    wire [16:0] i_add_i_i_i_i_i_i_76_c_compmm_m2412_b;
    logic [16:0] i_add_i_i_i_i_i_i_76_c_compmm_m2412_o;
    wire [16:0] i_add_i_i_i_i_i_i_76_c_compmm_m2412_q;
    wire [16:0] i_add_i_i_i_i_i_i_77_c_compmm_m2440_a;
    wire [16:0] i_add_i_i_i_i_i_i_77_c_compmm_m2440_b;
    logic [16:0] i_add_i_i_i_i_i_i_77_c_compmm_m2440_o;
    wire [16:0] i_add_i_i_i_i_i_i_77_c_compmm_m2440_q;
    wire [16:0] i_add_i_i_i_i_i_i_78_c_compmm_m2468_a;
    wire [16:0] i_add_i_i_i_i_i_i_78_c_compmm_m2468_b;
    logic [16:0] i_add_i_i_i_i_i_i_78_c_compmm_m2468_o;
    wire [16:0] i_add_i_i_i_i_i_i_78_c_compmm_m2468_q;
    wire [16:0] i_add_i_i_i_i_i_i_79_c_compmm_m2496_a;
    wire [16:0] i_add_i_i_i_i_i_i_79_c_compmm_m2496_b;
    logic [16:0] i_add_i_i_i_i_i_i_79_c_compmm_m2496_o;
    wire [16:0] i_add_i_i_i_i_i_i_79_c_compmm_m2496_q;
    wire [16:0] i_add_i_i_i_i_i_i_7_c_compmm_m478_a;
    wire [16:0] i_add_i_i_i_i_i_i_7_c_compmm_m478_b;
    logic [16:0] i_add_i_i_i_i_i_i_7_c_compmm_m478_o;
    wire [16:0] i_add_i_i_i_i_i_i_7_c_compmm_m478_q;
    wire [16:0] i_add_i_i_i_i_i_i_80_c_compmm_m2524_a;
    wire [16:0] i_add_i_i_i_i_i_i_80_c_compmm_m2524_b;
    logic [16:0] i_add_i_i_i_i_i_i_80_c_compmm_m2524_o;
    wire [16:0] i_add_i_i_i_i_i_i_80_c_compmm_m2524_q;
    wire [16:0] i_add_i_i_i_i_i_i_81_c_compmm_m2552_a;
    wire [16:0] i_add_i_i_i_i_i_i_81_c_compmm_m2552_b;
    logic [16:0] i_add_i_i_i_i_i_i_81_c_compmm_m2552_o;
    wire [16:0] i_add_i_i_i_i_i_i_81_c_compmm_m2552_q;
    wire [16:0] i_add_i_i_i_i_i_i_82_c_compmm_m2580_a;
    wire [16:0] i_add_i_i_i_i_i_i_82_c_compmm_m2580_b;
    logic [16:0] i_add_i_i_i_i_i_i_82_c_compmm_m2580_o;
    wire [16:0] i_add_i_i_i_i_i_i_82_c_compmm_m2580_q;
    wire [16:0] i_add_i_i_i_i_i_i_83_c_compmm_m2608_a;
    wire [16:0] i_add_i_i_i_i_i_i_83_c_compmm_m2608_b;
    logic [16:0] i_add_i_i_i_i_i_i_83_c_compmm_m2608_o;
    wire [16:0] i_add_i_i_i_i_i_i_83_c_compmm_m2608_q;
    wire [16:0] i_add_i_i_i_i_i_i_84_c_compmm_m2636_a;
    wire [16:0] i_add_i_i_i_i_i_i_84_c_compmm_m2636_b;
    logic [16:0] i_add_i_i_i_i_i_i_84_c_compmm_m2636_o;
    wire [16:0] i_add_i_i_i_i_i_i_84_c_compmm_m2636_q;
    wire [16:0] i_add_i_i_i_i_i_i_85_c_compmm_m2664_a;
    wire [16:0] i_add_i_i_i_i_i_i_85_c_compmm_m2664_b;
    logic [16:0] i_add_i_i_i_i_i_i_85_c_compmm_m2664_o;
    wire [16:0] i_add_i_i_i_i_i_i_85_c_compmm_m2664_q;
    wire [16:0] i_add_i_i_i_i_i_i_86_c_compmm_m2692_a;
    wire [16:0] i_add_i_i_i_i_i_i_86_c_compmm_m2692_b;
    logic [16:0] i_add_i_i_i_i_i_i_86_c_compmm_m2692_o;
    wire [16:0] i_add_i_i_i_i_i_i_86_c_compmm_m2692_q;
    wire [16:0] i_add_i_i_i_i_i_i_87_c_compmm_m2720_a;
    wire [16:0] i_add_i_i_i_i_i_i_87_c_compmm_m2720_b;
    logic [16:0] i_add_i_i_i_i_i_i_87_c_compmm_m2720_o;
    wire [16:0] i_add_i_i_i_i_i_i_87_c_compmm_m2720_q;
    wire [16:0] i_add_i_i_i_i_i_i_88_c_compmm_m2748_a;
    wire [16:0] i_add_i_i_i_i_i_i_88_c_compmm_m2748_b;
    logic [16:0] i_add_i_i_i_i_i_i_88_c_compmm_m2748_o;
    wire [16:0] i_add_i_i_i_i_i_i_88_c_compmm_m2748_q;
    wire [16:0] i_add_i_i_i_i_i_i_89_c_compmm_m2776_a;
    wire [16:0] i_add_i_i_i_i_i_i_89_c_compmm_m2776_b;
    logic [16:0] i_add_i_i_i_i_i_i_89_c_compmm_m2776_o;
    wire [16:0] i_add_i_i_i_i_i_i_89_c_compmm_m2776_q;
    wire [16:0] i_add_i_i_i_i_i_i_8_c_compmm_m506_a;
    wire [16:0] i_add_i_i_i_i_i_i_8_c_compmm_m506_b;
    logic [16:0] i_add_i_i_i_i_i_i_8_c_compmm_m506_o;
    wire [16:0] i_add_i_i_i_i_i_i_8_c_compmm_m506_q;
    wire [16:0] i_add_i_i_i_i_i_i_90_c_compmm_m2804_a;
    wire [16:0] i_add_i_i_i_i_i_i_90_c_compmm_m2804_b;
    logic [16:0] i_add_i_i_i_i_i_i_90_c_compmm_m2804_o;
    wire [16:0] i_add_i_i_i_i_i_i_90_c_compmm_m2804_q;
    wire [16:0] i_add_i_i_i_i_i_i_91_c_compmm_m2832_a;
    wire [16:0] i_add_i_i_i_i_i_i_91_c_compmm_m2832_b;
    logic [16:0] i_add_i_i_i_i_i_i_91_c_compmm_m2832_o;
    wire [16:0] i_add_i_i_i_i_i_i_91_c_compmm_m2832_q;
    wire [16:0] i_add_i_i_i_i_i_i_92_c_compmm_m2860_a;
    wire [16:0] i_add_i_i_i_i_i_i_92_c_compmm_m2860_b;
    logic [16:0] i_add_i_i_i_i_i_i_92_c_compmm_m2860_o;
    wire [16:0] i_add_i_i_i_i_i_i_92_c_compmm_m2860_q;
    wire [16:0] i_add_i_i_i_i_i_i_93_c_compmm_m2888_a;
    wire [16:0] i_add_i_i_i_i_i_i_93_c_compmm_m2888_b;
    logic [16:0] i_add_i_i_i_i_i_i_93_c_compmm_m2888_o;
    wire [16:0] i_add_i_i_i_i_i_i_93_c_compmm_m2888_q;
    wire [16:0] i_add_i_i_i_i_i_i_94_c_compmm_m2916_a;
    wire [16:0] i_add_i_i_i_i_i_i_94_c_compmm_m2916_b;
    logic [16:0] i_add_i_i_i_i_i_i_94_c_compmm_m2916_o;
    wire [16:0] i_add_i_i_i_i_i_i_94_c_compmm_m2916_q;
    wire [16:0] i_add_i_i_i_i_i_i_95_c_compmm_m2944_a;
    wire [16:0] i_add_i_i_i_i_i_i_95_c_compmm_m2944_b;
    logic [16:0] i_add_i_i_i_i_i_i_95_c_compmm_m2944_o;
    wire [16:0] i_add_i_i_i_i_i_i_95_c_compmm_m2944_q;
    wire [16:0] i_add_i_i_i_i_i_i_96_c_compmm_m2973_a;
    wire [16:0] i_add_i_i_i_i_i_i_96_c_compmm_m2973_b;
    logic [16:0] i_add_i_i_i_i_i_i_96_c_compmm_m2973_o;
    wire [16:0] i_add_i_i_i_i_i_i_96_c_compmm_m2973_q;
    wire [16:0] i_add_i_i_i_i_i_i_97_c_compmm_m3001_a;
    wire [16:0] i_add_i_i_i_i_i_i_97_c_compmm_m3001_b;
    logic [16:0] i_add_i_i_i_i_i_i_97_c_compmm_m3001_o;
    wire [16:0] i_add_i_i_i_i_i_i_97_c_compmm_m3001_q;
    wire [16:0] i_add_i_i_i_i_i_i_98_c_compmm_m3029_a;
    wire [16:0] i_add_i_i_i_i_i_i_98_c_compmm_m3029_b;
    logic [16:0] i_add_i_i_i_i_i_i_98_c_compmm_m3029_o;
    wire [16:0] i_add_i_i_i_i_i_i_98_c_compmm_m3029_q;
    wire [16:0] i_add_i_i_i_i_i_i_99_c_compmm_m3057_a;
    wire [16:0] i_add_i_i_i_i_i_i_99_c_compmm_m3057_b;
    logic [16:0] i_add_i_i_i_i_i_i_99_c_compmm_m3057_o;
    wire [16:0] i_add_i_i_i_i_i_i_99_c_compmm_m3057_q;
    wire [16:0] i_add_i_i_i_i_i_i_9_c_compmm_m534_a;
    wire [16:0] i_add_i_i_i_i_i_i_9_c_compmm_m534_b;
    logic [16:0] i_add_i_i_i_i_i_i_9_c_compmm_m534_o;
    wire [16:0] i_add_i_i_i_i_i_i_9_c_compmm_m534_q;
    wire [16:0] i_add_i_i_i_i_i_i_c_compmm_m282_a;
    wire [16:0] i_add_i_i_i_i_i_i_c_compmm_m282_b;
    logic [16:0] i_add_i_i_i_i_i_i_c_compmm_m282_o;
    wire [16:0] i_add_i_i_i_i_i_i_c_compmm_m282_q;
    wire [12:0] i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q;
    wire [28:0] i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_select_15_b;
    wire [28:0] i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_join_q;
    wire [15:0] i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_select_15_b;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6419_c_compmm_m257_out_dest_data_out_1_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6583_c_compmm_m193_out_dest_data_out_65_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_66147_c_compmm_m129_out_dest_data_out_129_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_67211_c_compmm_m65_out_dest_data_out_193_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6429_c_compmm_m247_out_dest_data_out_11_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6593_c_compmm_m183_out_dest_data_out_75_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_66157_c_compmm_m119_out_dest_data_out_139_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_67221_c_compmm_m55_out_dest_data_out_203_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6430_c_compmm_m246_out_dest_data_out_12_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6594_c_compmm_m182_out_dest_data_out_76_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_66158_c_compmm_m118_out_dest_data_out_140_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_67222_c_compmm_m54_out_dest_data_out_204_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6431_c_compmm_m245_out_dest_data_out_13_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6595_c_compmm_m181_out_dest_data_out_77_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_66159_c_compmm_m117_out_dest_data_out_141_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_67223_c_compmm_m53_out_dest_data_out_205_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6432_c_compmm_m244_out_dest_data_out_14_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6596_c_compmm_m180_out_dest_data_out_78_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_66160_c_compmm_m116_out_dest_data_out_142_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_67224_c_compmm_m52_out_dest_data_out_206_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6433_c_compmm_m243_out_dest_data_out_15_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6597_c_compmm_m179_out_dest_data_out_79_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_66161_c_compmm_m115_out_dest_data_out_143_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_67225_c_compmm_m51_out_dest_data_out_207_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6434_c_compmm_m242_out_dest_data_out_16_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6598_c_compmm_m178_out_dest_data_out_80_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_66162_c_compmm_m114_out_dest_data_out_144_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_67226_c_compmm_m50_out_dest_data_out_208_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6435_c_compmm_m241_out_dest_data_out_17_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6599_c_compmm_m177_out_dest_data_out_81_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_66163_c_compmm_m113_out_dest_data_out_145_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_67227_c_compmm_m49_out_dest_data_out_209_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_6436_c_compmm_m240_out_dest_data_out_18_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_65100_c_compmm_m176_out_dest_data_out_82_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_66164_c_compmm_m112_out_dest_data_out_146_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_67228_c_compmm_m48_out_dest_data_out_210_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_6437_c_compmm_m239_out_dest_data_out_19_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_65101_c_compmm_m175_out_dest_data_out_83_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_66165_c_compmm_m111_out_dest_data_out_147_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_67229_c_compmm_m47_out_dest_data_out_211_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_6438_c_compmm_m238_out_dest_data_out_20_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_65102_c_compmm_m174_out_dest_data_out_84_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_66166_c_compmm_m110_out_dest_data_out_148_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_67230_c_compmm_m46_out_dest_data_out_212_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6420_c_compmm_m256_out_dest_data_out_2_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6584_c_compmm_m192_out_dest_data_out_66_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_66148_c_compmm_m128_out_dest_data_out_130_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_67212_c_compmm_m64_out_dest_data_out_194_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_6439_c_compmm_m237_out_dest_data_out_21_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_65103_c_compmm_m173_out_dest_data_out_85_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_66167_c_compmm_m109_out_dest_data_out_149_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_67231_c_compmm_m45_out_dest_data_out_213_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_6440_c_compmm_m236_out_dest_data_out_22_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_65104_c_compmm_m172_out_dest_data_out_86_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_66168_c_compmm_m108_out_dest_data_out_150_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_67232_c_compmm_m44_out_dest_data_out_214_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_6441_c_compmm_m235_out_dest_data_out_23_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_65105_c_compmm_m171_out_dest_data_out_87_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_66169_c_compmm_m107_out_dest_data_out_151_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_67233_c_compmm_m43_out_dest_data_out_215_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_6442_c_compmm_m234_out_dest_data_out_24_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_65106_c_compmm_m170_out_dest_data_out_88_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_66170_c_compmm_m106_out_dest_data_out_152_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_67234_c_compmm_m42_out_dest_data_out_216_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_6443_c_compmm_m233_out_dest_data_out_25_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_65107_c_compmm_m169_out_dest_data_out_89_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_66171_c_compmm_m105_out_dest_data_out_153_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_67235_c_compmm_m41_out_dest_data_out_217_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_6444_c_compmm_m232_out_dest_data_out_26_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_65108_c_compmm_m168_out_dest_data_out_90_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_66172_c_compmm_m104_out_dest_data_out_154_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_67236_c_compmm_m40_out_dest_data_out_218_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_6445_c_compmm_m231_out_dest_data_out_27_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_65109_c_compmm_m167_out_dest_data_out_91_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_66173_c_compmm_m103_out_dest_data_out_155_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_67237_c_compmm_m39_out_dest_data_out_219_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_6446_c_compmm_m230_out_dest_data_out_28_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_65110_c_compmm_m166_out_dest_data_out_92_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_66174_c_compmm_m102_out_dest_data_out_156_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_67238_c_compmm_m38_out_dest_data_out_220_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_6447_c_compmm_m229_out_dest_data_out_29_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_65111_c_compmm_m165_out_dest_data_out_93_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_66175_c_compmm_m101_out_dest_data_out_157_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_67239_c_compmm_m37_out_dest_data_out_221_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_6448_c_compmm_m228_out_dest_data_out_30_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_65112_c_compmm_m164_out_dest_data_out_94_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_66176_c_compmm_m100_out_dest_data_out_158_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_67240_c_compmm_m36_out_dest_data_out_222_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6421_c_compmm_m255_out_dest_data_out_3_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6585_c_compmm_m191_out_dest_data_out_67_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_66149_c_compmm_m127_out_dest_data_out_131_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_67213_c_compmm_m63_out_dest_data_out_195_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_6449_c_compmm_m227_out_dest_data_out_31_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_65113_c_compmm_m163_out_dest_data_out_95_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_66177_c_compmm_m99_out_dest_data_out_159_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_67241_c_compmm_m35_out_dest_data_out_223_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_6450_c_compmm_m226_out_dest_data_out_32_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_65114_c_compmm_m162_out_dest_data_out_96_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_66178_c_compmm_m98_out_dest_data_out_160_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_67242_c_compmm_m34_out_dest_data_out_224_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_6451_c_compmm_m225_out_dest_data_out_33_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_65115_c_compmm_m161_out_dest_data_out_97_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_66179_c_compmm_m97_out_dest_data_out_161_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_67243_c_compmm_m33_out_dest_data_out_225_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_6452_c_compmm_m224_out_dest_data_out_34_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_65116_c_compmm_m160_out_dest_data_out_98_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_66180_c_compmm_m96_out_dest_data_out_162_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_67244_c_compmm_m32_out_dest_data_out_226_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_6453_c_compmm_m223_out_dest_data_out_35_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_65117_c_compmm_m159_out_dest_data_out_99_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_66181_c_compmm_m95_out_dest_data_out_163_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_67245_c_compmm_m31_out_dest_data_out_227_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_6454_c_compmm_m222_out_dest_data_out_36_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_65118_c_compmm_m158_out_dest_data_out_100_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_66182_c_compmm_m94_out_dest_data_out_164_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_67246_c_compmm_m30_out_dest_data_out_228_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_6455_c_compmm_m221_out_dest_data_out_37_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_65119_c_compmm_m157_out_dest_data_out_101_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_66183_c_compmm_m93_out_dest_data_out_165_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_67247_c_compmm_m29_out_dest_data_out_229_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_6456_c_compmm_m220_out_dest_data_out_38_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_65120_c_compmm_m156_out_dest_data_out_102_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_66184_c_compmm_m92_out_dest_data_out_166_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_67248_c_compmm_m28_out_dest_data_out_230_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_6457_c_compmm_m219_out_dest_data_out_39_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_65121_c_compmm_m155_out_dest_data_out_103_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_66185_c_compmm_m91_out_dest_data_out_167_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_67249_c_compmm_m27_out_dest_data_out_231_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_6458_c_compmm_m218_out_dest_data_out_40_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_65122_c_compmm_m154_out_dest_data_out_104_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_66186_c_compmm_m90_out_dest_data_out_168_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_67250_c_compmm_m26_out_dest_data_out_232_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6422_c_compmm_m254_out_dest_data_out_4_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6586_c_compmm_m190_out_dest_data_out_68_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_66150_c_compmm_m126_out_dest_data_out_132_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_67214_c_compmm_m62_out_dest_data_out_196_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_6459_c_compmm_m217_out_dest_data_out_41_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_65123_c_compmm_m153_out_dest_data_out_105_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_66187_c_compmm_m89_out_dest_data_out_169_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_67251_c_compmm_m25_out_dest_data_out_233_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_6460_c_compmm_m216_out_dest_data_out_42_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_65124_c_compmm_m152_out_dest_data_out_106_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_66188_c_compmm_m88_out_dest_data_out_170_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_67252_c_compmm_m24_out_dest_data_out_234_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_6461_c_compmm_m215_out_dest_data_out_43_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_65125_c_compmm_m151_out_dest_data_out_107_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_66189_c_compmm_m87_out_dest_data_out_171_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_67253_c_compmm_m23_out_dest_data_out_235_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_6462_c_compmm_m214_out_dest_data_out_44_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_65126_c_compmm_m150_out_dest_data_out_108_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_66190_c_compmm_m86_out_dest_data_out_172_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_67254_c_compmm_m22_out_dest_data_out_236_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_6463_c_compmm_m213_out_dest_data_out_45_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_65127_c_compmm_m149_out_dest_data_out_109_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_66191_c_compmm_m85_out_dest_data_out_173_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_67255_c_compmm_m21_out_dest_data_out_237_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_6464_c_compmm_m212_out_dest_data_out_46_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_65128_c_compmm_m148_out_dest_data_out_110_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_66192_c_compmm_m84_out_dest_data_out_174_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_67256_c_compmm_m20_out_dest_data_out_238_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_6465_c_compmm_m211_out_dest_data_out_47_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_65129_c_compmm_m147_out_dest_data_out_111_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_66193_c_compmm_m83_out_dest_data_out_175_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_67257_c_compmm_m19_out_dest_data_out_239_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_6466_c_compmm_m210_out_dest_data_out_48_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_65130_c_compmm_m146_out_dest_data_out_112_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_66194_c_compmm_m82_out_dest_data_out_176_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_67258_c_compmm_m18_out_dest_data_out_240_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_6467_c_compmm_m209_out_dest_data_out_49_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_65131_c_compmm_m145_out_dest_data_out_113_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_66195_c_compmm_m81_out_dest_data_out_177_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_67259_c_compmm_m17_out_dest_data_out_241_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_6468_c_compmm_m208_out_dest_data_out_50_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_65132_c_compmm_m144_out_dest_data_out_114_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_66196_c_compmm_m80_out_dest_data_out_178_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_67260_c_compmm_m16_out_dest_data_out_242_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6423_c_compmm_m253_out_dest_data_out_5_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6587_c_compmm_m189_out_dest_data_out_69_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_66151_c_compmm_m125_out_dest_data_out_133_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_67215_c_compmm_m61_out_dest_data_out_197_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_6469_c_compmm_m207_out_dest_data_out_51_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_65133_c_compmm_m143_out_dest_data_out_115_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_66197_c_compmm_m79_out_dest_data_out_179_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_67261_c_compmm_m15_out_dest_data_out_243_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_6470_c_compmm_m206_out_dest_data_out_52_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_65134_c_compmm_m142_out_dest_data_out_116_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_66198_c_compmm_m78_out_dest_data_out_180_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_67262_c_compmm_m14_out_dest_data_out_244_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_6471_c_compmm_m205_out_dest_data_out_53_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_65135_c_compmm_m141_out_dest_data_out_117_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_66199_c_compmm_m77_out_dest_data_out_181_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_67263_c_compmm_m13_out_dest_data_out_245_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_6472_c_compmm_m204_out_dest_data_out_54_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_65136_c_compmm_m140_out_dest_data_out_118_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_66200_c_compmm_m76_out_dest_data_out_182_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_67264_c_compmm_m12_out_dest_data_out_246_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_6473_c_compmm_m203_out_dest_data_out_55_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_65137_c_compmm_m139_out_dest_data_out_119_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_66201_c_compmm_m75_out_dest_data_out_183_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_67265_c_compmm_m11_out_dest_data_out_247_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_6474_c_compmm_m202_out_dest_data_out_56_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_65138_c_compmm_m138_out_dest_data_out_120_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_66202_c_compmm_m74_out_dest_data_out_184_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_67266_c_compmm_m10_out_dest_data_out_248_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_6475_c_compmm_m201_out_dest_data_out_57_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_65139_c_compmm_m137_out_dest_data_out_121_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_66203_c_compmm_m73_out_dest_data_out_185_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_67267_c_compmm_m9_out_dest_data_out_249_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_6476_c_compmm_m200_out_dest_data_out_58_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_65140_c_compmm_m136_out_dest_data_out_122_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_66204_c_compmm_m72_out_dest_data_out_186_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_67268_c_compmm_m8_out_dest_data_out_250_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_6477_c_compmm_m199_out_dest_data_out_59_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_65141_c_compmm_m135_out_dest_data_out_123_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_66205_c_compmm_m71_out_dest_data_out_187_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_67269_c_compmm_m7_out_dest_data_out_251_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_6478_c_compmm_m198_out_dest_data_out_60_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_65142_c_compmm_m134_out_dest_data_out_124_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_66206_c_compmm_m70_out_dest_data_out_188_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_67270_c_compmm_m6_out_dest_data_out_252_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6424_c_compmm_m252_out_dest_data_out_6_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6588_c_compmm_m188_out_dest_data_out_70_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_66152_c_compmm_m124_out_dest_data_out_134_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_67216_c_compmm_m60_out_dest_data_out_198_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_6479_c_compmm_m197_out_dest_data_out_61_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_65143_c_compmm_m133_out_dest_data_out_125_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_66207_c_compmm_m69_out_dest_data_out_189_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_67271_c_compmm_m5_out_dest_data_out_253_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_6480_c_compmm_m196_out_dest_data_out_62_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_65144_c_compmm_m132_out_dest_data_out_126_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_66208_c_compmm_m68_out_dest_data_out_190_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_67272_c_compmm_m4_out_dest_data_out_254_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_6481_c_compmm_m195_out_dest_data_out_63_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_65145_c_compmm_m131_out_dest_data_out_127_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_66209_c_compmm_m67_out_dest_data_out_191_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_67273_c_compmm_m3_out_dest_data_out_255_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_6482_c_compmm_m194_out_dest_data_out_64_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_65146_c_compmm_m130_out_dest_data_out_128_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_66210_c_compmm_m66_out_dest_data_out_192_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_67274_c_compmm_m2_out_dest_data_out_256_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6425_c_compmm_m251_out_dest_data_out_7_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6589_c_compmm_m187_out_dest_data_out_71_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_66153_c_compmm_m123_out_dest_data_out_135_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_67217_c_compmm_m59_out_dest_data_out_199_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6426_c_compmm_m250_out_dest_data_out_8_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6590_c_compmm_m186_out_dest_data_out_72_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_66154_c_compmm_m122_out_dest_data_out_136_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_67218_c_compmm_m58_out_dest_data_out_200_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6427_c_compmm_m249_out_dest_data_out_9_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6591_c_compmm_m185_out_dest_data_out_73_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_66155_c_compmm_m121_out_dest_data_out_137_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_67219_c_compmm_m57_out_dest_data_out_201_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6428_c_compmm_m248_out_dest_data_out_10_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6592_c_compmm_m184_out_dest_data_out_74_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_66156_c_compmm_m120_out_dest_data_out_138_0;
    wire [15:0] i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_67220_c_compmm_m56_out_dest_data_out_202_0;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_a;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_b;
    logic [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_o;
    wire [33:0] i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q;
    wire [28:0] i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_select_28_b;
    wire [28:0] i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_join_q;
    wire [15:0] i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28_b;
    wire [33:0] i_unnamed_c_compmm_m1005_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1005_vt_select_20_b;
    wire [11:0] i_unnamed_c_compmm_m1007_vt_const_33_q;
    wire [33:0] i_unnamed_c_compmm_m1007_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1007_vt_select_21_b;
    wire [14:0] i_unnamed_c_compmm_m1009_vt_const_15_q;
    wire [15:0] i_unnamed_c_compmm_m1009_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1009_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1017_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1017_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1019_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1019_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1021_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1021_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1033_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1033_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1035_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1035_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1037_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1037_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1045_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1045_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1047_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1047_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1049_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1049_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1061_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1061_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1063_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1063_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1065_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1065_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1073_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1073_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1075_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1075_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1077_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1077_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1089_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1089_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1091_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1091_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1093_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1093_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1101_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1101_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1103_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1103_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1105_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1105_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1117_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1117_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1119_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1119_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1121_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1121_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1129_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1129_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1131_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1131_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1133_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1133_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1145_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1145_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1147_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1147_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1149_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1149_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1158_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1158_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1160_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1160_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1162_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1162_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1174_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1174_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1176_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1176_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1178_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1178_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1186_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1186_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1188_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1188_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1190_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1190_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1202_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1202_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1204_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1204_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1206_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1206_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1214_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1214_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1216_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1216_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1218_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1218_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1230_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1230_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1232_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1232_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1234_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1234_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1242_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1242_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1244_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1244_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1246_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1246_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1258_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1258_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1260_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1260_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1262_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1262_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1270_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1270_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1272_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1272_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1274_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1274_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1286_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1286_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1288_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1288_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1290_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1290_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1298_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1298_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1300_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1300_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1302_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1302_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1314_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1314_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1316_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1316_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1318_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1318_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1326_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1326_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1328_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1328_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1330_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1330_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1342_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1342_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1344_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1344_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1346_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1346_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1354_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1354_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1356_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1356_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1358_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1358_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1370_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1370_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1372_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1372_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1374_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1374_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1382_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1382_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1384_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1384_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1386_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1386_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1398_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1398_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1400_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1400_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1402_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1402_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1410_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1410_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1412_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1412_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1414_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1414_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1426_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1426_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1428_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1428_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1430_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1430_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1438_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1438_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1440_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1440_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1442_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1442_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1454_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1454_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1456_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1456_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1458_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1458_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1466_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1466_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1468_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1468_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1470_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1470_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1482_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1482_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1484_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1484_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1486_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1486_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1494_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1494_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1496_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1496_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1498_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1498_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1510_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1510_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1512_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1512_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1514_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1514_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1522_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1522_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1524_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1524_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1526_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1526_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1538_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1538_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1540_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1540_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1542_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1542_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1550_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1550_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1552_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1552_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1554_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1554_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1566_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1566_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1568_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1568_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1570_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1570_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1578_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1578_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1580_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1580_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1582_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1582_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1594_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1594_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1596_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1596_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1598_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1598_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1606_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1606_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1608_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1608_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1610_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1610_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1622_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1622_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1624_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1624_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1626_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1626_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1634_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1634_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1636_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1636_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1638_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1638_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1650_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1650_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1652_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1652_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1654_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1654_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1662_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1662_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1664_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1664_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1666_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1666_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1678_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1678_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1680_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1680_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1682_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1682_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1690_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1690_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1692_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1692_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1694_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1694_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1706_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1706_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1708_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1708_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1710_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1710_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1718_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1718_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1720_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1720_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1722_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1722_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1734_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1734_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1736_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1736_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1738_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1738_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1746_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1746_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1748_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1748_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1750_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1750_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1762_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1762_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1764_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1764_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1766_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1766_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1774_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1774_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1776_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1776_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1778_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1778_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1790_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1790_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1792_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1792_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1794_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1794_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1802_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1802_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1804_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1804_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1806_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1806_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1818_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1818_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1820_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1820_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1822_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1822_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1830_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1830_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1832_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1832_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1834_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1834_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1846_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1846_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1848_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1848_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1850_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1850_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1858_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1858_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1860_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1860_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1862_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1862_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1874_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1874_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1876_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1876_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1878_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1878_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1886_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1886_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1888_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1888_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1890_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1890_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1902_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1902_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1904_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1904_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1906_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1906_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1914_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1914_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1916_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1916_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1918_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1918_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1930_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1930_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1932_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1932_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1934_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1934_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1942_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1942_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1944_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1944_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1946_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1946_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1958_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1958_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1960_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1960_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1962_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1962_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1970_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1970_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1972_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1972_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1974_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1974_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1986_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1986_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m1988_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m1988_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m1990_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m1990_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m1998_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m1998_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2000_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2000_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2002_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2002_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2014_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2014_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2016_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2016_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2018_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2018_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2026_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2026_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2028_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2028_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2030_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2030_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2042_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2042_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2044_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2044_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2046_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2046_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2055_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2055_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2057_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2057_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2059_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2059_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2071_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2071_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2073_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2073_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2075_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2075_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2083_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2083_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2085_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2085_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2087_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2087_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2099_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2099_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2101_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2101_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2103_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2103_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2111_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2111_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2113_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2113_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2115_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2115_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2127_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2127_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2129_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2129_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2131_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2131_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2139_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2139_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2141_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2141_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2143_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2143_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2155_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2155_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2157_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2157_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2159_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2159_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2167_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2167_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2169_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2169_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2171_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2171_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2183_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2183_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2185_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2185_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2187_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2187_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2195_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2195_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2197_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2197_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2199_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2199_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2211_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2211_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2213_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2213_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2215_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2215_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2223_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2223_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2225_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2225_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2227_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2227_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2239_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2239_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2241_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2241_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2243_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2243_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2251_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2251_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2253_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2253_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2255_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2255_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2267_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2267_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2269_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2269_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2271_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2271_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2279_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2279_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2281_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2281_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2283_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2283_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2295_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2295_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2297_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2297_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2299_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2299_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2307_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2307_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2309_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2309_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2311_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2311_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2323_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2323_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2325_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2325_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2327_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2327_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2335_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2335_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2337_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2337_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2339_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2339_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2351_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2351_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2353_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2353_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2355_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2355_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2363_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2363_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2365_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2365_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2367_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2367_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2379_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2379_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2381_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2381_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2383_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2383_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2391_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2391_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2393_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2393_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2395_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2395_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2407_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2407_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2409_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2409_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2411_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2411_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2419_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2419_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2421_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2421_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2423_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2423_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2435_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2435_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2437_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2437_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2439_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2439_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2447_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2447_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2449_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2449_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2451_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2451_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2463_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2463_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2465_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2465_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2467_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2467_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2475_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2475_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2477_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2477_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2479_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2479_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2491_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2491_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2493_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2493_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2495_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2495_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2503_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2503_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2505_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2505_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2507_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2507_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2519_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2519_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2521_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2521_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2523_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2523_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2531_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2531_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2533_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2533_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2535_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2535_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2547_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2547_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2549_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2549_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2551_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2551_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2559_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2559_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2561_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2561_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2563_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2563_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2575_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2575_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2577_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2577_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2579_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2579_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2587_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2587_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2589_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2589_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2591_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2591_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2603_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2603_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2605_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2605_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2607_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2607_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2615_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2615_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2617_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2617_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2619_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2619_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2631_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2631_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2633_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2633_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2635_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2635_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m263_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m263_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2643_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2643_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2645_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2645_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2647_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2647_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2659_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2659_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m265_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m265_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m2661_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2661_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2663_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2663_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2671_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2671_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2673_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2673_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2675_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2675_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m267_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m267_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2687_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2687_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2689_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2689_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2691_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2691_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2699_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2699_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2701_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2701_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2703_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2703_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2715_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2715_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2717_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2717_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2719_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2719_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2727_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2727_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2729_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2729_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2731_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2731_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2743_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2743_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2745_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2745_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2747_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2747_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2755_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2755_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2757_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2757_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2759_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2759_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2771_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2771_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2773_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2773_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2775_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2775_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m277_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m277_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2783_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2783_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2785_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2785_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2787_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2787_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2799_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2799_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m279_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m279_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m2801_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2801_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2803_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2803_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2811_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2811_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2813_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2813_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2815_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2815_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m281_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m281_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2827_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2827_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2829_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2829_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2831_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2831_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2839_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2839_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2841_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2841_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2843_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2843_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2855_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2855_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2857_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2857_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2859_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2859_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2867_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2867_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2869_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2869_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2871_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2871_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2883_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2883_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2885_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2885_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2887_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2887_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2895_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2895_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2897_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2897_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2899_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2899_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m289_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m289_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2911_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2911_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2913_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2913_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2915_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2915_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m291_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m291_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m2923_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2923_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2925_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2925_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2927_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2927_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2939_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2939_vt_select_20_b;
    wire [15:0] i_unnamed_c_compmm_m293_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m293_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2941_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2941_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2943_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2943_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2952_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2952_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2954_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2954_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2956_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2956_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2968_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2968_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2970_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2970_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2972_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2972_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2980_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2980_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2982_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2982_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m2984_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m2984_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m2996_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m2996_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m2998_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m2998_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3000_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3000_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3008_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3008_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3010_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3010_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3012_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3012_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3024_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3024_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3026_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3026_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3028_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3028_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3036_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3036_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3038_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3038_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3040_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3040_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3052_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3052_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3054_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3054_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3056_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3056_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m305_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m305_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3064_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3064_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3066_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3066_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3068_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3068_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m307_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m307_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m3080_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3080_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3082_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3082_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3084_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3084_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3092_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3092_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3094_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3094_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3096_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3096_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m309_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m309_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3108_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3108_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3110_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3110_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3112_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3112_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3120_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3120_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3122_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3122_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3124_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3124_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3136_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3136_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3138_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3138_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3140_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3140_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3148_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3148_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3150_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3150_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3152_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3152_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3164_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3164_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3166_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3166_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3168_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3168_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3176_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3176_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3178_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3178_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m317_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m317_vt_select_20_b;
    wire [15:0] i_unnamed_c_compmm_m3180_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3180_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3192_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3192_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3194_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3194_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3196_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3196_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m319_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m319_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m3204_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3204_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3206_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3206_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3208_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3208_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m321_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m321_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3220_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3220_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3222_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3222_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3224_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3224_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3232_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3232_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3234_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3234_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3236_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3236_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3248_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3248_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3250_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3250_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3252_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3252_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3260_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3260_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3262_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3262_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3264_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3264_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3276_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3276_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3278_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3278_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3280_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3280_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3288_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3288_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3290_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3290_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3292_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3292_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3304_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3304_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3306_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3306_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3308_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3308_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3316_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3316_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3318_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3318_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3320_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3320_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3332_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3332_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3334_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3334_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3336_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3336_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m333_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m333_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3344_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3344_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3346_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3346_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3348_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3348_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m335_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m335_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m3360_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3360_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3362_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3362_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3364_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3364_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3372_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3372_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3374_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3374_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3376_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3376_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m337_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m337_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3388_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3388_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3390_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3390_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3392_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3392_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3400_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3400_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3402_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3402_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3404_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3404_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3416_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3416_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3418_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3418_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3420_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3420_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3428_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3428_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3430_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3430_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3432_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3432_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3444_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3444_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3446_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3446_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3448_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3448_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3456_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3456_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3458_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3458_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m345_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m345_vt_select_20_b;
    wire [15:0] i_unnamed_c_compmm_m3460_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3460_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3472_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3472_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3474_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3474_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3476_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3476_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m347_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m347_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m3484_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3484_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3486_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3486_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3488_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3488_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m349_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m349_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3500_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3500_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3502_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3502_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3504_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3504_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3512_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3512_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3514_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3514_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3516_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3516_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3528_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3528_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3530_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3530_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3532_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3532_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3540_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3540_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3542_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3542_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3544_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3544_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3556_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3556_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3558_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3558_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3560_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3560_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3568_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3568_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3570_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3570_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3572_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3572_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3584_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3584_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3586_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3586_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3588_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3588_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3596_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3596_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3598_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3598_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3600_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3600_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3612_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3612_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3614_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3614_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3616_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3616_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m361_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m361_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3624_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3624_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3626_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3626_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3628_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3628_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m363_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m363_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m3640_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3640_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3642_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3642_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3644_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3644_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3652_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3652_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3654_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3654_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3656_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3656_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m365_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m365_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3668_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3668_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3670_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3670_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3672_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3672_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3680_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3680_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3682_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3682_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3684_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3684_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3696_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3696_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3698_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3698_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3700_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3700_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3708_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3708_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3710_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3710_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3712_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3712_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3724_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3724_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3726_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3726_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3728_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3728_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3736_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3736_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3738_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3738_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m373_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m373_vt_select_20_b;
    wire [15:0] i_unnamed_c_compmm_m3740_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3740_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3752_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3752_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3754_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3754_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3756_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3756_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m375_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m375_vt_select_21_b;
    wire [33:0] i_unnamed_c_compmm_m3764_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3764_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3766_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3766_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3768_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3768_vt_select_0_b;
    wire [15:0] i_unnamed_c_compmm_m377_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m377_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3780_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3780_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3782_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3782_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3784_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3784_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3792_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3792_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3794_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3794_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3796_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3796_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3808_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3808_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3810_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3810_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3812_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3812_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3820_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3820_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3822_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3822_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3824_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3824_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m3836_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m3836_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m3838_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m3838_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m3840_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m3840_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m389_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m389_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m391_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m391_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m393_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m393_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m401_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m401_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m403_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m403_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m405_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m405_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m417_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m417_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m419_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m419_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m421_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m421_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m429_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m429_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m431_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m431_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m433_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m433_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m445_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m445_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m447_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m447_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m449_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m449_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m457_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m457_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m459_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m459_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m461_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m461_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m473_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m473_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m475_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m475_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m477_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m477_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m485_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m485_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m487_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m487_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m489_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m489_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m501_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m501_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m503_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m503_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m505_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m505_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m513_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m513_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m515_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m515_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m517_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m517_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m529_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m529_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m531_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m531_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m533_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m533_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m541_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m541_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m543_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m543_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m545_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m545_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m557_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m557_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m559_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m559_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m561_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m561_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m569_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m569_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m571_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m571_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m573_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m573_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m585_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m585_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m587_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m587_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m589_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m589_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m597_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m597_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m599_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m599_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m601_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m601_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m613_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m613_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m615_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m615_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m617_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m617_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m625_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m625_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m627_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m627_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m629_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m629_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m641_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m641_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m643_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m643_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m645_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m645_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m653_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m653_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m655_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m655_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m657_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m657_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m669_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m669_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m671_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m671_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m673_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m673_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m681_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m681_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m683_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m683_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m685_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m685_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m697_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m697_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m699_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m699_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m701_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m701_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m709_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m709_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m711_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m711_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m713_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m713_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m725_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m725_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m727_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m727_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m729_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m729_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m737_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m737_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m739_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m739_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m741_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m741_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m753_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m753_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m755_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m755_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m757_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m757_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m765_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m765_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m767_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m767_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m769_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m769_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m781_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m781_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m783_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m783_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m785_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m785_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m793_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m793_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m795_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m795_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m797_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m797_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m809_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m809_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m811_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m811_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m813_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m813_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m821_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m821_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m823_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m823_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m825_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m825_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m837_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m837_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m839_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m839_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m841_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m841_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m849_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m849_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m851_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m851_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m853_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m853_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m865_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m865_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m867_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m867_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m869_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m869_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m877_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m877_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m879_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m879_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m881_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m881_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m893_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m893_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m895_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m895_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m897_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m897_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m905_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m905_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m907_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m907_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m909_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m909_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m921_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m921_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m923_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m923_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m925_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m925_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m933_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m933_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m935_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m935_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m937_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m937_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m949_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m949_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m951_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m951_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m953_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m953_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m961_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m961_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m963_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m963_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m965_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m965_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m977_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m977_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m979_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m979_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m981_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m981_vt_select_0_b;
    wire [33:0] i_unnamed_c_compmm_m989_vt_join_q;
    wire [20:0] i_unnamed_c_compmm_m989_vt_select_20_b;
    wire [33:0] i_unnamed_c_compmm_m991_vt_join_q;
    wire [21:0] i_unnamed_c_compmm_m991_vt_select_21_b;
    wire [15:0] i_unnamed_c_compmm_m993_vt_join_q;
    wire [0:0] i_unnamed_c_compmm_m993_vt_select_0_b;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg0_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg1_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg2_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg3_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg4_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg5_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg6_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg7_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg8_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg9_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg10_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg11_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg12_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg13_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg14_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg15_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg16_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg17_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg18_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg19_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg20_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg21_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg22_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg23_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg24_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg25_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg26_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg27_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg28_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg29_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg30_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg31_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg32_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg33_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg34_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg35_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg36_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg37_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg38_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg39_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg40_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg41_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg42_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg43_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg44_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg45_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg46_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg47_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg48_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg49_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg50_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg51_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg52_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg53_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg54_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg55_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg56_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg57_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg58_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg59_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg60_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg61_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg62_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg63_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg64_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg65_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg66_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg67_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg68_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg69_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg70_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg71_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg72_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg73_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg74_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg75_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg76_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg77_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg78_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg79_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg80_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg81_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg82_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg83_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg84_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg85_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg86_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg87_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg88_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg89_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg90_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg91_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg92_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg93_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg94_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg95_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg96_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg97_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg98_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg99_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg100_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg101_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg102_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg103_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg104_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg105_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg106_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg107_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg108_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg109_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg110_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg111_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg112_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg113_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg114_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg115_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg116_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg117_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg118_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg119_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg120_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg121_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg122_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg123_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg124_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg125_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg126_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg127_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg128_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg129_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg130_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg131_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg132_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg133_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg134_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg135_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg136_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg137_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg138_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg139_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg140_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg141_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg142_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg143_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg144_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg145_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg146_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg147_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg148_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg149_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg150_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg151_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg152_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg153_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg154_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg155_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg156_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg157_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg158_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg159_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg160_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg161_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg162_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg163_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg164_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg165_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg166_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg167_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg168_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg169_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg170_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg171_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg172_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg173_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg174_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg175_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg176_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg177_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg178_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg179_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg180_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg181_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg182_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg183_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg184_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg185_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg186_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg187_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg188_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg189_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg190_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg191_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg192_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg193_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg194_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg195_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg196_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg197_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg198_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg199_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg200_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg201_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg202_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg203_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg204_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg205_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg206_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg207_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg208_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg209_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg210_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg211_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg212_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg213_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg214_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg215_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg216_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg217_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg218_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg219_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg220_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg221_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg222_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg223_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg224_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg225_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg226_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg227_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg228_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg229_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg230_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg231_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg232_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg233_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg234_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg235_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg236_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg237_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg238_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg239_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg240_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg241_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg242_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg243_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg244_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg245_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg246_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg247_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg248_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg249_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg250_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg251_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg252_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg253_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg254_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg255_q;
    (* preserve_syn_only *) reg [0:0] valid_fanout_reg256_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15855_dupName_0_i_unnamed_c_compmm_m0_shift_x_b;
    wire [3:0] rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
    wire [33:0] rightShiftStage0Idx1_uid15857_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15860_dupName_0_i_unnamed_c_compmm_m0_shift_x_b;
    wire [7:0] rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
    wire [33:0] rightShiftStage1Idx1_uid15862_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15868_dupName_1_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15870_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15873_dupName_1_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15875_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15878_dupName_1_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15880_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15886_dupName_2_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15888_dupName_2_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15891_dupName_2_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15893_dupName_2_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15899_dupName_3_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15901_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15904_dupName_3_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15906_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15909_dupName_3_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15911_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15917_dupName_4_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15919_dupName_4_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15922_dupName_4_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15924_dupName_4_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15930_dupName_5_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15932_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15935_dupName_5_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15937_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15940_dupName_5_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15942_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15948_dupName_6_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15950_dupName_6_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15953_dupName_6_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15955_dupName_6_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15961_dupName_7_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15963_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15966_dupName_7_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15968_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid15971_dupName_7_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid15973_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid15979_dupName_8_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15981_dupName_8_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid15984_dupName_8_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15986_dupName_8_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid15992_dupName_9_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid15994_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid15997_dupName_9_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid15999_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16002_dupName_9_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16004_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16010_dupName_10_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16012_dupName_10_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16015_dupName_10_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16017_dupName_10_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16023_dupName_11_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16025_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16028_dupName_11_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16030_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16033_dupName_11_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16035_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16041_dupName_12_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16043_dupName_12_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16046_dupName_12_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16048_dupName_12_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16054_dupName_13_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16056_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16059_dupName_13_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16061_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16064_dupName_13_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16066_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16072_dupName_14_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16074_dupName_14_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16077_dupName_14_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16079_dupName_14_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16085_dupName_15_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16087_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16090_dupName_15_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16092_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16095_dupName_15_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16097_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16103_dupName_16_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16105_dupName_16_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16108_dupName_16_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16110_dupName_16_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16116_dupName_17_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16118_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16121_dupName_17_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16123_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16126_dupName_17_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16128_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16134_dupName_18_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16136_dupName_18_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16139_dupName_18_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16141_dupName_18_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16147_dupName_19_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16149_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16152_dupName_19_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16154_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16157_dupName_19_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16159_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16165_dupName_20_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16167_dupName_20_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16170_dupName_20_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16172_dupName_20_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16178_dupName_21_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16180_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16183_dupName_21_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16185_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16188_dupName_21_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16190_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16196_dupName_22_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16198_dupName_22_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16201_dupName_22_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16203_dupName_22_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16209_dupName_23_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16211_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16214_dupName_23_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16216_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16219_dupName_23_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16221_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16227_dupName_24_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16229_dupName_24_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16232_dupName_24_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16234_dupName_24_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16240_dupName_25_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16242_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16245_dupName_25_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16247_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16250_dupName_25_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16252_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16258_dupName_26_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16260_dupName_26_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16263_dupName_26_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16265_dupName_26_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16271_dupName_27_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16273_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16276_dupName_27_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16278_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16281_dupName_27_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16283_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16289_dupName_28_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16291_dupName_28_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16294_dupName_28_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16296_dupName_28_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16302_dupName_29_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16304_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16307_dupName_29_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16309_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16312_dupName_29_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16314_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16320_dupName_30_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16322_dupName_30_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16325_dupName_30_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16327_dupName_30_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16333_dupName_31_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16335_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16338_dupName_31_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16340_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16343_dupName_31_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16345_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16351_dupName_32_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16353_dupName_32_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16356_dupName_32_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16358_dupName_32_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16364_dupName_33_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16366_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16369_dupName_33_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16371_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16374_dupName_33_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16376_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16382_dupName_34_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16384_dupName_34_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16387_dupName_34_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16389_dupName_34_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16395_dupName_35_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16397_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16400_dupName_35_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16402_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16405_dupName_35_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16407_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16413_dupName_36_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16415_dupName_36_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16418_dupName_36_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16420_dupName_36_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16426_dupName_37_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16428_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16431_dupName_37_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16433_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16436_dupName_37_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16438_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16444_dupName_38_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16446_dupName_38_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16449_dupName_38_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16451_dupName_38_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16457_dupName_39_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16459_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16462_dupName_39_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16464_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16467_dupName_39_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16469_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16475_dupName_40_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16477_dupName_40_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16480_dupName_40_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16482_dupName_40_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16488_dupName_41_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16490_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16493_dupName_41_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16495_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16498_dupName_41_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16500_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16506_dupName_42_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16508_dupName_42_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16511_dupName_42_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16513_dupName_42_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16519_dupName_43_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16521_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16524_dupName_43_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16526_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16529_dupName_43_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16531_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16537_dupName_44_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16539_dupName_44_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16542_dupName_44_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16544_dupName_44_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16550_dupName_45_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16552_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16555_dupName_45_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16557_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16560_dupName_45_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16562_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16568_dupName_46_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16570_dupName_46_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16573_dupName_46_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16575_dupName_46_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16581_dupName_47_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16583_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16586_dupName_47_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16588_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16591_dupName_47_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16593_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16599_dupName_48_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16601_dupName_48_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16604_dupName_48_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16606_dupName_48_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16612_dupName_49_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16614_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16617_dupName_49_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16619_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16622_dupName_49_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16624_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16630_dupName_50_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16632_dupName_50_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16635_dupName_50_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16637_dupName_50_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16643_dupName_51_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16645_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16648_dupName_51_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16650_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16653_dupName_51_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16655_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16661_dupName_52_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16663_dupName_52_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16666_dupName_52_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16668_dupName_52_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16674_dupName_53_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16676_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16679_dupName_53_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16681_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16684_dupName_53_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16686_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16692_dupName_54_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16694_dupName_54_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16697_dupName_54_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16699_dupName_54_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16705_dupName_55_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16707_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16710_dupName_55_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16712_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16715_dupName_55_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16717_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16723_dupName_56_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16725_dupName_56_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16728_dupName_56_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16730_dupName_56_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16736_dupName_57_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16738_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16741_dupName_57_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16743_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16746_dupName_57_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16748_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16754_dupName_58_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16756_dupName_58_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16759_dupName_58_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16761_dupName_58_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16767_dupName_59_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16769_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16772_dupName_59_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16774_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16777_dupName_59_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16779_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16785_dupName_60_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16787_dupName_60_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16790_dupName_60_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16792_dupName_60_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16798_dupName_61_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16800_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16803_dupName_61_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16805_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16808_dupName_61_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16810_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16816_dupName_62_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16818_dupName_62_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16821_dupName_62_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16823_dupName_62_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16829_dupName_63_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16831_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16834_dupName_63_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16836_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16839_dupName_63_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16841_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16847_dupName_64_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16849_dupName_64_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16852_dupName_64_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16854_dupName_64_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16860_dupName_65_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16862_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16865_dupName_65_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16867_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16870_dupName_65_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16872_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16878_dupName_66_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16880_dupName_66_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16883_dupName_66_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16885_dupName_66_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16891_dupName_67_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16893_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16896_dupName_67_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16898_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16901_dupName_67_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16903_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16909_dupName_68_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16911_dupName_68_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16914_dupName_68_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16916_dupName_68_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16922_dupName_69_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16924_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16927_dupName_69_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16929_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16932_dupName_69_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16934_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16940_dupName_70_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16942_dupName_70_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16945_dupName_70_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16947_dupName_70_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16953_dupName_71_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16955_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16958_dupName_71_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16960_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16963_dupName_71_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16965_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid16971_dupName_72_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16973_dupName_72_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid16976_dupName_72_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16978_dupName_72_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid16984_dupName_73_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid16986_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid16989_dupName_73_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid16991_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid16994_dupName_73_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid16996_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17002_dupName_74_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17004_dupName_74_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17007_dupName_74_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17009_dupName_74_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17015_dupName_75_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17017_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17020_dupName_75_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17022_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17025_dupName_75_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17027_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17033_dupName_76_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17035_dupName_76_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17038_dupName_76_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17040_dupName_76_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17046_dupName_77_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17048_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17051_dupName_77_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17053_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17056_dupName_77_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17058_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17064_dupName_78_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17066_dupName_78_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17069_dupName_78_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17071_dupName_78_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17077_dupName_79_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17079_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17082_dupName_79_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17084_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17087_dupName_79_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17089_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17095_dupName_80_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17097_dupName_80_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17100_dupName_80_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17102_dupName_80_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17108_dupName_81_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17110_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17113_dupName_81_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17115_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17118_dupName_81_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17120_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17126_dupName_82_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17128_dupName_82_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17131_dupName_82_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17133_dupName_82_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17139_dupName_83_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17141_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17144_dupName_83_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17146_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17149_dupName_83_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17151_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17157_dupName_84_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17159_dupName_84_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17162_dupName_84_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17164_dupName_84_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17170_dupName_85_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17172_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17175_dupName_85_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17177_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17180_dupName_85_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17182_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17188_dupName_86_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17190_dupName_86_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17193_dupName_86_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17195_dupName_86_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17201_dupName_87_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17203_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17206_dupName_87_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17208_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17211_dupName_87_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17213_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17219_dupName_88_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17221_dupName_88_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17224_dupName_88_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17226_dupName_88_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17232_dupName_89_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17234_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17237_dupName_89_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17239_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17242_dupName_89_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17244_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17250_dupName_90_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17252_dupName_90_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17255_dupName_90_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17257_dupName_90_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17263_dupName_91_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17265_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17268_dupName_91_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17270_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17273_dupName_91_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17275_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17281_dupName_92_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17283_dupName_92_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17286_dupName_92_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17288_dupName_92_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17294_dupName_93_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17296_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17299_dupName_93_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17301_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17304_dupName_93_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17306_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17312_dupName_94_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17314_dupName_94_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17317_dupName_94_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17319_dupName_94_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17325_dupName_95_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17327_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17330_dupName_95_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17332_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17335_dupName_95_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17337_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17343_dupName_96_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17345_dupName_96_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17348_dupName_96_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17350_dupName_96_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17356_dupName_97_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17358_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17361_dupName_97_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17363_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17366_dupName_97_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17368_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17374_dupName_98_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17376_dupName_98_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17379_dupName_98_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17381_dupName_98_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17387_dupName_99_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17389_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17392_dupName_99_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17394_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17397_dupName_99_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17399_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17405_dupName_100_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17407_dupName_100_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17410_dupName_100_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17412_dupName_100_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17418_dupName_101_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17420_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17423_dupName_101_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17425_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17428_dupName_101_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17430_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17436_dupName_102_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17438_dupName_102_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17441_dupName_102_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17443_dupName_102_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17449_dupName_103_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17451_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17454_dupName_103_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17456_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17459_dupName_103_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17461_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17467_dupName_104_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17469_dupName_104_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17472_dupName_104_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17474_dupName_104_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17480_dupName_105_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17482_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17485_dupName_105_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17487_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17490_dupName_105_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17492_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17498_dupName_106_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17500_dupName_106_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17503_dupName_106_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17505_dupName_106_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17511_dupName_107_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17513_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17516_dupName_107_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17518_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17521_dupName_107_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17523_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17529_dupName_108_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17531_dupName_108_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17534_dupName_108_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17536_dupName_108_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17542_dupName_109_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17544_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17547_dupName_109_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17549_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17552_dupName_109_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17554_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17560_dupName_110_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17562_dupName_110_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17565_dupName_110_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17567_dupName_110_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17573_dupName_111_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17575_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17578_dupName_111_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17580_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17583_dupName_111_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17585_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17591_dupName_112_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17593_dupName_112_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17596_dupName_112_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17598_dupName_112_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17604_dupName_113_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17606_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17609_dupName_113_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17611_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17614_dupName_113_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17616_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17622_dupName_114_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17624_dupName_114_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17627_dupName_114_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17629_dupName_114_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17635_dupName_115_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17637_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17640_dupName_115_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17642_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17645_dupName_115_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17647_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17653_dupName_116_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17655_dupName_116_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17658_dupName_116_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17660_dupName_116_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17666_dupName_117_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17668_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17671_dupName_117_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17673_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17676_dupName_117_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17678_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17684_dupName_118_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17686_dupName_118_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17689_dupName_118_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17691_dupName_118_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17697_dupName_119_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17699_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17702_dupName_119_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17704_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17707_dupName_119_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17709_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17715_dupName_120_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17717_dupName_120_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17720_dupName_120_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17722_dupName_120_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17728_dupName_121_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17730_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17733_dupName_121_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17735_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17738_dupName_121_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17740_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17746_dupName_122_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17748_dupName_122_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17751_dupName_122_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17753_dupName_122_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17759_dupName_123_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17761_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17764_dupName_123_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17766_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17769_dupName_123_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17771_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17777_dupName_124_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17779_dupName_124_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17782_dupName_124_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17784_dupName_124_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17790_dupName_125_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17792_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17795_dupName_125_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17797_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17800_dupName_125_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17802_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17808_dupName_126_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17810_dupName_126_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17813_dupName_126_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17815_dupName_126_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17821_dupName_127_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17823_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17826_dupName_127_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17828_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17831_dupName_127_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17833_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17839_dupName_128_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17841_dupName_128_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17844_dupName_128_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17846_dupName_128_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17852_dupName_129_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17854_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17857_dupName_129_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17859_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17862_dupName_129_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17864_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17870_dupName_130_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17872_dupName_130_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17875_dupName_130_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17877_dupName_130_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17883_dupName_131_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17885_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17888_dupName_131_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17890_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17893_dupName_131_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17895_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17901_dupName_132_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17903_dupName_132_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17906_dupName_132_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17908_dupName_132_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17914_dupName_133_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17916_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17919_dupName_133_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17921_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17924_dupName_133_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17926_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17932_dupName_134_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17934_dupName_134_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17937_dupName_134_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17939_dupName_134_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17945_dupName_135_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17947_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17950_dupName_135_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17952_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17955_dupName_135_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17957_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17963_dupName_136_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17965_dupName_136_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17968_dupName_136_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17970_dupName_136_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid17976_dupName_137_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17978_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid17981_dupName_137_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid17983_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid17986_dupName_137_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid17988_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid17994_dupName_138_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid17996_dupName_138_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid17999_dupName_138_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18001_dupName_138_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18007_dupName_139_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18009_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18012_dupName_139_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18014_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18017_dupName_139_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18019_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18025_dupName_140_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18027_dupName_140_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18030_dupName_140_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18032_dupName_140_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18038_dupName_141_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18040_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18043_dupName_141_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18045_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18048_dupName_141_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18050_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18056_dupName_142_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18058_dupName_142_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18061_dupName_142_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18063_dupName_142_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18069_dupName_143_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18071_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18074_dupName_143_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18076_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18079_dupName_143_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18081_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18087_dupName_144_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18089_dupName_144_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18092_dupName_144_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18094_dupName_144_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18100_dupName_145_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18102_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18105_dupName_145_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18107_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18110_dupName_145_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18112_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18118_dupName_146_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18120_dupName_146_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18123_dupName_146_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18125_dupName_146_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18131_dupName_147_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18133_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18136_dupName_147_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18138_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18141_dupName_147_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18143_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18149_dupName_148_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18151_dupName_148_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18154_dupName_148_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18156_dupName_148_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18162_dupName_149_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18164_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18167_dupName_149_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18169_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18172_dupName_149_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18174_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18180_dupName_150_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18182_dupName_150_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18185_dupName_150_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18187_dupName_150_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18193_dupName_151_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18195_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18198_dupName_151_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18200_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18203_dupName_151_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18205_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18211_dupName_152_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18213_dupName_152_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18216_dupName_152_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18218_dupName_152_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18224_dupName_153_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18226_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18229_dupName_153_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18231_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18234_dupName_153_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18236_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18242_dupName_154_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18244_dupName_154_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18247_dupName_154_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18249_dupName_154_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18255_dupName_155_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18257_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18260_dupName_155_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18262_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18265_dupName_155_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18267_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18273_dupName_156_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18275_dupName_156_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18278_dupName_156_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18280_dupName_156_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18286_dupName_157_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18288_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18291_dupName_157_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18293_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18296_dupName_157_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18298_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18304_dupName_158_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18306_dupName_158_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18309_dupName_158_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18311_dupName_158_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18317_dupName_159_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18319_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18322_dupName_159_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18324_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18327_dupName_159_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18329_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18335_dupName_160_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18337_dupName_160_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18340_dupName_160_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18342_dupName_160_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18348_dupName_161_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18350_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18353_dupName_161_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18355_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18358_dupName_161_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18360_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18366_dupName_162_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18368_dupName_162_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18371_dupName_162_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18373_dupName_162_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18379_dupName_163_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18381_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18384_dupName_163_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18386_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18389_dupName_163_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18391_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18397_dupName_164_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18399_dupName_164_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18402_dupName_164_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18404_dupName_164_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18410_dupName_165_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18412_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18415_dupName_165_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18417_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18420_dupName_165_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18422_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18428_dupName_166_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18430_dupName_166_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18433_dupName_166_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18435_dupName_166_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18441_dupName_167_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18443_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18446_dupName_167_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18448_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18451_dupName_167_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18453_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18459_dupName_168_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18461_dupName_168_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18464_dupName_168_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18466_dupName_168_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18472_dupName_169_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18474_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18477_dupName_169_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18479_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18482_dupName_169_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18484_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18490_dupName_170_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18492_dupName_170_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18495_dupName_170_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18497_dupName_170_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18503_dupName_171_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18505_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18508_dupName_171_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18510_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18513_dupName_171_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18515_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18521_dupName_172_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18523_dupName_172_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18526_dupName_172_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18528_dupName_172_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18534_dupName_173_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18536_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18539_dupName_173_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18541_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18544_dupName_173_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18546_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18552_dupName_174_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18554_dupName_174_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18557_dupName_174_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18559_dupName_174_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18565_dupName_175_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18567_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18570_dupName_175_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18572_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18575_dupName_175_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18577_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18583_dupName_176_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18585_dupName_176_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18588_dupName_176_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18590_dupName_176_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18596_dupName_177_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18598_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18601_dupName_177_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18603_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18606_dupName_177_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18608_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18614_dupName_178_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18616_dupName_178_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18619_dupName_178_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18621_dupName_178_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18627_dupName_179_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18629_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18632_dupName_179_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18634_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18637_dupName_179_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18639_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18645_dupName_180_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18647_dupName_180_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18650_dupName_180_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18652_dupName_180_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18658_dupName_181_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18660_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18663_dupName_181_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18665_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18668_dupName_181_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18670_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18676_dupName_182_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18678_dupName_182_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18681_dupName_182_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18683_dupName_182_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18689_dupName_183_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18691_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18694_dupName_183_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18696_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18699_dupName_183_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18701_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18707_dupName_184_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18709_dupName_184_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18712_dupName_184_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18714_dupName_184_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18720_dupName_185_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18722_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18725_dupName_185_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18727_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18730_dupName_185_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18732_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18738_dupName_186_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18740_dupName_186_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18743_dupName_186_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18745_dupName_186_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18751_dupName_187_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18753_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18756_dupName_187_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18758_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18761_dupName_187_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18763_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18769_dupName_188_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18771_dupName_188_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18774_dupName_188_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18776_dupName_188_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18782_dupName_189_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18784_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18787_dupName_189_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18789_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18792_dupName_189_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18794_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18800_dupName_190_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18802_dupName_190_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18805_dupName_190_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18807_dupName_190_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18813_dupName_191_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18815_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18818_dupName_191_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18820_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18823_dupName_191_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18825_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18831_dupName_192_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18833_dupName_192_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18836_dupName_192_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18838_dupName_192_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18844_dupName_193_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18846_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18849_dupName_193_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18851_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18854_dupName_193_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18856_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18862_dupName_194_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18864_dupName_194_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18867_dupName_194_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18869_dupName_194_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18875_dupName_195_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18877_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18880_dupName_195_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18882_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18885_dupName_195_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18887_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18893_dupName_196_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18895_dupName_196_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18898_dupName_196_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18900_dupName_196_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18906_dupName_197_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18908_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18911_dupName_197_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18913_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18916_dupName_197_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18918_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18924_dupName_198_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18926_dupName_198_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18929_dupName_198_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18931_dupName_198_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18937_dupName_199_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18939_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18942_dupName_199_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18944_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18947_dupName_199_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18949_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18955_dupName_200_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18957_dupName_200_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18960_dupName_200_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18962_dupName_200_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18968_dupName_201_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18970_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid18973_dupName_201_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18975_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid18978_dupName_201_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid18980_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid18986_dupName_202_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid18988_dupName_202_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid18991_dupName_202_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid18993_dupName_202_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid18999_dupName_203_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19001_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19004_dupName_203_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19006_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19009_dupName_203_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19011_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19017_dupName_204_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19019_dupName_204_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19022_dupName_204_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19024_dupName_204_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19030_dupName_205_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19032_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19035_dupName_205_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19037_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19040_dupName_205_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19042_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19048_dupName_206_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19050_dupName_206_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19053_dupName_206_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19055_dupName_206_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19061_dupName_207_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19063_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19066_dupName_207_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19068_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19071_dupName_207_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19073_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19079_dupName_208_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19081_dupName_208_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19084_dupName_208_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19086_dupName_208_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19092_dupName_209_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19094_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19097_dupName_209_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19099_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19102_dupName_209_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19104_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19110_dupName_210_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19112_dupName_210_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19115_dupName_210_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19117_dupName_210_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19123_dupName_211_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19125_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19128_dupName_211_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19130_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19133_dupName_211_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19135_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19141_dupName_212_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19143_dupName_212_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19146_dupName_212_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19148_dupName_212_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19154_dupName_213_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19156_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19159_dupName_213_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19161_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19164_dupName_213_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19166_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19172_dupName_214_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19174_dupName_214_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19177_dupName_214_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19179_dupName_214_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19185_dupName_215_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19187_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19190_dupName_215_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19192_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19195_dupName_215_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19197_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19203_dupName_216_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19205_dupName_216_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19208_dupName_216_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19210_dupName_216_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19216_dupName_217_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19218_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19221_dupName_217_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19223_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19226_dupName_217_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19228_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19234_dupName_218_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19236_dupName_218_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19239_dupName_218_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19241_dupName_218_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19247_dupName_219_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19249_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19252_dupName_219_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19254_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19257_dupName_219_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19259_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19265_dupName_220_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19267_dupName_220_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19270_dupName_220_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19272_dupName_220_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19278_dupName_221_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19280_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19283_dupName_221_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19285_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19288_dupName_221_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19290_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19296_dupName_222_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19298_dupName_222_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19301_dupName_222_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19303_dupName_222_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19309_dupName_223_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19311_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19314_dupName_223_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19316_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19319_dupName_223_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19321_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19327_dupName_224_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19329_dupName_224_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19332_dupName_224_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19334_dupName_224_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19340_dupName_225_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19342_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19345_dupName_225_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19347_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19350_dupName_225_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19352_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19358_dupName_226_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19360_dupName_226_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19363_dupName_226_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19365_dupName_226_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19371_dupName_227_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19373_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19376_dupName_227_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19378_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19381_dupName_227_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19383_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19389_dupName_228_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19391_dupName_228_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19394_dupName_228_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19396_dupName_228_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19402_dupName_229_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19404_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19407_dupName_229_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19409_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19412_dupName_229_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19414_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19420_dupName_230_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19422_dupName_230_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19425_dupName_230_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19427_dupName_230_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19433_dupName_231_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19435_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19438_dupName_231_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19440_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19443_dupName_231_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19445_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19451_dupName_232_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19453_dupName_232_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19456_dupName_232_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19458_dupName_232_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19464_dupName_233_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19466_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19469_dupName_233_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19471_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19474_dupName_233_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19476_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19482_dupName_234_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19484_dupName_234_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19487_dupName_234_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19489_dupName_234_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19495_dupName_235_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19497_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19500_dupName_235_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19502_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19505_dupName_235_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19507_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19513_dupName_236_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19515_dupName_236_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19518_dupName_236_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19520_dupName_236_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19526_dupName_237_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19528_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19531_dupName_237_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19533_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19536_dupName_237_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19538_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19544_dupName_238_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19546_dupName_238_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19549_dupName_238_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19551_dupName_238_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19557_dupName_239_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19559_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19562_dupName_239_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19564_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19567_dupName_239_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19569_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19575_dupName_240_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19577_dupName_240_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19580_dupName_240_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19582_dupName_240_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19588_dupName_241_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19590_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19593_dupName_241_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19595_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19598_dupName_241_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19600_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19606_dupName_242_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19608_dupName_242_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19611_dupName_242_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19613_dupName_242_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19619_dupName_243_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19621_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19624_dupName_243_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19626_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19629_dupName_243_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19631_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19637_dupName_244_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19639_dupName_244_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19642_dupName_244_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19644_dupName_244_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19650_dupName_245_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19652_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19655_dupName_245_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19657_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19660_dupName_245_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19662_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19668_dupName_246_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19670_dupName_246_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19673_dupName_246_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19675_dupName_246_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19681_dupName_247_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19683_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19686_dupName_247_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19688_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19691_dupName_247_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19693_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19699_dupName_248_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19701_dupName_248_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19704_dupName_248_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19706_dupName_248_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19712_dupName_249_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19714_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19717_dupName_249_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19719_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19722_dupName_249_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19724_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19730_dupName_250_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19732_dupName_250_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19735_dupName_250_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19737_dupName_250_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19743_dupName_251_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19745_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19748_dupName_251_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19750_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19753_dupName_251_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19755_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19761_dupName_252_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19763_dupName_252_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19766_dupName_252_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19768_dupName_252_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19774_dupName_253_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19776_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19779_dupName_253_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19781_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19784_dupName_253_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19786_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19792_dupName_254_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19794_dupName_254_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19797_dupName_254_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19799_dupName_254_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19805_dupName_255_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19807_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19810_dupName_255_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19812_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19815_dupName_255_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19817_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19823_dupName_256_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19825_dupName_256_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19828_dupName_256_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19830_dupName_256_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19836_dupName_257_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19838_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19841_dupName_257_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19843_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19846_dupName_257_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19848_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19854_dupName_258_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19856_dupName_258_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19859_dupName_258_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19861_dupName_258_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19867_dupName_259_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19869_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19872_dupName_259_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19874_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19877_dupName_259_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19879_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19885_dupName_260_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19887_dupName_260_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19890_dupName_260_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19892_dupName_260_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19898_dupName_261_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19900_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19903_dupName_261_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19905_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19908_dupName_261_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19910_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19916_dupName_262_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19918_dupName_262_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19921_dupName_262_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19923_dupName_262_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19929_dupName_263_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19931_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19934_dupName_263_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19936_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19939_dupName_263_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19941_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19947_dupName_264_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19949_dupName_264_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19952_dupName_264_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19954_dupName_264_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19960_dupName_265_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19962_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19965_dupName_265_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19967_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid19970_dupName_265_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid19972_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid19978_dupName_266_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19980_dupName_266_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid19983_dupName_266_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19985_dupName_266_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid19991_dupName_267_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid19993_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid19996_dupName_267_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid19998_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20001_dupName_267_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20003_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20009_dupName_268_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20011_dupName_268_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20014_dupName_268_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20016_dupName_268_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20022_dupName_269_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20024_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20027_dupName_269_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20029_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20032_dupName_269_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20034_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20040_dupName_270_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20042_dupName_270_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20045_dupName_270_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20047_dupName_270_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20053_dupName_271_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20055_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20058_dupName_271_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20060_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20063_dupName_271_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20065_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20071_dupName_272_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20073_dupName_272_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20076_dupName_272_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20078_dupName_272_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20084_dupName_273_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20086_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20089_dupName_273_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20091_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20094_dupName_273_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20096_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20102_dupName_274_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20104_dupName_274_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20107_dupName_274_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20109_dupName_274_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20115_dupName_275_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20117_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20120_dupName_275_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20122_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20125_dupName_275_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20127_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20133_dupName_276_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20135_dupName_276_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20138_dupName_276_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20140_dupName_276_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20146_dupName_277_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20148_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20151_dupName_277_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20153_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20156_dupName_277_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20158_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20164_dupName_278_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20166_dupName_278_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20169_dupName_278_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20171_dupName_278_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20177_dupName_279_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20179_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20182_dupName_279_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20184_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20187_dupName_279_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20189_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20195_dupName_280_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20197_dupName_280_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20200_dupName_280_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20202_dupName_280_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20208_dupName_281_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20210_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20213_dupName_281_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20215_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20218_dupName_281_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20220_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20226_dupName_282_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20228_dupName_282_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20231_dupName_282_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20233_dupName_282_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20239_dupName_283_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20241_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20244_dupName_283_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20246_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20249_dupName_283_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20251_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20257_dupName_284_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20259_dupName_284_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20262_dupName_284_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20264_dupName_284_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20270_dupName_285_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20272_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20275_dupName_285_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20277_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20280_dupName_285_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20282_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20288_dupName_286_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20290_dupName_286_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20293_dupName_286_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20295_dupName_286_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20301_dupName_287_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20303_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20306_dupName_287_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20308_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20311_dupName_287_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20313_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20319_dupName_288_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20321_dupName_288_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20324_dupName_288_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20326_dupName_288_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20332_dupName_289_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20334_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20337_dupName_289_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20339_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20342_dupName_289_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20344_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20350_dupName_290_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20352_dupName_290_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20355_dupName_290_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20357_dupName_290_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20363_dupName_291_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20365_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20368_dupName_291_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20370_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20373_dupName_291_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20375_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20381_dupName_292_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20383_dupName_292_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20386_dupName_292_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20388_dupName_292_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20394_dupName_293_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20396_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20399_dupName_293_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20401_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20404_dupName_293_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20406_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20412_dupName_294_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20414_dupName_294_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20417_dupName_294_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20419_dupName_294_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20425_dupName_295_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20427_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20430_dupName_295_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20432_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20435_dupName_295_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20437_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20443_dupName_296_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20445_dupName_296_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20448_dupName_296_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20450_dupName_296_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20456_dupName_297_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20458_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20461_dupName_297_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20463_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20466_dupName_297_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20468_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20474_dupName_298_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20476_dupName_298_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20479_dupName_298_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20481_dupName_298_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20487_dupName_299_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20489_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20492_dupName_299_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20494_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20497_dupName_299_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20499_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20505_dupName_300_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20507_dupName_300_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20510_dupName_300_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20512_dupName_300_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20518_dupName_301_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20520_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20523_dupName_301_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20525_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20528_dupName_301_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20530_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20536_dupName_302_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20538_dupName_302_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20541_dupName_302_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20543_dupName_302_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20549_dupName_303_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20551_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20554_dupName_303_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20556_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20559_dupName_303_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20561_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20567_dupName_304_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20569_dupName_304_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20572_dupName_304_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20574_dupName_304_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20580_dupName_305_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20582_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20585_dupName_305_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20587_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20590_dupName_305_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20592_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20598_dupName_306_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20600_dupName_306_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20603_dupName_306_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20605_dupName_306_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20611_dupName_307_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20613_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20616_dupName_307_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20618_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20621_dupName_307_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20623_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20629_dupName_308_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20631_dupName_308_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20634_dupName_308_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20636_dupName_308_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20642_dupName_309_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20644_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20647_dupName_309_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20649_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20652_dupName_309_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20654_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20660_dupName_310_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20662_dupName_310_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20665_dupName_310_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20667_dupName_310_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20673_dupName_311_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20675_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20678_dupName_311_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20680_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20683_dupName_311_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20685_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20691_dupName_312_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20693_dupName_312_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20696_dupName_312_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20698_dupName_312_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20704_dupName_313_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20706_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20709_dupName_313_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20711_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20714_dupName_313_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20716_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20722_dupName_314_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20724_dupName_314_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20727_dupName_314_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20729_dupName_314_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20735_dupName_315_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20737_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20740_dupName_315_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20742_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20745_dupName_315_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20747_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20753_dupName_316_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20755_dupName_316_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20758_dupName_316_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20760_dupName_316_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20766_dupName_317_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20768_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20771_dupName_317_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20773_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20776_dupName_317_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20778_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20784_dupName_318_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20786_dupName_318_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20789_dupName_318_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20791_dupName_318_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20797_dupName_319_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20799_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20802_dupName_319_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20804_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20807_dupName_319_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20809_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20815_dupName_320_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20817_dupName_320_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20820_dupName_320_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20822_dupName_320_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20828_dupName_321_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20830_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20833_dupName_321_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20835_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20838_dupName_321_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20840_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20846_dupName_322_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20848_dupName_322_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20851_dupName_322_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20853_dupName_322_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20859_dupName_323_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20861_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20864_dupName_323_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20866_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20869_dupName_323_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20871_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20877_dupName_324_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20879_dupName_324_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20882_dupName_324_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20884_dupName_324_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20890_dupName_325_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20892_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20895_dupName_325_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20897_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20900_dupName_325_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20902_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20908_dupName_326_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20910_dupName_326_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20913_dupName_326_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20915_dupName_326_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20921_dupName_327_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20923_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20926_dupName_327_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20928_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20931_dupName_327_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20933_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20939_dupName_328_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20941_dupName_328_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20944_dupName_328_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20946_dupName_328_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20952_dupName_329_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20954_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20957_dupName_329_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20959_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20962_dupName_329_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20964_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid20970_dupName_330_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20972_dupName_330_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid20975_dupName_330_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20977_dupName_330_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid20983_dupName_331_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid20985_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid20988_dupName_331_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid20990_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid20993_dupName_331_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid20995_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21001_dupName_332_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21003_dupName_332_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21006_dupName_332_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21008_dupName_332_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21014_dupName_333_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21016_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21019_dupName_333_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21021_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21024_dupName_333_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21026_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21032_dupName_334_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21034_dupName_334_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21037_dupName_334_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21039_dupName_334_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21045_dupName_335_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21047_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21050_dupName_335_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21052_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21055_dupName_335_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21057_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21063_dupName_336_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21065_dupName_336_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21068_dupName_336_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21070_dupName_336_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21076_dupName_337_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21078_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21081_dupName_337_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21083_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21086_dupName_337_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21088_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21094_dupName_338_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21096_dupName_338_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21099_dupName_338_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21101_dupName_338_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21107_dupName_339_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21109_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21112_dupName_339_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21114_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21117_dupName_339_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21119_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21125_dupName_340_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21127_dupName_340_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21130_dupName_340_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21132_dupName_340_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21138_dupName_341_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21140_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21143_dupName_341_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21145_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21148_dupName_341_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21150_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21156_dupName_342_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21158_dupName_342_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21161_dupName_342_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21163_dupName_342_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21169_dupName_343_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21171_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21174_dupName_343_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21176_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21179_dupName_343_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21181_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21187_dupName_344_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21189_dupName_344_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21192_dupName_344_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21194_dupName_344_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21200_dupName_345_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21202_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21205_dupName_345_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21207_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21210_dupName_345_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21212_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21218_dupName_346_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21220_dupName_346_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21223_dupName_346_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21225_dupName_346_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21231_dupName_347_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21233_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21236_dupName_347_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21238_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21241_dupName_347_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21243_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21249_dupName_348_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21251_dupName_348_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21254_dupName_348_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21256_dupName_348_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21262_dupName_349_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21264_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21267_dupName_349_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21269_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21272_dupName_349_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21274_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21280_dupName_350_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21282_dupName_350_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21285_dupName_350_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21287_dupName_350_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21293_dupName_351_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21295_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21298_dupName_351_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21300_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21303_dupName_351_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21305_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21311_dupName_352_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21313_dupName_352_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21316_dupName_352_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21318_dupName_352_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21324_dupName_353_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21326_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21329_dupName_353_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21331_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21334_dupName_353_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21336_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21342_dupName_354_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21344_dupName_354_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21347_dupName_354_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21349_dupName_354_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21355_dupName_355_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21357_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21360_dupName_355_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21362_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21365_dupName_355_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21367_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21373_dupName_356_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21375_dupName_356_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21378_dupName_356_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21380_dupName_356_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21386_dupName_357_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21388_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21391_dupName_357_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21393_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21396_dupName_357_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21398_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21404_dupName_358_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21406_dupName_358_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21409_dupName_358_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21411_dupName_358_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21417_dupName_359_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21419_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21422_dupName_359_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21424_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21427_dupName_359_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21429_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21435_dupName_360_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21437_dupName_360_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21440_dupName_360_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21442_dupName_360_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21448_dupName_361_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21450_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21453_dupName_361_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21455_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21458_dupName_361_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21460_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21466_dupName_362_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21468_dupName_362_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21471_dupName_362_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21473_dupName_362_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21479_dupName_363_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21481_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21484_dupName_363_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21486_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21489_dupName_363_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21491_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21497_dupName_364_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21499_dupName_364_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21502_dupName_364_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21504_dupName_364_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21510_dupName_365_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21512_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21515_dupName_365_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21517_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21520_dupName_365_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21522_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21528_dupName_366_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21530_dupName_366_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21533_dupName_366_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21535_dupName_366_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21541_dupName_367_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21543_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21546_dupName_367_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21548_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21551_dupName_367_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21553_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21559_dupName_368_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21561_dupName_368_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21564_dupName_368_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21566_dupName_368_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21572_dupName_369_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21574_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21577_dupName_369_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21579_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21582_dupName_369_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21584_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21590_dupName_370_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21592_dupName_370_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21595_dupName_370_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21597_dupName_370_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21603_dupName_371_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21605_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21608_dupName_371_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21610_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21613_dupName_371_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21615_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21621_dupName_372_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21623_dupName_372_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21626_dupName_372_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21628_dupName_372_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21634_dupName_373_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21636_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21639_dupName_373_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21641_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21644_dupName_373_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21646_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21652_dupName_374_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21654_dupName_374_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21657_dupName_374_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21659_dupName_374_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21665_dupName_375_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21667_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21670_dupName_375_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21672_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21675_dupName_375_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21677_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21683_dupName_376_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21685_dupName_376_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21688_dupName_376_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21690_dupName_376_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21696_dupName_377_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21698_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21701_dupName_377_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21703_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21706_dupName_377_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21708_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21714_dupName_378_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21716_dupName_378_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21719_dupName_378_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21721_dupName_378_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21727_dupName_379_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21729_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21732_dupName_379_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21734_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21737_dupName_379_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21739_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21745_dupName_380_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21747_dupName_380_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21750_dupName_380_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21752_dupName_380_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21758_dupName_381_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21760_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21763_dupName_381_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21765_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21768_dupName_381_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21770_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21776_dupName_382_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21778_dupName_382_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21781_dupName_382_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21783_dupName_382_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21789_dupName_383_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21791_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21794_dupName_383_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21796_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21799_dupName_383_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21801_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21807_dupName_384_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21809_dupName_384_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21812_dupName_384_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21814_dupName_384_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21820_dupName_385_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21822_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21825_dupName_385_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21827_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21830_dupName_385_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21832_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21838_dupName_386_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21840_dupName_386_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21843_dupName_386_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21845_dupName_386_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21851_dupName_387_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21853_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21856_dupName_387_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21858_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21861_dupName_387_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21863_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21869_dupName_388_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21871_dupName_388_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21874_dupName_388_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21876_dupName_388_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21882_dupName_389_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21884_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21887_dupName_389_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21889_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21892_dupName_389_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21894_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21900_dupName_390_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21902_dupName_390_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21905_dupName_390_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21907_dupName_390_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21913_dupName_391_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21915_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21918_dupName_391_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21920_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21923_dupName_391_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21925_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21931_dupName_392_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21933_dupName_392_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21936_dupName_392_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21938_dupName_392_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21944_dupName_393_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21946_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21949_dupName_393_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21951_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21954_dupName_393_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21956_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21962_dupName_394_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21964_dupName_394_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21967_dupName_394_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21969_dupName_394_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid21975_dupName_395_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21977_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid21980_dupName_395_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid21982_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid21985_dupName_395_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid21987_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid21993_dupName_396_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid21995_dupName_396_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid21998_dupName_396_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22000_dupName_396_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22006_dupName_397_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22008_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22011_dupName_397_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22013_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22016_dupName_397_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22018_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22024_dupName_398_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22026_dupName_398_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22029_dupName_398_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22031_dupName_398_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22037_dupName_399_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22039_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22042_dupName_399_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22044_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22047_dupName_399_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22049_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22055_dupName_400_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22057_dupName_400_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22060_dupName_400_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22062_dupName_400_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22068_dupName_401_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22070_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22073_dupName_401_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22075_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22078_dupName_401_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22080_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22086_dupName_402_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22088_dupName_402_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22091_dupName_402_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22093_dupName_402_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22099_dupName_403_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22101_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22104_dupName_403_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22106_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22109_dupName_403_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22111_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22117_dupName_404_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22119_dupName_404_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22122_dupName_404_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22124_dupName_404_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22130_dupName_405_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22132_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22135_dupName_405_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22137_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22140_dupName_405_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22142_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22148_dupName_406_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22150_dupName_406_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22153_dupName_406_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22155_dupName_406_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22161_dupName_407_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22163_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22166_dupName_407_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22168_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22171_dupName_407_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22173_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22179_dupName_408_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22181_dupName_408_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22184_dupName_408_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22186_dupName_408_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22192_dupName_409_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22194_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22197_dupName_409_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22199_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22202_dupName_409_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22204_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22210_dupName_410_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22212_dupName_410_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22215_dupName_410_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22217_dupName_410_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22223_dupName_411_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22225_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22228_dupName_411_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22230_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22233_dupName_411_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22235_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22241_dupName_412_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22243_dupName_412_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22246_dupName_412_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22248_dupName_412_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22254_dupName_413_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22256_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22259_dupName_413_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22261_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22264_dupName_413_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22266_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22272_dupName_414_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22274_dupName_414_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22277_dupName_414_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22279_dupName_414_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22285_dupName_415_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22287_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22290_dupName_415_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22292_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22295_dupName_415_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22297_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22303_dupName_416_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22305_dupName_416_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22308_dupName_416_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22310_dupName_416_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22316_dupName_417_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22318_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22321_dupName_417_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22323_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22326_dupName_417_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22328_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22334_dupName_418_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22336_dupName_418_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22339_dupName_418_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22341_dupName_418_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22347_dupName_419_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22349_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22352_dupName_419_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22354_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22357_dupName_419_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22359_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22365_dupName_420_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22367_dupName_420_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22370_dupName_420_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22372_dupName_420_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22378_dupName_421_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22380_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22383_dupName_421_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22385_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22388_dupName_421_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22390_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22396_dupName_422_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22398_dupName_422_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22401_dupName_422_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22403_dupName_422_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22409_dupName_423_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22411_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22414_dupName_423_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22416_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22419_dupName_423_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22421_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22427_dupName_424_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22429_dupName_424_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22432_dupName_424_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22434_dupName_424_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22440_dupName_425_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22442_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22445_dupName_425_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22447_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22450_dupName_425_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22452_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22458_dupName_426_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22460_dupName_426_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22463_dupName_426_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22465_dupName_426_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22471_dupName_427_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22473_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22476_dupName_427_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22478_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22481_dupName_427_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22483_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22489_dupName_428_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22491_dupName_428_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22494_dupName_428_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22496_dupName_428_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22502_dupName_429_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22504_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22507_dupName_429_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22509_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22512_dupName_429_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22514_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22520_dupName_430_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22522_dupName_430_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22525_dupName_430_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22527_dupName_430_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22533_dupName_431_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22535_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22538_dupName_431_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22540_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22543_dupName_431_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22545_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22551_dupName_432_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22553_dupName_432_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22556_dupName_432_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22558_dupName_432_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22564_dupName_433_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22566_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22569_dupName_433_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22571_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22574_dupName_433_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22576_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22582_dupName_434_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22584_dupName_434_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22587_dupName_434_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22589_dupName_434_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22595_dupName_435_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22597_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22600_dupName_435_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22602_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22605_dupName_435_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22607_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22613_dupName_436_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22615_dupName_436_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22618_dupName_436_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22620_dupName_436_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22626_dupName_437_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22628_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22631_dupName_437_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22633_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22636_dupName_437_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22638_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22644_dupName_438_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22646_dupName_438_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22649_dupName_438_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22651_dupName_438_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22657_dupName_439_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22659_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22662_dupName_439_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22664_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22667_dupName_439_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22669_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22675_dupName_440_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22677_dupName_440_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22680_dupName_440_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22682_dupName_440_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22688_dupName_441_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22690_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22693_dupName_441_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22695_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22698_dupName_441_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22700_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22706_dupName_442_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22708_dupName_442_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22711_dupName_442_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22713_dupName_442_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22719_dupName_443_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22721_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22724_dupName_443_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22726_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22729_dupName_443_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22731_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22737_dupName_444_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22739_dupName_444_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22742_dupName_444_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22744_dupName_444_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22750_dupName_445_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22752_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22755_dupName_445_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22757_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22760_dupName_445_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22762_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22768_dupName_446_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22770_dupName_446_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22773_dupName_446_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22775_dupName_446_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22781_dupName_447_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22783_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22786_dupName_447_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22788_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22791_dupName_447_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22793_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22799_dupName_448_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22801_dupName_448_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22804_dupName_448_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22806_dupName_448_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22812_dupName_449_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22814_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22817_dupName_449_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22819_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22822_dupName_449_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22824_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22830_dupName_450_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22832_dupName_450_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22835_dupName_450_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22837_dupName_450_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22843_dupName_451_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22845_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22848_dupName_451_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22850_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22853_dupName_451_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22855_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22861_dupName_452_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22863_dupName_452_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22866_dupName_452_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22868_dupName_452_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22874_dupName_453_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22876_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22879_dupName_453_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22881_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22884_dupName_453_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22886_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22892_dupName_454_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22894_dupName_454_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22897_dupName_454_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22899_dupName_454_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22905_dupName_455_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22907_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22910_dupName_455_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22912_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22915_dupName_455_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22917_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22923_dupName_456_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22925_dupName_456_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22928_dupName_456_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22930_dupName_456_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22936_dupName_457_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22938_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22941_dupName_457_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22943_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22946_dupName_457_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22948_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22954_dupName_458_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22956_dupName_458_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22959_dupName_458_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22961_dupName_458_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22967_dupName_459_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22969_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid22972_dupName_459_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22974_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid22977_dupName_459_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid22979_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid22985_dupName_460_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid22987_dupName_460_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid22990_dupName_460_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid22992_dupName_460_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid22998_dupName_461_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23000_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23003_dupName_461_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23005_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23008_dupName_461_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23010_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23016_dupName_462_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23018_dupName_462_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23021_dupName_462_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23023_dupName_462_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23029_dupName_463_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23031_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23034_dupName_463_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23036_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23039_dupName_463_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23041_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23047_dupName_464_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23049_dupName_464_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23052_dupName_464_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23054_dupName_464_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23060_dupName_465_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23062_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23065_dupName_465_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23067_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23070_dupName_465_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23072_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23078_dupName_466_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23080_dupName_466_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23083_dupName_466_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23085_dupName_466_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23091_dupName_467_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23093_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23096_dupName_467_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23098_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23101_dupName_467_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23103_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23109_dupName_468_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23111_dupName_468_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23114_dupName_468_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23116_dupName_468_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23122_dupName_469_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23124_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23127_dupName_469_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23129_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23132_dupName_469_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23134_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23140_dupName_470_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23142_dupName_470_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23145_dupName_470_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23147_dupName_470_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23153_dupName_471_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23155_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23158_dupName_471_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23160_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23163_dupName_471_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23165_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23171_dupName_472_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23173_dupName_472_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23176_dupName_472_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23178_dupName_472_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23184_dupName_473_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23186_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23189_dupName_473_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23191_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23194_dupName_473_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23196_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23202_dupName_474_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23204_dupName_474_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23207_dupName_474_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23209_dupName_474_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23215_dupName_475_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23217_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23220_dupName_475_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23222_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23225_dupName_475_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23227_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23233_dupName_476_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23235_dupName_476_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23238_dupName_476_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23240_dupName_476_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23246_dupName_477_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23248_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23251_dupName_477_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23253_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23256_dupName_477_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23258_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23264_dupName_478_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23266_dupName_478_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23269_dupName_478_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23271_dupName_478_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23277_dupName_479_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23279_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23282_dupName_479_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23284_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23287_dupName_479_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23289_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23295_dupName_480_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23297_dupName_480_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23300_dupName_480_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23302_dupName_480_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23308_dupName_481_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23310_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23313_dupName_481_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23315_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23318_dupName_481_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23320_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23326_dupName_482_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23328_dupName_482_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23331_dupName_482_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23333_dupName_482_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23339_dupName_483_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23341_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23344_dupName_483_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23346_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23349_dupName_483_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23351_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23357_dupName_484_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23359_dupName_484_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23362_dupName_484_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23364_dupName_484_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23370_dupName_485_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23372_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23375_dupName_485_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23377_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23380_dupName_485_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23382_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23388_dupName_486_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23390_dupName_486_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23393_dupName_486_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23395_dupName_486_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23401_dupName_487_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23403_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23406_dupName_487_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23408_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23411_dupName_487_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23413_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23419_dupName_488_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23421_dupName_488_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23424_dupName_488_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23426_dupName_488_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23432_dupName_489_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23434_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23437_dupName_489_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23439_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23442_dupName_489_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23444_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23450_dupName_490_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23452_dupName_490_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23455_dupName_490_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23457_dupName_490_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23463_dupName_491_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23465_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23468_dupName_491_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23470_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23473_dupName_491_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23475_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23481_dupName_492_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23483_dupName_492_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23486_dupName_492_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23488_dupName_492_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23494_dupName_493_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23496_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23499_dupName_493_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23501_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23504_dupName_493_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23506_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23512_dupName_494_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23514_dupName_494_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23517_dupName_494_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23519_dupName_494_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23525_dupName_495_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23527_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23530_dupName_495_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23532_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23535_dupName_495_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23537_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23543_dupName_496_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23545_dupName_496_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23548_dupName_496_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23550_dupName_496_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23556_dupName_497_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23558_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23561_dupName_497_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23563_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23566_dupName_497_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23568_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23574_dupName_498_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23576_dupName_498_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23579_dupName_498_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23581_dupName_498_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23587_dupName_499_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23589_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23592_dupName_499_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23594_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23597_dupName_499_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23599_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23605_dupName_500_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23607_dupName_500_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23610_dupName_500_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23612_dupName_500_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23618_dupName_501_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23620_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23623_dupName_501_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23625_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23628_dupName_501_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23630_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23636_dupName_502_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23638_dupName_502_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23641_dupName_502_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23643_dupName_502_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23649_dupName_503_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23651_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23654_dupName_503_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23656_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23659_dupName_503_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23661_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23667_dupName_504_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23669_dupName_504_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23672_dupName_504_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23674_dupName_504_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23680_dupName_505_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23682_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23685_dupName_505_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23687_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23690_dupName_505_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23692_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23698_dupName_506_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23700_dupName_506_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23703_dupName_506_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23705_dupName_506_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23711_dupName_507_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23713_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23716_dupName_507_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23718_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23721_dupName_507_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23723_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23729_dupName_508_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23731_dupName_508_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23734_dupName_508_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23736_dupName_508_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid23742_dupName_509_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23744_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid23747_dupName_509_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23749_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid23752_dupName_509_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid23754_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage0Idx1Rng4_uid23760_dupName_510_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid23762_dupName_510_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage1Idx1Rng8_uid23765_dupName_510_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid23767_dupName_510_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23774_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23774_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23775_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23779_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23779_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23780_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23784_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23784_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23785_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23792_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23792_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23793_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23797_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23797_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23798_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23802_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23802_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23803_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23810_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23810_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23811_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23815_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23815_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23816_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23820_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23820_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23821_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23828_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23828_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23829_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23833_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23833_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23834_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23838_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23838_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23839_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23846_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23846_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23847_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23851_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23851_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23852_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23856_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23856_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23857_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23864_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23864_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23865_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23869_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23869_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23870_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23874_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23874_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23875_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23882_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23882_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23883_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23887_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23887_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23888_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23892_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23892_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23893_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23900_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23900_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23901_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23905_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23905_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23906_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23910_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23910_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23911_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23918_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23918_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23919_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23923_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23923_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23924_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23928_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23928_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23929_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23936_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23936_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23937_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23941_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23941_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23942_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23946_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23946_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23947_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23954_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23954_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23955_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23959_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23959_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23960_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23964_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23964_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23965_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23972_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23972_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23973_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23977_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23977_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23978_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23982_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid23982_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid23983_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23990_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid23990_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid23991_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23995_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid23995_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid23996_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24000_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24000_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24001_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24008_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24008_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24009_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24013_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24013_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24014_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24018_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24018_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24019_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24026_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24026_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24027_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24031_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24031_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24032_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24036_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24036_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24037_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24044_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24044_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24045_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24049_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24049_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24050_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24054_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24054_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24055_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24062_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24062_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24063_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24067_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24067_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24068_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24072_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24072_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24073_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24080_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24080_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24081_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24085_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24085_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24086_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24090_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24090_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24091_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24098_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24098_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24099_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24103_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24103_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24104_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24108_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24108_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24109_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24116_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24116_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24117_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24121_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24121_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24122_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24126_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24126_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24127_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24134_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24134_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24135_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24139_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24139_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24140_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24144_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24144_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24145_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24152_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24152_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24153_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24157_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24157_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24158_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24162_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24162_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24163_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24170_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24170_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24171_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24175_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24175_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24176_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24180_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24180_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24181_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24188_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24188_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24189_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24193_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24193_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24194_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24198_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24198_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24199_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24206_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24206_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24207_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24211_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24211_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24212_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24216_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24216_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24217_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24224_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24224_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24225_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24229_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24229_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24230_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24234_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24234_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24235_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24242_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24242_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24243_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24247_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24247_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24248_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24252_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24252_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24253_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24260_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24260_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24261_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24265_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24265_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24266_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24270_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24270_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24271_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24278_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24278_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24279_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24283_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24283_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24284_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24288_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24288_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24289_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24296_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24296_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24297_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24301_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24301_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24302_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24306_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24306_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24307_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24314_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24314_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24315_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24319_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24319_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24320_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24324_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24324_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24325_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24332_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24332_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24333_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24337_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24337_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24338_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24342_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24342_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24343_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24350_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24350_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24351_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24355_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24355_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24356_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24360_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24360_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24361_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24368_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24368_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24369_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24373_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24373_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24374_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24378_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24378_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24379_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24386_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24386_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24387_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24391_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24391_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24392_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24396_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24396_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24397_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24404_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24404_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24405_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24409_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24409_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24410_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24414_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24414_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24415_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24422_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24422_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24423_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24427_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24427_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24428_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24432_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24432_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24433_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24440_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24440_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24441_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24445_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24445_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24446_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24450_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24450_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24451_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24458_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24458_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24459_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24463_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24463_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24464_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24468_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24468_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24469_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24476_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24476_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24477_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24481_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24481_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24482_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24486_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24486_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24487_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24494_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24494_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24495_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24499_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24499_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24500_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24504_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24504_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24505_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24512_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24512_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24513_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24517_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24517_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24518_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24522_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24522_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24523_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24530_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24530_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24531_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24535_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24535_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24536_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24540_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24540_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24541_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24548_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24548_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24549_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24553_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24553_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24554_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24558_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24558_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24559_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24566_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24566_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24567_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24571_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24571_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24572_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24576_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24576_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24577_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24584_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24584_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24585_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24589_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24589_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24590_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24594_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24594_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24595_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24602_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24602_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24603_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24607_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24607_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24608_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24612_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24612_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24613_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24620_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24620_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24621_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24625_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24625_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24626_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24630_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24630_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24631_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24638_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24638_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24639_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24643_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24643_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24644_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24648_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24648_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24649_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24656_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24656_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24657_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24661_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24661_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24662_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24666_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24666_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24667_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24674_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24674_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24675_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24679_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24679_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24680_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24684_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24684_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24685_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24692_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24692_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24693_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24697_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24697_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24698_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24702_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24702_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24703_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24710_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24710_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24711_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24715_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24715_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24716_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24720_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24720_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24721_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24728_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24728_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24729_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24733_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24733_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24734_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24738_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24738_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24739_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24746_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24746_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24747_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24751_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24751_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24752_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24756_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24756_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24757_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24764_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24764_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24765_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24769_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24769_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24770_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24774_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24774_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24775_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24782_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24782_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24783_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24787_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24787_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24788_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24792_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24792_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24793_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24800_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24800_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24801_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24805_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24805_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24806_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24810_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24810_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24811_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24818_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24818_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24819_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24823_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24823_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24824_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24828_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24828_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24829_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24836_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24836_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24837_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24841_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24841_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24842_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24846_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24846_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24847_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24854_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24854_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24855_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24859_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24859_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24860_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24864_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24864_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24865_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24872_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24872_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24873_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24877_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24877_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24878_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24882_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24882_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24883_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24890_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24890_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24891_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24895_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24895_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24896_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24900_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24900_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24901_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24908_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24908_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24909_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24913_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24913_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24914_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24918_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24918_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24919_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24926_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24926_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24927_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24931_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24931_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24932_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24936_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24936_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24937_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24944_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24944_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24945_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24949_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24949_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24950_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24954_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24954_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24955_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24962_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24962_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24963_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24967_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24967_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24968_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24972_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24972_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24973_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24980_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24980_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24981_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24985_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid24985_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid24986_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24990_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid24990_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid24991_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24998_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid24998_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid24999_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25003_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25003_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25004_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25008_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25008_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25009_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25016_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25016_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25017_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25021_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25021_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25022_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25026_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25026_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25027_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25034_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25034_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25035_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25039_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25039_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25040_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25044_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25044_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25045_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25052_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25052_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25053_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25057_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25057_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25058_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25062_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25062_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25063_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25070_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25070_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25071_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25075_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25075_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25076_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25080_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25080_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25081_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25088_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25088_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25089_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25093_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25093_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25094_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25098_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25098_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25099_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25106_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25106_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25107_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25111_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25111_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25112_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25116_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25116_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25117_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25124_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25124_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25125_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25129_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25129_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25130_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25134_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25134_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25135_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25142_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25142_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25143_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25147_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25147_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25148_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25152_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25152_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25153_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25160_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25160_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25161_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25165_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25165_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25166_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25170_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25170_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25171_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25178_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25178_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25179_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25183_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25183_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25184_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25188_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25188_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25189_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25196_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25196_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25197_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25201_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25201_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25202_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25206_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25206_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25207_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25214_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25214_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25215_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25219_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25219_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25220_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25224_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25224_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25225_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25232_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25232_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25233_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25237_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25237_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25238_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25242_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25242_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25243_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25250_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25250_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25251_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25255_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25255_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25256_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25260_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25260_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25261_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25268_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25268_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25269_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25273_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25273_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25274_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25278_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25278_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25279_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25286_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25286_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25287_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25291_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25291_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25292_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25296_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25296_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25297_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25304_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25304_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25305_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25309_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25309_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25310_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25314_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25314_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25315_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25322_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25322_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25323_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25327_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25327_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25328_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25332_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25332_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25333_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25340_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25340_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25341_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25345_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25345_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25346_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25350_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25350_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25351_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25358_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25358_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25359_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25363_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25363_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25364_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25368_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25368_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25369_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25376_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25376_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25377_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25381_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25381_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25382_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25386_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25386_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25387_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25394_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25394_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25395_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25399_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25399_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25400_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25404_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25404_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25405_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25412_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25412_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25413_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25417_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25417_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25418_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25422_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25422_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25423_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25430_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25430_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25431_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25435_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25435_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25436_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25440_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25440_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25441_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25448_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25448_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25449_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25453_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25453_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25454_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25458_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25458_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25459_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25466_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25466_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25467_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25471_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25471_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25472_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25476_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25476_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25477_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25484_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25484_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25485_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25489_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25489_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25490_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25494_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25494_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25495_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25502_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25502_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25503_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25507_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25507_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25508_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25512_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25512_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25513_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25520_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25520_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25521_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25525_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25525_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25526_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25530_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25530_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25531_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25538_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25538_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25539_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25543_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25543_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25544_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25548_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25548_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25549_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25556_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25556_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25557_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25561_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25561_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25562_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25566_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25566_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25567_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25574_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25574_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25575_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25579_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25579_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25580_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25584_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25584_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25585_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25592_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25592_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25593_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25597_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25597_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25598_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25602_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25602_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25603_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25610_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25610_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25611_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25615_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25615_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25616_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25620_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25620_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25621_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25628_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25628_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25629_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25633_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25633_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25634_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25638_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25638_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25639_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25646_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25646_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25647_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25651_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25651_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25652_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25656_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25656_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25657_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25664_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25664_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25665_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25669_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25669_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25670_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25674_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25674_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25675_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25682_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25682_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25683_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25687_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25687_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25688_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25692_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25692_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25693_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25700_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25700_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25701_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25705_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25705_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25706_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25710_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25710_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25711_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25718_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25718_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25719_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25723_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25723_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25724_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25728_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25728_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25729_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25736_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25736_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25737_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25741_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25741_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25742_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25746_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25746_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25747_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25754_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25754_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25755_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25759_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25759_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25760_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25764_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25764_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25765_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25772_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25772_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25773_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25777_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25777_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25778_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25782_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25782_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25783_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25790_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25790_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25791_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25795_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25795_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25796_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25800_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25800_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25801_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25808_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25808_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25809_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25813_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25813_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25814_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25818_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25818_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25819_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25826_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25826_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25827_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25831_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25831_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25832_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25836_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25836_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25837_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25844_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25844_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25845_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25849_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25849_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25850_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25854_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25854_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25855_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25862_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25862_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25863_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25867_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25867_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25868_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25872_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25872_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25873_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25880_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25880_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25881_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25885_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25885_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25886_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25890_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25890_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25891_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25898_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25898_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25899_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25903_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25903_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25904_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25908_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25908_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25909_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25916_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25916_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25917_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25921_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25921_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25922_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25926_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25926_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25927_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25934_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25934_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25935_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25939_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25939_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25940_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25944_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25944_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25945_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25952_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25952_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25953_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25957_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25957_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25958_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25962_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25962_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25963_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25970_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25970_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25971_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25975_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25975_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25976_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25980_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25980_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25981_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25988_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid25988_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid25989_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25993_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid25993_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid25994_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25998_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid25998_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid25999_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26006_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26006_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26007_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26011_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26011_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26012_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26016_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26016_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26017_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26024_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26024_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26025_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26029_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26029_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26030_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26034_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26034_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26035_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26042_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26042_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26043_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26047_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26047_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26048_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26052_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26052_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26053_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26060_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26060_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26061_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26065_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26065_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26066_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26070_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26070_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26071_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26078_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26078_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26079_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26083_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26083_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26084_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26088_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26088_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26089_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26096_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26096_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26097_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26101_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26101_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26102_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26106_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26106_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26107_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26114_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26114_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26115_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26119_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26119_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26120_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26124_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26124_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26125_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26132_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26132_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26133_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26137_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26137_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26138_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26142_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26142_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26143_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26150_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26150_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26151_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26155_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26155_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26156_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26160_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26160_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26161_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26168_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26168_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26169_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26173_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26173_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26174_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26178_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26178_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26179_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26186_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26186_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26187_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26191_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26191_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26192_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26196_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26196_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26197_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26204_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26204_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26205_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26209_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26209_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26210_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26214_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26214_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26215_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26222_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26222_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26223_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26227_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26227_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26228_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26232_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26232_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26233_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26240_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26240_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26241_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26245_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26245_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26246_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26250_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26250_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26251_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26258_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26258_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26259_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26263_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26263_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26264_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26268_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26268_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26269_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26276_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26276_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26277_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26281_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26281_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26282_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26286_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26286_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26287_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26294_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26294_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26295_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26299_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26299_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26300_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26304_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26304_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26305_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26312_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26312_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26313_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26317_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26317_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26318_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26322_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26322_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26323_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26330_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26330_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26331_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26335_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26335_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26336_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26340_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26340_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26341_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26348_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26348_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26349_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26353_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26353_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26354_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26358_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26358_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26359_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26366_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26366_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26367_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26371_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26371_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26372_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26376_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26376_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26377_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26384_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26384_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26385_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26389_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26389_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26390_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26394_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26394_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26395_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26402_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26402_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26403_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26407_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26407_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26408_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26412_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26412_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26413_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26420_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26420_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26421_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26425_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26425_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26426_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26430_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26430_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26431_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26438_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26438_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26439_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26443_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26443_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26444_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26448_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26448_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26449_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26456_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26456_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26457_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26461_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26461_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26462_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26466_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26466_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26467_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26474_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26474_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26475_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26479_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26479_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26480_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26484_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26484_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26485_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26492_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26492_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26493_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26497_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26497_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26498_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26502_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26502_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26503_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26510_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26510_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26511_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26515_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26515_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26516_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26520_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26520_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26521_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26528_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26528_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26529_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26533_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26533_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26534_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26538_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26538_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26539_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26546_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26546_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26547_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26551_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26551_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26552_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26556_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26556_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26557_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26564_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26564_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26565_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26569_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26569_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26570_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26574_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26574_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26575_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26582_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26582_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26583_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26587_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26587_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26588_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26592_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26592_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26593_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26600_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26600_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26601_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26605_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26605_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26606_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26610_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26610_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26611_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26618_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26618_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26619_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26623_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26623_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26624_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26628_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26628_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26629_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26636_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26636_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26637_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26641_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26641_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26642_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26646_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26646_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26647_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26654_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26654_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26655_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26659_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26659_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26660_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26664_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26664_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26665_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26672_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26672_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26673_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26677_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26677_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26678_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26682_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26682_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26683_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26690_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26690_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26691_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26695_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26695_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26696_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26700_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26700_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26701_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26708_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26708_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26709_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26713_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26713_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26714_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26718_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26718_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26719_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26726_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26726_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26727_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26731_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26731_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26732_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26736_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26736_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26737_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26744_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26744_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26745_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26749_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26749_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26750_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26754_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26754_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26755_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26762_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26762_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26763_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26767_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26767_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26768_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26772_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26772_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26773_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26780_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26780_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26781_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26785_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26785_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26786_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26790_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26790_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26791_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26798_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26798_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26799_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26803_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26803_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26804_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26808_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26808_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26809_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26816_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26816_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26817_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26821_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26821_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26822_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26826_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26826_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26827_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26834_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26834_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26835_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26839_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26839_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26840_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26844_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26844_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26845_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26852_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26852_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26853_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26857_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26857_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26858_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26862_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26862_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26863_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26870_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26870_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26871_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26875_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26875_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26876_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26880_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26880_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26881_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26888_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26888_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26889_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26893_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26893_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26894_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26898_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26898_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26899_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26906_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26906_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26907_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26911_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26911_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26912_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26916_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26916_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26917_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26924_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26924_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26925_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26929_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26929_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26930_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26934_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26934_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26935_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26942_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26942_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26943_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26947_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26947_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26948_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26952_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26952_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26953_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26960_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26960_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26961_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26965_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26965_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26966_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26970_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26970_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26971_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26978_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26978_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26979_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26983_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid26983_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid26984_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26988_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid26988_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid26989_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26996_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid26996_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid26997_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27001_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27001_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27002_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27006_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27006_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27007_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27014_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27014_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27015_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27019_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27019_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27020_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27024_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27024_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27025_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27032_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27032_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27033_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27037_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27037_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27038_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27042_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27042_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27043_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27050_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27050_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27051_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27055_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27055_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27056_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27060_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27060_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27061_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27068_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27068_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27069_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27073_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27073_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27074_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27078_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27078_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27079_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27086_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27086_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27087_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27091_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27091_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27092_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27096_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27096_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27097_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27104_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27104_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27105_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27109_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27109_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27110_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27114_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27114_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27115_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27122_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27122_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27123_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27127_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27127_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27128_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27132_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27132_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27133_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27140_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27140_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27141_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27145_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27145_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27146_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27150_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27150_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27151_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27158_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27158_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27159_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27163_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27163_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27164_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27168_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27168_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27169_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27176_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27176_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27177_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27181_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27181_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27182_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27186_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27186_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27187_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27194_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27194_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27195_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27199_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27199_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27200_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27204_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27204_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27205_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27212_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27212_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27213_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27217_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27217_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27218_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27222_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27222_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27223_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27230_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27230_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27231_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27235_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27235_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27236_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27240_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27240_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27241_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27248_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27248_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27249_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27253_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27253_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27254_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27258_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27258_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27259_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27266_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27266_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27267_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27271_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27271_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27272_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27276_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27276_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27277_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27284_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27284_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27285_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27289_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27289_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27290_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27294_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27294_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27295_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27302_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27302_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27303_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27307_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27307_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27308_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27312_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27312_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27313_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27320_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27320_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27321_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27325_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27325_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27326_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27330_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27330_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27331_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27338_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27338_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27339_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27343_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27343_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27344_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27348_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27348_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27349_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27356_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27356_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27357_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27361_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27361_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27362_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27366_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27366_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27367_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27374_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27374_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27375_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27379_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27379_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27380_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27384_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27384_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27385_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27392_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27392_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27393_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27397_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27397_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27398_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27402_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27402_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27403_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27410_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27410_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27411_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27415_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27415_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27416_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27420_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27420_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27421_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27428_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27428_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27429_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27433_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27433_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27434_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27438_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27438_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27439_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27446_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27446_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27447_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27451_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27451_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27452_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27456_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27456_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27457_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27464_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27464_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27465_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27469_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27469_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27470_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27474_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27474_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27475_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27482_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27482_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27483_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27487_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27487_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27488_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27492_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27492_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27493_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27500_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27500_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27501_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27505_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27505_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27506_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27510_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27510_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27511_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27518_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27518_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27519_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27523_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27523_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27524_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27528_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27528_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27529_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27536_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27536_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27537_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27541_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27541_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27542_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27546_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27546_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27547_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27554_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27554_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27555_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27559_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27559_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27560_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27564_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27564_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27565_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27572_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27572_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27573_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27577_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27577_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27578_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27582_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27582_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27583_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27590_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27590_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27591_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27595_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27595_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27596_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27600_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27600_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27601_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27608_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27608_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27609_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27613_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27613_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27614_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27618_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27618_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27619_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27626_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27626_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27627_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27631_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27631_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27632_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27636_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27636_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27637_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27644_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27644_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27645_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27649_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27649_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27650_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27654_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27654_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27655_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27662_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27662_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27663_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27667_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27667_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27668_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27672_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27672_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27673_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27680_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27680_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27681_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27685_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27685_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27686_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27690_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27690_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27691_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27698_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27698_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27699_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27703_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27703_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27704_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27708_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27708_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27709_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27716_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27716_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27717_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27721_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27721_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27722_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27726_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27726_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27727_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27734_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27734_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27735_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27739_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27739_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27740_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27744_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27744_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27745_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27752_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27752_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27753_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27757_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27757_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27758_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27762_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27762_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27763_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27770_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27770_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27771_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27775_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27775_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27776_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27780_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27780_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27781_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27788_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27788_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27789_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27793_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27793_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27794_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27798_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27798_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27799_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27806_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27806_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27807_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27811_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27811_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27812_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27816_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27816_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27817_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27824_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27824_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27825_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27829_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27829_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27830_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27834_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27834_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27835_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27842_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27842_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27843_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27847_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27847_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27848_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27852_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27852_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27853_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27860_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27860_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27861_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27865_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27865_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27866_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27870_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27870_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27871_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27878_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27878_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27879_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27883_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27883_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27884_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27888_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27888_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27889_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27896_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27896_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27897_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27901_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27901_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27902_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27906_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27906_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27907_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27914_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27914_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27915_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27919_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27919_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27920_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27924_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27924_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27925_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27932_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27932_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27933_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27937_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27937_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27938_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27942_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27942_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27943_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27950_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27950_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27951_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27955_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27955_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27956_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27960_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27960_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27961_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27968_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27968_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27969_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27973_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27973_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27974_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27978_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27978_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27979_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27986_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid27986_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid27987_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27991_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid27991_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid27992_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27996_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid27996_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid27997_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28004_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28004_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28005_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28009_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28009_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28010_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28014_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28014_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28015_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28022_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28022_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28023_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28027_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28027_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28028_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28032_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28032_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28033_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28040_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28040_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28041_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28045_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28045_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28046_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28050_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28050_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28051_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28058_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28058_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28059_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28063_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28063_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28064_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28068_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28068_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28069_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28076_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28076_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28077_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28081_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28081_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28082_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28086_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28086_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28087_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28094_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28094_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28095_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28099_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28099_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28100_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28104_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28104_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28105_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28112_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28112_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28113_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28117_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28117_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28118_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28122_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28122_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28123_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28130_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28130_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28131_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28135_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28135_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28136_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28140_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28140_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28141_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28148_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28148_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28149_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28153_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28153_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28154_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28158_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28158_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28159_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28166_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28166_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28167_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28171_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28171_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28172_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28176_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28176_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28177_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28184_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28184_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28185_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28189_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28189_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28190_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28194_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28194_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28195_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28202_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28202_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28203_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28207_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28207_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28208_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28212_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28212_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28213_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28220_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28220_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28221_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28225_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28225_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28226_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28230_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28230_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28231_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28238_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28238_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28239_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28243_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28243_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28244_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28248_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28248_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28249_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28256_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28256_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28257_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28261_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28261_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28262_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28266_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28266_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28267_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28274_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28274_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28275_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28279_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28279_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28280_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28284_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28284_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28285_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28292_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28292_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28293_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28297_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28297_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28298_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28302_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28302_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28303_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28310_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28310_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28311_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28315_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28315_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28316_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28320_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28320_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28321_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28328_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in;
    wire [27:0] leftShiftStage0Idx1Rng1_uid28328_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage0Idx1_uid28329_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28333_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in;
    wire [24:0] leftShiftStage1Idx1Rng4_uid28333_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage1Idx1_uid28334_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28338_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in;
    wire [20:0] leftShiftStage2Idx1Rng8_uid28338_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b;
    wire [28:0] leftShiftStage2Idx1_uid28339_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
    wire [0:0] leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s;
    reg [28:0] leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
    wire [32:0] rightShiftStage0Idx1Rng1_uid28345_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage0Idx1_uid28347_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_q;
    wire [29:0] rightShiftStage1Idx1Rng4_uid28350_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage1Idx1_uid28352_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_q;
    wire [25:0] rightShiftStage2Idx1Rng8_uid28355_i_unnamed_c_compmm_m0_shift_x_b;
    wire [33:0] rightShiftStage2Idx1_uid28357_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_s;
    reg [33:0] rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_q;
    wire [0:0] i_unnamed_c_compmm_m1009_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1009_join_q;
    wire [0:0] i_unnamed_c_compmm_m1021_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1021_join_q;
    wire [0:0] i_unnamed_c_compmm_m1037_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1037_join_q;
    wire [0:0] i_unnamed_c_compmm_m1049_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1049_join_q;
    wire [0:0] i_unnamed_c_compmm_m1065_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1065_join_q;
    wire [0:0] i_unnamed_c_compmm_m1077_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1077_join_q;
    wire [0:0] i_unnamed_c_compmm_m1093_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1093_join_q;
    wire [0:0] i_unnamed_c_compmm_m1105_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1105_join_q;
    wire [0:0] i_unnamed_c_compmm_m1121_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1121_join_q;
    wire [0:0] i_unnamed_c_compmm_m1133_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1133_join_q;
    wire [0:0] i_unnamed_c_compmm_m1149_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1149_join_q;
    wire [0:0] i_unnamed_c_compmm_m1162_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1162_join_q;
    wire [0:0] i_unnamed_c_compmm_m1178_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1178_join_q;
    wire [0:0] i_unnamed_c_compmm_m1190_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1190_join_q;
    wire [0:0] i_unnamed_c_compmm_m1206_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1206_join_q;
    wire [0:0] i_unnamed_c_compmm_m1218_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1218_join_q;
    wire [0:0] i_unnamed_c_compmm_m1234_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1234_join_q;
    wire [0:0] i_unnamed_c_compmm_m1246_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1246_join_q;
    wire [0:0] i_unnamed_c_compmm_m1262_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1262_join_q;
    wire [0:0] i_unnamed_c_compmm_m1274_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1274_join_q;
    wire [0:0] i_unnamed_c_compmm_m1290_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1290_join_q;
    wire [0:0] i_unnamed_c_compmm_m1302_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1302_join_q;
    wire [0:0] i_unnamed_c_compmm_m1318_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1318_join_q;
    wire [0:0] i_unnamed_c_compmm_m1330_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1330_join_q;
    wire [0:0] i_unnamed_c_compmm_m1346_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1346_join_q;
    wire [0:0] i_unnamed_c_compmm_m1358_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1358_join_q;
    wire [0:0] i_unnamed_c_compmm_m1374_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1374_join_q;
    wire [0:0] i_unnamed_c_compmm_m1386_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1386_join_q;
    wire [0:0] i_unnamed_c_compmm_m1402_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1402_join_q;
    wire [0:0] i_unnamed_c_compmm_m1414_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1414_join_q;
    wire [0:0] i_unnamed_c_compmm_m1430_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1430_join_q;
    wire [0:0] i_unnamed_c_compmm_m1442_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1442_join_q;
    wire [0:0] i_unnamed_c_compmm_m1458_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1458_join_q;
    wire [0:0] i_unnamed_c_compmm_m1470_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1470_join_q;
    wire [0:0] i_unnamed_c_compmm_m1486_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1486_join_q;
    wire [0:0] i_unnamed_c_compmm_m1498_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1498_join_q;
    wire [0:0] i_unnamed_c_compmm_m1514_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1514_join_q;
    wire [0:0] i_unnamed_c_compmm_m1526_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1526_join_q;
    wire [0:0] i_unnamed_c_compmm_m1542_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1542_join_q;
    wire [0:0] i_unnamed_c_compmm_m1554_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1554_join_q;
    wire [0:0] i_unnamed_c_compmm_m1570_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1570_join_q;
    wire [0:0] i_unnamed_c_compmm_m1582_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1582_join_q;
    wire [0:0] i_unnamed_c_compmm_m1598_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1598_join_q;
    wire [0:0] i_unnamed_c_compmm_m1610_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1610_join_q;
    wire [0:0] i_unnamed_c_compmm_m1626_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1626_join_q;
    wire [0:0] i_unnamed_c_compmm_m1638_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1638_join_q;
    wire [0:0] i_unnamed_c_compmm_m1654_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1654_join_q;
    wire [0:0] i_unnamed_c_compmm_m1666_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1666_join_q;
    wire [0:0] i_unnamed_c_compmm_m1682_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1682_join_q;
    wire [0:0] i_unnamed_c_compmm_m1694_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1694_join_q;
    wire [0:0] i_unnamed_c_compmm_m1710_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1710_join_q;
    wire [0:0] i_unnamed_c_compmm_m1722_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1722_join_q;
    wire [0:0] i_unnamed_c_compmm_m1738_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1738_join_q;
    wire [0:0] i_unnamed_c_compmm_m1750_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1750_join_q;
    wire [0:0] i_unnamed_c_compmm_m1766_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1766_join_q;
    wire [0:0] i_unnamed_c_compmm_m1778_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1778_join_q;
    wire [0:0] i_unnamed_c_compmm_m1794_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1794_join_q;
    wire [0:0] i_unnamed_c_compmm_m1806_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1806_join_q;
    wire [0:0] i_unnamed_c_compmm_m1822_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1822_join_q;
    wire [0:0] i_unnamed_c_compmm_m1834_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1834_join_q;
    wire [0:0] i_unnamed_c_compmm_m1850_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1850_join_q;
    wire [0:0] i_unnamed_c_compmm_m1862_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1862_join_q;
    wire [0:0] i_unnamed_c_compmm_m1878_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1878_join_q;
    wire [0:0] i_unnamed_c_compmm_m1890_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1890_join_q;
    wire [0:0] i_unnamed_c_compmm_m1906_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1906_join_q;
    wire [0:0] i_unnamed_c_compmm_m1918_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1918_join_q;
    wire [0:0] i_unnamed_c_compmm_m1934_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1934_join_q;
    wire [0:0] i_unnamed_c_compmm_m1946_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1946_join_q;
    wire [0:0] i_unnamed_c_compmm_m1962_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1962_join_q;
    wire [0:0] i_unnamed_c_compmm_m1974_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1974_join_q;
    wire [0:0] i_unnamed_c_compmm_m1990_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m1990_join_q;
    wire [0:0] i_unnamed_c_compmm_m2002_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2002_join_q;
    wire [0:0] i_unnamed_c_compmm_m2018_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2018_join_q;
    wire [0:0] i_unnamed_c_compmm_m2030_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2030_join_q;
    wire [0:0] i_unnamed_c_compmm_m2046_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2046_join_q;
    wire [0:0] i_unnamed_c_compmm_m2059_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2059_join_q;
    wire [0:0] i_unnamed_c_compmm_m2075_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2075_join_q;
    wire [0:0] i_unnamed_c_compmm_m2087_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2087_join_q;
    wire [0:0] i_unnamed_c_compmm_m2103_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2103_join_q;
    wire [0:0] i_unnamed_c_compmm_m2115_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2115_join_q;
    wire [0:0] i_unnamed_c_compmm_m2131_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2131_join_q;
    wire [0:0] i_unnamed_c_compmm_m2143_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2143_join_q;
    wire [0:0] i_unnamed_c_compmm_m2159_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2159_join_q;
    wire [0:0] i_unnamed_c_compmm_m2171_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2171_join_q;
    wire [0:0] i_unnamed_c_compmm_m2187_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2187_join_q;
    wire [0:0] i_unnamed_c_compmm_m2199_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2199_join_q;
    wire [0:0] i_unnamed_c_compmm_m2215_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2215_join_q;
    wire [0:0] i_unnamed_c_compmm_m2227_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2227_join_q;
    wire [0:0] i_unnamed_c_compmm_m2243_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2243_join_q;
    wire [0:0] i_unnamed_c_compmm_m2255_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2255_join_q;
    wire [0:0] i_unnamed_c_compmm_m2271_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2271_join_q;
    wire [0:0] i_unnamed_c_compmm_m2283_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2283_join_q;
    wire [0:0] i_unnamed_c_compmm_m2299_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2299_join_q;
    wire [0:0] i_unnamed_c_compmm_m2311_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2311_join_q;
    wire [0:0] i_unnamed_c_compmm_m2327_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2327_join_q;
    wire [0:0] i_unnamed_c_compmm_m2339_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2339_join_q;
    wire [0:0] i_unnamed_c_compmm_m2355_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2355_join_q;
    wire [0:0] i_unnamed_c_compmm_m2367_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2367_join_q;
    wire [0:0] i_unnamed_c_compmm_m2383_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2383_join_q;
    wire [0:0] i_unnamed_c_compmm_m2395_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2395_join_q;
    wire [0:0] i_unnamed_c_compmm_m2411_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2411_join_q;
    wire [0:0] i_unnamed_c_compmm_m2423_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2423_join_q;
    wire [0:0] i_unnamed_c_compmm_m2439_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2439_join_q;
    wire [0:0] i_unnamed_c_compmm_m2451_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2451_join_q;
    wire [0:0] i_unnamed_c_compmm_m2467_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2467_join_q;
    wire [0:0] i_unnamed_c_compmm_m2479_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2479_join_q;
    wire [0:0] i_unnamed_c_compmm_m2495_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2495_join_q;
    wire [0:0] i_unnamed_c_compmm_m2507_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2507_join_q;
    wire [0:0] i_unnamed_c_compmm_m2523_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2523_join_q;
    wire [0:0] i_unnamed_c_compmm_m2535_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2535_join_q;
    wire [0:0] i_unnamed_c_compmm_m2551_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2551_join_q;
    wire [0:0] i_unnamed_c_compmm_m2563_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2563_join_q;
    wire [0:0] i_unnamed_c_compmm_m2579_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2579_join_q;
    wire [0:0] i_unnamed_c_compmm_m2591_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2591_join_q;
    wire [0:0] i_unnamed_c_compmm_m2607_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2607_join_q;
    wire [0:0] i_unnamed_c_compmm_m2619_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2619_join_q;
    wire [0:0] i_unnamed_c_compmm_m2635_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2635_join_q;
    wire [0:0] i_unnamed_c_compmm_m2647_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2647_join_q;
    wire [0:0] i_unnamed_c_compmm_m2663_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2663_join_q;
    wire [0:0] i_unnamed_c_compmm_m267_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m267_join_q;
    wire [0:0] i_unnamed_c_compmm_m2675_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2675_join_q;
    wire [0:0] i_unnamed_c_compmm_m2691_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2691_join_q;
    wire [0:0] i_unnamed_c_compmm_m2703_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2703_join_q;
    wire [0:0] i_unnamed_c_compmm_m2719_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2719_join_q;
    wire [0:0] i_unnamed_c_compmm_m2731_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2731_join_q;
    wire [0:0] i_unnamed_c_compmm_m2747_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2747_join_q;
    wire [0:0] i_unnamed_c_compmm_m2759_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2759_join_q;
    wire [0:0] i_unnamed_c_compmm_m2775_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2775_join_q;
    wire [0:0] i_unnamed_c_compmm_m2787_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2787_join_q;
    wire [0:0] i_unnamed_c_compmm_m2803_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2803_join_q;
    wire [0:0] i_unnamed_c_compmm_m281_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m281_join_q;
    wire [0:0] i_unnamed_c_compmm_m2815_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2815_join_q;
    wire [0:0] i_unnamed_c_compmm_m2831_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2831_join_q;
    wire [0:0] i_unnamed_c_compmm_m2843_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2843_join_q;
    wire [0:0] i_unnamed_c_compmm_m2859_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2859_join_q;
    wire [0:0] i_unnamed_c_compmm_m2871_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2871_join_q;
    wire [0:0] i_unnamed_c_compmm_m2887_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2887_join_q;
    wire [0:0] i_unnamed_c_compmm_m2899_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2899_join_q;
    wire [0:0] i_unnamed_c_compmm_m2915_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2915_join_q;
    wire [0:0] i_unnamed_c_compmm_m2927_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2927_join_q;
    wire [0:0] i_unnamed_c_compmm_m293_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m293_join_q;
    wire [0:0] i_unnamed_c_compmm_m2943_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2943_join_q;
    wire [0:0] i_unnamed_c_compmm_m2956_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2956_join_q;
    wire [0:0] i_unnamed_c_compmm_m2972_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2972_join_q;
    wire [0:0] i_unnamed_c_compmm_m2984_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m2984_join_q;
    wire [0:0] i_unnamed_c_compmm_m3000_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3000_join_q;
    wire [0:0] i_unnamed_c_compmm_m3012_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3012_join_q;
    wire [0:0] i_unnamed_c_compmm_m3028_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3028_join_q;
    wire [0:0] i_unnamed_c_compmm_m3040_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3040_join_q;
    wire [0:0] i_unnamed_c_compmm_m3056_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3056_join_q;
    wire [0:0] i_unnamed_c_compmm_m3068_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3068_join_q;
    wire [0:0] i_unnamed_c_compmm_m3084_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3084_join_q;
    wire [0:0] i_unnamed_c_compmm_m309_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m309_join_q;
    wire [0:0] i_unnamed_c_compmm_m3096_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3096_join_q;
    wire [0:0] i_unnamed_c_compmm_m3112_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3112_join_q;
    wire [0:0] i_unnamed_c_compmm_m3124_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3124_join_q;
    wire [0:0] i_unnamed_c_compmm_m3140_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3140_join_q;
    wire [0:0] i_unnamed_c_compmm_m3152_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3152_join_q;
    wire [0:0] i_unnamed_c_compmm_m3168_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3168_join_q;
    wire [0:0] i_unnamed_c_compmm_m3180_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3180_join_q;
    wire [0:0] i_unnamed_c_compmm_m3196_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3196_join_q;
    wire [0:0] i_unnamed_c_compmm_m3208_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3208_join_q;
    wire [0:0] i_unnamed_c_compmm_m321_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m321_join_q;
    wire [0:0] i_unnamed_c_compmm_m3224_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3224_join_q;
    wire [0:0] i_unnamed_c_compmm_m3236_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3236_join_q;
    wire [0:0] i_unnamed_c_compmm_m3252_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3252_join_q;
    wire [0:0] i_unnamed_c_compmm_m3264_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3264_join_q;
    wire [0:0] i_unnamed_c_compmm_m3280_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3280_join_q;
    wire [0:0] i_unnamed_c_compmm_m3292_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3292_join_q;
    wire [0:0] i_unnamed_c_compmm_m3308_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3308_join_q;
    wire [0:0] i_unnamed_c_compmm_m3320_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3320_join_q;
    wire [0:0] i_unnamed_c_compmm_m3336_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3336_join_q;
    wire [0:0] i_unnamed_c_compmm_m3348_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3348_join_q;
    wire [0:0] i_unnamed_c_compmm_m3364_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3364_join_q;
    wire [0:0] i_unnamed_c_compmm_m337_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m337_join_q;
    wire [0:0] i_unnamed_c_compmm_m3376_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3376_join_q;
    wire [0:0] i_unnamed_c_compmm_m3392_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3392_join_q;
    wire [0:0] i_unnamed_c_compmm_m3404_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3404_join_q;
    wire [0:0] i_unnamed_c_compmm_m3420_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3420_join_q;
    wire [0:0] i_unnamed_c_compmm_m3432_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3432_join_q;
    wire [0:0] i_unnamed_c_compmm_m3448_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3448_join_q;
    wire [0:0] i_unnamed_c_compmm_m3460_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3460_join_q;
    wire [0:0] i_unnamed_c_compmm_m3476_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3476_join_q;
    wire [0:0] i_unnamed_c_compmm_m3488_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3488_join_q;
    wire [0:0] i_unnamed_c_compmm_m349_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m349_join_q;
    wire [0:0] i_unnamed_c_compmm_m3504_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3504_join_q;
    wire [0:0] i_unnamed_c_compmm_m3516_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3516_join_q;
    wire [0:0] i_unnamed_c_compmm_m3532_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3532_join_q;
    wire [0:0] i_unnamed_c_compmm_m3544_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3544_join_q;
    wire [0:0] i_unnamed_c_compmm_m3560_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3560_join_q;
    wire [0:0] i_unnamed_c_compmm_m3572_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3572_join_q;
    wire [0:0] i_unnamed_c_compmm_m3588_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3588_join_q;
    wire [0:0] i_unnamed_c_compmm_m3600_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3600_join_q;
    wire [0:0] i_unnamed_c_compmm_m3616_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3616_join_q;
    wire [0:0] i_unnamed_c_compmm_m3628_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3628_join_q;
    wire [0:0] i_unnamed_c_compmm_m3644_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3644_join_q;
    wire [0:0] i_unnamed_c_compmm_m365_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m365_join_q;
    wire [0:0] i_unnamed_c_compmm_m3656_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3656_join_q;
    wire [0:0] i_unnamed_c_compmm_m3672_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3672_join_q;
    wire [0:0] i_unnamed_c_compmm_m3684_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3684_join_q;
    wire [0:0] i_unnamed_c_compmm_m3700_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3700_join_q;
    wire [0:0] i_unnamed_c_compmm_m3712_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3712_join_q;
    wire [0:0] i_unnamed_c_compmm_m3728_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3728_join_q;
    wire [0:0] i_unnamed_c_compmm_m3740_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3740_join_q;
    wire [0:0] i_unnamed_c_compmm_m3756_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3756_join_q;
    wire [0:0] i_unnamed_c_compmm_m3768_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3768_join_q;
    wire [0:0] i_unnamed_c_compmm_m377_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m377_join_q;
    wire [0:0] i_unnamed_c_compmm_m3784_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3784_join_q;
    wire [0:0] i_unnamed_c_compmm_m3796_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3796_join_q;
    wire [0:0] i_unnamed_c_compmm_m3812_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3812_join_q;
    wire [0:0] i_unnamed_c_compmm_m3824_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3824_join_q;
    wire [0:0] i_unnamed_c_compmm_m3840_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m3840_join_q;
    wire [0:0] i_unnamed_c_compmm_m393_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m393_join_q;
    wire [0:0] i_unnamed_c_compmm_m405_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m405_join_q;
    wire [0:0] i_unnamed_c_compmm_m421_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m421_join_q;
    wire [0:0] i_unnamed_c_compmm_m433_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m433_join_q;
    wire [0:0] i_unnamed_c_compmm_m449_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m449_join_q;
    wire [0:0] i_unnamed_c_compmm_m461_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m461_join_q;
    wire [0:0] i_unnamed_c_compmm_m477_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m477_join_q;
    wire [0:0] i_unnamed_c_compmm_m489_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m489_join_q;
    wire [0:0] i_unnamed_c_compmm_m505_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m505_join_q;
    wire [0:0] i_unnamed_c_compmm_m517_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m517_join_q;
    wire [0:0] i_unnamed_c_compmm_m533_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m533_join_q;
    wire [0:0] i_unnamed_c_compmm_m545_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m545_join_q;
    wire [0:0] i_unnamed_c_compmm_m561_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m561_join_q;
    wire [0:0] i_unnamed_c_compmm_m573_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m573_join_q;
    wire [0:0] i_unnamed_c_compmm_m589_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m589_join_q;
    wire [0:0] i_unnamed_c_compmm_m601_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m601_join_q;
    wire [0:0] i_unnamed_c_compmm_m617_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m617_join_q;
    wire [0:0] i_unnamed_c_compmm_m629_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m629_join_q;
    wire [0:0] i_unnamed_c_compmm_m645_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m645_join_q;
    wire [0:0] i_unnamed_c_compmm_m657_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m657_join_q;
    wire [0:0] i_unnamed_c_compmm_m673_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m673_join_q;
    wire [0:0] i_unnamed_c_compmm_m685_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m685_join_q;
    wire [0:0] i_unnamed_c_compmm_m701_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m701_join_q;
    wire [0:0] i_unnamed_c_compmm_m713_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m713_join_q;
    wire [0:0] i_unnamed_c_compmm_m729_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m729_join_q;
    wire [0:0] i_unnamed_c_compmm_m741_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m741_join_q;
    wire [0:0] i_unnamed_c_compmm_m757_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m757_join_q;
    wire [0:0] i_unnamed_c_compmm_m769_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m769_join_q;
    wire [0:0] i_unnamed_c_compmm_m785_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m785_join_q;
    wire [0:0] i_unnamed_c_compmm_m797_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m797_join_q;
    wire [0:0] i_unnamed_c_compmm_m813_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m813_join_q;
    wire [0:0] i_unnamed_c_compmm_m825_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m825_join_q;
    wire [0:0] i_unnamed_c_compmm_m841_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m841_join_q;
    wire [0:0] i_unnamed_c_compmm_m853_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m853_join_q;
    wire [0:0] i_unnamed_c_compmm_m869_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m869_join_q;
    wire [0:0] i_unnamed_c_compmm_m881_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m881_join_q;
    wire [0:0] i_unnamed_c_compmm_m897_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m897_join_q;
    wire [0:0] i_unnamed_c_compmm_m909_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m909_join_q;
    wire [0:0] i_unnamed_c_compmm_m925_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m925_join_q;
    wire [0:0] i_unnamed_c_compmm_m937_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m937_join_q;
    wire [0:0] i_unnamed_c_compmm_m953_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m953_join_q;
    wire [0:0] i_unnamed_c_compmm_m965_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m965_join_q;
    wire [0:0] i_unnamed_c_compmm_m981_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m981_join_q;
    wire [0:0] i_unnamed_c_compmm_m993_BitSelect_for_a_b;
    wire [15:0] i_unnamed_c_compmm_m993_join_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1;
    wire [15:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0;
    wire [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq;
    reg [32:0] i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1;
    wire i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena2;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_reset;
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ah [0:1];
    (* preserve_syn_only *) reg signed [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ch [0:1];
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_a0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_c0;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_a1;
    wire [15:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_c1;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_s0;
    wire [0:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_sna;
    wire [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_qq;
    reg [32:0] i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_q;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena0;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena1;
    wire i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena2;
    reg [0:0] redist0_i_unnamed_c_compmm_m3112_BitSelect_for_a_b_1_q;
    reg [0:0] redist1_valid_fanout_reg0_q_7_q;
    reg [0:0] redist2_i_unnamed_c_compmm_m993_vt_select_0_b_1_q;
    reg [0:0] redist3_i_unnamed_c_compmm_m981_vt_select_0_b_1_q;
    reg [0:0] redist4_i_unnamed_c_compmm_m965_vt_select_0_b_1_q;
    reg [0:0] redist5_i_unnamed_c_compmm_m953_vt_select_0_b_1_q;
    reg [0:0] redist6_i_unnamed_c_compmm_m937_vt_select_0_b_1_q;
    reg [0:0] redist7_i_unnamed_c_compmm_m925_vt_select_0_b_1_q;
    reg [0:0] redist8_i_unnamed_c_compmm_m909_vt_select_0_b_1_q;
    reg [0:0] redist9_i_unnamed_c_compmm_m897_vt_select_0_b_1_q;
    reg [0:0] redist10_i_unnamed_c_compmm_m881_vt_select_0_b_1_q;
    reg [0:0] redist11_i_unnamed_c_compmm_m869_vt_select_0_b_1_q;
    reg [0:0] redist12_i_unnamed_c_compmm_m853_vt_select_0_b_1_q;
    reg [0:0] redist13_i_unnamed_c_compmm_m841_vt_select_0_b_1_q;
    reg [0:0] redist14_i_unnamed_c_compmm_m825_vt_select_0_b_1_q;
    reg [0:0] redist15_i_unnamed_c_compmm_m813_vt_select_0_b_1_q;
    reg [0:0] redist16_i_unnamed_c_compmm_m797_vt_select_0_b_1_q;
    reg [0:0] redist17_i_unnamed_c_compmm_m785_vt_select_0_b_1_q;
    reg [0:0] redist18_i_unnamed_c_compmm_m769_vt_select_0_b_1_q;
    reg [0:0] redist19_i_unnamed_c_compmm_m757_vt_select_0_b_1_q;
    reg [0:0] redist20_i_unnamed_c_compmm_m741_vt_select_0_b_1_q;
    reg [0:0] redist21_i_unnamed_c_compmm_m729_vt_select_0_b_1_q;
    reg [0:0] redist22_i_unnamed_c_compmm_m713_vt_select_0_b_1_q;
    reg [0:0] redist23_i_unnamed_c_compmm_m701_vt_select_0_b_1_q;
    reg [0:0] redist24_i_unnamed_c_compmm_m685_vt_select_0_b_1_q;
    reg [0:0] redist25_i_unnamed_c_compmm_m673_vt_select_0_b_1_q;
    reg [0:0] redist26_i_unnamed_c_compmm_m657_vt_select_0_b_1_q;
    reg [0:0] redist27_i_unnamed_c_compmm_m645_vt_select_0_b_1_q;
    reg [0:0] redist28_i_unnamed_c_compmm_m629_vt_select_0_b_1_q;
    reg [0:0] redist29_i_unnamed_c_compmm_m617_vt_select_0_b_1_q;
    reg [0:0] redist30_i_unnamed_c_compmm_m601_vt_select_0_b_1_q;
    reg [0:0] redist31_i_unnamed_c_compmm_m589_vt_select_0_b_1_q;
    reg [0:0] redist32_i_unnamed_c_compmm_m573_vt_select_0_b_1_q;
    reg [0:0] redist33_i_unnamed_c_compmm_m561_vt_select_0_b_1_q;
    reg [0:0] redist34_i_unnamed_c_compmm_m545_vt_select_0_b_1_q;
    reg [0:0] redist35_i_unnamed_c_compmm_m533_vt_select_0_b_1_q;
    reg [0:0] redist36_i_unnamed_c_compmm_m517_vt_select_0_b_1_q;
    reg [0:0] redist37_i_unnamed_c_compmm_m505_vt_select_0_b_1_q;
    reg [0:0] redist38_i_unnamed_c_compmm_m489_vt_select_0_b_1_q;
    reg [0:0] redist39_i_unnamed_c_compmm_m477_vt_select_0_b_1_q;
    reg [0:0] redist40_i_unnamed_c_compmm_m461_vt_select_0_b_1_q;
    reg [0:0] redist41_i_unnamed_c_compmm_m449_vt_select_0_b_1_q;
    reg [0:0] redist42_i_unnamed_c_compmm_m433_vt_select_0_b_1_q;
    reg [0:0] redist43_i_unnamed_c_compmm_m421_vt_select_0_b_1_q;
    reg [0:0] redist44_i_unnamed_c_compmm_m405_vt_select_0_b_1_q;
    reg [0:0] redist45_i_unnamed_c_compmm_m393_vt_select_0_b_1_q;
    reg [0:0] redist46_i_unnamed_c_compmm_m3840_vt_select_0_b_1_q;
    reg [0:0] redist47_i_unnamed_c_compmm_m3824_vt_select_0_b_1_q;
    reg [0:0] redist48_i_unnamed_c_compmm_m3812_vt_select_0_b_1_q;
    reg [0:0] redist49_i_unnamed_c_compmm_m3796_vt_select_0_b_1_q;
    reg [0:0] redist50_i_unnamed_c_compmm_m3784_vt_select_0_b_1_q;
    reg [0:0] redist51_i_unnamed_c_compmm_m377_vt_select_0_b_1_q;
    reg [0:0] redist52_i_unnamed_c_compmm_m3768_vt_select_0_b_1_q;
    reg [0:0] redist53_i_unnamed_c_compmm_m3756_vt_select_0_b_1_q;
    reg [0:0] redist54_i_unnamed_c_compmm_m3740_vt_select_0_b_1_q;
    reg [0:0] redist55_i_unnamed_c_compmm_m3728_vt_select_0_b_1_q;
    reg [0:0] redist56_i_unnamed_c_compmm_m3712_vt_select_0_b_1_q;
    reg [0:0] redist57_i_unnamed_c_compmm_m3700_vt_select_0_b_1_q;
    reg [0:0] redist58_i_unnamed_c_compmm_m3684_vt_select_0_b_1_q;
    reg [0:0] redist59_i_unnamed_c_compmm_m3672_vt_select_0_b_1_q;
    reg [0:0] redist60_i_unnamed_c_compmm_m365_vt_select_0_b_1_q;
    reg [0:0] redist61_i_unnamed_c_compmm_m3656_vt_select_0_b_1_q;
    reg [0:0] redist62_i_unnamed_c_compmm_m3644_vt_select_0_b_1_q;
    reg [0:0] redist63_i_unnamed_c_compmm_m3628_vt_select_0_b_1_q;
    reg [0:0] redist64_i_unnamed_c_compmm_m3616_vt_select_0_b_1_q;
    reg [0:0] redist65_i_unnamed_c_compmm_m3600_vt_select_0_b_1_q;
    reg [0:0] redist66_i_unnamed_c_compmm_m3588_vt_select_0_b_1_q;
    reg [0:0] redist67_i_unnamed_c_compmm_m3572_vt_select_0_b_1_q;
    reg [0:0] redist68_i_unnamed_c_compmm_m3560_vt_select_0_b_1_q;
    reg [0:0] redist69_i_unnamed_c_compmm_m3544_vt_select_0_b_1_q;
    reg [0:0] redist70_i_unnamed_c_compmm_m3532_vt_select_0_b_1_q;
    reg [0:0] redist71_i_unnamed_c_compmm_m3516_vt_select_0_b_1_q;
    reg [0:0] redist72_i_unnamed_c_compmm_m3504_vt_select_0_b_1_q;
    reg [0:0] redist73_i_unnamed_c_compmm_m349_vt_select_0_b_1_q;
    reg [0:0] redist74_i_unnamed_c_compmm_m3488_vt_select_0_b_1_q;
    reg [0:0] redist75_i_unnamed_c_compmm_m3476_vt_select_0_b_1_q;
    reg [0:0] redist76_i_unnamed_c_compmm_m3460_vt_select_0_b_1_q;
    reg [0:0] redist77_i_unnamed_c_compmm_m3448_vt_select_0_b_1_q;
    reg [0:0] redist78_i_unnamed_c_compmm_m3432_vt_select_0_b_1_q;
    reg [0:0] redist79_i_unnamed_c_compmm_m3420_vt_select_0_b_1_q;
    reg [0:0] redist80_i_unnamed_c_compmm_m3404_vt_select_0_b_1_q;
    reg [0:0] redist81_i_unnamed_c_compmm_m3392_vt_select_0_b_1_q;
    reg [0:0] redist82_i_unnamed_c_compmm_m337_vt_select_0_b_1_q;
    reg [0:0] redist83_i_unnamed_c_compmm_m3376_vt_select_0_b_1_q;
    reg [0:0] redist84_i_unnamed_c_compmm_m3364_vt_select_0_b_1_q;
    reg [0:0] redist85_i_unnamed_c_compmm_m3348_vt_select_0_b_1_q;
    reg [0:0] redist86_i_unnamed_c_compmm_m3336_vt_select_0_b_1_q;
    reg [0:0] redist87_i_unnamed_c_compmm_m3320_vt_select_0_b_1_q;
    reg [0:0] redist88_i_unnamed_c_compmm_m3308_vt_select_0_b_1_q;
    reg [0:0] redist89_i_unnamed_c_compmm_m3292_vt_select_0_b_1_q;
    reg [0:0] redist90_i_unnamed_c_compmm_m3280_vt_select_0_b_1_q;
    reg [0:0] redist91_i_unnamed_c_compmm_m3264_vt_select_0_b_1_q;
    reg [0:0] redist92_i_unnamed_c_compmm_m3252_vt_select_0_b_1_q;
    reg [0:0] redist93_i_unnamed_c_compmm_m3236_vt_select_0_b_1_q;
    reg [0:0] redist94_i_unnamed_c_compmm_m3224_vt_select_0_b_1_q;
    reg [0:0] redist95_i_unnamed_c_compmm_m321_vt_select_0_b_1_q;
    reg [0:0] redist96_i_unnamed_c_compmm_m3208_vt_select_0_b_1_q;
    reg [0:0] redist97_i_unnamed_c_compmm_m3196_vt_select_0_b_1_q;
    reg [0:0] redist98_i_unnamed_c_compmm_m3180_vt_select_0_b_1_q;
    reg [0:0] redist99_i_unnamed_c_compmm_m3168_vt_select_0_b_1_q;
    reg [0:0] redist100_i_unnamed_c_compmm_m3152_vt_select_0_b_1_q;
    reg [0:0] redist101_i_unnamed_c_compmm_m3140_vt_select_0_b_1_q;
    reg [0:0] redist102_i_unnamed_c_compmm_m3124_vt_select_0_b_1_q;
    reg [0:0] redist103_i_unnamed_c_compmm_m309_vt_select_0_b_1_q;
    reg [0:0] redist104_i_unnamed_c_compmm_m3096_vt_select_0_b_1_q;
    reg [0:0] redist105_i_unnamed_c_compmm_m3084_vt_select_0_b_1_q;
    reg [0:0] redist106_i_unnamed_c_compmm_m3068_vt_select_0_b_1_q;
    reg [0:0] redist107_i_unnamed_c_compmm_m3056_vt_select_0_b_1_q;
    reg [0:0] redist108_i_unnamed_c_compmm_m3040_vt_select_0_b_1_q;
    reg [0:0] redist109_i_unnamed_c_compmm_m3028_vt_select_0_b_1_q;
    reg [0:0] redist110_i_unnamed_c_compmm_m3012_vt_select_0_b_1_q;
    reg [0:0] redist111_i_unnamed_c_compmm_m3000_vt_select_0_b_1_q;
    reg [0:0] redist112_i_unnamed_c_compmm_m2984_vt_select_0_b_1_q;
    reg [0:0] redist113_i_unnamed_c_compmm_m2972_vt_select_0_b_1_q;
    reg [0:0] redist114_i_unnamed_c_compmm_m2956_vt_select_0_b_1_q;
    reg [0:0] redist115_i_unnamed_c_compmm_m2943_vt_select_0_b_1_q;
    reg [0:0] redist116_i_unnamed_c_compmm_m293_vt_select_0_b_1_q;
    reg [0:0] redist117_i_unnamed_c_compmm_m2927_vt_select_0_b_1_q;
    reg [0:0] redist118_i_unnamed_c_compmm_m2915_vt_select_0_b_1_q;
    reg [0:0] redist119_i_unnamed_c_compmm_m2899_vt_select_0_b_1_q;
    reg [0:0] redist120_i_unnamed_c_compmm_m2887_vt_select_0_b_1_q;
    reg [0:0] redist121_i_unnamed_c_compmm_m2871_vt_select_0_b_1_q;
    reg [0:0] redist122_i_unnamed_c_compmm_m2859_vt_select_0_b_1_q;
    reg [0:0] redist123_i_unnamed_c_compmm_m2843_vt_select_0_b_1_q;
    reg [0:0] redist124_i_unnamed_c_compmm_m2831_vt_select_0_b_1_q;
    reg [0:0] redist125_i_unnamed_c_compmm_m2815_vt_select_0_b_1_q;
    reg [0:0] redist126_i_unnamed_c_compmm_m2803_vt_select_0_b_1_q;
    reg [0:0] redist127_i_unnamed_c_compmm_m2787_vt_select_0_b_1_q;
    reg [0:0] redist128_i_unnamed_c_compmm_m2775_vt_select_0_b_1_q;
    reg [0:0] redist129_i_unnamed_c_compmm_m2759_vt_select_0_b_1_q;
    reg [0:0] redist130_i_unnamed_c_compmm_m2747_vt_select_0_b_1_q;
    reg [0:0] redist131_i_unnamed_c_compmm_m2731_vt_select_0_b_1_q;
    reg [0:0] redist132_i_unnamed_c_compmm_m2719_vt_select_0_b_1_q;
    reg [0:0] redist133_i_unnamed_c_compmm_m2703_vt_select_0_b_1_q;
    reg [0:0] redist134_i_unnamed_c_compmm_m2691_vt_select_0_b_1_q;
    reg [0:0] redist135_i_unnamed_c_compmm_m2675_vt_select_0_b_1_q;
    reg [0:0] redist136_i_unnamed_c_compmm_m2663_vt_select_0_b_1_q;
    reg [0:0] redist137_i_unnamed_c_compmm_m2647_vt_select_0_b_1_q;
    reg [0:0] redist138_i_unnamed_c_compmm_m2635_vt_select_0_b_1_q;
    reg [0:0] redist139_i_unnamed_c_compmm_m2619_vt_select_0_b_1_q;
    reg [0:0] redist140_i_unnamed_c_compmm_m2607_vt_select_0_b_1_q;
    reg [0:0] redist141_i_unnamed_c_compmm_m2591_vt_select_0_b_1_q;
    reg [0:0] redist142_i_unnamed_c_compmm_m2579_vt_select_0_b_1_q;
    reg [0:0] redist143_i_unnamed_c_compmm_m2563_vt_select_0_b_1_q;
    reg [0:0] redist144_i_unnamed_c_compmm_m2551_vt_select_0_b_1_q;
    reg [0:0] redist145_i_unnamed_c_compmm_m2535_vt_select_0_b_1_q;
    reg [0:0] redist146_i_unnamed_c_compmm_m2523_vt_select_0_b_1_q;
    reg [0:0] redist147_i_unnamed_c_compmm_m2507_vt_select_0_b_1_q;
    reg [0:0] redist148_i_unnamed_c_compmm_m2495_vt_select_0_b_1_q;
    reg [0:0] redist149_i_unnamed_c_compmm_m2479_vt_select_0_b_1_q;
    reg [0:0] redist150_i_unnamed_c_compmm_m2467_vt_select_0_b_1_q;
    reg [0:0] redist151_i_unnamed_c_compmm_m2451_vt_select_0_b_1_q;
    reg [0:0] redist152_i_unnamed_c_compmm_m2439_vt_select_0_b_1_q;
    reg [0:0] redist153_i_unnamed_c_compmm_m2423_vt_select_0_b_1_q;
    reg [0:0] redist154_i_unnamed_c_compmm_m2411_vt_select_0_b_1_q;
    reg [0:0] redist155_i_unnamed_c_compmm_m2395_vt_select_0_b_1_q;
    reg [0:0] redist156_i_unnamed_c_compmm_m2383_vt_select_0_b_1_q;
    reg [0:0] redist157_i_unnamed_c_compmm_m2367_vt_select_0_b_1_q;
    reg [0:0] redist158_i_unnamed_c_compmm_m2355_vt_select_0_b_1_q;
    reg [0:0] redist159_i_unnamed_c_compmm_m2339_vt_select_0_b_1_q;
    reg [0:0] redist160_i_unnamed_c_compmm_m2327_vt_select_0_b_1_q;
    reg [0:0] redist161_i_unnamed_c_compmm_m2311_vt_select_0_b_1_q;
    reg [0:0] redist162_i_unnamed_c_compmm_m2299_vt_select_0_b_1_q;
    reg [0:0] redist163_i_unnamed_c_compmm_m2283_vt_select_0_b_1_q;
    reg [0:0] redist164_i_unnamed_c_compmm_m2271_vt_select_0_b_1_q;
    reg [0:0] redist165_i_unnamed_c_compmm_m2255_vt_select_0_b_1_q;
    reg [0:0] redist166_i_unnamed_c_compmm_m2243_vt_select_0_b_1_q;
    reg [0:0] redist167_i_unnamed_c_compmm_m2227_vt_select_0_b_1_q;
    reg [0:0] redist168_i_unnamed_c_compmm_m2215_vt_select_0_b_1_q;
    reg [0:0] redist169_i_unnamed_c_compmm_m2199_vt_select_0_b_1_q;
    reg [0:0] redist170_i_unnamed_c_compmm_m2187_vt_select_0_b_1_q;
    reg [0:0] redist171_i_unnamed_c_compmm_m2171_vt_select_0_b_1_q;
    reg [0:0] redist172_i_unnamed_c_compmm_m2159_vt_select_0_b_1_q;
    reg [0:0] redist173_i_unnamed_c_compmm_m2143_vt_select_0_b_1_q;
    reg [0:0] redist174_i_unnamed_c_compmm_m2131_vt_select_0_b_1_q;
    reg [0:0] redist175_i_unnamed_c_compmm_m2115_vt_select_0_b_1_q;
    reg [0:0] redist176_i_unnamed_c_compmm_m2103_vt_select_0_b_1_q;
    reg [0:0] redist177_i_unnamed_c_compmm_m2087_vt_select_0_b_1_q;
    reg [0:0] redist178_i_unnamed_c_compmm_m2075_vt_select_0_b_1_q;
    reg [0:0] redist179_i_unnamed_c_compmm_m2059_vt_select_0_b_1_q;
    reg [0:0] redist180_i_unnamed_c_compmm_m2046_vt_select_0_b_1_q;
    reg [0:0] redist181_i_unnamed_c_compmm_m2030_vt_select_0_b_1_q;
    reg [0:0] redist182_i_unnamed_c_compmm_m2018_vt_select_0_b_1_q;
    reg [0:0] redist183_i_unnamed_c_compmm_m2002_vt_select_0_b_1_q;
    reg [0:0] redist184_i_unnamed_c_compmm_m1990_vt_select_0_b_1_q;
    reg [0:0] redist185_i_unnamed_c_compmm_m1974_vt_select_0_b_1_q;
    reg [0:0] redist186_i_unnamed_c_compmm_m1962_vt_select_0_b_1_q;
    reg [0:0] redist187_i_unnamed_c_compmm_m1946_vt_select_0_b_1_q;
    reg [0:0] redist188_i_unnamed_c_compmm_m1934_vt_select_0_b_1_q;
    reg [0:0] redist189_i_unnamed_c_compmm_m1918_vt_select_0_b_1_q;
    reg [0:0] redist190_i_unnamed_c_compmm_m1906_vt_select_0_b_1_q;
    reg [0:0] redist191_i_unnamed_c_compmm_m1890_vt_select_0_b_1_q;
    reg [0:0] redist192_i_unnamed_c_compmm_m1878_vt_select_0_b_1_q;
    reg [0:0] redist193_i_unnamed_c_compmm_m1862_vt_select_0_b_1_q;
    reg [0:0] redist194_i_unnamed_c_compmm_m1850_vt_select_0_b_1_q;
    reg [0:0] redist195_i_unnamed_c_compmm_m1834_vt_select_0_b_1_q;
    reg [0:0] redist196_i_unnamed_c_compmm_m1822_vt_select_0_b_1_q;
    reg [0:0] redist197_i_unnamed_c_compmm_m1806_vt_select_0_b_1_q;
    reg [0:0] redist198_i_unnamed_c_compmm_m1794_vt_select_0_b_1_q;
    reg [0:0] redist199_i_unnamed_c_compmm_m1778_vt_select_0_b_1_q;
    reg [0:0] redist200_i_unnamed_c_compmm_m1766_vt_select_0_b_1_q;
    reg [0:0] redist201_i_unnamed_c_compmm_m1750_vt_select_0_b_1_q;
    reg [0:0] redist202_i_unnamed_c_compmm_m1738_vt_select_0_b_1_q;
    reg [0:0] redist203_i_unnamed_c_compmm_m1722_vt_select_0_b_1_q;
    reg [0:0] redist204_i_unnamed_c_compmm_m1710_vt_select_0_b_1_q;
    reg [0:0] redist205_i_unnamed_c_compmm_m1694_vt_select_0_b_1_q;
    reg [0:0] redist206_i_unnamed_c_compmm_m1682_vt_select_0_b_1_q;
    reg [0:0] redist207_i_unnamed_c_compmm_m1666_vt_select_0_b_1_q;
    reg [0:0] redist208_i_unnamed_c_compmm_m1654_vt_select_0_b_1_q;
    reg [0:0] redist209_i_unnamed_c_compmm_m1638_vt_select_0_b_1_q;
    reg [0:0] redist210_i_unnamed_c_compmm_m1626_vt_select_0_b_1_q;
    reg [0:0] redist211_i_unnamed_c_compmm_m1610_vt_select_0_b_1_q;
    reg [0:0] redist212_i_unnamed_c_compmm_m1598_vt_select_0_b_1_q;
    reg [0:0] redist213_i_unnamed_c_compmm_m1582_vt_select_0_b_1_q;
    reg [0:0] redist214_i_unnamed_c_compmm_m1570_vt_select_0_b_1_q;
    reg [0:0] redist215_i_unnamed_c_compmm_m1554_vt_select_0_b_1_q;
    reg [0:0] redist216_i_unnamed_c_compmm_m1542_vt_select_0_b_1_q;
    reg [0:0] redist217_i_unnamed_c_compmm_m1526_vt_select_0_b_1_q;
    reg [0:0] redist218_i_unnamed_c_compmm_m1514_vt_select_0_b_1_q;
    reg [0:0] redist219_i_unnamed_c_compmm_m1498_vt_select_0_b_1_q;
    reg [0:0] redist220_i_unnamed_c_compmm_m1486_vt_select_0_b_1_q;
    reg [0:0] redist221_i_unnamed_c_compmm_m1470_vt_select_0_b_1_q;
    reg [0:0] redist222_i_unnamed_c_compmm_m1458_vt_select_0_b_1_q;
    reg [0:0] redist223_i_unnamed_c_compmm_m1442_vt_select_0_b_1_q;
    reg [0:0] redist224_i_unnamed_c_compmm_m1430_vt_select_0_b_1_q;
    reg [0:0] redist225_i_unnamed_c_compmm_m1414_vt_select_0_b_1_q;
    reg [0:0] redist226_i_unnamed_c_compmm_m1402_vt_select_0_b_1_q;
    reg [0:0] redist227_i_unnamed_c_compmm_m1386_vt_select_0_b_1_q;
    reg [0:0] redist228_i_unnamed_c_compmm_m1374_vt_select_0_b_1_q;
    reg [0:0] redist229_i_unnamed_c_compmm_m1358_vt_select_0_b_1_q;
    reg [0:0] redist230_i_unnamed_c_compmm_m1346_vt_select_0_b_1_q;
    reg [0:0] redist231_i_unnamed_c_compmm_m1330_vt_select_0_b_1_q;
    reg [0:0] redist232_i_unnamed_c_compmm_m1318_vt_select_0_b_1_q;
    reg [0:0] redist233_i_unnamed_c_compmm_m1302_vt_select_0_b_1_q;
    reg [0:0] redist234_i_unnamed_c_compmm_m1290_vt_select_0_b_1_q;
    reg [0:0] redist235_i_unnamed_c_compmm_m1274_vt_select_0_b_1_q;
    reg [0:0] redist236_i_unnamed_c_compmm_m1262_vt_select_0_b_1_q;
    reg [0:0] redist237_i_unnamed_c_compmm_m1246_vt_select_0_b_1_q;
    reg [0:0] redist238_i_unnamed_c_compmm_m1234_vt_select_0_b_1_q;
    reg [0:0] redist239_i_unnamed_c_compmm_m1218_vt_select_0_b_1_q;
    reg [0:0] redist240_i_unnamed_c_compmm_m1206_vt_select_0_b_1_q;
    reg [0:0] redist241_i_unnamed_c_compmm_m1190_vt_select_0_b_1_q;
    reg [0:0] redist242_i_unnamed_c_compmm_m1178_vt_select_0_b_1_q;
    reg [0:0] redist243_i_unnamed_c_compmm_m1162_vt_select_0_b_1_q;
    reg [0:0] redist244_i_unnamed_c_compmm_m1149_vt_select_0_b_1_q;
    reg [0:0] redist245_i_unnamed_c_compmm_m1133_vt_select_0_b_1_q;
    reg [0:0] redist246_i_unnamed_c_compmm_m1121_vt_select_0_b_1_q;
    reg [0:0] redist247_i_unnamed_c_compmm_m1105_vt_select_0_b_1_q;
    reg [0:0] redist248_i_unnamed_c_compmm_m1093_vt_select_0_b_1_q;
    reg [0:0] redist249_i_unnamed_c_compmm_m1077_vt_select_0_b_1_q;
    reg [0:0] redist250_i_unnamed_c_compmm_m1065_vt_select_0_b_1_q;
    reg [0:0] redist251_i_unnamed_c_compmm_m1049_vt_select_0_b_1_q;
    reg [0:0] redist252_i_unnamed_c_compmm_m1037_vt_select_0_b_1_q;
    reg [0:0] redist253_i_unnamed_c_compmm_m1021_vt_select_0_b_1_q;
    reg [0:0] redist254_i_unnamed_c_compmm_m1009_vt_select_0_b_1_q;
    reg [15:0] redist255_i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28_b_1_q;
    reg [15:0] redist256_i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28_b_1_q;
    reg [15:0] redist257_i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28_b_1_q;
    reg [15:0] redist258_i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28_b_1_q;
    reg [15:0] redist259_i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28_b_1_q;
    reg [15:0] redist260_i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28_b_1_q;
    reg [15:0] redist261_i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28_b_1_q;
    reg [15:0] redist262_i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28_b_1_q;
    reg [15:0] redist263_i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28_b_1_q;
    reg [15:0] redist264_i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28_b_1_q;
    reg [15:0] redist265_i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28_b_1_q;
    reg [15:0] redist266_i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28_b_1_q;
    reg [15:0] redist267_i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28_b_1_q;
    reg [15:0] redist268_i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28_b_1_q;
    reg [15:0] redist269_i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28_b_1_q;
    reg [15:0] redist270_i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28_b_1_q;
    reg [15:0] redist271_i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28_b_1_q;
    reg [15:0] redist272_i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28_b_1_q;
    reg [15:0] redist273_i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28_b_1_q;
    reg [15:0] redist274_i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28_b_1_q;
    reg [15:0] redist275_i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28_b_1_q;
    reg [15:0] redist276_i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28_b_1_q;
    reg [15:0] redist277_i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28_b_1_q;
    reg [15:0] redist278_i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28_b_1_q;
    reg [15:0] redist279_i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28_b_1_q;
    reg [15:0] redist280_i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28_b_1_q;
    reg [15:0] redist281_i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28_b_1_q;
    reg [15:0] redist282_i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28_b_1_q;
    reg [15:0] redist283_i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28_b_1_q;
    reg [15:0] redist284_i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28_b_1_q;
    reg [15:0] redist285_i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28_b_1_q;
    reg [15:0] redist286_i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28_b_1_q;
    reg [15:0] redist287_i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28_b_1_q;
    reg [15:0] redist288_i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28_b_1_q;
    reg [15:0] redist289_i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28_b_1_q;
    reg [15:0] redist290_i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28_b_1_q;
    reg [15:0] redist291_i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28_b_1_q;
    reg [15:0] redist292_i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28_b_1_q;
    reg [15:0] redist293_i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28_b_1_q;
    reg [15:0] redist294_i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28_b_1_q;
    reg [15:0] redist295_i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28_b_1_q;
    reg [15:0] redist296_i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28_b_1_q;
    reg [15:0] redist297_i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28_b_1_q;
    reg [15:0] redist298_i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28_b_1_q;
    reg [15:0] redist299_i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28_b_1_q;
    reg [15:0] redist300_i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28_b_1_q;
    reg [15:0] redist301_i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28_b_1_q;
    reg [15:0] redist302_i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28_b_1_q;
    reg [15:0] redist303_i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28_b_1_q;
    reg [15:0] redist304_i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28_b_1_q;
    reg [15:0] redist305_i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28_b_1_q;
    reg [15:0] redist306_i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28_b_1_q;
    reg [15:0] redist307_i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28_b_1_q;
    reg [15:0] redist308_i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28_b_1_q;
    reg [15:0] redist309_i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28_b_1_q;
    reg [15:0] redist310_i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28_b_1_q;
    reg [15:0] redist311_i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28_b_1_q;
    reg [15:0] redist312_i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28_b_1_q;
    reg [15:0] redist313_i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28_b_1_q;
    reg [15:0] redist314_i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28_b_1_q;
    reg [15:0] redist315_i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28_b_1_q;
    reg [15:0] redist316_i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28_b_1_q;
    reg [15:0] redist317_i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28_b_1_q;
    reg [15:0] redist318_i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28_b_1_q;
    reg [15:0] redist319_i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28_b_1_q;
    reg [15:0] redist320_i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28_b_1_q;
    reg [15:0] redist321_i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28_b_1_q;
    reg [15:0] redist322_i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28_b_1_q;
    reg [15:0] redist323_i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28_b_1_q;
    reg [15:0] redist324_i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28_b_1_q;
    reg [15:0] redist325_i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28_b_1_q;
    reg [15:0] redist326_i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28_b_1_q;
    reg [15:0] redist327_i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28_b_1_q;
    reg [15:0] redist328_i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28_b_1_q;
    reg [15:0] redist329_i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28_b_1_q;
    reg [15:0] redist330_i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28_b_1_q;
    reg [15:0] redist331_i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28_b_1_q;
    reg [15:0] redist332_i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28_b_1_q;
    reg [15:0] redist333_i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28_b_1_q;
    reg [15:0] redist334_i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28_b_1_q;
    reg [15:0] redist335_i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28_b_1_q;
    reg [15:0] redist336_i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28_b_1_q;
    reg [15:0] redist337_i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28_b_1_q;
    reg [15:0] redist338_i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28_b_1_q;
    reg [15:0] redist339_i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28_b_1_q;
    reg [15:0] redist340_i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28_b_1_q;
    reg [15:0] redist341_i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28_b_1_q;
    reg [15:0] redist342_i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28_b_1_q;
    reg [15:0] redist343_i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28_b_1_q;
    reg [15:0] redist344_i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28_b_1_q;
    reg [15:0] redist345_i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28_b_1_q;
    reg [15:0] redist346_i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28_b_1_q;
    reg [15:0] redist347_i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28_b_1_q;
    reg [15:0] redist348_i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28_b_1_q;
    reg [15:0] redist349_i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28_b_1_q;
    reg [15:0] redist350_i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28_b_1_q;
    reg [15:0] redist351_i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28_b_1_q;
    reg [15:0] redist352_i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28_b_1_q;
    reg [15:0] redist353_i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28_b_1_q;
    reg [15:0] redist354_i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28_b_1_q;
    reg [15:0] redist355_i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28_b_1_q;
    reg [15:0] redist356_i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28_b_1_q;
    reg [15:0] redist357_i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28_b_1_q;
    reg [15:0] redist358_i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28_b_1_q;
    reg [15:0] redist359_i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28_b_1_q;
    reg [15:0] redist360_i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28_b_1_q;
    reg [15:0] redist361_i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28_b_1_q;
    reg [15:0] redist362_i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28_b_1_q;
    reg [15:0] redist363_i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28_b_1_q;
    reg [15:0] redist364_i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28_b_1_q;
    reg [15:0] redist365_i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28_b_1_q;
    reg [15:0] redist366_i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28_b_1_q;
    reg [15:0] redist367_i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28_b_1_q;
    reg [15:0] redist368_i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28_b_1_q;
    reg [15:0] redist369_i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28_b_1_q;
    reg [15:0] redist370_i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28_b_1_q;
    reg [15:0] redist371_i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28_b_1_q;
    reg [15:0] redist372_i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28_b_1_q;
    reg [15:0] redist373_i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28_b_1_q;
    reg [15:0] redist374_i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28_b_1_q;
    reg [15:0] redist375_i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28_b_1_q;
    reg [15:0] redist376_i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28_b_1_q;
    reg [15:0] redist377_i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28_b_1_q;
    reg [15:0] redist378_i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28_b_1_q;
    reg [15:0] redist379_i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28_b_1_q;
    reg [15:0] redist380_i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28_b_1_q;
    reg [15:0] redist381_i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28_b_1_q;
    reg [15:0] redist382_i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28_b_1_q;
    reg [15:0] redist383_i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28_b_1_q;
    reg [15:0] redist384_i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28_b_1_q;
    reg [15:0] redist385_i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28_b_1_q;
    reg [15:0] redist386_i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28_b_1_q;
    reg [15:0] redist387_i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28_b_1_q;
    reg [15:0] redist388_i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28_b_1_q;
    reg [15:0] redist389_i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28_b_1_q;
    reg [15:0] redist390_i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28_b_1_q;
    reg [15:0] redist391_i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28_b_1_q;
    reg [15:0] redist392_i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28_b_1_q;
    reg [15:0] redist393_i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28_b_1_q;
    reg [15:0] redist394_i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28_b_1_q;
    reg [15:0] redist395_i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28_b_1_q;
    reg [15:0] redist396_i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28_b_1_q;
    reg [15:0] redist397_i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28_b_1_q;
    reg [15:0] redist398_i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28_b_1_q;
    reg [15:0] redist399_i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28_b_1_q;
    reg [15:0] redist400_i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28_b_1_q;
    reg [15:0] redist401_i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28_b_1_q;
    reg [15:0] redist402_i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28_b_1_q;
    reg [15:0] redist403_i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28_b_1_q;
    reg [15:0] redist404_i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28_b_1_q;
    reg [15:0] redist405_i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28_b_1_q;
    reg [15:0] redist406_i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28_b_1_q;
    reg [15:0] redist407_i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28_b_1_q;
    reg [15:0] redist408_i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28_b_1_q;
    reg [15:0] redist409_i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28_b_1_q;
    reg [15:0] redist410_i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28_b_1_q;
    reg [15:0] redist411_i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28_b_1_q;
    reg [15:0] redist412_i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28_b_1_q;
    reg [15:0] redist413_i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28_b_1_q;
    reg [15:0] redist414_i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28_b_1_q;
    reg [15:0] redist415_i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28_b_1_q;
    reg [15:0] redist416_i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28_b_1_q;
    reg [15:0] redist417_i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28_b_1_q;
    reg [15:0] redist418_i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28_b_1_q;
    reg [15:0] redist419_i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28_b_1_q;
    reg [15:0] redist420_i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28_b_1_q;
    reg [15:0] redist421_i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28_b_1_q;
    reg [15:0] redist422_i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28_b_1_q;
    reg [15:0] redist423_i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28_b_1_q;
    reg [15:0] redist424_i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28_b_1_q;
    reg [15:0] redist425_i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28_b_1_q;
    reg [15:0] redist426_i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28_b_1_q;
    reg [15:0] redist427_i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28_b_1_q;
    reg [15:0] redist428_i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28_b_1_q;
    reg [15:0] redist429_i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28_b_1_q;
    reg [15:0] redist430_i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28_b_1_q;
    reg [15:0] redist431_i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28_b_1_q;
    reg [15:0] redist432_i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28_b_1_q;
    reg [15:0] redist433_i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28_b_1_q;
    reg [15:0] redist434_i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28_b_1_q;
    reg [15:0] redist435_i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28_b_1_q;
    reg [15:0] redist436_i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28_b_1_q;
    reg [15:0] redist437_i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28_b_1_q;
    reg [15:0] redist438_i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28_b_1_q;
    reg [15:0] redist439_i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28_b_1_q;
    reg [15:0] redist440_i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28_b_1_q;
    reg [15:0] redist441_i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28_b_1_q;
    reg [15:0] redist442_i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28_b_1_q;
    reg [15:0] redist443_i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28_b_1_q;
    reg [15:0] redist444_i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28_b_1_q;
    reg [15:0] redist445_i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28_b_1_q;
    reg [15:0] redist446_i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28_b_1_q;
    reg [15:0] redist447_i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28_b_1_q;
    reg [15:0] redist448_i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28_b_1_q;
    reg [15:0] redist449_i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28_b_1_q;
    reg [15:0] redist450_i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28_b_1_q;
    reg [15:0] redist451_i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28_b_1_q;
    reg [15:0] redist452_i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28_b_1_q;
    reg [15:0] redist453_i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28_b_1_q;
    reg [15:0] redist454_i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28_b_1_q;
    reg [15:0] redist455_i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28_b_1_q;
    reg [15:0] redist456_i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28_b_1_q;
    reg [15:0] redist457_i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28_b_1_q;
    reg [15:0] redist458_i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28_b_1_q;
    reg [15:0] redist459_i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28_b_1_q;
    reg [15:0] redist460_i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28_b_1_q;
    reg [15:0] redist461_i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28_b_1_q;
    reg [15:0] redist462_i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28_b_1_q;
    reg [15:0] redist463_i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28_b_1_q;
    reg [15:0] redist464_i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28_b_1_q;
    reg [15:0] redist465_i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28_b_1_q;
    reg [15:0] redist466_i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28_b_1_q;
    reg [15:0] redist467_i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28_b_1_q;
    reg [15:0] redist468_i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28_b_1_q;
    reg [15:0] redist469_i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28_b_1_q;
    reg [15:0] redist470_i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28_b_1_q;
    reg [15:0] redist471_i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28_b_1_q;
    reg [15:0] redist472_i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28_b_1_q;
    reg [15:0] redist473_i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28_b_1_q;
    reg [15:0] redist474_i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28_b_1_q;
    reg [15:0] redist475_i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28_b_1_q;
    reg [15:0] redist476_i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28_b_1_q;
    reg [15:0] redist477_i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28_b_1_q;
    reg [15:0] redist478_i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28_b_1_q;
    reg [15:0] redist479_i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28_b_1_q;
    reg [15:0] redist480_i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28_b_1_q;
    reg [15:0] redist481_i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28_b_1_q;
    reg [15:0] redist482_i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28_b_1_q;
    reg [15:0] redist483_i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28_b_1_q;
    reg [15:0] redist484_i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28_b_1_q;
    reg [15:0] redist485_i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28_b_1_q;
    reg [15:0] redist486_i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28_b_1_q;
    reg [15:0] redist487_i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28_b_1_q;
    reg [15:0] redist488_i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28_b_1_q;
    reg [15:0] redist489_i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28_b_1_q;
    reg [15:0] redist490_i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28_b_1_q;
    reg [15:0] redist491_i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28_b_1_q;
    reg [15:0] redist492_i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28_b_1_q;
    reg [15:0] redist493_i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28_b_1_q;
    reg [15:0] redist494_i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28_b_1_q;
    reg [15:0] redist495_i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28_b_1_q;
    reg [15:0] redist496_i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28_b_1_q;
    reg [15:0] redist497_i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28_b_1_q;
    reg [15:0] redist498_i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28_b_1_q;
    reg [15:0] redist499_i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28_b_1_q;
    reg [15:0] redist500_i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28_b_1_q;
    reg [15:0] redist501_i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28_b_1_q;
    reg [15:0] redist502_i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28_b_1_q;
    reg [15:0] redist503_sync_together4364_aunroll_x_in_c1_eni5_1_tpl_1_q;
    reg [15:0] redist504_sync_together4364_aunroll_x_in_c1_eni5_2_tpl_1_q;
    reg [15:0] redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2_q;
    reg [15:0] redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2_delay_0;
    reg [15:0] redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2_q;
    reg [15:0] redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2_delay_0;
    reg [15:0] redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_q;
    reg [15:0] redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_delay_0;
    reg [15:0] redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_delay_1;
    reg [15:0] redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_q;
    reg [15:0] redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_delay_0;
    reg [15:0] redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_delay_1;
    reg [15:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_q;
    reg [15:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_q;
    reg [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_q;
    reg [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_delay_0;
    reg [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_delay_1;
    reg [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_q;
    reg [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_delay_0;
    reg [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_delay_1;
    reg [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_q;
    reg [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_delay_0;
    reg [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_delay_1;
    reg [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_q;
    reg [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_delay_0;
    reg [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_delay_1;
    reg [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_q;
    reg [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_delay_0;
    reg [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_q;
    reg [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_delay_0;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_q;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_delay_0;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_delay_1;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_q;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_delay_0;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_delay_1;
    reg [0:0] redist760_sync_together4364_aunroll_x_in_i_valid_1_q;
    reg [0:0] redist761_sync_together4364_aunroll_x_in_i_valid_3_q;
    reg [0:0] redist761_sync_together4364_aunroll_x_in_i_valid_3_delay_0;
    reg [0:0] redist762_sync_together4364_aunroll_x_in_i_valid_5_q;
    reg [0:0] redist762_sync_together4364_aunroll_x_in_i_valid_5_delay_0;
    reg [0:0] redist763_sync_together4364_aunroll_x_in_i_valid_7_q;
    reg [0:0] redist763_sync_together4364_aunroll_x_in_i_valid_7_delay_0;
    reg [0:0] redist764_sync_together4364_aunroll_x_in_i_valid_9_q;
    reg [0:0] redist764_sync_together4364_aunroll_x_in_i_valid_9_delay_0;
    reg [0:0] redist765_sync_together4364_aunroll_x_in_i_valid_11_q;
    reg [0:0] redist765_sync_together4364_aunroll_x_in_i_valid_11_delay_0;
    reg [0:0] redist766_sync_together4364_aunroll_x_in_i_valid_13_q;
    reg [0:0] redist766_sync_together4364_aunroll_x_in_i_valid_13_delay_0;
    reg [0:0] redist767_sync_together4364_aunroll_x_in_i_valid_15_q;
    reg [0:0] redist767_sync_together4364_aunroll_x_in_i_valid_15_delay_0;
    reg [0:0] redist768_sync_together4364_aunroll_x_in_i_valid_17_q;
    reg [0:0] redist768_sync_together4364_aunroll_x_in_i_valid_17_delay_0;
    reg [0:0] redist769_sync_together4364_aunroll_x_in_i_valid_19_q;
    reg [0:0] redist769_sync_together4364_aunroll_x_in_i_valid_19_delay_0;
    reg [0:0] redist770_sync_together4364_aunroll_x_in_i_valid_21_q;
    reg [0:0] redist770_sync_together4364_aunroll_x_in_i_valid_21_delay_0;
    reg [0:0] redist771_sync_together4364_aunroll_x_in_i_valid_23_q;
    reg [0:0] redist771_sync_together4364_aunroll_x_in_i_valid_23_delay_0;
    reg [0:0] redist772_sync_together4364_aunroll_x_in_i_valid_25_q;
    reg [0:0] redist772_sync_together4364_aunroll_x_in_i_valid_25_delay_0;
    reg [0:0] redist773_sync_together4364_aunroll_x_in_i_valid_27_q;
    reg [0:0] redist773_sync_together4364_aunroll_x_in_i_valid_27_delay_0;
    reg [0:0] redist774_sync_together4364_aunroll_x_in_i_valid_29_q;
    reg [0:0] redist774_sync_together4364_aunroll_x_in_i_valid_29_delay_0;
    reg [0:0] redist775_sync_together4364_aunroll_x_in_i_valid_31_q;
    reg [0:0] redist775_sync_together4364_aunroll_x_in_i_valid_31_delay_0;
    reg [0:0] redist776_sync_together4364_aunroll_x_in_i_valid_33_q;
    reg [0:0] redist776_sync_together4364_aunroll_x_in_i_valid_33_delay_0;
    reg [0:0] redist777_sync_together4364_aunroll_x_in_i_valid_35_q;
    reg [0:0] redist777_sync_together4364_aunroll_x_in_i_valid_35_delay_0;
    reg [0:0] redist778_sync_together4364_aunroll_x_in_i_valid_37_q;
    reg [0:0] redist778_sync_together4364_aunroll_x_in_i_valid_37_delay_0;
    reg [0:0] redist779_sync_together4364_aunroll_x_in_i_valid_39_q;
    reg [0:0] redist779_sync_together4364_aunroll_x_in_i_valid_39_delay_0;
    reg [0:0] redist780_sync_together4364_aunroll_x_in_i_valid_41_q;
    reg [0:0] redist780_sync_together4364_aunroll_x_in_i_valid_41_delay_0;
    reg [0:0] redist781_sync_together4364_aunroll_x_in_i_valid_43_q;
    reg [0:0] redist781_sync_together4364_aunroll_x_in_i_valid_43_delay_0;
    reg [0:0] redist782_sync_together4364_aunroll_x_in_i_valid_45_q;
    reg [0:0] redist782_sync_together4364_aunroll_x_in_i_valid_45_delay_0;
    reg [0:0] redist783_sync_together4364_aunroll_x_in_i_valid_47_q;
    reg [0:0] redist783_sync_together4364_aunroll_x_in_i_valid_47_delay_0;
    reg [0:0] redist784_sync_together4364_aunroll_x_in_i_valid_49_q;
    reg [0:0] redist784_sync_together4364_aunroll_x_in_i_valid_49_delay_0;
    reg [0:0] redist785_sync_together4364_aunroll_x_in_i_valid_51_q;
    reg [0:0] redist785_sync_together4364_aunroll_x_in_i_valid_51_delay_0;
    reg [0:0] redist786_sync_together4364_aunroll_x_in_i_valid_53_q;
    reg [0:0] redist786_sync_together4364_aunroll_x_in_i_valid_53_delay_0;
    reg [0:0] redist787_sync_together4364_aunroll_x_in_i_valid_55_q;
    reg [0:0] redist787_sync_together4364_aunroll_x_in_i_valid_55_delay_0;
    reg [0:0] redist788_sync_together4364_aunroll_x_in_i_valid_57_q;
    reg [0:0] redist788_sync_together4364_aunroll_x_in_i_valid_57_delay_0;
    reg [0:0] redist789_sync_together4364_aunroll_x_in_i_valid_59_q;
    reg [0:0] redist789_sync_together4364_aunroll_x_in_i_valid_59_delay_0;
    reg [0:0] redist790_sync_together4364_aunroll_x_in_i_valid_61_q;
    reg [0:0] redist790_sync_together4364_aunroll_x_in_i_valid_61_delay_0;
    reg [0:0] redist791_sync_together4364_aunroll_x_in_i_valid_63_q;
    reg [0:0] redist791_sync_together4364_aunroll_x_in_i_valid_63_delay_0;
    reg [0:0] redist792_sync_together4364_aunroll_x_in_i_valid_65_q;
    reg [0:0] redist792_sync_together4364_aunroll_x_in_i_valid_65_delay_0;
    reg [0:0] redist793_sync_together4364_aunroll_x_in_i_valid_67_q;
    reg [0:0] redist793_sync_together4364_aunroll_x_in_i_valid_67_delay_0;
    reg [0:0] redist794_sync_together4364_aunroll_x_in_i_valid_69_q;
    reg [0:0] redist794_sync_together4364_aunroll_x_in_i_valid_69_delay_0;
    reg [0:0] redist795_sync_together4364_aunroll_x_in_i_valid_71_q;
    reg [0:0] redist795_sync_together4364_aunroll_x_in_i_valid_71_delay_0;
    reg [0:0] redist796_sync_together4364_aunroll_x_in_i_valid_73_q;
    reg [0:0] redist796_sync_together4364_aunroll_x_in_i_valid_73_delay_0;
    reg [0:0] redist797_sync_together4364_aunroll_x_in_i_valid_75_q;
    reg [0:0] redist797_sync_together4364_aunroll_x_in_i_valid_75_delay_0;
    reg [0:0] redist798_sync_together4364_aunroll_x_in_i_valid_77_q;
    reg [0:0] redist798_sync_together4364_aunroll_x_in_i_valid_77_delay_0;
    reg [0:0] redist799_sync_together4364_aunroll_x_in_i_valid_79_q;
    reg [0:0] redist799_sync_together4364_aunroll_x_in_i_valid_79_delay_0;
    reg [0:0] redist800_sync_together4364_aunroll_x_in_i_valid_81_q;
    reg [0:0] redist800_sync_together4364_aunroll_x_in_i_valid_81_delay_0;
    reg [0:0] redist801_sync_together4364_aunroll_x_in_i_valid_83_q;
    reg [0:0] redist801_sync_together4364_aunroll_x_in_i_valid_83_delay_0;
    reg [0:0] redist802_sync_together4364_aunroll_x_in_i_valid_85_q;
    reg [0:0] redist802_sync_together4364_aunroll_x_in_i_valid_85_delay_0;
    reg [0:0] redist803_sync_together4364_aunroll_x_in_i_valid_87_q;
    reg [0:0] redist803_sync_together4364_aunroll_x_in_i_valid_87_delay_0;
    reg [0:0] redist804_sync_together4364_aunroll_x_in_i_valid_89_q;
    reg [0:0] redist804_sync_together4364_aunroll_x_in_i_valid_89_delay_0;
    reg [0:0] redist805_sync_together4364_aunroll_x_in_i_valid_91_q;
    reg [0:0] redist805_sync_together4364_aunroll_x_in_i_valid_91_delay_0;
    reg [0:0] redist806_sync_together4364_aunroll_x_in_i_valid_93_q;
    reg [0:0] redist806_sync_together4364_aunroll_x_in_i_valid_93_delay_0;
    reg [0:0] redist807_sync_together4364_aunroll_x_in_i_valid_95_q;
    reg [0:0] redist807_sync_together4364_aunroll_x_in_i_valid_95_delay_0;
    reg [0:0] redist808_sync_together4364_aunroll_x_in_i_valid_97_q;
    reg [0:0] redist808_sync_together4364_aunroll_x_in_i_valid_97_delay_0;
    reg [0:0] redist809_sync_together4364_aunroll_x_in_i_valid_99_q;
    reg [0:0] redist809_sync_together4364_aunroll_x_in_i_valid_99_delay_0;
    reg [0:0] redist810_sync_together4364_aunroll_x_in_i_valid_101_q;
    reg [0:0] redist810_sync_together4364_aunroll_x_in_i_valid_101_delay_0;
    reg [0:0] redist811_sync_together4364_aunroll_x_in_i_valid_103_q;
    reg [0:0] redist811_sync_together4364_aunroll_x_in_i_valid_103_delay_0;
    reg [0:0] redist812_sync_together4364_aunroll_x_in_i_valid_105_q;
    reg [0:0] redist812_sync_together4364_aunroll_x_in_i_valid_105_delay_0;
    reg [0:0] redist813_sync_together4364_aunroll_x_in_i_valid_107_q;
    reg [0:0] redist813_sync_together4364_aunroll_x_in_i_valid_107_delay_0;
    reg [0:0] redist814_sync_together4364_aunroll_x_in_i_valid_109_q;
    reg [0:0] redist814_sync_together4364_aunroll_x_in_i_valid_109_delay_0;
    reg [0:0] redist815_sync_together4364_aunroll_x_in_i_valid_111_q;
    reg [0:0] redist815_sync_together4364_aunroll_x_in_i_valid_111_delay_0;
    reg [0:0] redist816_sync_together4364_aunroll_x_in_i_valid_113_q;
    reg [0:0] redist816_sync_together4364_aunroll_x_in_i_valid_113_delay_0;
    reg [0:0] redist817_sync_together4364_aunroll_x_in_i_valid_115_q;
    reg [0:0] redist817_sync_together4364_aunroll_x_in_i_valid_115_delay_0;
    reg [0:0] redist818_sync_together4364_aunroll_x_in_i_valid_117_q;
    reg [0:0] redist818_sync_together4364_aunroll_x_in_i_valid_117_delay_0;
    reg [0:0] redist819_sync_together4364_aunroll_x_in_i_valid_119_q;
    reg [0:0] redist819_sync_together4364_aunroll_x_in_i_valid_119_delay_0;
    reg [0:0] redist820_sync_together4364_aunroll_x_in_i_valid_121_q;
    reg [0:0] redist820_sync_together4364_aunroll_x_in_i_valid_121_delay_0;
    reg [0:0] redist821_sync_together4364_aunroll_x_in_i_valid_123_q;
    reg [0:0] redist821_sync_together4364_aunroll_x_in_i_valid_123_delay_0;
    reg [0:0] redist822_sync_together4364_aunroll_x_in_i_valid_125_q;
    reg [0:0] redist822_sync_together4364_aunroll_x_in_i_valid_125_delay_0;
    reg [0:0] redist823_sync_together4364_aunroll_x_in_i_valid_127_q;
    reg [0:0] redist823_sync_together4364_aunroll_x_in_i_valid_127_delay_0;
    reg [0:0] redist824_sync_together4364_aunroll_x_in_i_valid_129_q;
    reg [0:0] redist824_sync_together4364_aunroll_x_in_i_valid_129_delay_0;
    reg [0:0] redist825_sync_together4364_aunroll_x_in_i_valid_131_q;
    reg [0:0] redist825_sync_together4364_aunroll_x_in_i_valid_131_delay_0;
    reg [0:0] redist826_sync_together4364_aunroll_x_in_i_valid_133_q;
    reg [0:0] redist826_sync_together4364_aunroll_x_in_i_valid_133_delay_0;
    reg [0:0] redist827_sync_together4364_aunroll_x_in_i_valid_135_q;
    reg [0:0] redist827_sync_together4364_aunroll_x_in_i_valid_135_delay_0;
    reg [0:0] redist828_sync_together4364_aunroll_x_in_i_valid_137_q;
    reg [0:0] redist828_sync_together4364_aunroll_x_in_i_valid_137_delay_0;
    reg [0:0] redist829_sync_together4364_aunroll_x_in_i_valid_139_q;
    reg [0:0] redist829_sync_together4364_aunroll_x_in_i_valid_139_delay_0;
    reg [0:0] redist830_sync_together4364_aunroll_x_in_i_valid_141_q;
    reg [0:0] redist830_sync_together4364_aunroll_x_in_i_valid_141_delay_0;
    reg [0:0] redist831_sync_together4364_aunroll_x_in_i_valid_143_q;
    reg [0:0] redist831_sync_together4364_aunroll_x_in_i_valid_143_delay_0;
    reg [0:0] redist832_sync_together4364_aunroll_x_in_i_valid_145_q;
    reg [0:0] redist832_sync_together4364_aunroll_x_in_i_valid_145_delay_0;
    reg [0:0] redist833_sync_together4364_aunroll_x_in_i_valid_147_q;
    reg [0:0] redist833_sync_together4364_aunroll_x_in_i_valid_147_delay_0;
    reg [0:0] redist834_sync_together4364_aunroll_x_in_i_valid_149_q;
    reg [0:0] redist834_sync_together4364_aunroll_x_in_i_valid_149_delay_0;
    reg [0:0] redist835_sync_together4364_aunroll_x_in_i_valid_151_q;
    reg [0:0] redist835_sync_together4364_aunroll_x_in_i_valid_151_delay_0;
    reg [0:0] redist836_sync_together4364_aunroll_x_in_i_valid_153_q;
    reg [0:0] redist836_sync_together4364_aunroll_x_in_i_valid_153_delay_0;
    reg [0:0] redist837_sync_together4364_aunroll_x_in_i_valid_155_q;
    reg [0:0] redist837_sync_together4364_aunroll_x_in_i_valid_155_delay_0;
    reg [0:0] redist838_sync_together4364_aunroll_x_in_i_valid_157_q;
    reg [0:0] redist838_sync_together4364_aunroll_x_in_i_valid_157_delay_0;
    reg [0:0] redist839_sync_together4364_aunroll_x_in_i_valid_159_q;
    reg [0:0] redist839_sync_together4364_aunroll_x_in_i_valid_159_delay_0;
    reg [0:0] redist840_sync_together4364_aunroll_x_in_i_valid_161_q;
    reg [0:0] redist840_sync_together4364_aunroll_x_in_i_valid_161_delay_0;
    reg [0:0] redist841_sync_together4364_aunroll_x_in_i_valid_163_q;
    reg [0:0] redist841_sync_together4364_aunroll_x_in_i_valid_163_delay_0;
    reg [0:0] redist842_sync_together4364_aunroll_x_in_i_valid_165_q;
    reg [0:0] redist842_sync_together4364_aunroll_x_in_i_valid_165_delay_0;
    reg [0:0] redist843_sync_together4364_aunroll_x_in_i_valid_167_q;
    reg [0:0] redist843_sync_together4364_aunroll_x_in_i_valid_167_delay_0;
    reg [0:0] redist844_sync_together4364_aunroll_x_in_i_valid_169_q;
    reg [0:0] redist844_sync_together4364_aunroll_x_in_i_valid_169_delay_0;
    reg [0:0] redist845_sync_together4364_aunroll_x_in_i_valid_171_q;
    reg [0:0] redist845_sync_together4364_aunroll_x_in_i_valid_171_delay_0;
    reg [0:0] redist846_sync_together4364_aunroll_x_in_i_valid_173_q;
    reg [0:0] redist846_sync_together4364_aunroll_x_in_i_valid_173_delay_0;
    reg [0:0] redist847_sync_together4364_aunroll_x_in_i_valid_175_q;
    reg [0:0] redist847_sync_together4364_aunroll_x_in_i_valid_175_delay_0;
    reg [0:0] redist848_sync_together4364_aunroll_x_in_i_valid_177_q;
    reg [0:0] redist848_sync_together4364_aunroll_x_in_i_valid_177_delay_0;
    reg [0:0] redist849_sync_together4364_aunroll_x_in_i_valid_179_q;
    reg [0:0] redist849_sync_together4364_aunroll_x_in_i_valid_179_delay_0;
    reg [0:0] redist850_sync_together4364_aunroll_x_in_i_valid_181_q;
    reg [0:0] redist850_sync_together4364_aunroll_x_in_i_valid_181_delay_0;
    reg [0:0] redist851_sync_together4364_aunroll_x_in_i_valid_183_q;
    reg [0:0] redist851_sync_together4364_aunroll_x_in_i_valid_183_delay_0;
    reg [0:0] redist852_sync_together4364_aunroll_x_in_i_valid_185_q;
    reg [0:0] redist852_sync_together4364_aunroll_x_in_i_valid_185_delay_0;
    reg [0:0] redist853_sync_together4364_aunroll_x_in_i_valid_187_q;
    reg [0:0] redist853_sync_together4364_aunroll_x_in_i_valid_187_delay_0;
    reg [0:0] redist854_sync_together4364_aunroll_x_in_i_valid_189_q;
    reg [0:0] redist854_sync_together4364_aunroll_x_in_i_valid_189_delay_0;
    reg [0:0] redist855_sync_together4364_aunroll_x_in_i_valid_191_q;
    reg [0:0] redist855_sync_together4364_aunroll_x_in_i_valid_191_delay_0;
    reg [0:0] redist856_sync_together4364_aunroll_x_in_i_valid_193_q;
    reg [0:0] redist856_sync_together4364_aunroll_x_in_i_valid_193_delay_0;
    reg [0:0] redist857_sync_together4364_aunroll_x_in_i_valid_195_q;
    reg [0:0] redist857_sync_together4364_aunroll_x_in_i_valid_195_delay_0;
    reg [0:0] redist858_sync_together4364_aunroll_x_in_i_valid_197_q;
    reg [0:0] redist858_sync_together4364_aunroll_x_in_i_valid_197_delay_0;
    reg [0:0] redist859_sync_together4364_aunroll_x_in_i_valid_199_q;
    reg [0:0] redist859_sync_together4364_aunroll_x_in_i_valid_199_delay_0;
    reg [0:0] redist860_sync_together4364_aunroll_x_in_i_valid_201_q;
    reg [0:0] redist860_sync_together4364_aunroll_x_in_i_valid_201_delay_0;
    reg [0:0] redist861_sync_together4364_aunroll_x_in_i_valid_203_q;
    reg [0:0] redist861_sync_together4364_aunroll_x_in_i_valid_203_delay_0;
    reg [0:0] redist862_sync_together4364_aunroll_x_in_i_valid_205_q;
    reg [0:0] redist862_sync_together4364_aunroll_x_in_i_valid_205_delay_0;
    reg [0:0] redist863_sync_together4364_aunroll_x_in_i_valid_207_q;
    reg [0:0] redist863_sync_together4364_aunroll_x_in_i_valid_207_delay_0;
    reg [0:0] redist864_sync_together4364_aunroll_x_in_i_valid_209_q;
    reg [0:0] redist864_sync_together4364_aunroll_x_in_i_valid_209_delay_0;
    reg [0:0] redist865_sync_together4364_aunroll_x_in_i_valid_211_q;
    reg [0:0] redist865_sync_together4364_aunroll_x_in_i_valid_211_delay_0;
    reg [0:0] redist866_sync_together4364_aunroll_x_in_i_valid_213_q;
    reg [0:0] redist866_sync_together4364_aunroll_x_in_i_valid_213_delay_0;
    reg [0:0] redist867_sync_together4364_aunroll_x_in_i_valid_215_q;
    reg [0:0] redist867_sync_together4364_aunroll_x_in_i_valid_215_delay_0;
    reg [0:0] redist868_sync_together4364_aunroll_x_in_i_valid_217_q;
    reg [0:0] redist868_sync_together4364_aunroll_x_in_i_valid_217_delay_0;
    reg [0:0] redist869_sync_together4364_aunroll_x_in_i_valid_219_q;
    reg [0:0] redist869_sync_together4364_aunroll_x_in_i_valid_219_delay_0;
    reg [0:0] redist870_sync_together4364_aunroll_x_in_i_valid_221_q;
    reg [0:0] redist870_sync_together4364_aunroll_x_in_i_valid_221_delay_0;
    reg [0:0] redist871_sync_together4364_aunroll_x_in_i_valid_223_q;
    reg [0:0] redist871_sync_together4364_aunroll_x_in_i_valid_223_delay_0;
    reg [0:0] redist872_sync_together4364_aunroll_x_in_i_valid_225_q;
    reg [0:0] redist872_sync_together4364_aunroll_x_in_i_valid_225_delay_0;
    reg [0:0] redist873_sync_together4364_aunroll_x_in_i_valid_227_q;
    reg [0:0] redist873_sync_together4364_aunroll_x_in_i_valid_227_delay_0;
    reg [0:0] redist874_sync_together4364_aunroll_x_in_i_valid_229_q;
    reg [0:0] redist874_sync_together4364_aunroll_x_in_i_valid_229_delay_0;
    reg [0:0] redist875_sync_together4364_aunroll_x_in_i_valid_231_q;
    reg [0:0] redist875_sync_together4364_aunroll_x_in_i_valid_231_delay_0;
    reg [0:0] redist876_sync_together4364_aunroll_x_in_i_valid_233_q;
    reg [0:0] redist876_sync_together4364_aunroll_x_in_i_valid_233_delay_0;
    reg [0:0] redist877_sync_together4364_aunroll_x_in_i_valid_235_q;
    reg [0:0] redist877_sync_together4364_aunroll_x_in_i_valid_235_delay_0;
    reg [0:0] redist878_sync_together4364_aunroll_x_in_i_valid_237_q;
    reg [0:0] redist878_sync_together4364_aunroll_x_in_i_valid_237_delay_0;
    reg [0:0] redist879_sync_together4364_aunroll_x_in_i_valid_239_q;
    reg [0:0] redist879_sync_together4364_aunroll_x_in_i_valid_239_delay_0;
    reg [0:0] redist880_sync_together4364_aunroll_x_in_i_valid_241_q;
    reg [0:0] redist880_sync_together4364_aunroll_x_in_i_valid_241_delay_0;
    reg [0:0] redist881_sync_together4364_aunroll_x_in_i_valid_243_q;
    reg [0:0] redist881_sync_together4364_aunroll_x_in_i_valid_243_delay_0;
    reg [0:0] redist882_sync_together4364_aunroll_x_in_i_valid_245_q;
    reg [0:0] redist882_sync_together4364_aunroll_x_in_i_valid_245_delay_0;
    reg [0:0] redist883_sync_together4364_aunroll_x_in_i_valid_247_q;
    reg [0:0] redist883_sync_together4364_aunroll_x_in_i_valid_247_delay_0;
    reg [0:0] redist884_sync_together4364_aunroll_x_in_i_valid_249_q;
    reg [0:0] redist884_sync_together4364_aunroll_x_in_i_valid_249_delay_0;
    reg [0:0] redist885_sync_together4364_aunroll_x_in_i_valid_251_q;
    reg [0:0] redist885_sync_together4364_aunroll_x_in_i_valid_251_delay_0;
    reg [0:0] redist886_sync_together4364_aunroll_x_in_i_valid_253_q;
    reg [0:0] redist886_sync_together4364_aunroll_x_in_i_valid_253_delay_0;
    reg [15:0] redist887_i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x_b_1_q;
    reg [15:0] redist888_i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x_b_1_q;
    reg [15:0] redist889_i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x_b_1_q;
    reg [15:0] redist890_i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x_b_1_q;
    reg [15:0] redist891_i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x_b_1_q;
    reg [15:0] redist892_i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x_b_1_q;
    reg [15:0] redist893_i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x_b_1_q;
    reg [15:0] redist894_i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x_b_1_q;
    reg [15:0] redist895_i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x_b_1_q;
    reg [15:0] redist896_i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x_b_1_q;
    reg [15:0] redist897_i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x_b_1_q;
    reg [15:0] redist898_i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x_b_1_q;
    reg [15:0] redist899_i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x_b_1_q;
    reg [15:0] redist900_i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x_b_1_q;
    reg [15:0] redist901_i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x_b_1_q;
    reg [15:0] redist902_i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x_b_1_q;
    reg [15:0] redist903_i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x_b_1_q;
    reg [15:0] redist904_i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x_b_1_q;
    reg [15:0] redist905_i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x_b_1_q;
    reg [15:0] redist906_i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x_b_1_q;
    reg [15:0] redist907_i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x_b_1_q;
    reg [15:0] redist908_i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x_b_1_q;
    reg [15:0] redist909_i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x_b_1_q;
    reg [15:0] redist910_i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x_b_1_q;
    reg [15:0] redist911_i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x_b_1_q;
    reg [15:0] redist912_i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x_b_1_q;
    reg [15:0] redist913_i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x_b_1_q;
    reg [15:0] redist914_i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x_b_1_q;
    reg [15:0] redist915_i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x_b_1_q;
    reg [15:0] redist916_i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x_b_1_q;
    reg [15:0] redist917_i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x_b_1_q;
    reg [15:0] redist918_i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x_b_1_q;
    reg [15:0] redist919_i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x_b_1_q;
    reg [15:0] redist920_i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x_b_1_q;
    reg [15:0] redist921_i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x_b_1_q;
    reg [15:0] redist922_i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x_b_1_q;
    reg [15:0] redist923_i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x_b_1_q;
    reg [15:0] redist924_i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x_b_1_q;
    reg [15:0] redist925_i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x_b_1_q;
    reg [15:0] redist926_i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x_b_1_q;
    reg [15:0] redist927_i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x_b_1_q;
    reg [15:0] redist928_i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x_b_1_q;
    reg [15:0] redist929_i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x_b_1_q;
    reg [15:0] redist930_i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x_b_1_q;
    reg [15:0] redist931_i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x_b_1_q;
    reg [15:0] redist932_i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x_b_1_q;
    reg [15:0] redist933_i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x_b_1_q;
    reg [15:0] redist934_i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x_b_1_q;
    reg [15:0] redist935_i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x_b_1_q;
    reg [15:0] redist936_i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x_b_1_q;
    reg [15:0] redist937_i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x_b_1_q;
    reg [15:0] redist938_i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x_b_1_q;
    reg [15:0] redist939_i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x_b_1_q;
    reg [15:0] redist940_i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x_b_1_q;
    reg [15:0] redist941_i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x_b_1_q;
    reg [15:0] redist942_i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x_b_1_q;
    reg [15:0] redist943_i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x_b_1_q;
    reg [15:0] redist944_i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x_b_1_q;
    reg [15:0] redist945_i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x_b_1_q;
    reg [15:0] redist946_i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x_b_1_q;
    reg [15:0] redist947_i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x_b_1_q;
    reg [15:0] redist948_i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x_b_1_q;
    reg [15:0] redist949_i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x_b_1_q;
    reg [15:0] redist950_i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x_b_1_q;
    reg [15:0] redist951_i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x_b_1_q;
    reg [15:0] redist952_i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x_b_1_q;
    reg [15:0] redist953_i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x_b_1_q;
    reg [15:0] redist954_i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x_b_1_q;
    reg [15:0] redist955_i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x_b_1_q;
    reg [15:0] redist956_i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x_b_1_q;
    reg [15:0] redist957_i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x_b_1_q;
    reg [15:0] redist958_i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x_b_1_q;
    reg [15:0] redist959_i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x_b_1_q;
    reg [15:0] redist960_i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x_b_1_q;
    reg [15:0] redist961_i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x_b_1_q;
    reg [15:0] redist962_i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x_b_1_q;
    reg [15:0] redist963_i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x_b_1_q;
    reg [15:0] redist964_i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x_b_1_q;
    reg [15:0] redist965_i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x_b_1_q;
    reg [15:0] redist966_i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x_b_1_q;
    reg [15:0] redist967_i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x_b_1_q;
    reg [15:0] redist968_i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x_b_1_q;
    reg [15:0] redist969_i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x_b_1_q;
    reg [15:0] redist970_i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x_b_1_q;
    reg [15:0] redist971_i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x_b_1_q;
    reg [15:0] redist972_i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x_b_1_q;
    reg [15:0] redist973_i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x_b_1_q;
    reg [15:0] redist974_i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x_b_1_q;
    reg [15:0] redist975_i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x_b_1_q;
    reg [15:0] redist976_i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x_b_1_q;
    reg [15:0] redist977_i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x_b_1_q;
    reg [15:0] redist978_i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x_b_1_q;
    reg [15:0] redist979_i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x_b_1_q;
    reg [15:0] redist980_i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x_b_1_q;
    reg [15:0] redist981_i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x_b_1_q;
    reg [15:0] redist982_i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x_b_1_q;
    reg [15:0] redist983_i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x_b_1_q;
    reg [15:0] redist984_i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x_b_1_q;
    reg [15:0] redist985_i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x_b_1_q;
    reg [15:0] redist986_i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x_b_1_q;
    reg [15:0] redist987_i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x_b_1_q;
    reg [15:0] redist988_i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x_b_1_q;
    reg [15:0] redist989_i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x_b_1_q;
    reg [15:0] redist990_i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x_b_1_q;
    reg [15:0] redist991_i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x_b_1_q;
    reg [15:0] redist992_i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x_b_1_q;
    reg [15:0] redist993_i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x_b_1_q;
    reg [15:0] redist994_i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x_b_1_q;
    reg [15:0] redist995_i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x_b_1_q;
    reg [15:0] redist996_i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x_b_1_q;
    reg [15:0] redist997_i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x_b_1_q;
    reg [15:0] redist998_i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x_b_1_q;
    reg [15:0] redist999_i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x_b_1_q;
    reg [15:0] redist1000_i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x_b_1_q;
    reg [15:0] redist1001_i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x_b_1_q;
    reg [15:0] redist1002_i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x_b_1_q;
    reg [15:0] redist1003_i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x_b_1_q;
    reg [15:0] redist1004_i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x_b_1_q;
    reg [15:0] redist1005_i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x_b_1_q;
    reg [15:0] redist1006_i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x_b_1_q;
    reg [15:0] redist1007_i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x_b_1_q;
    reg [15:0] redist1008_i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x_b_1_q;
    reg [15:0] redist1009_i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x_b_1_q;
    reg [15:0] redist1010_i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x_b_1_q;
    reg [15:0] redist1011_i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x_b_1_q;
    reg [15:0] redist1012_i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x_b_1_q;
    reg [15:0] redist1013_i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x_b_1_q;
    reg [15:0] redist1014_i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x_b_1_q;
    reg [15:0] redist1015_i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x_b_1_q;
    reg [15:0] redist1016_i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x_b_1_q;
    reg [15:0] redist1017_i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x_b_1_q;
    reg [15:0] redist1018_i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x_b_1_q;
    reg [15:0] redist1019_i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x_b_1_q;
    reg [15:0] redist1020_i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x_b_1_q;
    reg [15:0] redist1021_i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x_b_1_q;
    reg [15:0] redist1022_i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x_b_1_q;
    reg [15:0] redist1023_i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x_b_1_q;
    reg [15:0] redist1024_i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x_b_1_q;
    reg [15:0] redist1025_i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x_b_1_q;
    reg [15:0] redist1026_i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x_b_1_q;
    reg [15:0] redist1027_i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x_b_1_q;
    reg [15:0] redist1028_i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x_b_1_q;
    reg [15:0] redist1029_i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x_b_1_q;
    reg [15:0] redist1030_i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x_b_1_q;
    reg [15:0] redist1031_i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x_b_1_q;
    reg [15:0] redist1032_i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x_b_1_q;
    reg [15:0] redist1033_i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x_b_1_q;
    reg [15:0] redist1034_i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x_b_1_q;
    reg [15:0] redist1035_i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x_b_1_q;
    reg [15:0] redist1036_i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x_b_1_q;
    reg [15:0] redist1037_i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x_b_1_q;
    reg [15:0] redist1038_i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x_b_1_q;
    reg [15:0] redist1039_i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x_b_1_q;
    reg [15:0] redist1040_i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x_b_1_q;
    reg [15:0] redist1041_i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x_b_1_q;
    reg [15:0] redist1042_i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x_b_1_q;
    reg [15:0] redist1043_i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x_b_1_q;
    reg [15:0] redist1044_i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x_b_1_q;
    reg [15:0] redist1045_i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x_b_1_q;
    reg [15:0] redist1046_i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x_b_1_q;
    reg [15:0] redist1047_i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x_b_1_q;
    reg [15:0] redist1048_i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x_b_1_q;
    reg [15:0] redist1049_i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x_b_1_q;
    reg [15:0] redist1050_i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x_b_1_q;
    reg [15:0] redist1051_i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x_b_1_q;
    reg [15:0] redist1052_i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x_b_1_q;
    reg [15:0] redist1053_i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x_b_1_q;
    reg [15:0] redist1054_i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x_b_1_q;
    reg [15:0] redist1055_i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x_b_1_q;
    reg [15:0] redist1056_i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x_b_1_q;
    reg [15:0] redist1057_i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x_b_1_q;
    reg [15:0] redist1058_i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x_b_1_q;
    reg [15:0] redist1059_i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x_b_1_q;
    reg [15:0] redist1060_i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x_b_1_q;
    reg [15:0] redist1061_i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x_b_1_q;
    reg [15:0] redist1062_i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x_b_1_q;
    reg [15:0] redist1063_i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x_b_1_q;
    reg [15:0] redist1064_i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x_b_1_q;
    reg [15:0] redist1065_i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x_b_1_q;
    reg [15:0] redist1066_i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x_b_1_q;
    reg [15:0] redist1067_i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x_b_1_q;
    reg [15:0] redist1068_i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x_b_1_q;
    reg [15:0] redist1069_i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x_b_1_q;
    reg [15:0] redist1070_i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x_b_1_q;
    reg [15:0] redist1071_i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x_b_1_q;
    reg [15:0] redist1072_i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x_b_1_q;
    reg [15:0] redist1073_i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x_b_1_q;
    reg [15:0] redist1074_i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x_b_1_q;
    reg [15:0] redist1075_i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x_b_1_q;
    reg [15:0] redist1076_i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x_b_1_q;
    reg [15:0] redist1077_i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x_b_1_q;
    reg [15:0] redist1078_i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x_b_1_q;
    reg [15:0] redist1079_i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x_b_1_q;
    reg [15:0] redist1080_i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x_b_1_q;
    reg [15:0] redist1081_i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x_b_1_q;
    reg [15:0] redist1082_i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x_b_1_q;
    reg [15:0] redist1083_i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x_b_1_q;
    reg [15:0] redist1084_i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x_b_1_q;
    reg [15:0] redist1085_i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x_b_1_q;
    reg [15:0] redist1086_i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x_b_1_q;
    reg [15:0] redist1087_i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x_b_1_q;
    reg [15:0] redist1088_i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x_b_1_q;
    reg [15:0] redist1089_i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x_b_1_q;
    reg [15:0] redist1090_i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x_b_1_q;
    reg [15:0] redist1091_i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x_b_1_q;
    reg [15:0] redist1092_i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x_b_1_q;
    reg [15:0] redist1093_i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x_b_1_q;
    reg [15:0] redist1094_i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x_b_1_q;
    reg [15:0] redist1095_i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x_b_1_q;
    reg [15:0] redist1096_i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x_b_1_q;
    reg [15:0] redist1097_i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x_b_1_q;
    reg [15:0] redist1098_i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x_b_1_q;
    reg [15:0] redist1099_i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x_b_1_q;
    reg [15:0] redist1100_i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x_b_1_q;
    reg [15:0] redist1101_i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x_b_1_q;
    reg [15:0] redist1102_i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x_b_1_q;
    reg [15:0] redist1103_i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x_b_1_q;
    reg [15:0] redist1104_i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x_b_1_q;
    reg [15:0] redist1105_i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x_b_1_q;
    reg [15:0] redist1106_i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x_b_1_q;
    reg [15:0] redist1107_i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x_b_1_q;
    reg [15:0] redist1108_i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x_b_1_q;
    reg [15:0] redist1109_i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x_b_1_q;
    reg [15:0] redist1110_i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x_b_1_q;
    reg [15:0] redist1111_i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x_b_1_q;
    reg [15:0] redist1112_i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x_b_1_q;
    reg [15:0] redist1113_i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x_b_1_q;
    reg [15:0] redist1114_i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x_b_1_q;
    reg [15:0] redist1115_i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x_b_1_q;
    reg [15:0] redist1116_i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x_b_1_q;
    reg [15:0] redist1117_i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x_b_1_q;
    reg [15:0] redist1118_i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x_b_1_q;
    reg [15:0] redist1119_i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x_b_1_q;
    reg [15:0] redist1120_i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x_b_1_q;
    reg [15:0] redist1121_i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x_b_1_q;
    reg [15:0] redist1122_i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x_b_1_q;
    reg [15:0] redist1123_i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x_b_1_q;
    reg [15:0] redist1124_i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x_b_1_q;
    reg [15:0] redist1125_i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x_b_1_q;
    reg [15:0] redist1126_i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x_b_1_q;
    reg [15:0] redist1127_i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x_b_1_q;
    reg [15:0] redist1128_i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x_b_1_q;
    reg [15:0] redist1129_i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x_b_1_q;
    reg [15:0] redist1130_i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x_b_1_q;
    reg [15:0] redist1131_i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x_b_1_q;
    reg [15:0] redist1132_i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x_b_1_q;
    reg [15:0] redist1133_i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x_b_1_q;
    reg [15:0] redist1134_i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x_b_1_q;
    reg [15:0] redist1135_i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x_b_1_q;
    reg [15:0] redist1136_i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x_b_1_q;
    reg [15:0] redist1137_i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x_b_1_q;
    reg [15:0] redist1138_i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x_b_1_q;
    reg [15:0] redist1139_i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x_b_1_q;
    reg [15:0] redist1140_i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x_b_1_q;
    reg [15:0] redist1141_bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x_b_1_q;
    reg [15:0] redist1142_bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x_b_1_q;
    reg [15:0] redist1143_bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x_b_1_q;
    reg [15:0] redist1144_bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x_b_1_q;
    reg [15:0] redist1145_bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x_b_1_q;
    reg [15:0] redist1146_bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x_b_1_q;
    reg [15:0] redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_inputreg0_q;
    reg [15:0] redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_inputreg0_q;
    reg [15:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_inputreg0_q;
    reg [15:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_outputreg0_q;
    wire redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_reset0;
    wire [15:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_ia;
    wire [1:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_aa;
    wire [1:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_ab;
    wire [15:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_iq;
    wire [15:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_q;
    wire [1:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_i = 2'b11;
    wire [1:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_offset_q;
    wire [2:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_a;
    wire [2:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_b;
    logic [2:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_o;
    wire [2:0] redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_q;
    reg [15:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_inputreg0_q;
    reg [15:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_outputreg0_q;
    wire redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_reset0;
    wire [15:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_ia;
    wire [1:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_aa;
    wire [1:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_ab;
    wire [15:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_iq;
    wire [15:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_q;
    wire [1:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_i = 2'b11;
    wire [2:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_a;
    wire [2:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_b;
    logic [2:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_o;
    wire [2:0] redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_q;
    reg [15:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_inputreg0_q;
    reg [15:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_outputreg0_q;
    wire redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_reset0;
    wire [15:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_ia;
    wire [2:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_aa;
    wire [2:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_ab;
    wire [15:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_iq;
    wire [15:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_q;
    wire [2:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_i = 3'b111;
    wire [2:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_offset_q;
    wire [3:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_a;
    wire [3:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_b;
    logic [3:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_o;
    wire [3:0] redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_q;
    reg [15:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_inputreg0_q;
    reg [15:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_outputreg0_q;
    wire redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_reset0;
    wire [15:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_ia;
    wire [2:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_aa;
    wire [2:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_ab;
    wire [15:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_iq;
    wire [15:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_q;
    wire [2:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_i = 3'b111;
    wire [3:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_a;
    wire [3:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_b;
    logic [3:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_o;
    wire [3:0] redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_q;
    reg [15:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_inputreg0_q;
    reg [15:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_outputreg0_q;
    wire redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_reset0;
    wire [15:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_ia;
    wire [2:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_aa;
    wire [2:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_ab;
    wire [15:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_iq;
    wire [15:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_q;
    wire [2:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_i = 3'b111;
    wire [2:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_offset_q;
    wire [3:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_a;
    wire [3:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_b;
    logic [3:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_o;
    wire [3:0] redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_q;
    reg [15:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_inputreg0_q;
    reg [15:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_outputreg0_q;
    wire redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_reset0;
    wire [15:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_ia;
    wire [2:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_aa;
    wire [2:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_ab;
    wire [15:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_iq;
    wire [15:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_q;
    wire [2:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_i = 3'b111;
    wire [3:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_a;
    wire [3:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_b;
    logic [3:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_o;
    wire [3:0] redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_q;
    reg [15:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_inputreg0_q;
    reg [15:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_outputreg0_q;
    wire redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_reset0;
    wire [15:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_ia;
    wire [3:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_aa;
    wire [3:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_ab;
    wire [15:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_iq;
    wire [15:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_q;
    wire [3:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_i = 4'b1111;
    wire [3:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_offset_q;
    wire [4:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_a;
    wire [4:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_b;
    logic [4:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_o;
    wire [4:0] redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_q;
    reg [15:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_inputreg0_q;
    reg [15:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_outputreg0_q;
    wire redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_reset0;
    wire [15:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_ia;
    wire [3:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_aa;
    wire [3:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_ab;
    wire [15:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_iq;
    wire [15:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_q;
    wire [3:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_i = 4'b1111;
    wire [4:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_a;
    wire [4:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_b;
    logic [4:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_o;
    wire [4:0] redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_q;
    reg [15:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_inputreg0_q;
    reg [15:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_outputreg0_q;
    wire redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_reset0;
    wire [15:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_ia;
    wire [3:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_aa;
    wire [3:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_ab;
    wire [15:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_iq;
    wire [15:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_q;
    wire [3:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_i = 4'b1111;
    wire [3:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_offset_q;
    wire [4:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_a;
    wire [4:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_b;
    logic [4:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_o;
    wire [4:0] redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_q;
    reg [15:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_inputreg0_q;
    reg [15:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_outputreg0_q;
    wire redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_reset0;
    wire [15:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_ia;
    wire [3:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_aa;
    wire [3:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_ab;
    wire [15:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_iq;
    wire [15:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_q;
    wire [3:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_i = 4'b1111;
    wire [4:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_a;
    wire [4:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_b;
    logic [4:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_o;
    wire [4:0] redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_q;
    reg [15:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_inputreg0_q;
    reg [15:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_outputreg0_q;
    wire redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_reset0;
    wire [15:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_ia;
    wire [3:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_aa;
    wire [3:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_ab;
    wire [15:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_iq;
    wire [15:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_q;
    wire [3:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_i = 4'b1111;
    wire [3:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_offset_q;
    wire [4:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_a;
    wire [4:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_b;
    logic [4:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_o;
    wire [4:0] redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_q;
    reg [15:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_inputreg0_q;
    reg [15:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_outputreg0_q;
    wire redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_reset0;
    wire [15:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_ia;
    wire [3:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_aa;
    wire [3:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_ab;
    wire [15:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_iq;
    wire [15:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_q;
    wire [3:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_i = 4'b1111;
    wire [4:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_a;
    wire [4:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_b;
    logic [4:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_o;
    wire [4:0] redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_q;
    reg [15:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_inputreg0_q;
    reg [15:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_outputreg0_q;
    wire redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_reset0;
    wire [15:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_ia;
    wire [3:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_aa;
    wire [3:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_ab;
    wire [15:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_iq;
    wire [15:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_q;
    wire [3:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_i = 4'b1111;
    wire [3:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_offset_q;
    wire [4:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_a;
    wire [4:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_b;
    logic [4:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_o;
    wire [4:0] redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_q;
    reg [15:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_inputreg0_q;
    reg [15:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_outputreg0_q;
    wire redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_reset0;
    wire [15:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_ia;
    wire [3:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_aa;
    wire [3:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_ab;
    wire [15:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_iq;
    wire [15:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_q;
    wire [3:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_i = 4'b1111;
    wire [4:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_a;
    wire [4:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_b;
    logic [4:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_o;
    wire [4:0] redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_q;
    reg [15:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_inputreg0_q;
    reg [15:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_outputreg0_q;
    wire redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_reset0;
    wire [15:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_ia;
    wire [4:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_aa;
    wire [4:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_ab;
    wire [15:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_iq;
    wire [15:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_q;
    wire [4:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_i = 5'b11111;
    wire [4:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_offset_q;
    wire [5:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_a;
    wire [5:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_b;
    logic [5:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_o;
    wire [5:0] redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_q;
    reg [15:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_inputreg0_q;
    reg [15:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_outputreg0_q;
    wire redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_reset0;
    wire [15:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_ia;
    wire [4:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_aa;
    wire [4:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_ab;
    wire [15:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_iq;
    wire [15:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_q;
    wire [4:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_i = 5'b11111;
    wire [5:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_a;
    wire [5:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_b;
    logic [5:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_o;
    wire [5:0] redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_q;
    reg [15:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_inputreg0_q;
    reg [15:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_outputreg0_q;
    wire redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_reset0;
    wire [15:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_ia;
    wire [4:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_aa;
    wire [4:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_ab;
    wire [15:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_iq;
    wire [15:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_q;
    wire [4:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_i = 5'b11111;
    wire [4:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_offset_q;
    wire [5:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_a;
    wire [5:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_b;
    logic [5:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_o;
    wire [5:0] redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_q;
    reg [15:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_inputreg0_q;
    reg [15:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_outputreg0_q;
    wire redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_reset0;
    wire [15:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_ia;
    wire [4:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_aa;
    wire [4:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_ab;
    wire [15:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_iq;
    wire [15:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_q;
    wire [4:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_i = 5'b11111;
    wire [5:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_a;
    wire [5:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_b;
    logic [5:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_o;
    wire [5:0] redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_q;
    reg [15:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_inputreg0_q;
    reg [15:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_outputreg0_q;
    wire redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_reset0;
    wire [15:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_ia;
    wire [4:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_aa;
    wire [4:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_ab;
    wire [15:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_iq;
    wire [15:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_q;
    wire [4:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_i = 5'b11111;
    wire [4:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_offset_q;
    wire [5:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_a;
    wire [5:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_b;
    logic [5:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_o;
    wire [5:0] redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_q;
    reg [15:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_inputreg0_q;
    reg [15:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_outputreg0_q;
    wire redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_reset0;
    wire [15:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_ia;
    wire [4:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_aa;
    wire [4:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_ab;
    wire [15:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_iq;
    wire [15:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_q;
    wire [4:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_i = 5'b11111;
    wire [5:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_a;
    wire [5:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_b;
    logic [5:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_o;
    wire [5:0] redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_q;
    reg [15:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_inputreg0_q;
    reg [15:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_outputreg0_q;
    wire redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_reset0;
    wire [15:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_ia;
    wire [4:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_aa;
    wire [4:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_ab;
    wire [15:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_iq;
    wire [15:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_q;
    wire [4:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_i = 5'b11111;
    wire [4:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_offset_q;
    wire [5:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_a;
    wire [5:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_b;
    logic [5:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_o;
    wire [5:0] redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_q;
    reg [15:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_inputreg0_q;
    reg [15:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_outputreg0_q;
    wire redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_reset0;
    wire [15:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_ia;
    wire [4:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_aa;
    wire [4:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_ab;
    wire [15:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_iq;
    wire [15:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_q;
    wire [4:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_i = 5'b11111;
    wire [5:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_a;
    wire [5:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_b;
    logic [5:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_o;
    wire [5:0] redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_q;
    reg [15:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_inputreg0_q;
    reg [15:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_outputreg0_q;
    wire redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_reset0;
    wire [15:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_ia;
    wire [4:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_aa;
    wire [4:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_ab;
    wire [15:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_iq;
    wire [15:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_q;
    wire [4:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_i = 5'b11111;
    wire [4:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_offset_q;
    wire [5:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_a;
    wire [5:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_b;
    logic [5:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_o;
    wire [5:0] redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_q;
    reg [15:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_inputreg0_q;
    reg [15:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_outputreg0_q;
    wire redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_reset0;
    wire [15:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_ia;
    wire [4:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_aa;
    wire [4:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_ab;
    wire [15:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_iq;
    wire [15:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_q;
    wire [4:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_i = 5'b11111;
    wire [5:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_a;
    wire [5:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_b;
    logic [5:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_o;
    wire [5:0] redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_q;
    reg [15:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_inputreg0_q;
    reg [15:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_outputreg0_q;
    wire redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_reset0;
    wire [15:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_ia;
    wire [4:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_aa;
    wire [4:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_ab;
    wire [15:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_iq;
    wire [15:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_q;
    wire [4:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_i = 5'b11111;
    wire [4:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_offset_q;
    wire [5:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_a;
    wire [5:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_b;
    logic [5:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_o;
    wire [5:0] redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_q;
    reg [15:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_inputreg0_q;
    reg [15:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_outputreg0_q;
    wire redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_reset0;
    wire [15:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_ia;
    wire [4:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_aa;
    wire [4:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_ab;
    wire [15:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_iq;
    wire [15:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_q;
    wire [4:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_i = 5'b11111;
    wire [5:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_a;
    wire [5:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_b;
    logic [5:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_o;
    wire [5:0] redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_q;
    reg [15:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_inputreg0_q;
    reg [15:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_outputreg0_q;
    wire redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_reset0;
    wire [15:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_ia;
    wire [4:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_aa;
    wire [4:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_ab;
    wire [15:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_iq;
    wire [15:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_q;
    wire [4:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_i = 5'b11111;
    wire [4:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_offset_q;
    wire [5:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_a;
    wire [5:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_b;
    logic [5:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_o;
    wire [5:0] redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_q;
    reg [15:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_inputreg0_q;
    reg [15:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_outputreg0_q;
    wire redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_reset0;
    wire [15:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_ia;
    wire [4:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_aa;
    wire [4:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_ab;
    wire [15:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_iq;
    wire [15:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_q;
    wire [4:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_i = 5'b11111;
    wire [5:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_a;
    wire [5:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_b;
    logic [5:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_o;
    wire [5:0] redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_q;
    reg [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_inputreg0_q;
    reg [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_outputreg0_q;
    reg [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_inputreg0_q;
    reg [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_outputreg0_q;
    reg [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_inputreg0_q;
    reg [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_outputreg0_q;
    wire redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_reset0;
    wire [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_ia;
    wire [1:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_aa;
    wire [1:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_ab;
    wire [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_iq;
    wire [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_q;
    wire [1:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_i = 2'b11;
    wire [1:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_offset_q;
    wire [2:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_a;
    wire [2:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_b;
    logic [2:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_o;
    wire [2:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_q;
    reg [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_inputreg0_q;
    reg [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_outputreg0_q;
    wire redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_reset0;
    wire [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_ia;
    wire [1:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_aa;
    wire [1:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_ab;
    wire [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_iq;
    wire [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_q;
    wire [1:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_i = 2'b11;
    wire [2:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_a;
    wire [2:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_b;
    logic [2:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_o;
    wire [2:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_q;
    reg [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_inputreg0_q;
    reg [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_outputreg0_q;
    wire redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_reset0;
    wire [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_ia;
    wire [2:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_aa;
    wire [2:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_ab;
    wire [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_iq;
    wire [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_q;
    wire [2:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_i = 3'b111;
    wire [2:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_offset_q;
    wire [3:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_a;
    wire [3:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_b;
    logic [3:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_o;
    wire [3:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_q;
    reg [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_inputreg0_q;
    reg [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_outputreg0_q;
    wire redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_reset0;
    wire [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_ia;
    wire [2:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_aa;
    wire [2:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_ab;
    wire [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_iq;
    wire [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_q;
    wire [2:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_i = 3'b111;
    wire [3:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_a;
    wire [3:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_b;
    logic [3:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_o;
    wire [3:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_q;
    reg [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_inputreg0_q;
    reg [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_outputreg0_q;
    wire redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_reset0;
    wire [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_ia;
    wire [2:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_aa;
    wire [2:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_ab;
    wire [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_iq;
    wire [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_q;
    wire [2:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_i = 3'b111;
    wire [2:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_offset_q;
    wire [3:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_a;
    wire [3:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_b;
    logic [3:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_o;
    wire [3:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_q;
    reg [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_inputreg0_q;
    reg [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_outputreg0_q;
    wire redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_reset0;
    wire [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_ia;
    wire [2:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_aa;
    wire [2:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_ab;
    wire [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_iq;
    wire [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_q;
    wire [2:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_i = 3'b111;
    wire [3:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_a;
    wire [3:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_b;
    logic [3:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_o;
    wire [3:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_q;
    reg [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_inputreg0_q;
    reg [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_outputreg0_q;
    wire redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_reset0;
    wire [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_ia;
    wire [3:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_aa;
    wire [3:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_ab;
    wire [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_iq;
    wire [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_q;
    wire [3:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_i = 4'b1111;
    wire [3:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_offset_q;
    wire [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_a;
    wire [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_b;
    logic [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_o;
    wire [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_q;
    reg [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_inputreg0_q;
    reg [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_outputreg0_q;
    wire redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_reset0;
    wire [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_ia;
    wire [3:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_aa;
    wire [3:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_ab;
    wire [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_iq;
    wire [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_q;
    wire [3:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_i = 4'b1111;
    wire [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_a;
    wire [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_b;
    logic [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_o;
    wire [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_q;
    reg [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_inputreg0_q;
    reg [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_outputreg0_q;
    wire redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_reset0;
    wire [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_ia;
    wire [3:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_aa;
    wire [3:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_ab;
    wire [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_iq;
    wire [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_q;
    wire [3:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_i = 4'b1111;
    wire [3:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_offset_q;
    wire [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_a;
    wire [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_b;
    logic [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_o;
    wire [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_q;
    reg [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_inputreg0_q;
    reg [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_outputreg0_q;
    wire redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_reset0;
    wire [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_ia;
    wire [3:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_aa;
    wire [3:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_ab;
    wire [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_iq;
    wire [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_q;
    wire [3:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_i = 4'b1111;
    wire [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_a;
    wire [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_b;
    logic [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_o;
    wire [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_q;
    reg [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_inputreg0_q;
    reg [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_outputreg0_q;
    wire redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_reset0;
    wire [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_ia;
    wire [3:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_aa;
    wire [3:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_ab;
    wire [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_iq;
    wire [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_q;
    wire [3:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_i = 4'b1111;
    wire [3:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_offset_q;
    wire [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_a;
    wire [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_b;
    logic [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_o;
    wire [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_q;
    reg [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_inputreg0_q;
    reg [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_outputreg0_q;
    wire redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_reset0;
    wire [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_ia;
    wire [3:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_aa;
    wire [3:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_ab;
    wire [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_iq;
    wire [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_q;
    wire [3:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_i = 4'b1111;
    wire [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_a;
    wire [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_b;
    logic [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_o;
    wire [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_q;
    reg [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_inputreg0_q;
    reg [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_outputreg0_q;
    wire redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_reset0;
    wire [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_ia;
    wire [3:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_aa;
    wire [3:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_ab;
    wire [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_iq;
    wire [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_q;
    wire [3:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_i = 4'b1111;
    wire [3:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_offset_q;
    wire [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_a;
    wire [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_b;
    logic [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_o;
    wire [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_q;
    reg [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_inputreg0_q;
    reg [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_outputreg0_q;
    wire redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_reset0;
    wire [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_ia;
    wire [3:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_aa;
    wire [3:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_ab;
    wire [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_iq;
    wire [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_q;
    wire [3:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_i = 4'b1111;
    wire [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_a;
    wire [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_b;
    logic [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_o;
    wire [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_q;
    reg [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_inputreg0_q;
    reg [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_outputreg0_q;
    wire redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_reset0;
    wire [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_ia;
    wire [4:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_aa;
    wire [4:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_ab;
    wire [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_iq;
    wire [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_q;
    wire [4:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_i = 5'b11111;
    wire [4:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_offset_q;
    wire [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_a;
    wire [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_b;
    logic [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_o;
    wire [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_q;
    reg [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_inputreg0_q;
    reg [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_outputreg0_q;
    wire redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_reset0;
    wire [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_ia;
    wire [4:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_aa;
    wire [4:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_ab;
    wire [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_iq;
    wire [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_q;
    wire [4:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_i = 5'b11111;
    wire [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_a;
    wire [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_b;
    logic [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_o;
    wire [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_q;
    reg [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_inputreg0_q;
    reg [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_outputreg0_q;
    wire redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_reset0;
    wire [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_ia;
    wire [4:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_aa;
    wire [4:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_ab;
    wire [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_iq;
    wire [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_q;
    wire [4:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_i = 5'b11111;
    wire [4:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_offset_q;
    wire [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_a;
    wire [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_b;
    logic [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_o;
    wire [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_q;
    reg [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_inputreg0_q;
    reg [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_outputreg0_q;
    wire redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_reset0;
    wire [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_ia;
    wire [4:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_aa;
    wire [4:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_ab;
    wire [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_iq;
    wire [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_q;
    wire [4:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_i = 5'b11111;
    wire [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_a;
    wire [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_b;
    logic [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_o;
    wire [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_q;
    reg [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_inputreg0_q;
    reg [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_outputreg0_q;
    wire redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_reset0;
    wire [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_ia;
    wire [4:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_aa;
    wire [4:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_ab;
    wire [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_iq;
    wire [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_q;
    wire [4:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_i = 5'b11111;
    wire [4:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_offset_q;
    wire [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_a;
    wire [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_b;
    logic [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_o;
    wire [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_q;
    reg [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_inputreg0_q;
    reg [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_outputreg0_q;
    wire redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_reset0;
    wire [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_ia;
    wire [4:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_aa;
    wire [4:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_ab;
    wire [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_iq;
    wire [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_q;
    wire [4:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_i = 5'b11111;
    wire [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_a;
    wire [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_b;
    logic [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_o;
    wire [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_q;
    reg [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_inputreg0_q;
    reg [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_outputreg0_q;
    wire redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_reset0;
    wire [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_ia;
    wire [4:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_aa;
    wire [4:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_ab;
    wire [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_iq;
    wire [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_q;
    wire [4:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_i = 5'b11111;
    wire [4:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_offset_q;
    wire [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_a;
    wire [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_b;
    logic [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_o;
    wire [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_q;
    reg [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_inputreg0_q;
    reg [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_outputreg0_q;
    wire redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_reset0;
    wire [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_ia;
    wire [4:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_aa;
    wire [4:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_ab;
    wire [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_iq;
    wire [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_q;
    wire [4:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_i = 5'b11111;
    wire [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_a;
    wire [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_b;
    logic [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_o;
    wire [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_q;
    reg [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_inputreg0_q;
    reg [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_outputreg0_q;
    wire redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_reset0;
    wire [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_ia;
    wire [4:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_aa;
    wire [4:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_ab;
    wire [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_iq;
    wire [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_q;
    wire [4:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_i = 5'b11111;
    wire [4:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_offset_q;
    wire [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_a;
    wire [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_b;
    logic [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_o;
    wire [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_q;
    reg [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_inputreg0_q;
    reg [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_outputreg0_q;
    wire redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_reset0;
    wire [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_ia;
    wire [4:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_aa;
    wire [4:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_ab;
    wire [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_iq;
    wire [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_q;
    wire [4:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_i = 5'b11111;
    wire [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_a;
    wire [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_b;
    logic [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_o;
    wire [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_q;
    reg [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_inputreg0_q;
    reg [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_outputreg0_q;
    wire redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_reset0;
    wire [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_ia;
    wire [4:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_aa;
    wire [4:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_ab;
    wire [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_iq;
    wire [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_q;
    wire [4:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_i = 5'b11111;
    wire [4:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_offset_q;
    wire [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_a;
    wire [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_b;
    logic [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_o;
    wire [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_q;
    reg [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_inputreg0_q;
    reg [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_outputreg0_q;
    wire redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_reset0;
    wire [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_ia;
    wire [4:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_aa;
    wire [4:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_ab;
    wire [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_iq;
    wire [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_q;
    wire [4:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_i = 5'b11111;
    wire [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_a;
    wire [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_b;
    logic [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_o;
    wire [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_q;
    reg [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_inputreg0_q;
    reg [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_outputreg0_q;
    wire redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_reset0;
    wire [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_ia;
    wire [4:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_aa;
    wire [4:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_ab;
    wire [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_iq;
    wire [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_q;
    wire [4:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_i = 5'b11111;
    wire [4:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q;
    wire [5:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_a;
    wire [5:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_b;
    logic [5:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_o;
    wire [5:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_q;
    reg [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_inputreg0_q;
    reg [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_outputreg0_q;
    wire redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_reset0;
    wire [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_ia;
    wire [4:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_aa;
    wire [4:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_ab;
    wire [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_iq;
    wire [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_q;
    wire [4:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_i = 5'b11111;
    wire [5:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_a;
    wire [5:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_b;
    logic [5:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_o;
    wire [5:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_q;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_inputreg0_q;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_inputreg0_q;
    reg [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_inputreg0_q;
    reg [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_outputreg0_q;
    wire redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_reset0;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_ia;
    wire [1:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_aa;
    wire [1:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_ab;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_iq;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_q;
    wire [1:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_i = 2'b11;
    wire [2:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_a;
    wire [2:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_b;
    logic [2:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_o;
    wire [2:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_q;
    reg [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_inputreg0_q;
    reg [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_outputreg0_q;
    wire redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_reset0;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_ia;
    wire [1:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_aa;
    wire [1:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_ab;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_iq;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_q;
    wire [1:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [1:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_i = 2'b11;
    wire [2:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_a;
    wire [2:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_b;
    logic [2:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_o;
    wire [2:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_q;
    reg [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_inputreg0_q;
    reg [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_outputreg0_q;
    wire redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_reset0;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_ia;
    wire [2:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_aa;
    wire [2:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_ab;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_iq;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_q;
    wire [2:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_i = 3'b111;
    wire [3:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_a;
    wire [3:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_b;
    logic [3:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_o;
    wire [3:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_q;
    reg [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_inputreg0_q;
    reg [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_outputreg0_q;
    wire redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_reset0;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_ia;
    wire [2:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_aa;
    wire [2:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_ab;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_iq;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_q;
    wire [2:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_i = 3'b111;
    wire [3:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_a;
    wire [3:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_b;
    logic [3:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_o;
    wire [3:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_q;
    reg [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_inputreg0_q;
    reg [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_outputreg0_q;
    wire redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_reset0;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_ia;
    wire [2:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_aa;
    wire [2:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_ab;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_iq;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_q;
    wire [2:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_i = 3'b111;
    wire [3:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_a;
    wire [3:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_b;
    logic [3:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_o;
    wire [3:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_q;
    reg [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_inputreg0_q;
    reg [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_outputreg0_q;
    wire redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_reset0;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_ia;
    wire [2:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_aa;
    wire [2:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_ab;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_iq;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_q;
    wire [2:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [2:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_i = 3'b111;
    wire [3:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_a;
    wire [3:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_b;
    logic [3:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_o;
    wire [3:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_q;
    reg [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_inputreg0_q;
    reg [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_outputreg0_q;
    wire redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_reset0;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_ia;
    wire [3:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_aa;
    wire [3:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_ab;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_iq;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_q;
    wire [3:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_i = 4'b1111;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_a;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_b;
    logic [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_o;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_q;
    reg [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_inputreg0_q;
    reg [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_outputreg0_q;
    wire redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_reset0;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_ia;
    wire [3:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_aa;
    wire [3:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_ab;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_iq;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_q;
    wire [3:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_i = 4'b1111;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_a;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_b;
    logic [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_o;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_q;
    reg [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_inputreg0_q;
    reg [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_outputreg0_q;
    wire redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_reset0;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_ia;
    wire [3:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_aa;
    wire [3:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_ab;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_iq;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_q;
    wire [3:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_i = 4'b1111;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_a;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_b;
    logic [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_o;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_q;
    reg [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_inputreg0_q;
    reg [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_outputreg0_q;
    wire redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_reset0;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_ia;
    wire [3:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_aa;
    wire [3:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_ab;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_iq;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_q;
    wire [3:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_i = 4'b1111;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_a;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_b;
    logic [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_o;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_q;
    reg [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_inputreg0_q;
    reg [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_outputreg0_q;
    wire redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_reset0;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_ia;
    wire [3:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_aa;
    wire [3:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_ab;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_iq;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_q;
    wire [3:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_i = 4'b1111;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_a;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_b;
    logic [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_o;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_q;
    reg [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_inputreg0_q;
    reg [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_outputreg0_q;
    wire redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_reset0;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_ia;
    wire [3:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_aa;
    wire [3:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_ab;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_iq;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_q;
    wire [3:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [3:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_i = 4'b1111;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_a;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_b;
    logic [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_o;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_q;
    reg [15:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_inputreg0_q;
    reg [15:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_outputreg0_q;
    wire redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_reset0;
    wire [15:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_ia;
    wire [6:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_aa;
    wire [6:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_ab;
    wire [15:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_iq;
    wire [15:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_q;
    wire [6:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_i = 7'b1111111;
    wire [6:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_offset_q;
    wire [7:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_a;
    wire [7:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_b;
    logic [7:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_o;
    wire [7:0] redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_q;
    reg [15:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_inputreg0_q;
    reg [15:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_outputreg0_q;
    wire redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_reset0;
    wire [15:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_ia;
    wire [6:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_aa;
    wire [6:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_ab;
    wire [15:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_iq;
    wire [15:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_q;
    wire [6:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_i = 7'b1111111;
    wire [7:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_a;
    wire [7:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_b;
    logic [7:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_o;
    wire [7:0] redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_q;
    reg [15:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_inputreg0_q;
    reg [15:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_outputreg0_q;
    wire redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_reset0;
    wire [15:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_ia;
    wire [6:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_aa;
    wire [6:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_ab;
    wire [15:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_iq;
    wire [15:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_q;
    wire [6:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_i = 7'b1111111;
    wire [6:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_offset_q;
    wire [7:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_a;
    wire [7:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_b;
    logic [7:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_o;
    wire [7:0] redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_q;
    reg [15:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_inputreg0_q;
    reg [15:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_outputreg0_q;
    wire redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_reset0;
    wire [15:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_ia;
    wire [6:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_aa;
    wire [6:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_ab;
    wire [15:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_iq;
    wire [15:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_q;
    wire [6:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_i = 7'b1111111;
    wire [7:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_a;
    wire [7:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_b;
    logic [7:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_o;
    wire [7:0] redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_q;
    reg [15:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_inputreg0_q;
    reg [15:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_outputreg0_q;
    wire redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_reset0;
    wire [15:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_ia;
    wire [6:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_aa;
    wire [6:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_ab;
    wire [15:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_iq;
    wire [15:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_q;
    wire [6:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_i = 7'b1111111;
    wire [6:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_offset_q;
    wire [7:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_a;
    wire [7:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_b;
    logic [7:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_o;
    wire [7:0] redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_q;
    reg [15:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_inputreg0_q;
    reg [15:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_outputreg0_q;
    wire redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_reset0;
    wire [15:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_ia;
    wire [6:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_aa;
    wire [6:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_ab;
    wire [15:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_iq;
    wire [15:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_q;
    wire [6:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_i = 7'b1111111;
    wire [7:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_a;
    wire [7:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_b;
    logic [7:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_o;
    wire [7:0] redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_q;
    reg [15:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_inputreg0_q;
    reg [15:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_outputreg0_q;
    wire redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_reset0;
    wire [15:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_ia;
    wire [6:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_aa;
    wire [6:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_ab;
    wire [15:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_iq;
    wire [15:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_q;
    wire [6:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_i = 7'b1111111;
    wire [6:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_offset_q;
    wire [7:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_a;
    wire [7:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_b;
    logic [7:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_o;
    wire [7:0] redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_q;
    reg [15:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_inputreg0_q;
    reg [15:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_outputreg0_q;
    wire redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_reset0;
    wire [15:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_ia;
    wire [6:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_aa;
    wire [6:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_ab;
    wire [15:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_iq;
    wire [15:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_q;
    wire [6:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_i = 7'b1111111;
    wire [7:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_a;
    wire [7:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_b;
    logic [7:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_o;
    wire [7:0] redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_q;
    reg [15:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_inputreg0_q;
    reg [15:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_outputreg0_q;
    wire redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_reset0;
    wire [15:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_ia;
    wire [6:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_aa;
    wire [6:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_ab;
    wire [15:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_iq;
    wire [15:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_q;
    wire [6:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_i = 7'b1111111;
    wire [6:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_offset_q;
    wire [7:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_a;
    wire [7:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_b;
    logic [7:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_o;
    wire [7:0] redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_q;
    reg [15:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_inputreg0_q;
    reg [15:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_outputreg0_q;
    wire redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_reset0;
    wire [15:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_ia;
    wire [6:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_aa;
    wire [6:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_ab;
    wire [15:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_iq;
    wire [15:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_q;
    wire [6:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_i = 7'b1111111;
    wire [7:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_a;
    wire [7:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_b;
    logic [7:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_o;
    wire [7:0] redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_q;
    reg [15:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_inputreg0_q;
    reg [15:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_outputreg0_q;
    wire redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_reset0;
    wire [15:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_ia;
    wire [6:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_aa;
    wire [6:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_ab;
    wire [15:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_iq;
    wire [15:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_q;
    wire [6:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_i = 7'b1111111;
    wire [6:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_offset_q;
    wire [7:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_a;
    wire [7:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_b;
    logic [7:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_o;
    wire [7:0] redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_q;
    reg [15:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_inputreg0_q;
    reg [15:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_outputreg0_q;
    wire redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_reset0;
    wire [15:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_ia;
    wire [6:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_aa;
    wire [6:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_ab;
    wire [15:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_iq;
    wire [15:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_q;
    wire [6:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_i = 7'b1111111;
    wire [7:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_a;
    wire [7:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_b;
    logic [7:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_o;
    wire [7:0] redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_q;
    reg [15:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_inputreg0_q;
    reg [15:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_outputreg0_q;
    wire redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_reset0;
    wire [15:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_ia;
    wire [6:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_aa;
    wire [6:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_ab;
    wire [15:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_iq;
    wire [15:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_q;
    wire [6:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_i = 7'b1111111;
    wire [6:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_offset_q;
    wire [7:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_a;
    wire [7:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_b;
    logic [7:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_o;
    wire [7:0] redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_q;
    reg [15:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_inputreg0_q;
    reg [15:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_outputreg0_q;
    wire redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_reset0;
    wire [15:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_ia;
    wire [6:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_aa;
    wire [6:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_ab;
    wire [15:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_iq;
    wire [15:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_q;
    wire [6:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_i = 7'b1111111;
    wire [7:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_a;
    wire [7:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_b;
    logic [7:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_o;
    wire [7:0] redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_q;
    reg [15:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_inputreg0_q;
    reg [15:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_outputreg0_q;
    wire redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_reset0;
    wire [15:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_ia;
    wire [6:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_aa;
    wire [6:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_ab;
    wire [15:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_iq;
    wire [15:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_q;
    wire [6:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_i = 7'b1111111;
    wire [6:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_offset_q;
    wire [7:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_a;
    wire [7:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_b;
    logic [7:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_o;
    wire [7:0] redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_q;
    reg [15:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_inputreg0_q;
    reg [15:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_outputreg0_q;
    wire redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_reset0;
    wire [15:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_ia;
    wire [6:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_aa;
    wire [6:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_ab;
    wire [15:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_iq;
    wire [15:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_q;
    wire [6:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_i = 7'b1111111;
    wire [7:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_a;
    wire [7:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_b;
    logic [7:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_o;
    wire [7:0] redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_q;
    reg [15:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_inputreg0_q;
    reg [15:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_outputreg0_q;
    wire redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_reset0;
    wire [15:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_ia;
    wire [6:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_aa;
    wire [6:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_ab;
    wire [15:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_iq;
    wire [15:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_q;
    wire [6:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_i = 7'b1111111;
    wire [6:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_offset_q;
    wire [7:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_a;
    wire [7:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_b;
    logic [7:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_o;
    wire [7:0] redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_q;
    reg [15:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_inputreg0_q;
    reg [15:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_outputreg0_q;
    wire redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_reset0;
    wire [15:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_ia;
    wire [6:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_aa;
    wire [6:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_ab;
    wire [15:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_iq;
    wire [15:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_q;
    wire [6:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_i = 7'b1111111;
    wire [7:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_a;
    wire [7:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_b;
    logic [7:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_o;
    wire [7:0] redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_q;
    reg [15:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_inputreg0_q;
    reg [15:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_outputreg0_q;
    wire redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_reset0;
    wire [15:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_ia;
    wire [6:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_aa;
    wire [6:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_ab;
    wire [15:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_iq;
    wire [15:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_q;
    wire [6:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_i = 7'b1111111;
    wire [6:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_offset_q;
    wire [7:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_a;
    wire [7:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_b;
    logic [7:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_o;
    wire [7:0] redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_q;
    reg [15:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_inputreg0_q;
    reg [15:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_outputreg0_q;
    wire redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_reset0;
    wire [15:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_ia;
    wire [6:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_aa;
    wire [6:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_ab;
    wire [15:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_iq;
    wire [15:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_q;
    wire [6:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_i = 7'b1111111;
    wire [7:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_a;
    wire [7:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_b;
    logic [7:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_o;
    wire [7:0] redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_q;
    reg [15:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_inputreg0_q;
    reg [15:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_outputreg0_q;
    wire redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_reset0;
    wire [15:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_ia;
    wire [6:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_aa;
    wire [6:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_ab;
    wire [15:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_iq;
    wire [15:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_q;
    wire [6:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_i = 7'b1111111;
    wire [6:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_offset_q;
    wire [7:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_a;
    wire [7:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_b;
    logic [7:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_o;
    wire [7:0] redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_q;
    reg [15:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_inputreg0_q;
    reg [15:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_outputreg0_q;
    wire redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_reset0;
    wire [15:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_ia;
    wire [6:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_aa;
    wire [6:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_ab;
    wire [15:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_iq;
    wire [15:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_q;
    wire [6:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_i = 7'b1111111;
    wire [7:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_a;
    wire [7:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_b;
    logic [7:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_o;
    wire [7:0] redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_q;
    reg [15:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_inputreg0_q;
    reg [15:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_outputreg0_q;
    wire redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_reset0;
    wire [15:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_ia;
    wire [6:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_aa;
    wire [6:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_ab;
    wire [15:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_iq;
    wire [15:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_q;
    wire [6:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_i = 7'b1111111;
    wire [6:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_offset_q;
    wire [7:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_a;
    wire [7:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_b;
    logic [7:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_o;
    wire [7:0] redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_q;
    reg [15:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_inputreg0_q;
    reg [15:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_outputreg0_q;
    wire redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_reset0;
    wire [15:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_ia;
    wire [6:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_aa;
    wire [6:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_ab;
    wire [15:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_iq;
    wire [15:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_q;
    wire [6:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_i = 7'b1111111;
    wire [7:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_a;
    wire [7:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_b;
    logic [7:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_o;
    wire [7:0] redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_q;
    reg [15:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_inputreg0_q;
    reg [15:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_outputreg0_q;
    wire redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_reset0;
    wire [15:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_ia;
    wire [6:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_aa;
    wire [6:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_ab;
    wire [15:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_iq;
    wire [15:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_q;
    wire [6:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_i = 7'b1111111;
    wire [6:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_offset_q;
    wire [7:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_a;
    wire [7:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_b;
    logic [7:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_o;
    wire [7:0] redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_q;
    reg [15:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_inputreg0_q;
    reg [15:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_outputreg0_q;
    wire redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_reset0;
    wire [15:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_ia;
    wire [6:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_aa;
    wire [6:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_ab;
    wire [15:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_iq;
    wire [15:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_q;
    wire [6:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_i = 7'b1111111;
    wire [7:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_a;
    wire [7:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_b;
    logic [7:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_o;
    wire [7:0] redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_q;
    reg [15:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_inputreg0_q;
    reg [15:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_outputreg0_q;
    wire redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_reset0;
    wire [15:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_ia;
    wire [6:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_aa;
    wire [6:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_ab;
    wire [15:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_iq;
    wire [15:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_q;
    wire [6:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_i = 7'b1111111;
    wire [6:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_offset_q;
    wire [7:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_a;
    wire [7:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_b;
    logic [7:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_o;
    wire [7:0] redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_q;
    reg [15:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_inputreg0_q;
    reg [15:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_outputreg0_q;
    wire redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_reset0;
    wire [15:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_ia;
    wire [6:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_aa;
    wire [6:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_ab;
    wire [15:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_iq;
    wire [15:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_q;
    wire [6:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_i = 7'b1111111;
    wire [7:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_a;
    wire [7:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_b;
    logic [7:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_o;
    wire [7:0] redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_q;
    reg [15:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_inputreg0_q;
    reg [15:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_outputreg0_q;
    wire redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_reset0;
    wire [15:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_ia;
    wire [6:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_aa;
    wire [6:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_ab;
    wire [15:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_iq;
    wire [15:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_q;
    wire [6:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_i = 7'b1111111;
    wire [6:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_offset_q;
    wire [7:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_a;
    wire [7:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_b;
    logic [7:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_o;
    wire [7:0] redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_q;
    reg [15:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_inputreg0_q;
    reg [15:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_outputreg0_q;
    wire redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_reset0;
    wire [15:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_ia;
    wire [6:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_aa;
    wire [6:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_ab;
    wire [15:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_iq;
    wire [15:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_q;
    wire [6:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_i = 7'b1111111;
    wire [7:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_a;
    wire [7:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_b;
    logic [7:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_o;
    wire [7:0] redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_q;
    reg [15:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_inputreg0_q;
    reg [15:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_outputreg0_q;
    wire redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_reset0;
    wire [15:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_ia;
    wire [6:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_aa;
    wire [6:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_ab;
    wire [15:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_iq;
    wire [15:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_q;
    wire [6:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_i = 7'b1111111;
    wire [6:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_offset_q;
    wire [7:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_a;
    wire [7:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_b;
    logic [7:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_o;
    wire [7:0] redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_q;
    reg [15:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_inputreg0_q;
    reg [15:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_outputreg0_q;
    wire redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_reset0;
    wire [15:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_ia;
    wire [6:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_aa;
    wire [6:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_ab;
    wire [15:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_iq;
    wire [15:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_q;
    wire [6:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_i = 7'b1111111;
    wire [7:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_a;
    wire [7:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_b;
    logic [7:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_o;
    wire [7:0] redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_q;
    reg [15:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_inputreg0_q;
    reg [15:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_outputreg0_q;
    wire redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_reset0;
    wire [15:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_ia;
    wire [6:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_aa;
    wire [6:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_ab;
    wire [15:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_iq;
    wire [15:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_q;
    wire [6:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_i = 7'b1111111;
    wire [6:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_offset_q;
    wire [7:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_a;
    wire [7:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_b;
    logic [7:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_o;
    wire [7:0] redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_q;
    reg [15:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_inputreg0_q;
    reg [15:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_outputreg0_q;
    wire redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_reset0;
    wire [15:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_ia;
    wire [6:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_aa;
    wire [6:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_ab;
    wire [15:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_iq;
    wire [15:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_q;
    wire [6:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_i = 7'b1111111;
    wire [7:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_a;
    wire [7:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_b;
    logic [7:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_o;
    wire [7:0] redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_q;
    reg [15:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_inputreg0_q;
    reg [15:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_outputreg0_q;
    wire redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_reset0;
    wire [15:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_ia;
    wire [6:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_aa;
    wire [6:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_ab;
    wire [15:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_iq;
    wire [15:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_q;
    wire [6:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_i = 7'b1111111;
    wire [6:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_offset_q;
    wire [7:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_a;
    wire [7:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_b;
    logic [7:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_o;
    wire [7:0] redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_q;
    reg [15:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_inputreg0_q;
    reg [15:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_outputreg0_q;
    wire redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_reset0;
    wire [15:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_ia;
    wire [6:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_aa;
    wire [6:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_ab;
    wire [15:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_iq;
    wire [15:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_q;
    wire [6:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_i = 7'b1111111;
    wire [7:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_a;
    wire [7:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_b;
    logic [7:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_o;
    wire [7:0] redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_q;
    reg [15:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_inputreg0_q;
    reg [15:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_outputreg0_q;
    wire redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_reset0;
    wire [15:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_ia;
    wire [6:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_aa;
    wire [6:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_ab;
    wire [15:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_iq;
    wire [15:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_q;
    wire [6:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_i = 7'b1111111;
    wire [6:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_offset_q;
    wire [7:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_a;
    wire [7:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_b;
    logic [7:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_o;
    wire [7:0] redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_q;
    reg [15:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_inputreg0_q;
    reg [15:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_outputreg0_q;
    wire redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_reset0;
    wire [15:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_ia;
    wire [6:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_aa;
    wire [6:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_ab;
    wire [15:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_iq;
    wire [15:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_q;
    wire [6:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_i = 7'b1111111;
    wire [7:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_a;
    wire [7:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_b;
    logic [7:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_o;
    wire [7:0] redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_q;
    reg [15:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_inputreg0_q;
    reg [15:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_outputreg0_q;
    wire redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_reset0;
    wire [15:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_ia;
    wire [6:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_aa;
    wire [6:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_ab;
    wire [15:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_iq;
    wire [15:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_q;
    wire [6:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_i = 7'b1111111;
    wire [6:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_offset_q;
    wire [7:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_a;
    wire [7:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_b;
    logic [7:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_o;
    wire [7:0] redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_q;
    reg [15:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_inputreg0_q;
    reg [15:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_outputreg0_q;
    wire redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_reset0;
    wire [15:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_ia;
    wire [6:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_aa;
    wire [6:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_ab;
    wire [15:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_iq;
    wire [15:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_q;
    wire [6:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_i = 7'b1111111;
    wire [7:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_a;
    wire [7:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_b;
    logic [7:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_o;
    wire [7:0] redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_q;
    reg [15:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_inputreg0_q;
    reg [15:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_outputreg0_q;
    wire redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_reset0;
    wire [15:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_ia;
    wire [6:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_aa;
    wire [6:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_ab;
    wire [15:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_iq;
    wire [15:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_q;
    wire [6:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_i = 7'b1111111;
    wire [6:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_offset_q;
    wire [7:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_a;
    wire [7:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_b;
    logic [7:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_o;
    wire [7:0] redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_q;
    reg [15:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_inputreg0_q;
    reg [15:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_outputreg0_q;
    wire redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_reset0;
    wire [15:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_ia;
    wire [6:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_aa;
    wire [6:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_ab;
    wire [15:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_iq;
    wire [15:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_q;
    wire [6:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_i = 7'b1111111;
    wire [7:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_a;
    wire [7:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_b;
    logic [7:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_o;
    wire [7:0] redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_q;
    reg [15:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_inputreg0_q;
    reg [15:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_outputreg0_q;
    wire redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_reset0;
    wire [15:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_ia;
    wire [6:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_aa;
    wire [6:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_ab;
    wire [15:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_iq;
    wire [15:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_q;
    wire [6:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_i = 7'b1111111;
    wire [6:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_offset_q;
    wire [7:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_a;
    wire [7:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_b;
    logic [7:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_o;
    wire [7:0] redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_q;
    reg [15:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_inputreg0_q;
    reg [15:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_outputreg0_q;
    wire redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_reset0;
    wire [15:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_ia;
    wire [6:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_aa;
    wire [6:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_ab;
    wire [15:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_iq;
    wire [15:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_q;
    wire [6:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_i = 7'b1111111;
    wire [7:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_a;
    wire [7:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_b;
    logic [7:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_o;
    wire [7:0] redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_q;
    reg [15:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_inputreg0_q;
    reg [15:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_outputreg0_q;
    wire redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_reset0;
    wire [15:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_ia;
    wire [6:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_aa;
    wire [6:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_ab;
    wire [15:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_iq;
    wire [15:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_q;
    wire [6:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_i = 7'b1111111;
    wire [6:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_offset_q;
    wire [7:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_a;
    wire [7:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_b;
    logic [7:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_o;
    wire [7:0] redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_q;
    reg [15:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_inputreg0_q;
    reg [15:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_outputreg0_q;
    wire redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_reset0;
    wire [15:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_ia;
    wire [6:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_aa;
    wire [6:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_ab;
    wire [15:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_iq;
    wire [15:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_q;
    wire [6:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_i = 7'b1111111;
    wire [7:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_a;
    wire [7:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_b;
    logic [7:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_o;
    wire [7:0] redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_q;
    reg [15:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_inputreg0_q;
    reg [15:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_outputreg0_q;
    wire redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_reset0;
    wire [15:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_ia;
    wire [6:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_aa;
    wire [6:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_ab;
    wire [15:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_iq;
    wire [15:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_q;
    wire [6:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_i = 7'b1111111;
    wire [6:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_offset_q;
    wire [7:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_a;
    wire [7:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_b;
    logic [7:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_o;
    wire [7:0] redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_q;
    reg [15:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_inputreg0_q;
    reg [15:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_outputreg0_q;
    wire redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_reset0;
    wire [15:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_ia;
    wire [6:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_aa;
    wire [6:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_ab;
    wire [15:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_iq;
    wire [15:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_q;
    wire [6:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [6:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_i = 7'b1111111;
    wire [7:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_a;
    wire [7:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_b;
    logic [7:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_o;
    wire [7:0] redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_q;
    reg [15:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_inputreg0_q;
    reg [15:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_outputreg0_q;
    wire redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_reset0;
    wire [15:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_ia;
    wire [7:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_aa;
    wire [7:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_ab;
    wire [15:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_iq;
    wire [15:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_q;
    wire [7:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_i = 8'b11111111;
    wire [7:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_offset_q;
    wire [8:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_a;
    wire [8:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_b;
    logic [8:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_o;
    wire [8:0] redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_q;
    reg [15:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_inputreg0_q;
    reg [15:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_outputreg0_q;
    wire redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_reset0;
    wire [15:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_ia;
    wire [7:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_aa;
    wire [7:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_ab;
    wire [15:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_iq;
    wire [15:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_q;
    wire [7:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_i = 8'b11111111;
    wire [8:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_a;
    wire [8:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_b;
    logic [8:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_o;
    wire [8:0] redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_q;
    reg [15:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_inputreg0_q;
    reg [15:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_outputreg0_q;
    wire redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_reset0;
    wire [15:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_ia;
    wire [7:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_aa;
    wire [7:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_ab;
    wire [15:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_iq;
    wire [15:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_q;
    wire [7:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_i = 8'b11111111;
    wire [7:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_offset_q;
    wire [8:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_a;
    wire [8:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_b;
    logic [8:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_o;
    wire [8:0] redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_q;
    reg [15:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_inputreg0_q;
    reg [15:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_outputreg0_q;
    wire redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_reset0;
    wire [15:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_ia;
    wire [7:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_aa;
    wire [7:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_ab;
    wire [15:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_iq;
    wire [15:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_q;
    wire [7:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_i = 8'b11111111;
    wire [8:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_a;
    wire [8:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_b;
    logic [8:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_o;
    wire [8:0] redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_q;
    reg [15:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_inputreg0_q;
    reg [15:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_outputreg0_q;
    wire redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_reset0;
    wire [15:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_ia;
    wire [7:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_aa;
    wire [7:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_ab;
    wire [15:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_iq;
    wire [15:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_q;
    wire [7:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_i = 8'b11111111;
    wire [7:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_offset_q;
    wire [8:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_a;
    wire [8:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_b;
    logic [8:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_o;
    wire [8:0] redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_q;
    reg [15:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_inputreg0_q;
    reg [15:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_outputreg0_q;
    wire redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_reset0;
    wire [15:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_ia;
    wire [7:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_aa;
    wire [7:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_ab;
    wire [15:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_iq;
    wire [15:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_q;
    wire [7:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_i = 8'b11111111;
    wire [8:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_a;
    wire [8:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_b;
    logic [8:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_o;
    wire [8:0] redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_q;
    reg [15:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_inputreg0_q;
    reg [15:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_outputreg0_q;
    wire redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_reset0;
    wire [15:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_ia;
    wire [7:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_aa;
    wire [7:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_ab;
    wire [15:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_iq;
    wire [15:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_q;
    wire [7:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_i = 8'b11111111;
    wire [7:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_offset_q;
    wire [8:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_a;
    wire [8:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_b;
    logic [8:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_o;
    wire [8:0] redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_q;
    reg [15:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_inputreg0_q;
    reg [15:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_outputreg0_q;
    wire redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_reset0;
    wire [15:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_ia;
    wire [7:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_aa;
    wire [7:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_ab;
    wire [15:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_iq;
    wire [15:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_q;
    wire [7:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_i = 8'b11111111;
    wire [8:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_a;
    wire [8:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_b;
    logic [8:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_o;
    wire [8:0] redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_q;
    reg [15:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_inputreg0_q;
    reg [15:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_outputreg0_q;
    wire redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_reset0;
    wire [15:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_ia;
    wire [7:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_aa;
    wire [7:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_ab;
    wire [15:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_iq;
    wire [15:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_q;
    wire [7:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_i = 8'b11111111;
    wire [7:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_offset_q;
    wire [8:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_a;
    wire [8:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_b;
    logic [8:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_o;
    wire [8:0] redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_q;
    reg [15:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_inputreg0_q;
    reg [15:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_outputreg0_q;
    wire redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_reset0;
    wire [15:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_ia;
    wire [7:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_aa;
    wire [7:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_ab;
    wire [15:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_iq;
    wire [15:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_q;
    wire [7:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_i = 8'b11111111;
    wire [8:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_a;
    wire [8:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_b;
    logic [8:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_o;
    wire [8:0] redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_q;
    reg [15:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_inputreg0_q;
    reg [15:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_outputreg0_q;
    wire redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_reset0;
    wire [15:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_ia;
    wire [7:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_aa;
    wire [7:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_ab;
    wire [15:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_iq;
    wire [15:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_q;
    wire [7:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_i = 8'b11111111;
    wire [7:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_offset_q;
    wire [8:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_a;
    wire [8:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_b;
    logic [8:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_o;
    wire [8:0] redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_q;
    reg [15:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_inputreg0_q;
    reg [15:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_outputreg0_q;
    wire redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_reset0;
    wire [15:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_ia;
    wire [7:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_aa;
    wire [7:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_ab;
    wire [15:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_iq;
    wire [15:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_q;
    wire [7:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_i = 8'b11111111;
    wire [8:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_a;
    wire [8:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_b;
    logic [8:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_o;
    wire [8:0] redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_q;
    reg [15:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_inputreg0_q;
    reg [15:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_outputreg0_q;
    wire redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_reset0;
    wire [15:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_ia;
    wire [7:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_aa;
    wire [7:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_ab;
    wire [15:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_iq;
    wire [15:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_q;
    wire [7:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_i = 8'b11111111;
    wire [7:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_offset_q;
    wire [8:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_a;
    wire [8:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_b;
    logic [8:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_o;
    wire [8:0] redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_q;
    reg [15:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_inputreg0_q;
    reg [15:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_outputreg0_q;
    wire redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_reset0;
    wire [15:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_ia;
    wire [7:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_aa;
    wire [7:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_ab;
    wire [15:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_iq;
    wire [15:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_q;
    wire [7:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_i = 8'b11111111;
    wire [8:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_a;
    wire [8:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_b;
    logic [8:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_o;
    wire [8:0] redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_q;
    reg [15:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_inputreg0_q;
    reg [15:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_outputreg0_q;
    wire redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_reset0;
    wire [15:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_ia;
    wire [7:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_aa;
    wire [7:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_ab;
    wire [15:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_iq;
    wire [15:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_q;
    wire [7:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_i = 8'b11111111;
    wire [7:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_offset_q;
    wire [8:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_a;
    wire [8:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_b;
    logic [8:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_o;
    wire [8:0] redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_q;
    reg [15:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_inputreg0_q;
    reg [15:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_outputreg0_q;
    wire redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_reset0;
    wire [15:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_ia;
    wire [7:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_aa;
    wire [7:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_ab;
    wire [15:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_iq;
    wire [15:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_q;
    wire [7:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_i = 8'b11111111;
    wire [8:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_a;
    wire [8:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_b;
    logic [8:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_o;
    wire [8:0] redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_q;
    reg [15:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_inputreg0_q;
    reg [15:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_outputreg0_q;
    wire redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_reset0;
    wire [15:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_ia;
    wire [7:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_aa;
    wire [7:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_ab;
    wire [15:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_iq;
    wire [15:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_q;
    wire [7:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_i = 8'b11111111;
    wire [7:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_offset_q;
    wire [8:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_a;
    wire [8:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_b;
    logic [8:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_o;
    wire [8:0] redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_q;
    reg [15:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_inputreg0_q;
    reg [15:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_outputreg0_q;
    wire redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_reset0;
    wire [15:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_ia;
    wire [7:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_aa;
    wire [7:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_ab;
    wire [15:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_iq;
    wire [15:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_q;
    wire [7:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_i = 8'b11111111;
    wire [8:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_a;
    wire [8:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_b;
    logic [8:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_o;
    wire [8:0] redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_q;
    reg [15:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_inputreg0_q;
    reg [15:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_outputreg0_q;
    wire redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_reset0;
    wire [15:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_ia;
    wire [7:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_aa;
    wire [7:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_ab;
    wire [15:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_iq;
    wire [15:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_q;
    wire [7:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_i = 8'b11111111;
    wire [7:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_offset_q;
    wire [8:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_a;
    wire [8:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_b;
    logic [8:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_o;
    wire [8:0] redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_q;
    reg [15:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_inputreg0_q;
    reg [15:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_outputreg0_q;
    wire redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_reset0;
    wire [15:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_ia;
    wire [7:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_aa;
    wire [7:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_ab;
    wire [15:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_iq;
    wire [15:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_q;
    wire [7:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_i = 8'b11111111;
    wire [8:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_a;
    wire [8:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_b;
    logic [8:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_o;
    wire [8:0] redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_q;
    reg [15:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_inputreg0_q;
    reg [15:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_outputreg0_q;
    wire redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_reset0;
    wire [15:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_ia;
    wire [7:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_aa;
    wire [7:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_ab;
    wire [15:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_iq;
    wire [15:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_q;
    wire [7:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_i = 8'b11111111;
    wire [7:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_offset_q;
    wire [8:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_a;
    wire [8:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_b;
    logic [8:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_o;
    wire [8:0] redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_q;
    reg [15:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_inputreg0_q;
    reg [15:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_outputreg0_q;
    wire redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_reset0;
    wire [15:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_ia;
    wire [7:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_aa;
    wire [7:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_ab;
    wire [15:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_iq;
    wire [15:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_q;
    wire [7:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_i = 8'b11111111;
    wire [8:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_a;
    wire [8:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_b;
    logic [8:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_o;
    wire [8:0] redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_q;
    reg [15:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_inputreg0_q;
    reg [15:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_outputreg0_q;
    wire redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_reset0;
    wire [15:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_ia;
    wire [7:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_aa;
    wire [7:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_ab;
    wire [15:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_iq;
    wire [15:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_q;
    wire [7:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_i = 8'b11111111;
    wire [7:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_offset_q;
    wire [8:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_a;
    wire [8:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_b;
    logic [8:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_o;
    wire [8:0] redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_q;
    reg [15:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_inputreg0_q;
    reg [15:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_outputreg0_q;
    wire redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_reset0;
    wire [15:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_ia;
    wire [7:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_aa;
    wire [7:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_ab;
    wire [15:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_iq;
    wire [15:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_q;
    wire [7:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_i = 8'b11111111;
    wire [8:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_a;
    wire [8:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_b;
    logic [8:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_o;
    wire [8:0] redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_q;
    reg [15:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_inputreg0_q;
    reg [15:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_outputreg0_q;
    wire redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_reset0;
    wire [15:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_ia;
    wire [7:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_aa;
    wire [7:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_ab;
    wire [15:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_iq;
    wire [15:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_q;
    wire [7:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_i = 8'b11111111;
    wire [7:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_offset_q;
    wire [8:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_a;
    wire [8:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_b;
    logic [8:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_o;
    wire [8:0] redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_q;
    reg [15:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_inputreg0_q;
    reg [15:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_outputreg0_q;
    wire redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_reset0;
    wire [15:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_ia;
    wire [7:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_aa;
    wire [7:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_ab;
    wire [15:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_iq;
    wire [15:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_q;
    wire [7:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_i = 8'b11111111;
    wire [8:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_a;
    wire [8:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_b;
    logic [8:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_o;
    wire [8:0] redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_q;
    reg [15:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_inputreg0_q;
    reg [15:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_outputreg0_q;
    wire redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_reset0;
    wire [15:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_ia;
    wire [7:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_aa;
    wire [7:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_ab;
    wire [15:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_iq;
    wire [15:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_q;
    wire [7:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_i = 8'b11111111;
    wire [7:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_offset_q;
    wire [8:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_a;
    wire [8:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_b;
    logic [8:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_o;
    wire [8:0] redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_q;
    reg [15:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_inputreg0_q;
    reg [15:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_outputreg0_q;
    wire redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_reset0;
    wire [15:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_ia;
    wire [7:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_aa;
    wire [7:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_ab;
    wire [15:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_iq;
    wire [15:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_q;
    wire [7:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_i = 8'b11111111;
    wire [8:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_a;
    wire [8:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_b;
    logic [8:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_o;
    wire [8:0] redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_q;
    reg [15:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_inputreg0_q;
    reg [15:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_outputreg0_q;
    wire redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_reset0;
    wire [15:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_ia;
    wire [7:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_aa;
    wire [7:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_ab;
    wire [15:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_iq;
    wire [15:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_q;
    wire [7:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_i = 8'b11111111;
    wire [7:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_offset_q;
    wire [8:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_a;
    wire [8:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_b;
    logic [8:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_o;
    wire [8:0] redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_q;
    reg [15:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_inputreg0_q;
    reg [15:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_outputreg0_q;
    wire redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_reset0;
    wire [15:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_ia;
    wire [7:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_aa;
    wire [7:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_ab;
    wire [15:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_iq;
    wire [15:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_q;
    wire [7:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_i = 8'b11111111;
    wire [8:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_a;
    wire [8:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_b;
    logic [8:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_o;
    wire [8:0] redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_q;
    reg [15:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_inputreg0_q;
    reg [15:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_outputreg0_q;
    wire redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_reset0;
    wire [15:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_ia;
    wire [7:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_aa;
    wire [7:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_ab;
    wire [15:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_iq;
    wire [15:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_q;
    wire [7:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_i = 8'b11111111;
    wire [7:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_offset_q;
    wire [8:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_a;
    wire [8:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_b;
    logic [8:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_o;
    wire [8:0] redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_q;
    reg [15:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_inputreg0_q;
    reg [15:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_outputreg0_q;
    wire redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_reset0;
    wire [15:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_ia;
    wire [7:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_aa;
    wire [7:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_ab;
    wire [15:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_iq;
    wire [15:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_q;
    wire [7:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_i = 8'b11111111;
    wire [8:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_a;
    wire [8:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_b;
    logic [8:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_o;
    wire [8:0] redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_q;
    reg [15:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_inputreg0_q;
    reg [15:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_outputreg0_q;
    wire redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_reset0;
    wire [15:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_ia;
    wire [7:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_aa;
    wire [7:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_ab;
    wire [15:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_iq;
    wire [15:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_q;
    wire [7:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_i = 8'b11111111;
    wire [7:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_offset_q;
    wire [8:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_a;
    wire [8:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_b;
    logic [8:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_o;
    wire [8:0] redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_q;
    reg [15:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_inputreg0_q;
    reg [15:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_outputreg0_q;
    wire redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_reset0;
    wire [15:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_ia;
    wire [7:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_aa;
    wire [7:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_ab;
    wire [15:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_iq;
    wire [15:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_q;
    wire [7:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_i = 8'b11111111;
    wire [8:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_a;
    wire [8:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_b;
    logic [8:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_o;
    wire [8:0] redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_q;
    reg [15:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_inputreg0_q;
    reg [15:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_outputreg0_q;
    wire redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_reset0;
    wire [15:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_ia;
    wire [7:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_aa;
    wire [7:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_ab;
    wire [15:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_iq;
    wire [15:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_q;
    wire [7:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_i = 8'b11111111;
    wire [7:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_offset_q;
    wire [8:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_a;
    wire [8:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_b;
    logic [8:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_o;
    wire [8:0] redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_q;
    reg [15:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_inputreg0_q;
    reg [15:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_outputreg0_q;
    wire redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_reset0;
    wire [15:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_ia;
    wire [7:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_aa;
    wire [7:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_ab;
    wire [15:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_iq;
    wire [15:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_q;
    wire [7:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_i = 8'b11111111;
    wire [8:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_a;
    wire [8:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_b;
    logic [8:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_o;
    wire [8:0] redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_q;
    reg [15:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_inputreg0_q;
    reg [15:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_outputreg0_q;
    wire redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_reset0;
    wire [15:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_ia;
    wire [7:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_aa;
    wire [7:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_ab;
    wire [15:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_iq;
    wire [15:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_q;
    wire [7:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_i = 8'b11111111;
    wire [7:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_offset_q;
    wire [8:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_a;
    wire [8:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_b;
    logic [8:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_o;
    wire [8:0] redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_q;
    reg [15:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_inputreg0_q;
    reg [15:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_outputreg0_q;
    wire redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_reset0;
    wire [15:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_ia;
    wire [7:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_aa;
    wire [7:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_ab;
    wire [15:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_iq;
    wire [15:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_q;
    wire [7:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_i = 8'b11111111;
    wire [8:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_a;
    wire [8:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_b;
    logic [8:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_o;
    wire [8:0] redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_q;
    reg [15:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_inputreg0_q;
    reg [15:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_outputreg0_q;
    wire redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_reset0;
    wire [15:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_ia;
    wire [7:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_aa;
    wire [7:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_ab;
    wire [15:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_iq;
    wire [15:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_q;
    wire [7:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_i = 8'b11111111;
    wire [7:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_offset_q;
    wire [8:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_a;
    wire [8:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_b;
    logic [8:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_o;
    wire [8:0] redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_q;
    reg [15:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_inputreg0_q;
    reg [15:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_outputreg0_q;
    wire redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_reset0;
    wire [15:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_ia;
    wire [7:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_aa;
    wire [7:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_ab;
    wire [15:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_iq;
    wire [15:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_q;
    wire [7:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_i = 8'b11111111;
    wire [8:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_a;
    wire [8:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_b;
    logic [8:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_o;
    wire [8:0] redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_q;
    reg [15:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_inputreg0_q;
    reg [15:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_outputreg0_q;
    wire redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_reset0;
    wire [15:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_ia;
    wire [7:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_aa;
    wire [7:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_ab;
    wire [15:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_iq;
    wire [15:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_q;
    wire [7:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_i = 8'b11111111;
    wire [7:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_offset_q;
    wire [8:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_a;
    wire [8:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_b;
    logic [8:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_o;
    wire [8:0] redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_q;
    reg [15:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_inputreg0_q;
    reg [15:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_outputreg0_q;
    wire redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_reset0;
    wire [15:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_ia;
    wire [7:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_aa;
    wire [7:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_ab;
    wire [15:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_iq;
    wire [15:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_q;
    wire [7:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_i = 8'b11111111;
    wire [8:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_a;
    wire [8:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_b;
    logic [8:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_o;
    wire [8:0] redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_q;
    reg [15:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_inputreg0_q;
    reg [15:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_outputreg0_q;
    wire redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_reset0;
    wire [15:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_ia;
    wire [7:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_aa;
    wire [7:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_ab;
    wire [15:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_iq;
    wire [15:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_q;
    wire [7:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_i = 8'b11111111;
    wire [7:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_offset_q;
    wire [8:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_a;
    wire [8:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_b;
    logic [8:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_o;
    wire [8:0] redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_q;
    reg [15:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_inputreg0_q;
    reg [15:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_outputreg0_q;
    wire redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_reset0;
    wire [15:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_ia;
    wire [7:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_aa;
    wire [7:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_ab;
    wire [15:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_iq;
    wire [15:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_q;
    wire [7:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_i = 8'b11111111;
    wire [8:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_a;
    wire [8:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_b;
    logic [8:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_o;
    wire [8:0] redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_q;
    reg [15:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_inputreg0_q;
    reg [15:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_outputreg0_q;
    wire redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_reset0;
    wire [15:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_ia;
    wire [7:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_aa;
    wire [7:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_ab;
    wire [15:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_iq;
    wire [15:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_q;
    wire [7:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_i = 8'b11111111;
    wire [7:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_offset_q;
    wire [8:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_a;
    wire [8:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_b;
    logic [8:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_o;
    wire [8:0] redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_q;
    reg [15:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_inputreg0_q;
    reg [15:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_outputreg0_q;
    wire redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_reset0;
    wire [15:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_ia;
    wire [7:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_aa;
    wire [7:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_ab;
    wire [15:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_iq;
    wire [15:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_q;
    wire [7:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_i = 8'b11111111;
    wire [8:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_a;
    wire [8:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_b;
    logic [8:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_o;
    wire [8:0] redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_q;
    reg [15:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_inputreg0_q;
    reg [15:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_outputreg0_q;
    wire redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_reset0;
    wire [15:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_ia;
    wire [7:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_aa;
    wire [7:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_ab;
    wire [15:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_iq;
    wire [15:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_q;
    wire [7:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_i = 8'b11111111;
    wire [7:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_offset_q;
    wire [8:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_a;
    wire [8:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_b;
    logic [8:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_o;
    wire [8:0] redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_q;
    reg [15:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_inputreg0_q;
    reg [15:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_outputreg0_q;
    wire redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_reset0;
    wire [15:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_ia;
    wire [7:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_aa;
    wire [7:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_ab;
    wire [15:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_iq;
    wire [15:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_q;
    wire [7:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_i = 8'b11111111;
    wire [8:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_a;
    wire [8:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_b;
    logic [8:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_o;
    wire [8:0] redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_q;
    reg [15:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_inputreg0_q;
    reg [15:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_outputreg0_q;
    wire redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_reset0;
    wire [15:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_ia;
    wire [7:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_aa;
    wire [7:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_ab;
    wire [15:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_iq;
    wire [15:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_q;
    wire [7:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_i = 8'b11111111;
    wire [7:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_offset_q;
    wire [8:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_a;
    wire [8:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_b;
    logic [8:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_o;
    wire [8:0] redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_q;
    reg [15:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_inputreg0_q;
    reg [15:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_outputreg0_q;
    wire redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_reset0;
    wire [15:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_ia;
    wire [7:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_aa;
    wire [7:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_ab;
    wire [15:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_iq;
    wire [15:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_q;
    wire [7:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_i = 8'b11111111;
    wire [8:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_a;
    wire [8:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_b;
    logic [8:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_o;
    wire [8:0] redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_q;
    reg [15:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_inputreg0_q;
    reg [15:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_outputreg0_q;
    wire redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_reset0;
    wire [15:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_ia;
    wire [7:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_aa;
    wire [7:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_ab;
    wire [15:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_iq;
    wire [15:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_q;
    wire [7:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_i = 8'b11111111;
    wire [7:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_offset_q;
    wire [8:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_a;
    wire [8:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_b;
    logic [8:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_o;
    wire [8:0] redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_q;
    reg [15:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_inputreg0_q;
    reg [15:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_outputreg0_q;
    wire redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_reset0;
    wire [15:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_ia;
    wire [7:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_aa;
    wire [7:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_ab;
    wire [15:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_iq;
    wire [15:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_q;
    wire [7:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_i = 8'b11111111;
    wire [8:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_a;
    wire [8:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_b;
    logic [8:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_o;
    wire [8:0] redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_q;
    reg [15:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_inputreg0_q;
    reg [15:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_outputreg0_q;
    wire redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_reset0;
    wire [15:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_ia;
    wire [7:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_aa;
    wire [7:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_ab;
    wire [15:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_iq;
    wire [15:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_q;
    wire [7:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_i = 8'b11111111;
    wire [7:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_offset_q;
    wire [8:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_a;
    wire [8:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_b;
    logic [8:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_o;
    wire [8:0] redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_q;
    reg [15:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_inputreg0_q;
    reg [15:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_outputreg0_q;
    wire redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_reset0;
    wire [15:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_ia;
    wire [7:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_aa;
    wire [7:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_ab;
    wire [15:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_iq;
    wire [15:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_q;
    wire [7:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_i = 8'b11111111;
    wire [8:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_a;
    wire [8:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_b;
    logic [8:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_o;
    wire [8:0] redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_q;
    reg [15:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_inputreg0_q;
    reg [15:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_outputreg0_q;
    wire redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_reset0;
    wire [15:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_ia;
    wire [7:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_aa;
    wire [7:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_ab;
    wire [15:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_iq;
    wire [15:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_q;
    wire [7:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_i = 8'b11111111;
    wire [7:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_offset_q;
    wire [8:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_a;
    wire [8:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_b;
    logic [8:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_o;
    wire [8:0] redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_q;
    reg [15:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_inputreg0_q;
    reg [15:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_outputreg0_q;
    wire redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_reset0;
    wire [15:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_ia;
    wire [7:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_aa;
    wire [7:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_ab;
    wire [15:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_iq;
    wire [15:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_q;
    wire [7:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_i = 8'b11111111;
    wire [8:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_a;
    wire [8:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_b;
    logic [8:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_o;
    wire [8:0] redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_q;
    reg [15:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_inputreg0_q;
    reg [15:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_outputreg0_q;
    wire redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_reset0;
    wire [15:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_ia;
    wire [7:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_aa;
    wire [7:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_ab;
    wire [15:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_iq;
    wire [15:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_q;
    wire [7:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_i = 8'b11111111;
    wire [7:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_offset_q;
    wire [8:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_a;
    wire [8:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_b;
    logic [8:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_o;
    wire [8:0] redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_q;
    reg [15:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_inputreg0_q;
    reg [15:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_outputreg0_q;
    wire redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_reset0;
    wire [15:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_ia;
    wire [7:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_aa;
    wire [7:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_ab;
    wire [15:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_iq;
    wire [15:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_q;
    wire [7:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_i = 8'b11111111;
    wire [8:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_a;
    wire [8:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_b;
    logic [8:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_o;
    wire [8:0] redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_q;
    reg [15:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_inputreg0_q;
    reg [15:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_outputreg0_q;
    wire redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_reset0;
    wire [15:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_ia;
    wire [7:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_aa;
    wire [7:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_ab;
    wire [15:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_iq;
    wire [15:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_q;
    wire [7:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_i = 8'b11111111;
    wire [7:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_offset_q;
    wire [8:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_a;
    wire [8:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_b;
    logic [8:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_o;
    wire [8:0] redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_q;
    reg [15:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_inputreg0_q;
    reg [15:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_outputreg0_q;
    wire redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_reset0;
    wire [15:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_ia;
    wire [7:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_aa;
    wire [7:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_ab;
    wire [15:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_iq;
    wire [15:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_q;
    wire [7:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_i = 8'b11111111;
    wire [8:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_a;
    wire [8:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_b;
    logic [8:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_o;
    wire [8:0] redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_q;
    reg [15:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_inputreg0_q;
    reg [15:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_outputreg0_q;
    wire redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_reset0;
    wire [15:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_ia;
    wire [7:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_aa;
    wire [7:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_ab;
    wire [15:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_iq;
    wire [15:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_q;
    wire [7:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_i = 8'b11111111;
    wire [7:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_offset_q;
    wire [8:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_a;
    wire [8:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_b;
    logic [8:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_o;
    wire [8:0] redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_q;
    reg [15:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_inputreg0_q;
    reg [15:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_outputreg0_q;
    wire redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_reset0;
    wire [15:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_ia;
    wire [7:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_aa;
    wire [7:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_ab;
    wire [15:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_iq;
    wire [15:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_q;
    wire [7:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_i = 8'b11111111;
    wire [8:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_a;
    wire [8:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_b;
    logic [8:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_o;
    wire [8:0] redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_q;
    reg [15:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_inputreg0_q;
    reg [15:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_outputreg0_q;
    wire redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_reset0;
    wire [15:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_ia;
    wire [7:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_aa;
    wire [7:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_ab;
    wire [15:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_iq;
    wire [15:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_q;
    wire [7:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_i = 8'b11111111;
    wire [7:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_offset_q;
    wire [8:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_a;
    wire [8:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_b;
    logic [8:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_o;
    wire [8:0] redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_q;
    reg [15:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_inputreg0_q;
    reg [15:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_outputreg0_q;
    wire redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_reset0;
    wire [15:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_ia;
    wire [7:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_aa;
    wire [7:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_ab;
    wire [15:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_iq;
    wire [15:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_q;
    wire [7:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_i = 8'b11111111;
    wire [8:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_a;
    wire [8:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_b;
    logic [8:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_o;
    wire [8:0] redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_q;
    reg [15:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_inputreg0_q;
    reg [15:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_outputreg0_q;
    wire redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_reset0;
    wire [15:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_ia;
    wire [7:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_aa;
    wire [7:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_ab;
    wire [15:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_iq;
    wire [15:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_q;
    wire [7:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_i = 8'b11111111;
    wire [7:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_offset_q;
    wire [8:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_a;
    wire [8:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_b;
    logic [8:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_o;
    wire [8:0] redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_q;
    reg [15:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_inputreg0_q;
    reg [15:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_outputreg0_q;
    wire redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_reset0;
    wire [15:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_ia;
    wire [7:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_aa;
    wire [7:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_ab;
    wire [15:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_iq;
    wire [15:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_q;
    wire [7:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_i = 8'b11111111;
    wire [8:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_a;
    wire [8:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_b;
    logic [8:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_o;
    wire [8:0] redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_q;
    reg [15:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_inputreg0_q;
    reg [15:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_outputreg0_q;
    wire redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_reset0;
    wire [15:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_ia;
    wire [7:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_aa;
    wire [7:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_ab;
    wire [15:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_iq;
    wire [15:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_q;
    wire [7:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_i = 8'b11111111;
    wire [7:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_offset_q;
    wire [8:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_a;
    wire [8:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_b;
    logic [8:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_o;
    wire [8:0] redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_q;
    reg [15:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_inputreg0_q;
    reg [15:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_outputreg0_q;
    wire redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_reset0;
    wire [15:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_ia;
    wire [7:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_aa;
    wire [7:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_ab;
    wire [15:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_iq;
    wire [15:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_q;
    wire [7:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_i = 8'b11111111;
    wire [8:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_a;
    wire [8:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_b;
    logic [8:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_o;
    wire [8:0] redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_q;
    reg [15:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_inputreg0_q;
    reg [15:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_outputreg0_q;
    wire redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_reset0;
    wire [15:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_ia;
    wire [7:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_aa;
    wire [7:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_ab;
    wire [15:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_iq;
    wire [15:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_q;
    wire [7:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_i = 8'b11111111;
    wire [7:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_offset_q;
    wire [8:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_a;
    wire [8:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_b;
    logic [8:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_o;
    wire [8:0] redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_q;
    reg [15:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_inputreg0_q;
    reg [15:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_outputreg0_q;
    wire redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_reset0;
    wire [15:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_ia;
    wire [7:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_aa;
    wire [7:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_ab;
    wire [15:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_iq;
    wire [15:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_q;
    wire [7:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_i = 8'b11111111;
    wire [8:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_a;
    wire [8:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_b;
    logic [8:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_o;
    wire [8:0] redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_q;
    reg [15:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_inputreg0_q;
    reg [15:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_outputreg0_q;
    wire redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_reset0;
    wire [15:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_ia;
    wire [7:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_aa;
    wire [7:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_ab;
    wire [15:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_iq;
    wire [15:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_q;
    wire [7:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_i = 8'b11111111;
    wire [7:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_offset_q;
    wire [8:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_a;
    wire [8:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_b;
    logic [8:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_o;
    wire [8:0] redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_q;
    reg [15:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_inputreg0_q;
    reg [15:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_outputreg0_q;
    wire redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_reset0;
    wire [15:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_ia;
    wire [7:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_aa;
    wire [7:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_ab;
    wire [15:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_iq;
    wire [15:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_q;
    wire [7:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_i = 8'b11111111;
    wire [8:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_a;
    wire [8:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_b;
    logic [8:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_o;
    wire [8:0] redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_q;
    reg [15:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_inputreg0_q;
    reg [15:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_outputreg0_q;
    wire redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_reset0;
    wire [15:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_ia;
    wire [7:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_aa;
    wire [7:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_ab;
    wire [15:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_iq;
    wire [15:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_q;
    wire [7:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_i = 8'b11111111;
    wire [7:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_offset_q;
    wire [8:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_a;
    wire [8:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_b;
    logic [8:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_o;
    wire [8:0] redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_q;
    reg [15:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_inputreg0_q;
    reg [15:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_outputreg0_q;
    wire redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_reset0;
    wire [15:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_ia;
    wire [7:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_aa;
    wire [7:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_ab;
    wire [15:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_iq;
    wire [15:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_q;
    wire [7:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_i = 8'b11111111;
    wire [8:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_a;
    wire [8:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_b;
    logic [8:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_o;
    wire [8:0] redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_q;
    reg [15:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_inputreg0_q;
    reg [15:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_outputreg0_q;
    wire redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_reset0;
    wire [15:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_ia;
    wire [7:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_aa;
    wire [7:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_ab;
    wire [15:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_iq;
    wire [15:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_q;
    wire [7:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_i = 8'b11111111;
    wire [7:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_offset_q;
    wire [8:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_a;
    wire [8:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_b;
    logic [8:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_o;
    wire [8:0] redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_q;
    reg [15:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_inputreg0_q;
    reg [15:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_outputreg0_q;
    wire redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_reset0;
    wire [15:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_ia;
    wire [7:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_aa;
    wire [7:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_ab;
    wire [15:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_iq;
    wire [15:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_q;
    wire [7:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_i = 8'b11111111;
    wire [8:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_a;
    wire [8:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_b;
    logic [8:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_o;
    wire [8:0] redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_q;
    reg [15:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_inputreg0_q;
    reg [15:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_outputreg0_q;
    wire redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_reset0;
    wire [15:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_ia;
    wire [7:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_aa;
    wire [7:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_ab;
    wire [15:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_iq;
    wire [15:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_q;
    wire [7:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_i = 8'b11111111;
    wire [7:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_offset_q;
    wire [8:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_a;
    wire [8:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_b;
    logic [8:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_o;
    wire [8:0] redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_q;
    reg [15:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_inputreg0_q;
    reg [15:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_outputreg0_q;
    wire redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_reset0;
    wire [15:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_ia;
    wire [7:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_aa;
    wire [7:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_ab;
    wire [15:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_iq;
    wire [15:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_q;
    wire [7:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_i = 8'b11111111;
    wire [8:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_a;
    wire [8:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_b;
    logic [8:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_o;
    wire [8:0] redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_q;
    reg [15:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_inputreg0_q;
    reg [15:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_outputreg0_q;
    wire redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_reset0;
    wire [15:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_ia;
    wire [7:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_aa;
    wire [7:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_ab;
    wire [15:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_iq;
    wire [15:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_q;
    wire [7:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_i = 8'b11111111;
    wire [7:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_offset_q;
    wire [8:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_a;
    wire [8:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_b;
    logic [8:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_o;
    wire [8:0] redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_q;
    reg [15:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_inputreg0_q;
    reg [15:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_outputreg0_q;
    wire redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_reset0;
    wire [15:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_ia;
    wire [7:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_aa;
    wire [7:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_ab;
    wire [15:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_iq;
    wire [15:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_q;
    wire [7:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_i = 8'b11111111;
    wire [8:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_a;
    wire [8:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_b;
    logic [8:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_o;
    wire [8:0] redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_q;
    reg [15:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_inputreg0_q;
    reg [15:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_outputreg0_q;
    wire redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_reset0;
    wire [15:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_ia;
    wire [7:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_aa;
    wire [7:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_ab;
    wire [15:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_iq;
    wire [15:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_q;
    wire [7:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_i = 8'b11111111;
    wire [7:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_offset_q;
    wire [8:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_a;
    wire [8:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_b;
    logic [8:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_o;
    wire [8:0] redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_q;
    reg [15:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_inputreg0_q;
    reg [15:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_outputreg0_q;
    wire redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_reset0;
    wire [15:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_ia;
    wire [7:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_aa;
    wire [7:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_ab;
    wire [15:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_iq;
    wire [15:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_q;
    wire [7:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_i = 8'b11111111;
    wire [8:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_a;
    wire [8:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_b;
    logic [8:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_o;
    wire [8:0] redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_q;
    reg [15:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_inputreg0_q;
    reg [15:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_outputreg0_q;
    wire redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_reset0;
    wire [15:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_ia;
    wire [7:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_aa;
    wire [7:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_ab;
    wire [15:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_iq;
    wire [15:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_q;
    wire [7:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_i = 8'b11111111;
    wire [7:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_offset_q;
    wire [8:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_a;
    wire [8:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_b;
    logic [8:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_o;
    wire [8:0] redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_q;
    reg [15:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_inputreg0_q;
    reg [15:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_outputreg0_q;
    wire redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_reset0;
    wire [15:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_ia;
    wire [7:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_aa;
    wire [7:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_ab;
    wire [15:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_iq;
    wire [15:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_q;
    wire [7:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_i = 8'b11111111;
    wire [8:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_a;
    wire [8:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_b;
    logic [8:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_o;
    wire [8:0] redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_q;
    reg [15:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_inputreg0_q;
    reg [15:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_outputreg0_q;
    wire redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_reset0;
    wire [15:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_ia;
    wire [7:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_aa;
    wire [7:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_ab;
    wire [15:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_iq;
    wire [15:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_q;
    wire [7:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_i = 8'b11111111;
    wire [7:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_offset_q;
    wire [8:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_a;
    wire [8:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_b;
    logic [8:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_o;
    wire [8:0] redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_q;
    reg [15:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_inputreg0_q;
    reg [15:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_outputreg0_q;
    wire redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_reset0;
    wire [15:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_ia;
    wire [7:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_aa;
    wire [7:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_ab;
    wire [15:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_iq;
    wire [15:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_q;
    wire [7:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_i = 8'b11111111;
    wire [8:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_a;
    wire [8:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_b;
    logic [8:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_o;
    wire [8:0] redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_q;
    reg [15:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_inputreg0_q;
    reg [15:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_outputreg0_q;
    wire redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_reset0;
    wire [15:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_ia;
    wire [7:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_aa;
    wire [7:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_ab;
    wire [15:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_iq;
    wire [15:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_q;
    wire [7:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_i = 8'b11111111;
    wire [7:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_offset_q;
    wire [8:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_a;
    wire [8:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_b;
    logic [8:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_o;
    wire [8:0] redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_q;
    reg [15:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_inputreg0_q;
    reg [15:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_outputreg0_q;
    wire redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_reset0;
    wire [15:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_ia;
    wire [7:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_aa;
    wire [7:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_ab;
    wire [15:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_iq;
    wire [15:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_q;
    wire [7:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_i = 8'b11111111;
    wire [8:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_a;
    wire [8:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_b;
    logic [8:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_o;
    wire [8:0] redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_q;
    reg [15:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_inputreg0_q;
    reg [15:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_outputreg0_q;
    wire redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_reset0;
    wire [15:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_ia;
    wire [7:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_aa;
    wire [7:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_ab;
    wire [15:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_iq;
    wire [15:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_q;
    wire [7:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_i = 8'b11111111;
    wire [7:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_offset_q;
    wire [8:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_a;
    wire [8:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_b;
    logic [8:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_o;
    wire [8:0] redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_q;
    reg [15:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_inputreg0_q;
    reg [15:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_outputreg0_q;
    wire redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_reset0;
    wire [15:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_ia;
    wire [7:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_aa;
    wire [7:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_ab;
    wire [15:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_iq;
    wire [15:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_q;
    wire [7:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_i = 8'b11111111;
    wire [8:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_a;
    wire [8:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_b;
    logic [8:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_o;
    wire [8:0] redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_q;
    reg [15:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_inputreg0_q;
    reg [15:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_outputreg0_q;
    wire redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_reset0;
    wire [15:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_ia;
    wire [7:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_aa;
    wire [7:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_ab;
    wire [15:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_iq;
    wire [15:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_q;
    wire [7:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_i = 8'b11111111;
    wire [7:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_offset_q;
    wire [8:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_a;
    wire [8:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_b;
    logic [8:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_o;
    wire [8:0] redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_q;
    reg [15:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_inputreg0_q;
    reg [15:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_outputreg0_q;
    wire redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_reset0;
    wire [15:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_ia;
    wire [7:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_aa;
    wire [7:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_ab;
    wire [15:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_iq;
    wire [15:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_q;
    wire [7:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_i = 8'b11111111;
    wire [8:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_a;
    wire [8:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_b;
    logic [8:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_o;
    wire [8:0] redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_q;
    reg [15:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_inputreg0_q;
    reg [15:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_outputreg0_q;
    wire redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_reset0;
    wire [15:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_ia;
    wire [7:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_aa;
    wire [7:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_ab;
    wire [15:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_iq;
    wire [15:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_q;
    wire [7:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_i = 8'b11111111;
    wire [7:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_offset_q;
    wire [8:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_a;
    wire [8:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_b;
    logic [8:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_o;
    wire [8:0] redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_q;
    reg [15:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_inputreg0_q;
    reg [15:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_outputreg0_q;
    wire redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_reset0;
    wire [15:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_ia;
    wire [7:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_aa;
    wire [7:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_ab;
    wire [15:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_iq;
    wire [15:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_q;
    wire [7:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_i = 8'b11111111;
    wire [8:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_a;
    wire [8:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_b;
    logic [8:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_o;
    wire [8:0] redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_q;
    reg [15:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_inputreg0_q;
    reg [15:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_outputreg0_q;
    wire redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_reset0;
    wire [15:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_ia;
    wire [7:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_aa;
    wire [7:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_ab;
    wire [15:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_iq;
    wire [15:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_q;
    wire [7:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_i = 8'b11111111;
    wire [7:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_offset_q;
    wire [8:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_a;
    wire [8:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_b;
    logic [8:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_o;
    wire [8:0] redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_q;
    reg [15:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_inputreg0_q;
    reg [15:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_outputreg0_q;
    wire redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_reset0;
    wire [15:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_ia;
    wire [7:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_aa;
    wire [7:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_ab;
    wire [15:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_iq;
    wire [15:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_q;
    wire [7:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_i = 8'b11111111;
    wire [8:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_a;
    wire [8:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_b;
    logic [8:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_o;
    wire [8:0] redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_q;
    reg [15:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_inputreg0_q;
    reg [15:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_outputreg0_q;
    wire redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_reset0;
    wire [15:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_ia;
    wire [7:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_aa;
    wire [7:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_ab;
    wire [15:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_iq;
    wire [15:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_q;
    wire [7:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_i = 8'b11111111;
    wire [7:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_offset_q;
    wire [8:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_a;
    wire [8:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_b;
    logic [8:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_o;
    wire [8:0] redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_q;
    reg [15:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_inputreg0_q;
    reg [15:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_outputreg0_q;
    wire redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_reset0;
    wire [15:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_ia;
    wire [7:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_aa;
    wire [7:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_ab;
    wire [15:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_iq;
    wire [15:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_q;
    wire [7:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_i = 8'b11111111;
    wire [8:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_a;
    wire [8:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_b;
    logic [8:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_o;
    wire [8:0] redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_q;
    reg [15:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_inputreg0_q;
    reg [15:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_outputreg0_q;
    wire redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_reset0;
    wire [15:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_ia;
    wire [7:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_aa;
    wire [7:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_ab;
    wire [15:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_iq;
    wire [15:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_q;
    wire [7:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_i = 8'b11111111;
    wire [7:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_offset_q;
    wire [8:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_a;
    wire [8:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_b;
    logic [8:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_o;
    wire [8:0] redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_q;
    reg [15:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_inputreg0_q;
    reg [15:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_outputreg0_q;
    wire redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_reset0;
    wire [15:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_ia;
    wire [7:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_aa;
    wire [7:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_ab;
    wire [15:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_iq;
    wire [15:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_q;
    wire [7:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_i = 8'b11111111;
    wire [8:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_a;
    wire [8:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_b;
    logic [8:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_o;
    wire [8:0] redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_q;
    reg [15:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_inputreg0_q;
    reg [15:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_outputreg0_q;
    wire redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_reset0;
    wire [15:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_ia;
    wire [7:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_aa;
    wire [7:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_ab;
    wire [15:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_iq;
    wire [15:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_q;
    wire [7:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_i = 8'b11111111;
    wire [7:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_offset_q;
    wire [8:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_a;
    wire [8:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_b;
    logic [8:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_o;
    wire [8:0] redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_q;
    reg [15:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_inputreg0_q;
    reg [15:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_outputreg0_q;
    wire redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_reset0;
    wire [15:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_ia;
    wire [7:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_aa;
    wire [7:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_ab;
    wire [15:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_iq;
    wire [15:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_q;
    wire [7:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_i = 8'b11111111;
    wire [8:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_a;
    wire [8:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_b;
    logic [8:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_o;
    wire [8:0] redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_q;
    reg [15:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_inputreg0_q;
    reg [15:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_outputreg0_q;
    wire redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_reset0;
    wire [15:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_ia;
    wire [7:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_aa;
    wire [7:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_ab;
    wire [15:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_iq;
    wire [15:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_q;
    wire [7:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_i = 8'b11111111;
    wire [7:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_offset_q;
    wire [8:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_a;
    wire [8:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_b;
    logic [8:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_o;
    wire [8:0] redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_q;
    reg [15:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_inputreg0_q;
    reg [15:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_outputreg0_q;
    wire redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_reset0;
    wire [15:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_ia;
    wire [7:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_aa;
    wire [7:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_ab;
    wire [15:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_iq;
    wire [15:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_q;
    wire [7:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_i = 8'b11111111;
    wire [8:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_a;
    wire [8:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_b;
    logic [8:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_o;
    wire [8:0] redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_q;
    reg [15:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_inputreg0_q;
    reg [15:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_outputreg0_q;
    wire redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_reset0;
    wire [15:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_ia;
    wire [7:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_aa;
    wire [7:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_ab;
    wire [15:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_iq;
    wire [15:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_q;
    wire [7:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_i = 8'b11111111;
    wire [7:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_offset_q;
    wire [8:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_a;
    wire [8:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_b;
    logic [8:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_o;
    wire [8:0] redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_q;
    reg [15:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_inputreg0_q;
    reg [15:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_outputreg0_q;
    wire redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_reset0;
    wire [15:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_ia;
    wire [7:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_aa;
    wire [7:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_ab;
    wire [15:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_iq;
    wire [15:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_q;
    wire [7:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_i = 8'b11111111;
    wire [8:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_a;
    wire [8:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_b;
    logic [8:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_o;
    wire [8:0] redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_q;
    reg [15:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_inputreg0_q;
    reg [15:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_outputreg0_q;
    wire redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_reset0;
    wire [15:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_ia;
    wire [7:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_aa;
    wire [7:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_ab;
    wire [15:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_iq;
    wire [15:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_q;
    wire [7:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_i = 8'b11111111;
    wire [7:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_offset_q;
    wire [8:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_a;
    wire [8:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_b;
    logic [8:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_o;
    wire [8:0] redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_q;
    reg [15:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_inputreg0_q;
    reg [15:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_outputreg0_q;
    wire redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_reset0;
    wire [15:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_ia;
    wire [7:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_aa;
    wire [7:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_ab;
    wire [15:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_iq;
    wire [15:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_q;
    wire [7:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_i = 8'b11111111;
    wire [8:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_a;
    wire [8:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_b;
    logic [8:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_o;
    wire [8:0] redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_q;
    reg [15:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_inputreg0_q;
    reg [15:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_outputreg0_q;
    wire redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_reset0;
    wire [15:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_ia;
    wire [7:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_aa;
    wire [7:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_ab;
    wire [15:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_iq;
    wire [15:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_q;
    wire [7:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_i = 8'b11111111;
    wire [7:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_offset_q;
    wire [8:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_a;
    wire [8:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_b;
    logic [8:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_o;
    wire [8:0] redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_q;
    reg [15:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_inputreg0_q;
    reg [15:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_outputreg0_q;
    wire redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_reset0;
    wire [15:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_ia;
    wire [7:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_aa;
    wire [7:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_ab;
    wire [15:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_iq;
    wire [15:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_q;
    wire [7:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_i = 8'b11111111;
    wire [8:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_a;
    wire [8:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_b;
    logic [8:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_o;
    wire [8:0] redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_q;
    reg [15:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_inputreg0_q;
    reg [15:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_outputreg0_q;
    wire redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_reset0;
    wire [15:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_ia;
    wire [7:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_aa;
    wire [7:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_ab;
    wire [15:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_iq;
    wire [15:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_q;
    wire [7:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_i = 8'b11111111;
    wire [7:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_offset_q;
    wire [8:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_a;
    wire [8:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_b;
    logic [8:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_o;
    wire [8:0] redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_q;
    reg [15:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_inputreg0_q;
    reg [15:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_outputreg0_q;
    wire redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_reset0;
    wire [15:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_ia;
    wire [7:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_aa;
    wire [7:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_ab;
    wire [15:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_iq;
    wire [15:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_q;
    wire [7:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_i = 8'b11111111;
    wire [8:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_a;
    wire [8:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_b;
    logic [8:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_o;
    wire [8:0] redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_q;
    reg [15:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_inputreg0_q;
    reg [15:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_outputreg0_q;
    wire redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_reset0;
    wire [15:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_ia;
    wire [7:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_aa;
    wire [7:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_ab;
    wire [15:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_iq;
    wire [15:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_q;
    wire [7:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_i = 8'b11111111;
    wire [7:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_offset_q;
    wire [8:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_a;
    wire [8:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_b;
    logic [8:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_o;
    wire [8:0] redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_q;
    reg [15:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_inputreg0_q;
    reg [15:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_outputreg0_q;
    wire redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_reset0;
    wire [15:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_ia;
    wire [7:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_aa;
    wire [7:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_ab;
    wire [15:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_iq;
    wire [15:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_q;
    wire [7:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_i = 8'b11111111;
    wire [8:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_a;
    wire [8:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_b;
    logic [8:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_o;
    wire [8:0] redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_q;
    reg [15:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_inputreg0_q;
    reg [15:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_outputreg0_q;
    wire redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_reset0;
    wire [15:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_ia;
    wire [7:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_aa;
    wire [7:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_ab;
    wire [15:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_iq;
    wire [15:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_q;
    wire [7:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_i = 8'b11111111;
    wire [7:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_offset_q;
    wire [8:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_a;
    wire [8:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_b;
    logic [8:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_o;
    wire [8:0] redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_q;
    reg [15:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_inputreg0_q;
    reg [15:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_outputreg0_q;
    wire redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_reset0;
    wire [15:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_ia;
    wire [7:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_aa;
    wire [7:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_ab;
    wire [15:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_iq;
    wire [15:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_q;
    wire [7:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_i = 8'b11111111;
    wire [8:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_a;
    wire [8:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_b;
    logic [8:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_o;
    wire [8:0] redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_q;
    reg [15:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_inputreg0_q;
    reg [15:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_outputreg0_q;
    wire redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_reset0;
    wire [15:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_ia;
    wire [7:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_aa;
    wire [7:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_ab;
    wire [15:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_iq;
    wire [15:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_q;
    wire [7:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_i = 8'b11111111;
    wire [7:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_offset_q;
    wire [8:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_a;
    wire [8:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_b;
    logic [8:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_o;
    wire [8:0] redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_q;
    reg [15:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_inputreg0_q;
    reg [15:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_outputreg0_q;
    wire redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_reset0;
    wire [15:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_ia;
    wire [7:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_aa;
    wire [7:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_ab;
    wire [15:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_iq;
    wire [15:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_q;
    wire [7:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_i = 8'b11111111;
    wire [8:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_a;
    wire [8:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_b;
    logic [8:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_o;
    wire [8:0] redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_q;
    reg [15:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_inputreg0_q;
    reg [15:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_outputreg0_q;
    wire redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_reset0;
    wire [15:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_ia;
    wire [7:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_aa;
    wire [7:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_ab;
    wire [15:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_iq;
    wire [15:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_q;
    wire [7:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_i = 8'b11111111;
    wire [7:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_offset_q;
    wire [8:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_a;
    wire [8:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_b;
    logic [8:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_o;
    wire [8:0] redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_q;
    reg [15:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_inputreg0_q;
    reg [15:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_outputreg0_q;
    wire redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_reset0;
    wire [15:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_ia;
    wire [7:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_aa;
    wire [7:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_ab;
    wire [15:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_iq;
    wire [15:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_q;
    wire [7:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_i = 8'b11111111;
    wire [8:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_a;
    wire [8:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_b;
    logic [8:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_o;
    wire [8:0] redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_q;
    reg [15:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_inputreg0_q;
    reg [15:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_outputreg0_q;
    wire redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_reset0;
    wire [15:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_ia;
    wire [7:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_aa;
    wire [7:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_ab;
    wire [15:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_iq;
    wire [15:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_q;
    wire [7:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_i = 8'b11111111;
    wire [7:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_offset_q;
    wire [8:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_a;
    wire [8:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_b;
    logic [8:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_o;
    wire [8:0] redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_q;
    reg [15:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_inputreg0_q;
    reg [15:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_outputreg0_q;
    wire redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_reset0;
    wire [15:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_ia;
    wire [7:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_aa;
    wire [7:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_ab;
    wire [15:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_iq;
    wire [15:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_q;
    wire [7:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_i = 8'b11111111;
    wire [8:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_a;
    wire [8:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_b;
    logic [8:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_o;
    wire [8:0] redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_q;
    reg [15:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_inputreg0_q;
    reg [15:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_outputreg0_q;
    wire redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_reset0;
    wire [15:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_ia;
    wire [7:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_aa;
    wire [7:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_ab;
    wire [15:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_iq;
    wire [15:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_q;
    wire [7:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_i = 8'b11111111;
    wire [7:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_offset_q;
    wire [8:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_a;
    wire [8:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_b;
    logic [8:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_o;
    wire [8:0] redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_q;
    reg [15:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_inputreg0_q;
    reg [15:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_outputreg0_q;
    wire redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_reset0;
    wire [15:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_ia;
    wire [7:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_aa;
    wire [7:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_ab;
    wire [15:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_iq;
    wire [15:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_q;
    wire [7:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [7:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_i = 8'b11111111;
    wire [8:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_a;
    wire [8:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_b;
    logic [8:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_o;
    wire [8:0] redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_q;
    reg [63:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_inputreg0_q;
    reg [63:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_outputreg0_q;
    wire redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_reset0;
    wire [63:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_ia;
    wire [8:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_aa;
    wire [8:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_ab;
    wire [63:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_iq;
    wire [63:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_q;
    wire [8:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [8:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_i = 9'b111111111;
    wire [8:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_offset_q;
    wire [9:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_a;
    wire [9:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_b;
    logic [9:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_o;
    wire [9:0] redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_q;
    reg [15:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_inputreg0_q;
    reg [15:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_outputreg0_q;
    wire redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_reset0;
    wire [15:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_ia;
    wire [4:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_aa;
    wire [4:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_ab;
    wire [15:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_iq;
    wire [15:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_q;
    wire [4:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_a;
    wire [5:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_b;
    logic [5:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_o;
    wire [5:0] redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_q;
    reg [15:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_inputreg0_q;
    reg [15:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_outputreg0_q;
    wire redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_reset0;
    wire [15:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_ia;
    wire [4:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_aa;
    wire [4:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_ab;
    wire [15:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_iq;
    wire [15:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_q;
    wire [4:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_a;
    wire [5:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_b;
    logic [5:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_o;
    wire [5:0] redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_q;
    reg [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_inputreg0_q;
    reg [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_outputreg0_q;
    wire redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_reset0;
    wire [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_ia;
    wire [4:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_aa;
    wire [4:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_ab;
    wire [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_iq;
    wire [15:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_q;
    wire [4:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_a;
    wire [5:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_b;
    logic [5:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_o;
    wire [5:0] redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_q;
    reg [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_inputreg0_q;
    reg [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_outputreg0_q;
    wire redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_reset0;
    wire [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_ia;
    wire [4:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_aa;
    wire [4:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_ab;
    wire [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_iq;
    wire [15:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_q;
    wire [4:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_a;
    wire [5:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_b;
    logic [5:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_o;
    wire [5:0] redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_q;
    reg [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_inputreg0_q;
    reg [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_outputreg0_q;
    wire redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_reset0;
    wire [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_ia;
    wire [4:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_aa;
    wire [4:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_ab;
    wire [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_iq;
    wire [15:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_q;
    wire [4:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_a;
    wire [5:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_b;
    logic [5:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_o;
    wire [5:0] redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_q;
    reg [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_inputreg0_q;
    reg [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_outputreg0_q;
    wire redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_reset0;
    wire [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_ia;
    wire [4:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_aa;
    wire [4:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_ab;
    wire [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_iq;
    wire [15:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_q;
    wire [4:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_a;
    wire [5:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_b;
    logic [5:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_o;
    wire [5:0] redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_q;
    reg [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_inputreg0_q;
    reg [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_outputreg0_q;
    wire redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_reset0;
    wire [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_ia;
    wire [4:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_aa;
    wire [4:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_ab;
    wire [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_iq;
    wire [15:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_q;
    wire [4:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_a;
    wire [5:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_b;
    logic [5:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_o;
    wire [5:0] redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_q;
    reg [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_inputreg0_q;
    reg [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_outputreg0_q;
    wire redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_reset0;
    wire [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_ia;
    wire [4:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_aa;
    wire [4:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_ab;
    wire [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_iq;
    wire [15:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_q;
    wire [4:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_a;
    wire [5:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_b;
    logic [5:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_o;
    wire [5:0] redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_q;
    reg [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_inputreg0_q;
    reg [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_outputreg0_q;
    wire redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_reset0;
    wire [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_ia;
    wire [4:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_aa;
    wire [4:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_ab;
    wire [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_iq;
    wire [15:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_q;
    wire [4:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_a;
    wire [5:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_b;
    logic [5:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_o;
    wire [5:0] redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_q;
    reg [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_inputreg0_q;
    reg [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_outputreg0_q;
    wire redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_reset0;
    wire [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_ia;
    wire [4:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_aa;
    wire [4:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_ab;
    wire [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_iq;
    wire [15:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_q;
    wire [4:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_a;
    wire [5:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_b;
    logic [5:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_o;
    wire [5:0] redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_q;
    reg [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_inputreg0_q;
    reg [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_outputreg0_q;
    wire redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_reset0;
    wire [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_ia;
    wire [4:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_aa;
    wire [4:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_ab;
    wire [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_iq;
    wire [15:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_q;
    wire [4:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_a;
    wire [5:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_b;
    logic [5:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_o;
    wire [5:0] redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_q;
    reg [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_inputreg0_q;
    reg [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_outputreg0_q;
    wire redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_reset0;
    wire [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_ia;
    wire [4:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_aa;
    wire [4:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_ab;
    wire [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_iq;
    wire [15:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_q;
    wire [4:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_a;
    wire [5:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_b;
    logic [5:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_o;
    wire [5:0] redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_q;
    reg [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_inputreg0_q;
    reg [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_outputreg0_q;
    wire redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_reset0;
    wire [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_ia;
    wire [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_aa;
    wire [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_ab;
    wire [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_iq;
    wire [15:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_q;
    wire [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_a;
    wire [5:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_b;
    logic [5:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_o;
    wire [5:0] redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_q;
    reg [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_inputreg0_q;
    reg [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_outputreg0_q;
    wire redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_reset0;
    wire [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_ia;
    wire [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_aa;
    wire [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_ab;
    wire [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_iq;
    wire [15:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_q;
    wire [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_a;
    wire [5:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_b;
    logic [5:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_o;
    wire [5:0] redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_q;
    reg [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_inputreg0_q;
    reg [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_outputreg0_q;
    wire redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_reset0;
    wire [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_ia;
    wire [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_aa;
    wire [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_ab;
    wire [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_iq;
    wire [15:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_q;
    wire [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_a;
    wire [5:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_b;
    logic [5:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_o;
    wire [5:0] redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_q;
    reg [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_inputreg0_q;
    reg [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_outputreg0_q;
    wire redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_reset0;
    wire [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_ia;
    wire [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_aa;
    wire [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_ab;
    wire [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_iq;
    wire [15:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_q;
    wire [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_a;
    wire [5:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_b;
    logic [5:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_o;
    wire [5:0] redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_q;
    reg [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_inputreg0_q;
    reg [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_outputreg0_q;
    wire redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_reset0;
    wire [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_ia;
    wire [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_aa;
    wire [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_ab;
    wire [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_iq;
    wire [15:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_q;
    wire [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_a;
    wire [5:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_b;
    logic [5:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_o;
    wire [5:0] redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_q;
    reg [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_inputreg0_q;
    reg [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_outputreg0_q;
    wire redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_reset0;
    wire [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_ia;
    wire [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_aa;
    wire [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_ab;
    wire [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_iq;
    wire [15:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_q;
    wire [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_a;
    wire [5:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_b;
    logic [5:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_o;
    wire [5:0] redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_q;
    reg [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_inputreg0_q;
    reg [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_outputreg0_q;
    wire redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_reset0;
    wire [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_ia;
    wire [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_aa;
    wire [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_ab;
    wire [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_iq;
    wire [15:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_q;
    wire [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_a;
    wire [5:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_b;
    logic [5:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_o;
    wire [5:0] redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_q;
    reg [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_inputreg0_q;
    reg [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_outputreg0_q;
    wire redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_reset0;
    wire [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_ia;
    wire [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_aa;
    wire [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_ab;
    wire [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_iq;
    wire [15:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_q;
    wire [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_a;
    wire [5:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_b;
    logic [5:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_o;
    wire [5:0] redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_q;
    reg [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_inputreg0_q;
    reg [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_outputreg0_q;
    wire redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_reset0;
    wire [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_ia;
    wire [4:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_aa;
    wire [4:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_ab;
    wire [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_iq;
    wire [15:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_q;
    wire [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_a;
    wire [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_b;
    logic [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_o;
    wire [5:0] redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_q;
    reg [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_inputreg0_q;
    reg [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_outputreg0_q;
    wire redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_reset0;
    wire [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_ia;
    wire [4:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_aa;
    wire [4:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_ab;
    wire [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_iq;
    wire [15:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_q;
    wire [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_a;
    wire [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_b;
    logic [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_o;
    wire [5:0] redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_q;
    reg [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_inputreg0_q;
    reg [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_outputreg0_q;
    wire redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_reset0;
    wire [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_ia;
    wire [4:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_aa;
    wire [4:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_ab;
    wire [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_iq;
    wire [15:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_q;
    wire [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_a;
    wire [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_b;
    logic [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_o;
    wire [5:0] redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_q;
    reg [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_inputreg0_q;
    reg [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_outputreg0_q;
    wire redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_reset0;
    wire [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_ia;
    wire [4:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_aa;
    wire [4:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_ab;
    wire [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_iq;
    wire [15:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_q;
    wire [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_a;
    wire [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_b;
    logic [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_o;
    wire [5:0] redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_q;
    reg [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_inputreg0_q;
    reg [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_outputreg0_q;
    wire redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_reset0;
    wire [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_ia;
    wire [4:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_aa;
    wire [4:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_ab;
    wire [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_iq;
    wire [15:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_q;
    wire [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_a;
    wire [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_b;
    logic [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_o;
    wire [5:0] redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_q;
    reg [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_inputreg0_q;
    reg [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_outputreg0_q;
    wire redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_reset0;
    wire [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_ia;
    wire [4:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_aa;
    wire [4:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_ab;
    wire [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_iq;
    wire [15:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_q;
    wire [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_a;
    wire [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_b;
    logic [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_o;
    wire [5:0] redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_q;
    reg [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_inputreg0_q;
    reg [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_outputreg0_q;
    wire redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_reset0;
    wire [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_ia;
    wire [4:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_aa;
    wire [4:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_ab;
    wire [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_iq;
    wire [15:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_q;
    wire [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_a;
    wire [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_b;
    logic [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_o;
    wire [5:0] redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_q;
    reg [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_inputreg0_q;
    reg [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_outputreg0_q;
    wire redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_reset0;
    wire [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_ia;
    wire [4:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_aa;
    wire [4:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_ab;
    wire [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_iq;
    wire [15:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_q;
    wire [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_a;
    wire [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_b;
    logic [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_o;
    wire [5:0] redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_q;
    reg [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_inputreg0_q;
    reg [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_outputreg0_q;
    wire redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_reset0;
    wire [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_ia;
    wire [4:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_aa;
    wire [4:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_ab;
    wire [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_iq;
    wire [15:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_q;
    wire [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_a;
    wire [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_b;
    logic [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_o;
    wire [5:0] redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_q;
    reg [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_inputreg0_q;
    reg [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_outputreg0_q;
    wire redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_reset0;
    wire [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_ia;
    wire [4:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_aa;
    wire [4:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_ab;
    wire [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_iq;
    wire [15:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_q;
    wire [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_a;
    wire [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_b;
    logic [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_o;
    wire [5:0] redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_q;
    reg [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_inputreg0_q;
    reg [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_outputreg0_q;
    wire redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_reset0;
    wire [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_ia;
    wire [4:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_aa;
    wire [4:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_ab;
    wire [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_iq;
    wire [15:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_q;
    wire [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_a;
    wire [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_b;
    logic [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_o;
    wire [5:0] redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_q;
    reg [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_inputreg0_q;
    reg [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_outputreg0_q;
    wire redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_reset0;
    wire [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_ia;
    wire [4:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_aa;
    wire [4:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_ab;
    wire [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_iq;
    wire [15:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_q;
    wire [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_a;
    wire [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_b;
    logic [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_o;
    wire [5:0] redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_q;
    reg [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_inputreg0_q;
    reg [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_outputreg0_q;
    wire redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_reset0;
    wire [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_ia;
    wire [4:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_aa;
    wire [4:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_ab;
    wire [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_iq;
    wire [15:0] redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_q;
    reg [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_inputreg0_q;
    reg [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_outputreg0_q;
    wire redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_reset0;
    wire [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_ia;
    wire [4:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_aa;
    wire [4:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_ab;
    wire [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_iq;
    wire [15:0] redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_q;
    reg [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_inputreg0_q;
    reg [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_outputreg0_q;
    wire redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_reset0;
    wire [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_ia;
    wire [4:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_aa;
    wire [4:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_ab;
    wire [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_iq;
    wire [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_q;
    wire [4:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_a;
    wire [5:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_b;
    logic [5:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_o;
    wire [5:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_q;
    reg [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_inputreg0_q;
    reg [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_outputreg0_q;
    wire redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_reset0;
    wire [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_ia;
    wire [4:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_aa;
    wire [4:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_ab;
    wire [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_iq;
    wire [15:0] redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_q;
    reg [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_inputreg0_q;
    reg [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_outputreg0_q;
    wire redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_reset0;
    wire [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_ia;
    wire [4:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_aa;
    wire [4:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_ab;
    wire [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_iq;
    wire [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_q;
    wire [4:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_a;
    wire [5:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_b;
    logic [5:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_o;
    wire [5:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_q;
    reg [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_inputreg0_q;
    reg [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_outputreg0_q;
    wire redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_reset0;
    wire [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_ia;
    wire [4:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_aa;
    wire [4:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_ab;
    wire [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_iq;
    wire [15:0] redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_q;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_inputreg0_q;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_outputreg0_q;
    wire redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_reset0;
    wire [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_ia;
    wire [4:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_aa;
    wire [4:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_ab;
    wire [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_iq;
    wire [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_q;
    wire [4:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_a;
    wire [5:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_b;
    logic [5:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_o;
    wire [5:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_q;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_inputreg0_q;
    reg [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_outputreg0_q;
    wire redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_reset0;
    wire [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_ia;
    wire [4:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_aa;
    wire [4:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_ab;
    wire [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_iq;
    wire [15:0] redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_q;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_inputreg0_q;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_outputreg0_q;
    wire redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_reset0;
    wire [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_ia;
    wire [4:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_aa;
    wire [4:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_ab;
    wire [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_iq;
    wire [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_q;
    wire [4:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_a;
    wire [5:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_b;
    logic [5:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_o;
    wire [5:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_q;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_inputreg0_q;
    reg [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_outputreg0_q;
    wire redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_reset0;
    wire [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_ia;
    wire [4:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_aa;
    wire [4:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_ab;
    wire [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_iq;
    wire [15:0] redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_q;
    reg [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_inputreg0_q;
    reg [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_outputreg0_q;
    wire redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_reset0;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_ia;
    wire [4:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_aa;
    wire [4:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_ab;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_iq;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_q;
    wire [4:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_a;
    wire [5:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_b;
    logic [5:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_o;
    wire [5:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_q;
    reg [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_inputreg0_q;
    reg [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_outputreg0_q;
    wire redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_reset0;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_ia;
    wire [4:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_aa;
    wire [4:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_ab;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_iq;
    wire [15:0] redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_q;
    reg [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_inputreg0_q;
    reg [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_outputreg0_q;
    wire redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_reset0;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_ia;
    wire [4:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_aa;
    wire [4:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_ab;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_iq;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_q;
    wire [4:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_a;
    wire [5:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_b;
    logic [5:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_o;
    wire [5:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_q;
    reg [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_inputreg0_q;
    reg [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_outputreg0_q;
    wire redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_reset0;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_ia;
    wire [4:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_aa;
    wire [4:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_ab;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_iq;
    wire [15:0] redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_q;
    reg [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_inputreg0_q;
    reg [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_outputreg0_q;
    wire redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_reset0;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_ia;
    wire [4:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_aa;
    wire [4:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_ab;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_iq;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_q;
    wire [4:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_a;
    wire [5:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_b;
    logic [5:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_o;
    wire [5:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_q;
    reg [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_inputreg0_q;
    reg [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_outputreg0_q;
    wire redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_reset0;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_ia;
    wire [4:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_aa;
    wire [4:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_ab;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_iq;
    wire [15:0] redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_q;
    reg [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_inputreg0_q;
    reg [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_outputreg0_q;
    wire redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_reset0;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_ia;
    wire [4:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_aa;
    wire [4:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_ab;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_iq;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_q;
    wire [4:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_a;
    wire [5:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_b;
    logic [5:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_o;
    wire [5:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_q;
    reg [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_inputreg0_q;
    reg [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_outputreg0_q;
    wire redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_reset0;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_ia;
    wire [4:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_aa;
    wire [4:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_ab;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_iq;
    wire [15:0] redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_q;
    reg [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_inputreg0_q;
    reg [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_outputreg0_q;
    wire redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_reset0;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_ia;
    wire [4:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_aa;
    wire [4:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_ab;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_iq;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_q;
    wire [4:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_a;
    wire [5:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_b;
    logic [5:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_o;
    wire [5:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_q;
    reg [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_inputreg0_q;
    reg [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_outputreg0_q;
    wire redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_reset0;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_ia;
    wire [4:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_aa;
    wire [4:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_ab;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_iq;
    wire [15:0] redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_q;
    reg [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_inputreg0_q;
    reg [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_outputreg0_q;
    wire redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_reset0;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_ia;
    wire [4:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_aa;
    wire [4:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_ab;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_iq;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_q;
    wire [4:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_a;
    wire [5:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_b;
    logic [5:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_o;
    wire [5:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_q;
    reg [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_inputreg0_q;
    reg [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_outputreg0_q;
    wire redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_reset0;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_ia;
    wire [4:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_aa;
    wire [4:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_ab;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_iq;
    wire [15:0] redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_q;
    reg [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_inputreg0_q;
    reg [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_outputreg0_q;
    wire redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_reset0;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_ia;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_aa;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_ab;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_iq;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_q;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_a;
    wire [5:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_b;
    logic [5:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_o;
    wire [5:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_q;
    reg [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_inputreg0_q;
    reg [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_outputreg0_q;
    wire redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_reset0;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_ia;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_aa;
    wire [4:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_ab;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_iq;
    wire [15:0] redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_q;
    reg [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_inputreg0_q;
    reg [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_outputreg0_q;
    wire redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_reset0;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_ia;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_aa;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_ab;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_iq;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_q;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_a;
    wire [5:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_b;
    logic [5:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_o;
    wire [5:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_q;
    reg [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_inputreg0_q;
    reg [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_outputreg0_q;
    wire redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_reset0;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_ia;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_aa;
    wire [4:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_ab;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_iq;
    wire [15:0] redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_q;
    reg [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_inputreg0_q;
    reg [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_outputreg0_q;
    wire redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_reset0;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_ia;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_aa;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_ab;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_iq;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_q;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_a;
    wire [5:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_b;
    logic [5:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_o;
    wire [5:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_q;
    reg [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_inputreg0_q;
    reg [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_outputreg0_q;
    wire redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_reset0;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_ia;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_aa;
    wire [4:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_ab;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_iq;
    wire [15:0] redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_q;
    reg [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_inputreg0_q;
    reg [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_outputreg0_q;
    wire redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_reset0;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_ia;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_aa;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_ab;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_iq;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_q;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_a;
    wire [5:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_b;
    logic [5:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_o;
    wire [5:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_q;
    reg [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_inputreg0_q;
    reg [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_outputreg0_q;
    wire redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_reset0;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_ia;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_aa;
    wire [4:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_ab;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_iq;
    wire [15:0] redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_q;
    wire redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_reset0;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_ia;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_aa;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_ab;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_iq;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_q;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_i = 5'b11111;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_offset_q;
    wire [5:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_a;
    wire [5:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_b;
    logic [5:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_o;
    wire [5:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_q;
    wire redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_reset0;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_ia;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_aa;
    wire [4:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_ab;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_iq;
    wire [15:0] redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_q;
    wire redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_reset0;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_ia;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_aa;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_ab;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_iq;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_q;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_q;
    // Initial-value here is arbitrary, but a resolved value is necessary for simulation.
    (* preserve_syn_only *) reg [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_i = 5'b11111;
    wire [5:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_a;
    wire [5:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_b;
    logic [5:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_o;
    wire [5:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_q;
    wire redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_reset0;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_ia;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_aa;
    wire [4:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_ab;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_iq;
    wire [15:0] redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_q;


    // VCC(CONSTANT,1)
    assign VCC_q = $unsigned(1'b1);

    // redist760_sync_together4364_aunroll_x_in_i_valid_1(DELAY,29888)
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist760_sync_together4364_aunroll_x_in_i_valid_1_q <= '0;
        end
        else
        begin
            redist760_sync_together4364_aunroll_x_in_i_valid_1_q <= $unsigned(in_i_valid);
        end
    end

    // redist761_sync_together4364_aunroll_x_in_i_valid_3(DELAY,29889)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist761_sync_together4364_aunroll_x_in_i_valid_3_delay_0 <= $unsigned(redist760_sync_together4364_aunroll_x_in_i_valid_1_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist761_sync_together4364_aunroll_x_in_i_valid_3_q <= '0;
        end
        else
        begin
            redist761_sync_together4364_aunroll_x_in_i_valid_3_q <= redist761_sync_together4364_aunroll_x_in_i_valid_3_delay_0;
        end
    end

    // redist762_sync_together4364_aunroll_x_in_i_valid_5(DELAY,29890)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist762_sync_together4364_aunroll_x_in_i_valid_5_delay_0 <= $unsigned(redist761_sync_together4364_aunroll_x_in_i_valid_3_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist762_sync_together4364_aunroll_x_in_i_valid_5_q <= '0;
        end
        else
        begin
            redist762_sync_together4364_aunroll_x_in_i_valid_5_q <= redist762_sync_together4364_aunroll_x_in_i_valid_5_delay_0;
        end
    end

    // redist763_sync_together4364_aunroll_x_in_i_valid_7(DELAY,29891)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist763_sync_together4364_aunroll_x_in_i_valid_7_delay_0 <= $unsigned(redist762_sync_together4364_aunroll_x_in_i_valid_5_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist763_sync_together4364_aunroll_x_in_i_valid_7_q <= '0;
        end
        else
        begin
            redist763_sync_together4364_aunroll_x_in_i_valid_7_q <= redist763_sync_together4364_aunroll_x_in_i_valid_7_delay_0;
        end
    end

    // redist764_sync_together4364_aunroll_x_in_i_valid_9(DELAY,29892)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist764_sync_together4364_aunroll_x_in_i_valid_9_delay_0 <= $unsigned(redist763_sync_together4364_aunroll_x_in_i_valid_7_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist764_sync_together4364_aunroll_x_in_i_valid_9_q <= '0;
        end
        else
        begin
            redist764_sync_together4364_aunroll_x_in_i_valid_9_q <= redist764_sync_together4364_aunroll_x_in_i_valid_9_delay_0;
        end
    end

    // redist765_sync_together4364_aunroll_x_in_i_valid_11(DELAY,29893)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist765_sync_together4364_aunroll_x_in_i_valid_11_delay_0 <= $unsigned(redist764_sync_together4364_aunroll_x_in_i_valid_9_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist765_sync_together4364_aunroll_x_in_i_valid_11_q <= '0;
        end
        else
        begin
            redist765_sync_together4364_aunroll_x_in_i_valid_11_q <= redist765_sync_together4364_aunroll_x_in_i_valid_11_delay_0;
        end
    end

    // redist766_sync_together4364_aunroll_x_in_i_valid_13(DELAY,29894)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist766_sync_together4364_aunroll_x_in_i_valid_13_delay_0 <= $unsigned(redist765_sync_together4364_aunroll_x_in_i_valid_11_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist766_sync_together4364_aunroll_x_in_i_valid_13_q <= '0;
        end
        else
        begin
            redist766_sync_together4364_aunroll_x_in_i_valid_13_q <= redist766_sync_together4364_aunroll_x_in_i_valid_13_delay_0;
        end
    end

    // redist767_sync_together4364_aunroll_x_in_i_valid_15(DELAY,29895)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist767_sync_together4364_aunroll_x_in_i_valid_15_delay_0 <= $unsigned(redist766_sync_together4364_aunroll_x_in_i_valid_13_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist767_sync_together4364_aunroll_x_in_i_valid_15_q <= '0;
        end
        else
        begin
            redist767_sync_together4364_aunroll_x_in_i_valid_15_q <= redist767_sync_together4364_aunroll_x_in_i_valid_15_delay_0;
        end
    end

    // redist768_sync_together4364_aunroll_x_in_i_valid_17(DELAY,29896)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist768_sync_together4364_aunroll_x_in_i_valid_17_delay_0 <= $unsigned(redist767_sync_together4364_aunroll_x_in_i_valid_15_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist768_sync_together4364_aunroll_x_in_i_valid_17_q <= '0;
        end
        else
        begin
            redist768_sync_together4364_aunroll_x_in_i_valid_17_q <= redist768_sync_together4364_aunroll_x_in_i_valid_17_delay_0;
        end
    end

    // redist769_sync_together4364_aunroll_x_in_i_valid_19(DELAY,29897)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist769_sync_together4364_aunroll_x_in_i_valid_19_delay_0 <= $unsigned(redist768_sync_together4364_aunroll_x_in_i_valid_17_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist769_sync_together4364_aunroll_x_in_i_valid_19_q <= '0;
        end
        else
        begin
            redist769_sync_together4364_aunroll_x_in_i_valid_19_q <= redist769_sync_together4364_aunroll_x_in_i_valid_19_delay_0;
        end
    end

    // redist770_sync_together4364_aunroll_x_in_i_valid_21(DELAY,29898)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist770_sync_together4364_aunroll_x_in_i_valid_21_delay_0 <= $unsigned(redist769_sync_together4364_aunroll_x_in_i_valid_19_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist770_sync_together4364_aunroll_x_in_i_valid_21_q <= '0;
        end
        else
        begin
            redist770_sync_together4364_aunroll_x_in_i_valid_21_q <= redist770_sync_together4364_aunroll_x_in_i_valid_21_delay_0;
        end
    end

    // redist771_sync_together4364_aunroll_x_in_i_valid_23(DELAY,29899)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist771_sync_together4364_aunroll_x_in_i_valid_23_delay_0 <= $unsigned(redist770_sync_together4364_aunroll_x_in_i_valid_21_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist771_sync_together4364_aunroll_x_in_i_valid_23_q <= '0;
        end
        else
        begin
            redist771_sync_together4364_aunroll_x_in_i_valid_23_q <= redist771_sync_together4364_aunroll_x_in_i_valid_23_delay_0;
        end
    end

    // redist772_sync_together4364_aunroll_x_in_i_valid_25(DELAY,29900)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist772_sync_together4364_aunroll_x_in_i_valid_25_delay_0 <= $unsigned(redist771_sync_together4364_aunroll_x_in_i_valid_23_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist772_sync_together4364_aunroll_x_in_i_valid_25_q <= '0;
        end
        else
        begin
            redist772_sync_together4364_aunroll_x_in_i_valid_25_q <= redist772_sync_together4364_aunroll_x_in_i_valid_25_delay_0;
        end
    end

    // redist773_sync_together4364_aunroll_x_in_i_valid_27(DELAY,29901)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist773_sync_together4364_aunroll_x_in_i_valid_27_delay_0 <= $unsigned(redist772_sync_together4364_aunroll_x_in_i_valid_25_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist773_sync_together4364_aunroll_x_in_i_valid_27_q <= '0;
        end
        else
        begin
            redist773_sync_together4364_aunroll_x_in_i_valid_27_q <= redist773_sync_together4364_aunroll_x_in_i_valid_27_delay_0;
        end
    end

    // redist774_sync_together4364_aunroll_x_in_i_valid_29(DELAY,29902)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist774_sync_together4364_aunroll_x_in_i_valid_29_delay_0 <= $unsigned(redist773_sync_together4364_aunroll_x_in_i_valid_27_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist774_sync_together4364_aunroll_x_in_i_valid_29_q <= '0;
        end
        else
        begin
            redist774_sync_together4364_aunroll_x_in_i_valid_29_q <= redist774_sync_together4364_aunroll_x_in_i_valid_29_delay_0;
        end
    end

    // redist775_sync_together4364_aunroll_x_in_i_valid_31(DELAY,29903)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist775_sync_together4364_aunroll_x_in_i_valid_31_delay_0 <= $unsigned(redist774_sync_together4364_aunroll_x_in_i_valid_29_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist775_sync_together4364_aunroll_x_in_i_valid_31_q <= '0;
        end
        else
        begin
            redist775_sync_together4364_aunroll_x_in_i_valid_31_q <= redist775_sync_together4364_aunroll_x_in_i_valid_31_delay_0;
        end
    end

    // redist776_sync_together4364_aunroll_x_in_i_valid_33(DELAY,29904)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist776_sync_together4364_aunroll_x_in_i_valid_33_delay_0 <= $unsigned(redist775_sync_together4364_aunroll_x_in_i_valid_31_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist776_sync_together4364_aunroll_x_in_i_valid_33_q <= '0;
        end
        else
        begin
            redist776_sync_together4364_aunroll_x_in_i_valid_33_q <= redist776_sync_together4364_aunroll_x_in_i_valid_33_delay_0;
        end
    end

    // redist777_sync_together4364_aunroll_x_in_i_valid_35(DELAY,29905)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist777_sync_together4364_aunroll_x_in_i_valid_35_delay_0 <= $unsigned(redist776_sync_together4364_aunroll_x_in_i_valid_33_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist777_sync_together4364_aunroll_x_in_i_valid_35_q <= '0;
        end
        else
        begin
            redist777_sync_together4364_aunroll_x_in_i_valid_35_q <= redist777_sync_together4364_aunroll_x_in_i_valid_35_delay_0;
        end
    end

    // redist778_sync_together4364_aunroll_x_in_i_valid_37(DELAY,29906)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist778_sync_together4364_aunroll_x_in_i_valid_37_delay_0 <= $unsigned(redist777_sync_together4364_aunroll_x_in_i_valid_35_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist778_sync_together4364_aunroll_x_in_i_valid_37_q <= '0;
        end
        else
        begin
            redist778_sync_together4364_aunroll_x_in_i_valid_37_q <= redist778_sync_together4364_aunroll_x_in_i_valid_37_delay_0;
        end
    end

    // redist779_sync_together4364_aunroll_x_in_i_valid_39(DELAY,29907)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist779_sync_together4364_aunroll_x_in_i_valid_39_delay_0 <= $unsigned(redist778_sync_together4364_aunroll_x_in_i_valid_37_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist779_sync_together4364_aunroll_x_in_i_valid_39_q <= '0;
        end
        else
        begin
            redist779_sync_together4364_aunroll_x_in_i_valid_39_q <= redist779_sync_together4364_aunroll_x_in_i_valid_39_delay_0;
        end
    end

    // redist780_sync_together4364_aunroll_x_in_i_valid_41(DELAY,29908)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist780_sync_together4364_aunroll_x_in_i_valid_41_delay_0 <= $unsigned(redist779_sync_together4364_aunroll_x_in_i_valid_39_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist780_sync_together4364_aunroll_x_in_i_valid_41_q <= '0;
        end
        else
        begin
            redist780_sync_together4364_aunroll_x_in_i_valid_41_q <= redist780_sync_together4364_aunroll_x_in_i_valid_41_delay_0;
        end
    end

    // redist781_sync_together4364_aunroll_x_in_i_valid_43(DELAY,29909)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist781_sync_together4364_aunroll_x_in_i_valid_43_delay_0 <= $unsigned(redist780_sync_together4364_aunroll_x_in_i_valid_41_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist781_sync_together4364_aunroll_x_in_i_valid_43_q <= '0;
        end
        else
        begin
            redist781_sync_together4364_aunroll_x_in_i_valid_43_q <= redist781_sync_together4364_aunroll_x_in_i_valid_43_delay_0;
        end
    end

    // redist782_sync_together4364_aunroll_x_in_i_valid_45(DELAY,29910)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist782_sync_together4364_aunroll_x_in_i_valid_45_delay_0 <= $unsigned(redist781_sync_together4364_aunroll_x_in_i_valid_43_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist782_sync_together4364_aunroll_x_in_i_valid_45_q <= '0;
        end
        else
        begin
            redist782_sync_together4364_aunroll_x_in_i_valid_45_q <= redist782_sync_together4364_aunroll_x_in_i_valid_45_delay_0;
        end
    end

    // redist783_sync_together4364_aunroll_x_in_i_valid_47(DELAY,29911)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist783_sync_together4364_aunroll_x_in_i_valid_47_delay_0 <= $unsigned(redist782_sync_together4364_aunroll_x_in_i_valid_45_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist783_sync_together4364_aunroll_x_in_i_valid_47_q <= '0;
        end
        else
        begin
            redist783_sync_together4364_aunroll_x_in_i_valid_47_q <= redist783_sync_together4364_aunroll_x_in_i_valid_47_delay_0;
        end
    end

    // redist784_sync_together4364_aunroll_x_in_i_valid_49(DELAY,29912)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist784_sync_together4364_aunroll_x_in_i_valid_49_delay_0 <= $unsigned(redist783_sync_together4364_aunroll_x_in_i_valid_47_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist784_sync_together4364_aunroll_x_in_i_valid_49_q <= '0;
        end
        else
        begin
            redist784_sync_together4364_aunroll_x_in_i_valid_49_q <= redist784_sync_together4364_aunroll_x_in_i_valid_49_delay_0;
        end
    end

    // redist785_sync_together4364_aunroll_x_in_i_valid_51(DELAY,29913)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist785_sync_together4364_aunroll_x_in_i_valid_51_delay_0 <= $unsigned(redist784_sync_together4364_aunroll_x_in_i_valid_49_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist785_sync_together4364_aunroll_x_in_i_valid_51_q <= '0;
        end
        else
        begin
            redist785_sync_together4364_aunroll_x_in_i_valid_51_q <= redist785_sync_together4364_aunroll_x_in_i_valid_51_delay_0;
        end
    end

    // redist786_sync_together4364_aunroll_x_in_i_valid_53(DELAY,29914)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist786_sync_together4364_aunroll_x_in_i_valid_53_delay_0 <= $unsigned(redist785_sync_together4364_aunroll_x_in_i_valid_51_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist786_sync_together4364_aunroll_x_in_i_valid_53_q <= '0;
        end
        else
        begin
            redist786_sync_together4364_aunroll_x_in_i_valid_53_q <= redist786_sync_together4364_aunroll_x_in_i_valid_53_delay_0;
        end
    end

    // redist787_sync_together4364_aunroll_x_in_i_valid_55(DELAY,29915)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist787_sync_together4364_aunroll_x_in_i_valid_55_delay_0 <= $unsigned(redist786_sync_together4364_aunroll_x_in_i_valid_53_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist787_sync_together4364_aunroll_x_in_i_valid_55_q <= '0;
        end
        else
        begin
            redist787_sync_together4364_aunroll_x_in_i_valid_55_q <= redist787_sync_together4364_aunroll_x_in_i_valid_55_delay_0;
        end
    end

    // redist788_sync_together4364_aunroll_x_in_i_valid_57(DELAY,29916)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist788_sync_together4364_aunroll_x_in_i_valid_57_delay_0 <= $unsigned(redist787_sync_together4364_aunroll_x_in_i_valid_55_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist788_sync_together4364_aunroll_x_in_i_valid_57_q <= '0;
        end
        else
        begin
            redist788_sync_together4364_aunroll_x_in_i_valid_57_q <= redist788_sync_together4364_aunroll_x_in_i_valid_57_delay_0;
        end
    end

    // redist789_sync_together4364_aunroll_x_in_i_valid_59(DELAY,29917)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist789_sync_together4364_aunroll_x_in_i_valid_59_delay_0 <= $unsigned(redist788_sync_together4364_aunroll_x_in_i_valid_57_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist789_sync_together4364_aunroll_x_in_i_valid_59_q <= '0;
        end
        else
        begin
            redist789_sync_together4364_aunroll_x_in_i_valid_59_q <= redist789_sync_together4364_aunroll_x_in_i_valid_59_delay_0;
        end
    end

    // redist790_sync_together4364_aunroll_x_in_i_valid_61(DELAY,29918)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist790_sync_together4364_aunroll_x_in_i_valid_61_delay_0 <= $unsigned(redist789_sync_together4364_aunroll_x_in_i_valid_59_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist790_sync_together4364_aunroll_x_in_i_valid_61_q <= '0;
        end
        else
        begin
            redist790_sync_together4364_aunroll_x_in_i_valid_61_q <= redist790_sync_together4364_aunroll_x_in_i_valid_61_delay_0;
        end
    end

    // redist791_sync_together4364_aunroll_x_in_i_valid_63(DELAY,29919)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist791_sync_together4364_aunroll_x_in_i_valid_63_delay_0 <= $unsigned(redist790_sync_together4364_aunroll_x_in_i_valid_61_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist791_sync_together4364_aunroll_x_in_i_valid_63_q <= '0;
        end
        else
        begin
            redist791_sync_together4364_aunroll_x_in_i_valid_63_q <= redist791_sync_together4364_aunroll_x_in_i_valid_63_delay_0;
        end
    end

    // redist792_sync_together4364_aunroll_x_in_i_valid_65(DELAY,29920)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist792_sync_together4364_aunroll_x_in_i_valid_65_delay_0 <= $unsigned(redist791_sync_together4364_aunroll_x_in_i_valid_63_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist792_sync_together4364_aunroll_x_in_i_valid_65_q <= '0;
        end
        else
        begin
            redist792_sync_together4364_aunroll_x_in_i_valid_65_q <= redist792_sync_together4364_aunroll_x_in_i_valid_65_delay_0;
        end
    end

    // redist793_sync_together4364_aunroll_x_in_i_valid_67(DELAY,29921)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist793_sync_together4364_aunroll_x_in_i_valid_67_delay_0 <= $unsigned(redist792_sync_together4364_aunroll_x_in_i_valid_65_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist793_sync_together4364_aunroll_x_in_i_valid_67_q <= '0;
        end
        else
        begin
            redist793_sync_together4364_aunroll_x_in_i_valid_67_q <= redist793_sync_together4364_aunroll_x_in_i_valid_67_delay_0;
        end
    end

    // redist794_sync_together4364_aunroll_x_in_i_valid_69(DELAY,29922)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist794_sync_together4364_aunroll_x_in_i_valid_69_delay_0 <= $unsigned(redist793_sync_together4364_aunroll_x_in_i_valid_67_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist794_sync_together4364_aunroll_x_in_i_valid_69_q <= '0;
        end
        else
        begin
            redist794_sync_together4364_aunroll_x_in_i_valid_69_q <= redist794_sync_together4364_aunroll_x_in_i_valid_69_delay_0;
        end
    end

    // redist795_sync_together4364_aunroll_x_in_i_valid_71(DELAY,29923)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist795_sync_together4364_aunroll_x_in_i_valid_71_delay_0 <= $unsigned(redist794_sync_together4364_aunroll_x_in_i_valid_69_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist795_sync_together4364_aunroll_x_in_i_valid_71_q <= '0;
        end
        else
        begin
            redist795_sync_together4364_aunroll_x_in_i_valid_71_q <= redist795_sync_together4364_aunroll_x_in_i_valid_71_delay_0;
        end
    end

    // redist796_sync_together4364_aunroll_x_in_i_valid_73(DELAY,29924)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist796_sync_together4364_aunroll_x_in_i_valid_73_delay_0 <= $unsigned(redist795_sync_together4364_aunroll_x_in_i_valid_71_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist796_sync_together4364_aunroll_x_in_i_valid_73_q <= '0;
        end
        else
        begin
            redist796_sync_together4364_aunroll_x_in_i_valid_73_q <= redist796_sync_together4364_aunroll_x_in_i_valid_73_delay_0;
        end
    end

    // redist797_sync_together4364_aunroll_x_in_i_valid_75(DELAY,29925)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist797_sync_together4364_aunroll_x_in_i_valid_75_delay_0 <= $unsigned(redist796_sync_together4364_aunroll_x_in_i_valid_73_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist797_sync_together4364_aunroll_x_in_i_valid_75_q <= '0;
        end
        else
        begin
            redist797_sync_together4364_aunroll_x_in_i_valid_75_q <= redist797_sync_together4364_aunroll_x_in_i_valid_75_delay_0;
        end
    end

    // redist798_sync_together4364_aunroll_x_in_i_valid_77(DELAY,29926)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist798_sync_together4364_aunroll_x_in_i_valid_77_delay_0 <= $unsigned(redist797_sync_together4364_aunroll_x_in_i_valid_75_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist798_sync_together4364_aunroll_x_in_i_valid_77_q <= '0;
        end
        else
        begin
            redist798_sync_together4364_aunroll_x_in_i_valid_77_q <= redist798_sync_together4364_aunroll_x_in_i_valid_77_delay_0;
        end
    end

    // redist799_sync_together4364_aunroll_x_in_i_valid_79(DELAY,29927)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist799_sync_together4364_aunroll_x_in_i_valid_79_delay_0 <= $unsigned(redist798_sync_together4364_aunroll_x_in_i_valid_77_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist799_sync_together4364_aunroll_x_in_i_valid_79_q <= '0;
        end
        else
        begin
            redist799_sync_together4364_aunroll_x_in_i_valid_79_q <= redist799_sync_together4364_aunroll_x_in_i_valid_79_delay_0;
        end
    end

    // redist800_sync_together4364_aunroll_x_in_i_valid_81(DELAY,29928)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist800_sync_together4364_aunroll_x_in_i_valid_81_delay_0 <= $unsigned(redist799_sync_together4364_aunroll_x_in_i_valid_79_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist800_sync_together4364_aunroll_x_in_i_valid_81_q <= '0;
        end
        else
        begin
            redist800_sync_together4364_aunroll_x_in_i_valid_81_q <= redist800_sync_together4364_aunroll_x_in_i_valid_81_delay_0;
        end
    end

    // redist801_sync_together4364_aunroll_x_in_i_valid_83(DELAY,29929)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist801_sync_together4364_aunroll_x_in_i_valid_83_delay_0 <= $unsigned(redist800_sync_together4364_aunroll_x_in_i_valid_81_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist801_sync_together4364_aunroll_x_in_i_valid_83_q <= '0;
        end
        else
        begin
            redist801_sync_together4364_aunroll_x_in_i_valid_83_q <= redist801_sync_together4364_aunroll_x_in_i_valid_83_delay_0;
        end
    end

    // redist802_sync_together4364_aunroll_x_in_i_valid_85(DELAY,29930)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist802_sync_together4364_aunroll_x_in_i_valid_85_delay_0 <= $unsigned(redist801_sync_together4364_aunroll_x_in_i_valid_83_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist802_sync_together4364_aunroll_x_in_i_valid_85_q <= '0;
        end
        else
        begin
            redist802_sync_together4364_aunroll_x_in_i_valid_85_q <= redist802_sync_together4364_aunroll_x_in_i_valid_85_delay_0;
        end
    end

    // redist803_sync_together4364_aunroll_x_in_i_valid_87(DELAY,29931)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist803_sync_together4364_aunroll_x_in_i_valid_87_delay_0 <= $unsigned(redist802_sync_together4364_aunroll_x_in_i_valid_85_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist803_sync_together4364_aunroll_x_in_i_valid_87_q <= '0;
        end
        else
        begin
            redist803_sync_together4364_aunroll_x_in_i_valid_87_q <= redist803_sync_together4364_aunroll_x_in_i_valid_87_delay_0;
        end
    end

    // redist804_sync_together4364_aunroll_x_in_i_valid_89(DELAY,29932)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist804_sync_together4364_aunroll_x_in_i_valid_89_delay_0 <= $unsigned(redist803_sync_together4364_aunroll_x_in_i_valid_87_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist804_sync_together4364_aunroll_x_in_i_valid_89_q <= '0;
        end
        else
        begin
            redist804_sync_together4364_aunroll_x_in_i_valid_89_q <= redist804_sync_together4364_aunroll_x_in_i_valid_89_delay_0;
        end
    end

    // redist805_sync_together4364_aunroll_x_in_i_valid_91(DELAY,29933)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist805_sync_together4364_aunroll_x_in_i_valid_91_delay_0 <= $unsigned(redist804_sync_together4364_aunroll_x_in_i_valid_89_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist805_sync_together4364_aunroll_x_in_i_valid_91_q <= '0;
        end
        else
        begin
            redist805_sync_together4364_aunroll_x_in_i_valid_91_q <= redist805_sync_together4364_aunroll_x_in_i_valid_91_delay_0;
        end
    end

    // redist806_sync_together4364_aunroll_x_in_i_valid_93(DELAY,29934)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist806_sync_together4364_aunroll_x_in_i_valid_93_delay_0 <= $unsigned(redist805_sync_together4364_aunroll_x_in_i_valid_91_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist806_sync_together4364_aunroll_x_in_i_valid_93_q <= '0;
        end
        else
        begin
            redist806_sync_together4364_aunroll_x_in_i_valid_93_q <= redist806_sync_together4364_aunroll_x_in_i_valid_93_delay_0;
        end
    end

    // redist807_sync_together4364_aunroll_x_in_i_valid_95(DELAY,29935)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist807_sync_together4364_aunroll_x_in_i_valid_95_delay_0 <= $unsigned(redist806_sync_together4364_aunroll_x_in_i_valid_93_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist807_sync_together4364_aunroll_x_in_i_valid_95_q <= '0;
        end
        else
        begin
            redist807_sync_together4364_aunroll_x_in_i_valid_95_q <= redist807_sync_together4364_aunroll_x_in_i_valid_95_delay_0;
        end
    end

    // redist808_sync_together4364_aunroll_x_in_i_valid_97(DELAY,29936)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist808_sync_together4364_aunroll_x_in_i_valid_97_delay_0 <= $unsigned(redist807_sync_together4364_aunroll_x_in_i_valid_95_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist808_sync_together4364_aunroll_x_in_i_valid_97_q <= '0;
        end
        else
        begin
            redist808_sync_together4364_aunroll_x_in_i_valid_97_q <= redist808_sync_together4364_aunroll_x_in_i_valid_97_delay_0;
        end
    end

    // redist809_sync_together4364_aunroll_x_in_i_valid_99(DELAY,29937)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist809_sync_together4364_aunroll_x_in_i_valid_99_delay_0 <= $unsigned(redist808_sync_together4364_aunroll_x_in_i_valid_97_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist809_sync_together4364_aunroll_x_in_i_valid_99_q <= '0;
        end
        else
        begin
            redist809_sync_together4364_aunroll_x_in_i_valid_99_q <= redist809_sync_together4364_aunroll_x_in_i_valid_99_delay_0;
        end
    end

    // redist810_sync_together4364_aunroll_x_in_i_valid_101(DELAY,29938)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist810_sync_together4364_aunroll_x_in_i_valid_101_delay_0 <= $unsigned(redist809_sync_together4364_aunroll_x_in_i_valid_99_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist810_sync_together4364_aunroll_x_in_i_valid_101_q <= '0;
        end
        else
        begin
            redist810_sync_together4364_aunroll_x_in_i_valid_101_q <= redist810_sync_together4364_aunroll_x_in_i_valid_101_delay_0;
        end
    end

    // redist811_sync_together4364_aunroll_x_in_i_valid_103(DELAY,29939)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist811_sync_together4364_aunroll_x_in_i_valid_103_delay_0 <= $unsigned(redist810_sync_together4364_aunroll_x_in_i_valid_101_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist811_sync_together4364_aunroll_x_in_i_valid_103_q <= '0;
        end
        else
        begin
            redist811_sync_together4364_aunroll_x_in_i_valid_103_q <= redist811_sync_together4364_aunroll_x_in_i_valid_103_delay_0;
        end
    end

    // redist812_sync_together4364_aunroll_x_in_i_valid_105(DELAY,29940)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist812_sync_together4364_aunroll_x_in_i_valid_105_delay_0 <= $unsigned(redist811_sync_together4364_aunroll_x_in_i_valid_103_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist812_sync_together4364_aunroll_x_in_i_valid_105_q <= '0;
        end
        else
        begin
            redist812_sync_together4364_aunroll_x_in_i_valid_105_q <= redist812_sync_together4364_aunroll_x_in_i_valid_105_delay_0;
        end
    end

    // redist813_sync_together4364_aunroll_x_in_i_valid_107(DELAY,29941)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist813_sync_together4364_aunroll_x_in_i_valid_107_delay_0 <= $unsigned(redist812_sync_together4364_aunroll_x_in_i_valid_105_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist813_sync_together4364_aunroll_x_in_i_valid_107_q <= '0;
        end
        else
        begin
            redist813_sync_together4364_aunroll_x_in_i_valid_107_q <= redist813_sync_together4364_aunroll_x_in_i_valid_107_delay_0;
        end
    end

    // redist814_sync_together4364_aunroll_x_in_i_valid_109(DELAY,29942)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist814_sync_together4364_aunroll_x_in_i_valid_109_delay_0 <= $unsigned(redist813_sync_together4364_aunroll_x_in_i_valid_107_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist814_sync_together4364_aunroll_x_in_i_valid_109_q <= '0;
        end
        else
        begin
            redist814_sync_together4364_aunroll_x_in_i_valid_109_q <= redist814_sync_together4364_aunroll_x_in_i_valid_109_delay_0;
        end
    end

    // redist815_sync_together4364_aunroll_x_in_i_valid_111(DELAY,29943)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist815_sync_together4364_aunroll_x_in_i_valid_111_delay_0 <= $unsigned(redist814_sync_together4364_aunroll_x_in_i_valid_109_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist815_sync_together4364_aunroll_x_in_i_valid_111_q <= '0;
        end
        else
        begin
            redist815_sync_together4364_aunroll_x_in_i_valid_111_q <= redist815_sync_together4364_aunroll_x_in_i_valid_111_delay_0;
        end
    end

    // redist816_sync_together4364_aunroll_x_in_i_valid_113(DELAY,29944)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist816_sync_together4364_aunroll_x_in_i_valid_113_delay_0 <= $unsigned(redist815_sync_together4364_aunroll_x_in_i_valid_111_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist816_sync_together4364_aunroll_x_in_i_valid_113_q <= '0;
        end
        else
        begin
            redist816_sync_together4364_aunroll_x_in_i_valid_113_q <= redist816_sync_together4364_aunroll_x_in_i_valid_113_delay_0;
        end
    end

    // redist817_sync_together4364_aunroll_x_in_i_valid_115(DELAY,29945)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist817_sync_together4364_aunroll_x_in_i_valid_115_delay_0 <= $unsigned(redist816_sync_together4364_aunroll_x_in_i_valid_113_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist817_sync_together4364_aunroll_x_in_i_valid_115_q <= '0;
        end
        else
        begin
            redist817_sync_together4364_aunroll_x_in_i_valid_115_q <= redist817_sync_together4364_aunroll_x_in_i_valid_115_delay_0;
        end
    end

    // redist818_sync_together4364_aunroll_x_in_i_valid_117(DELAY,29946)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist818_sync_together4364_aunroll_x_in_i_valid_117_delay_0 <= $unsigned(redist817_sync_together4364_aunroll_x_in_i_valid_115_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist818_sync_together4364_aunroll_x_in_i_valid_117_q <= '0;
        end
        else
        begin
            redist818_sync_together4364_aunroll_x_in_i_valid_117_q <= redist818_sync_together4364_aunroll_x_in_i_valid_117_delay_0;
        end
    end

    // redist819_sync_together4364_aunroll_x_in_i_valid_119(DELAY,29947)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist819_sync_together4364_aunroll_x_in_i_valid_119_delay_0 <= $unsigned(redist818_sync_together4364_aunroll_x_in_i_valid_117_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist819_sync_together4364_aunroll_x_in_i_valid_119_q <= '0;
        end
        else
        begin
            redist819_sync_together4364_aunroll_x_in_i_valid_119_q <= redist819_sync_together4364_aunroll_x_in_i_valid_119_delay_0;
        end
    end

    // redist820_sync_together4364_aunroll_x_in_i_valid_121(DELAY,29948)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist820_sync_together4364_aunroll_x_in_i_valid_121_delay_0 <= $unsigned(redist819_sync_together4364_aunroll_x_in_i_valid_119_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist820_sync_together4364_aunroll_x_in_i_valid_121_q <= '0;
        end
        else
        begin
            redist820_sync_together4364_aunroll_x_in_i_valid_121_q <= redist820_sync_together4364_aunroll_x_in_i_valid_121_delay_0;
        end
    end

    // redist821_sync_together4364_aunroll_x_in_i_valid_123(DELAY,29949)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist821_sync_together4364_aunroll_x_in_i_valid_123_delay_0 <= $unsigned(redist820_sync_together4364_aunroll_x_in_i_valid_121_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist821_sync_together4364_aunroll_x_in_i_valid_123_q <= '0;
        end
        else
        begin
            redist821_sync_together4364_aunroll_x_in_i_valid_123_q <= redist821_sync_together4364_aunroll_x_in_i_valid_123_delay_0;
        end
    end

    // redist822_sync_together4364_aunroll_x_in_i_valid_125(DELAY,29950)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist822_sync_together4364_aunroll_x_in_i_valid_125_delay_0 <= $unsigned(redist821_sync_together4364_aunroll_x_in_i_valid_123_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist822_sync_together4364_aunroll_x_in_i_valid_125_q <= '0;
        end
        else
        begin
            redist822_sync_together4364_aunroll_x_in_i_valid_125_q <= redist822_sync_together4364_aunroll_x_in_i_valid_125_delay_0;
        end
    end

    // redist823_sync_together4364_aunroll_x_in_i_valid_127(DELAY,29951)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist823_sync_together4364_aunroll_x_in_i_valid_127_delay_0 <= $unsigned(redist822_sync_together4364_aunroll_x_in_i_valid_125_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist823_sync_together4364_aunroll_x_in_i_valid_127_q <= '0;
        end
        else
        begin
            redist823_sync_together4364_aunroll_x_in_i_valid_127_q <= redist823_sync_together4364_aunroll_x_in_i_valid_127_delay_0;
        end
    end

    // redist824_sync_together4364_aunroll_x_in_i_valid_129(DELAY,29952)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist824_sync_together4364_aunroll_x_in_i_valid_129_delay_0 <= $unsigned(redist823_sync_together4364_aunroll_x_in_i_valid_127_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist824_sync_together4364_aunroll_x_in_i_valid_129_q <= '0;
        end
        else
        begin
            redist824_sync_together4364_aunroll_x_in_i_valid_129_q <= redist824_sync_together4364_aunroll_x_in_i_valid_129_delay_0;
        end
    end

    // redist825_sync_together4364_aunroll_x_in_i_valid_131(DELAY,29953)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist825_sync_together4364_aunroll_x_in_i_valid_131_delay_0 <= $unsigned(redist824_sync_together4364_aunroll_x_in_i_valid_129_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist825_sync_together4364_aunroll_x_in_i_valid_131_q <= '0;
        end
        else
        begin
            redist825_sync_together4364_aunroll_x_in_i_valid_131_q <= redist825_sync_together4364_aunroll_x_in_i_valid_131_delay_0;
        end
    end

    // redist826_sync_together4364_aunroll_x_in_i_valid_133(DELAY,29954)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist826_sync_together4364_aunroll_x_in_i_valid_133_delay_0 <= $unsigned(redist825_sync_together4364_aunroll_x_in_i_valid_131_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist826_sync_together4364_aunroll_x_in_i_valid_133_q <= '0;
        end
        else
        begin
            redist826_sync_together4364_aunroll_x_in_i_valid_133_q <= redist826_sync_together4364_aunroll_x_in_i_valid_133_delay_0;
        end
    end

    // redist827_sync_together4364_aunroll_x_in_i_valid_135(DELAY,29955)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist827_sync_together4364_aunroll_x_in_i_valid_135_delay_0 <= $unsigned(redist826_sync_together4364_aunroll_x_in_i_valid_133_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist827_sync_together4364_aunroll_x_in_i_valid_135_q <= '0;
        end
        else
        begin
            redist827_sync_together4364_aunroll_x_in_i_valid_135_q <= redist827_sync_together4364_aunroll_x_in_i_valid_135_delay_0;
        end
    end

    // redist828_sync_together4364_aunroll_x_in_i_valid_137(DELAY,29956)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist828_sync_together4364_aunroll_x_in_i_valid_137_delay_0 <= $unsigned(redist827_sync_together4364_aunroll_x_in_i_valid_135_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist828_sync_together4364_aunroll_x_in_i_valid_137_q <= '0;
        end
        else
        begin
            redist828_sync_together4364_aunroll_x_in_i_valid_137_q <= redist828_sync_together4364_aunroll_x_in_i_valid_137_delay_0;
        end
    end

    // redist829_sync_together4364_aunroll_x_in_i_valid_139(DELAY,29957)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist829_sync_together4364_aunroll_x_in_i_valid_139_delay_0 <= $unsigned(redist828_sync_together4364_aunroll_x_in_i_valid_137_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist829_sync_together4364_aunroll_x_in_i_valid_139_q <= '0;
        end
        else
        begin
            redist829_sync_together4364_aunroll_x_in_i_valid_139_q <= redist829_sync_together4364_aunroll_x_in_i_valid_139_delay_0;
        end
    end

    // redist830_sync_together4364_aunroll_x_in_i_valid_141(DELAY,29958)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist830_sync_together4364_aunroll_x_in_i_valid_141_delay_0 <= $unsigned(redist829_sync_together4364_aunroll_x_in_i_valid_139_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist830_sync_together4364_aunroll_x_in_i_valid_141_q <= '0;
        end
        else
        begin
            redist830_sync_together4364_aunroll_x_in_i_valid_141_q <= redist830_sync_together4364_aunroll_x_in_i_valid_141_delay_0;
        end
    end

    // redist831_sync_together4364_aunroll_x_in_i_valid_143(DELAY,29959)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist831_sync_together4364_aunroll_x_in_i_valid_143_delay_0 <= $unsigned(redist830_sync_together4364_aunroll_x_in_i_valid_141_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist831_sync_together4364_aunroll_x_in_i_valid_143_q <= '0;
        end
        else
        begin
            redist831_sync_together4364_aunroll_x_in_i_valid_143_q <= redist831_sync_together4364_aunroll_x_in_i_valid_143_delay_0;
        end
    end

    // redist832_sync_together4364_aunroll_x_in_i_valid_145(DELAY,29960)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist832_sync_together4364_aunroll_x_in_i_valid_145_delay_0 <= $unsigned(redist831_sync_together4364_aunroll_x_in_i_valid_143_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist832_sync_together4364_aunroll_x_in_i_valid_145_q <= '0;
        end
        else
        begin
            redist832_sync_together4364_aunroll_x_in_i_valid_145_q <= redist832_sync_together4364_aunroll_x_in_i_valid_145_delay_0;
        end
    end

    // redist833_sync_together4364_aunroll_x_in_i_valid_147(DELAY,29961)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist833_sync_together4364_aunroll_x_in_i_valid_147_delay_0 <= $unsigned(redist832_sync_together4364_aunroll_x_in_i_valid_145_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist833_sync_together4364_aunroll_x_in_i_valid_147_q <= '0;
        end
        else
        begin
            redist833_sync_together4364_aunroll_x_in_i_valid_147_q <= redist833_sync_together4364_aunroll_x_in_i_valid_147_delay_0;
        end
    end

    // redist834_sync_together4364_aunroll_x_in_i_valid_149(DELAY,29962)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist834_sync_together4364_aunroll_x_in_i_valid_149_delay_0 <= $unsigned(redist833_sync_together4364_aunroll_x_in_i_valid_147_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist834_sync_together4364_aunroll_x_in_i_valid_149_q <= '0;
        end
        else
        begin
            redist834_sync_together4364_aunroll_x_in_i_valid_149_q <= redist834_sync_together4364_aunroll_x_in_i_valid_149_delay_0;
        end
    end

    // redist835_sync_together4364_aunroll_x_in_i_valid_151(DELAY,29963)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist835_sync_together4364_aunroll_x_in_i_valid_151_delay_0 <= $unsigned(redist834_sync_together4364_aunroll_x_in_i_valid_149_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist835_sync_together4364_aunroll_x_in_i_valid_151_q <= '0;
        end
        else
        begin
            redist835_sync_together4364_aunroll_x_in_i_valid_151_q <= redist835_sync_together4364_aunroll_x_in_i_valid_151_delay_0;
        end
    end

    // redist836_sync_together4364_aunroll_x_in_i_valid_153(DELAY,29964)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist836_sync_together4364_aunroll_x_in_i_valid_153_delay_0 <= $unsigned(redist835_sync_together4364_aunroll_x_in_i_valid_151_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist836_sync_together4364_aunroll_x_in_i_valid_153_q <= '0;
        end
        else
        begin
            redist836_sync_together4364_aunroll_x_in_i_valid_153_q <= redist836_sync_together4364_aunroll_x_in_i_valid_153_delay_0;
        end
    end

    // redist837_sync_together4364_aunroll_x_in_i_valid_155(DELAY,29965)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist837_sync_together4364_aunroll_x_in_i_valid_155_delay_0 <= $unsigned(redist836_sync_together4364_aunroll_x_in_i_valid_153_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist837_sync_together4364_aunroll_x_in_i_valid_155_q <= '0;
        end
        else
        begin
            redist837_sync_together4364_aunroll_x_in_i_valid_155_q <= redist837_sync_together4364_aunroll_x_in_i_valid_155_delay_0;
        end
    end

    // redist838_sync_together4364_aunroll_x_in_i_valid_157(DELAY,29966)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist838_sync_together4364_aunroll_x_in_i_valid_157_delay_0 <= $unsigned(redist837_sync_together4364_aunroll_x_in_i_valid_155_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist838_sync_together4364_aunroll_x_in_i_valid_157_q <= '0;
        end
        else
        begin
            redist838_sync_together4364_aunroll_x_in_i_valid_157_q <= redist838_sync_together4364_aunroll_x_in_i_valid_157_delay_0;
        end
    end

    // redist839_sync_together4364_aunroll_x_in_i_valid_159(DELAY,29967)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist839_sync_together4364_aunroll_x_in_i_valid_159_delay_0 <= $unsigned(redist838_sync_together4364_aunroll_x_in_i_valid_157_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist839_sync_together4364_aunroll_x_in_i_valid_159_q <= '0;
        end
        else
        begin
            redist839_sync_together4364_aunroll_x_in_i_valid_159_q <= redist839_sync_together4364_aunroll_x_in_i_valid_159_delay_0;
        end
    end

    // redist840_sync_together4364_aunroll_x_in_i_valid_161(DELAY,29968)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist840_sync_together4364_aunroll_x_in_i_valid_161_delay_0 <= $unsigned(redist839_sync_together4364_aunroll_x_in_i_valid_159_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist840_sync_together4364_aunroll_x_in_i_valid_161_q <= '0;
        end
        else
        begin
            redist840_sync_together4364_aunroll_x_in_i_valid_161_q <= redist840_sync_together4364_aunroll_x_in_i_valid_161_delay_0;
        end
    end

    // redist841_sync_together4364_aunroll_x_in_i_valid_163(DELAY,29969)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist841_sync_together4364_aunroll_x_in_i_valid_163_delay_0 <= $unsigned(redist840_sync_together4364_aunroll_x_in_i_valid_161_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist841_sync_together4364_aunroll_x_in_i_valid_163_q <= '0;
        end
        else
        begin
            redist841_sync_together4364_aunroll_x_in_i_valid_163_q <= redist841_sync_together4364_aunroll_x_in_i_valid_163_delay_0;
        end
    end

    // redist842_sync_together4364_aunroll_x_in_i_valid_165(DELAY,29970)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist842_sync_together4364_aunroll_x_in_i_valid_165_delay_0 <= $unsigned(redist841_sync_together4364_aunroll_x_in_i_valid_163_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist842_sync_together4364_aunroll_x_in_i_valid_165_q <= '0;
        end
        else
        begin
            redist842_sync_together4364_aunroll_x_in_i_valid_165_q <= redist842_sync_together4364_aunroll_x_in_i_valid_165_delay_0;
        end
    end

    // redist843_sync_together4364_aunroll_x_in_i_valid_167(DELAY,29971)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist843_sync_together4364_aunroll_x_in_i_valid_167_delay_0 <= $unsigned(redist842_sync_together4364_aunroll_x_in_i_valid_165_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist843_sync_together4364_aunroll_x_in_i_valid_167_q <= '0;
        end
        else
        begin
            redist843_sync_together4364_aunroll_x_in_i_valid_167_q <= redist843_sync_together4364_aunroll_x_in_i_valid_167_delay_0;
        end
    end

    // redist844_sync_together4364_aunroll_x_in_i_valid_169(DELAY,29972)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist844_sync_together4364_aunroll_x_in_i_valid_169_delay_0 <= $unsigned(redist843_sync_together4364_aunroll_x_in_i_valid_167_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist844_sync_together4364_aunroll_x_in_i_valid_169_q <= '0;
        end
        else
        begin
            redist844_sync_together4364_aunroll_x_in_i_valid_169_q <= redist844_sync_together4364_aunroll_x_in_i_valid_169_delay_0;
        end
    end

    // redist845_sync_together4364_aunroll_x_in_i_valid_171(DELAY,29973)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist845_sync_together4364_aunroll_x_in_i_valid_171_delay_0 <= $unsigned(redist844_sync_together4364_aunroll_x_in_i_valid_169_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist845_sync_together4364_aunroll_x_in_i_valid_171_q <= '0;
        end
        else
        begin
            redist845_sync_together4364_aunroll_x_in_i_valid_171_q <= redist845_sync_together4364_aunroll_x_in_i_valid_171_delay_0;
        end
    end

    // redist846_sync_together4364_aunroll_x_in_i_valid_173(DELAY,29974)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist846_sync_together4364_aunroll_x_in_i_valid_173_delay_0 <= $unsigned(redist845_sync_together4364_aunroll_x_in_i_valid_171_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist846_sync_together4364_aunroll_x_in_i_valid_173_q <= '0;
        end
        else
        begin
            redist846_sync_together4364_aunroll_x_in_i_valid_173_q <= redist846_sync_together4364_aunroll_x_in_i_valid_173_delay_0;
        end
    end

    // redist847_sync_together4364_aunroll_x_in_i_valid_175(DELAY,29975)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist847_sync_together4364_aunroll_x_in_i_valid_175_delay_0 <= $unsigned(redist846_sync_together4364_aunroll_x_in_i_valid_173_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist847_sync_together4364_aunroll_x_in_i_valid_175_q <= '0;
        end
        else
        begin
            redist847_sync_together4364_aunroll_x_in_i_valid_175_q <= redist847_sync_together4364_aunroll_x_in_i_valid_175_delay_0;
        end
    end

    // redist848_sync_together4364_aunroll_x_in_i_valid_177(DELAY,29976)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist848_sync_together4364_aunroll_x_in_i_valid_177_delay_0 <= $unsigned(redist847_sync_together4364_aunroll_x_in_i_valid_175_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist848_sync_together4364_aunroll_x_in_i_valid_177_q <= '0;
        end
        else
        begin
            redist848_sync_together4364_aunroll_x_in_i_valid_177_q <= redist848_sync_together4364_aunroll_x_in_i_valid_177_delay_0;
        end
    end

    // redist849_sync_together4364_aunroll_x_in_i_valid_179(DELAY,29977)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist849_sync_together4364_aunroll_x_in_i_valid_179_delay_0 <= $unsigned(redist848_sync_together4364_aunroll_x_in_i_valid_177_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist849_sync_together4364_aunroll_x_in_i_valid_179_q <= '0;
        end
        else
        begin
            redist849_sync_together4364_aunroll_x_in_i_valid_179_q <= redist849_sync_together4364_aunroll_x_in_i_valid_179_delay_0;
        end
    end

    // redist850_sync_together4364_aunroll_x_in_i_valid_181(DELAY,29978)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist850_sync_together4364_aunroll_x_in_i_valid_181_delay_0 <= $unsigned(redist849_sync_together4364_aunroll_x_in_i_valid_179_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist850_sync_together4364_aunroll_x_in_i_valid_181_q <= '0;
        end
        else
        begin
            redist850_sync_together4364_aunroll_x_in_i_valid_181_q <= redist850_sync_together4364_aunroll_x_in_i_valid_181_delay_0;
        end
    end

    // redist851_sync_together4364_aunroll_x_in_i_valid_183(DELAY,29979)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist851_sync_together4364_aunroll_x_in_i_valid_183_delay_0 <= $unsigned(redist850_sync_together4364_aunroll_x_in_i_valid_181_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist851_sync_together4364_aunroll_x_in_i_valid_183_q <= '0;
        end
        else
        begin
            redist851_sync_together4364_aunroll_x_in_i_valid_183_q <= redist851_sync_together4364_aunroll_x_in_i_valid_183_delay_0;
        end
    end

    // redist852_sync_together4364_aunroll_x_in_i_valid_185(DELAY,29980)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist852_sync_together4364_aunroll_x_in_i_valid_185_delay_0 <= $unsigned(redist851_sync_together4364_aunroll_x_in_i_valid_183_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist852_sync_together4364_aunroll_x_in_i_valid_185_q <= '0;
        end
        else
        begin
            redist852_sync_together4364_aunroll_x_in_i_valid_185_q <= redist852_sync_together4364_aunroll_x_in_i_valid_185_delay_0;
        end
    end

    // redist853_sync_together4364_aunroll_x_in_i_valid_187(DELAY,29981)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist853_sync_together4364_aunroll_x_in_i_valid_187_delay_0 <= $unsigned(redist852_sync_together4364_aunroll_x_in_i_valid_185_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist853_sync_together4364_aunroll_x_in_i_valid_187_q <= '0;
        end
        else
        begin
            redist853_sync_together4364_aunroll_x_in_i_valid_187_q <= redist853_sync_together4364_aunroll_x_in_i_valid_187_delay_0;
        end
    end

    // redist854_sync_together4364_aunroll_x_in_i_valid_189(DELAY,29982)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist854_sync_together4364_aunroll_x_in_i_valid_189_delay_0 <= $unsigned(redist853_sync_together4364_aunroll_x_in_i_valid_187_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist854_sync_together4364_aunroll_x_in_i_valid_189_q <= '0;
        end
        else
        begin
            redist854_sync_together4364_aunroll_x_in_i_valid_189_q <= redist854_sync_together4364_aunroll_x_in_i_valid_189_delay_0;
        end
    end

    // redist855_sync_together4364_aunroll_x_in_i_valid_191(DELAY,29983)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist855_sync_together4364_aunroll_x_in_i_valid_191_delay_0 <= $unsigned(redist854_sync_together4364_aunroll_x_in_i_valid_189_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist855_sync_together4364_aunroll_x_in_i_valid_191_q <= '0;
        end
        else
        begin
            redist855_sync_together4364_aunroll_x_in_i_valid_191_q <= redist855_sync_together4364_aunroll_x_in_i_valid_191_delay_0;
        end
    end

    // redist856_sync_together4364_aunroll_x_in_i_valid_193(DELAY,29984)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist856_sync_together4364_aunroll_x_in_i_valid_193_delay_0 <= $unsigned(redist855_sync_together4364_aunroll_x_in_i_valid_191_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist856_sync_together4364_aunroll_x_in_i_valid_193_q <= '0;
        end
        else
        begin
            redist856_sync_together4364_aunroll_x_in_i_valid_193_q <= redist856_sync_together4364_aunroll_x_in_i_valid_193_delay_0;
        end
    end

    // redist857_sync_together4364_aunroll_x_in_i_valid_195(DELAY,29985)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist857_sync_together4364_aunroll_x_in_i_valid_195_delay_0 <= $unsigned(redist856_sync_together4364_aunroll_x_in_i_valid_193_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist857_sync_together4364_aunroll_x_in_i_valid_195_q <= '0;
        end
        else
        begin
            redist857_sync_together4364_aunroll_x_in_i_valid_195_q <= redist857_sync_together4364_aunroll_x_in_i_valid_195_delay_0;
        end
    end

    // redist858_sync_together4364_aunroll_x_in_i_valid_197(DELAY,29986)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist858_sync_together4364_aunroll_x_in_i_valid_197_delay_0 <= $unsigned(redist857_sync_together4364_aunroll_x_in_i_valid_195_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist858_sync_together4364_aunroll_x_in_i_valid_197_q <= '0;
        end
        else
        begin
            redist858_sync_together4364_aunroll_x_in_i_valid_197_q <= redist858_sync_together4364_aunroll_x_in_i_valid_197_delay_0;
        end
    end

    // redist859_sync_together4364_aunroll_x_in_i_valid_199(DELAY,29987)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist859_sync_together4364_aunroll_x_in_i_valid_199_delay_0 <= $unsigned(redist858_sync_together4364_aunroll_x_in_i_valid_197_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist859_sync_together4364_aunroll_x_in_i_valid_199_q <= '0;
        end
        else
        begin
            redist859_sync_together4364_aunroll_x_in_i_valid_199_q <= redist859_sync_together4364_aunroll_x_in_i_valid_199_delay_0;
        end
    end

    // redist860_sync_together4364_aunroll_x_in_i_valid_201(DELAY,29988)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist860_sync_together4364_aunroll_x_in_i_valid_201_delay_0 <= $unsigned(redist859_sync_together4364_aunroll_x_in_i_valid_199_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist860_sync_together4364_aunroll_x_in_i_valid_201_q <= '0;
        end
        else
        begin
            redist860_sync_together4364_aunroll_x_in_i_valid_201_q <= redist860_sync_together4364_aunroll_x_in_i_valid_201_delay_0;
        end
    end

    // redist861_sync_together4364_aunroll_x_in_i_valid_203(DELAY,29989)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist861_sync_together4364_aunroll_x_in_i_valid_203_delay_0 <= $unsigned(redist860_sync_together4364_aunroll_x_in_i_valid_201_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist861_sync_together4364_aunroll_x_in_i_valid_203_q <= '0;
        end
        else
        begin
            redist861_sync_together4364_aunroll_x_in_i_valid_203_q <= redist861_sync_together4364_aunroll_x_in_i_valid_203_delay_0;
        end
    end

    // redist862_sync_together4364_aunroll_x_in_i_valid_205(DELAY,29990)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist862_sync_together4364_aunroll_x_in_i_valid_205_delay_0 <= $unsigned(redist861_sync_together4364_aunroll_x_in_i_valid_203_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist862_sync_together4364_aunroll_x_in_i_valid_205_q <= '0;
        end
        else
        begin
            redist862_sync_together4364_aunroll_x_in_i_valid_205_q <= redist862_sync_together4364_aunroll_x_in_i_valid_205_delay_0;
        end
    end

    // redist863_sync_together4364_aunroll_x_in_i_valid_207(DELAY,29991)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist863_sync_together4364_aunroll_x_in_i_valid_207_delay_0 <= $unsigned(redist862_sync_together4364_aunroll_x_in_i_valid_205_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist863_sync_together4364_aunroll_x_in_i_valid_207_q <= '0;
        end
        else
        begin
            redist863_sync_together4364_aunroll_x_in_i_valid_207_q <= redist863_sync_together4364_aunroll_x_in_i_valid_207_delay_0;
        end
    end

    // redist864_sync_together4364_aunroll_x_in_i_valid_209(DELAY,29992)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist864_sync_together4364_aunroll_x_in_i_valid_209_delay_0 <= $unsigned(redist863_sync_together4364_aunroll_x_in_i_valid_207_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist864_sync_together4364_aunroll_x_in_i_valid_209_q <= '0;
        end
        else
        begin
            redist864_sync_together4364_aunroll_x_in_i_valid_209_q <= redist864_sync_together4364_aunroll_x_in_i_valid_209_delay_0;
        end
    end

    // redist865_sync_together4364_aunroll_x_in_i_valid_211(DELAY,29993)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist865_sync_together4364_aunroll_x_in_i_valid_211_delay_0 <= $unsigned(redist864_sync_together4364_aunroll_x_in_i_valid_209_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist865_sync_together4364_aunroll_x_in_i_valid_211_q <= '0;
        end
        else
        begin
            redist865_sync_together4364_aunroll_x_in_i_valid_211_q <= redist865_sync_together4364_aunroll_x_in_i_valid_211_delay_0;
        end
    end

    // redist866_sync_together4364_aunroll_x_in_i_valid_213(DELAY,29994)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist866_sync_together4364_aunroll_x_in_i_valid_213_delay_0 <= $unsigned(redist865_sync_together4364_aunroll_x_in_i_valid_211_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist866_sync_together4364_aunroll_x_in_i_valid_213_q <= '0;
        end
        else
        begin
            redist866_sync_together4364_aunroll_x_in_i_valid_213_q <= redist866_sync_together4364_aunroll_x_in_i_valid_213_delay_0;
        end
    end

    // redist867_sync_together4364_aunroll_x_in_i_valid_215(DELAY,29995)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist867_sync_together4364_aunroll_x_in_i_valid_215_delay_0 <= $unsigned(redist866_sync_together4364_aunroll_x_in_i_valid_213_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist867_sync_together4364_aunroll_x_in_i_valid_215_q <= '0;
        end
        else
        begin
            redist867_sync_together4364_aunroll_x_in_i_valid_215_q <= redist867_sync_together4364_aunroll_x_in_i_valid_215_delay_0;
        end
    end

    // redist868_sync_together4364_aunroll_x_in_i_valid_217(DELAY,29996)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist868_sync_together4364_aunroll_x_in_i_valid_217_delay_0 <= $unsigned(redist867_sync_together4364_aunroll_x_in_i_valid_215_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist868_sync_together4364_aunroll_x_in_i_valid_217_q <= '0;
        end
        else
        begin
            redist868_sync_together4364_aunroll_x_in_i_valid_217_q <= redist868_sync_together4364_aunroll_x_in_i_valid_217_delay_0;
        end
    end

    // redist869_sync_together4364_aunroll_x_in_i_valid_219(DELAY,29997)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist869_sync_together4364_aunroll_x_in_i_valid_219_delay_0 <= $unsigned(redist868_sync_together4364_aunroll_x_in_i_valid_217_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist869_sync_together4364_aunroll_x_in_i_valid_219_q <= '0;
        end
        else
        begin
            redist869_sync_together4364_aunroll_x_in_i_valid_219_q <= redist869_sync_together4364_aunroll_x_in_i_valid_219_delay_0;
        end
    end

    // redist870_sync_together4364_aunroll_x_in_i_valid_221(DELAY,29998)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist870_sync_together4364_aunroll_x_in_i_valid_221_delay_0 <= $unsigned(redist869_sync_together4364_aunroll_x_in_i_valid_219_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist870_sync_together4364_aunroll_x_in_i_valid_221_q <= '0;
        end
        else
        begin
            redist870_sync_together4364_aunroll_x_in_i_valid_221_q <= redist870_sync_together4364_aunroll_x_in_i_valid_221_delay_0;
        end
    end

    // redist871_sync_together4364_aunroll_x_in_i_valid_223(DELAY,29999)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist871_sync_together4364_aunroll_x_in_i_valid_223_delay_0 <= $unsigned(redist870_sync_together4364_aunroll_x_in_i_valid_221_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist871_sync_together4364_aunroll_x_in_i_valid_223_q <= '0;
        end
        else
        begin
            redist871_sync_together4364_aunroll_x_in_i_valid_223_q <= redist871_sync_together4364_aunroll_x_in_i_valid_223_delay_0;
        end
    end

    // redist872_sync_together4364_aunroll_x_in_i_valid_225(DELAY,30000)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist872_sync_together4364_aunroll_x_in_i_valid_225_delay_0 <= $unsigned(redist871_sync_together4364_aunroll_x_in_i_valid_223_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist872_sync_together4364_aunroll_x_in_i_valid_225_q <= '0;
        end
        else
        begin
            redist872_sync_together4364_aunroll_x_in_i_valid_225_q <= redist872_sync_together4364_aunroll_x_in_i_valid_225_delay_0;
        end
    end

    // redist873_sync_together4364_aunroll_x_in_i_valid_227(DELAY,30001)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist873_sync_together4364_aunroll_x_in_i_valid_227_delay_0 <= $unsigned(redist872_sync_together4364_aunroll_x_in_i_valid_225_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist873_sync_together4364_aunroll_x_in_i_valid_227_q <= '0;
        end
        else
        begin
            redist873_sync_together4364_aunroll_x_in_i_valid_227_q <= redist873_sync_together4364_aunroll_x_in_i_valid_227_delay_0;
        end
    end

    // redist874_sync_together4364_aunroll_x_in_i_valid_229(DELAY,30002)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist874_sync_together4364_aunroll_x_in_i_valid_229_delay_0 <= $unsigned(redist873_sync_together4364_aunroll_x_in_i_valid_227_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist874_sync_together4364_aunroll_x_in_i_valid_229_q <= '0;
        end
        else
        begin
            redist874_sync_together4364_aunroll_x_in_i_valid_229_q <= redist874_sync_together4364_aunroll_x_in_i_valid_229_delay_0;
        end
    end

    // redist875_sync_together4364_aunroll_x_in_i_valid_231(DELAY,30003)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist875_sync_together4364_aunroll_x_in_i_valid_231_delay_0 <= $unsigned(redist874_sync_together4364_aunroll_x_in_i_valid_229_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist875_sync_together4364_aunroll_x_in_i_valid_231_q <= '0;
        end
        else
        begin
            redist875_sync_together4364_aunroll_x_in_i_valid_231_q <= redist875_sync_together4364_aunroll_x_in_i_valid_231_delay_0;
        end
    end

    // redist876_sync_together4364_aunroll_x_in_i_valid_233(DELAY,30004)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist876_sync_together4364_aunroll_x_in_i_valid_233_delay_0 <= $unsigned(redist875_sync_together4364_aunroll_x_in_i_valid_231_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist876_sync_together4364_aunroll_x_in_i_valid_233_q <= '0;
        end
        else
        begin
            redist876_sync_together4364_aunroll_x_in_i_valid_233_q <= redist876_sync_together4364_aunroll_x_in_i_valid_233_delay_0;
        end
    end

    // redist877_sync_together4364_aunroll_x_in_i_valid_235(DELAY,30005)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist877_sync_together4364_aunroll_x_in_i_valid_235_delay_0 <= $unsigned(redist876_sync_together4364_aunroll_x_in_i_valid_233_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist877_sync_together4364_aunroll_x_in_i_valid_235_q <= '0;
        end
        else
        begin
            redist877_sync_together4364_aunroll_x_in_i_valid_235_q <= redist877_sync_together4364_aunroll_x_in_i_valid_235_delay_0;
        end
    end

    // redist878_sync_together4364_aunroll_x_in_i_valid_237(DELAY,30006)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist878_sync_together4364_aunroll_x_in_i_valid_237_delay_0 <= $unsigned(redist877_sync_together4364_aunroll_x_in_i_valid_235_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist878_sync_together4364_aunroll_x_in_i_valid_237_q <= '0;
        end
        else
        begin
            redist878_sync_together4364_aunroll_x_in_i_valid_237_q <= redist878_sync_together4364_aunroll_x_in_i_valid_237_delay_0;
        end
    end

    // redist879_sync_together4364_aunroll_x_in_i_valid_239(DELAY,30007)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist879_sync_together4364_aunroll_x_in_i_valid_239_delay_0 <= $unsigned(redist878_sync_together4364_aunroll_x_in_i_valid_237_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist879_sync_together4364_aunroll_x_in_i_valid_239_q <= '0;
        end
        else
        begin
            redist879_sync_together4364_aunroll_x_in_i_valid_239_q <= redist879_sync_together4364_aunroll_x_in_i_valid_239_delay_0;
        end
    end

    // redist880_sync_together4364_aunroll_x_in_i_valid_241(DELAY,30008)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist880_sync_together4364_aunroll_x_in_i_valid_241_delay_0 <= $unsigned(redist879_sync_together4364_aunroll_x_in_i_valid_239_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist880_sync_together4364_aunroll_x_in_i_valid_241_q <= '0;
        end
        else
        begin
            redist880_sync_together4364_aunroll_x_in_i_valid_241_q <= redist880_sync_together4364_aunroll_x_in_i_valid_241_delay_0;
        end
    end

    // redist881_sync_together4364_aunroll_x_in_i_valid_243(DELAY,30009)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist881_sync_together4364_aunroll_x_in_i_valid_243_delay_0 <= $unsigned(redist880_sync_together4364_aunroll_x_in_i_valid_241_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist881_sync_together4364_aunroll_x_in_i_valid_243_q <= '0;
        end
        else
        begin
            redist881_sync_together4364_aunroll_x_in_i_valid_243_q <= redist881_sync_together4364_aunroll_x_in_i_valid_243_delay_0;
        end
    end

    // redist882_sync_together4364_aunroll_x_in_i_valid_245(DELAY,30010)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist882_sync_together4364_aunroll_x_in_i_valid_245_delay_0 <= $unsigned(redist881_sync_together4364_aunroll_x_in_i_valid_243_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist882_sync_together4364_aunroll_x_in_i_valid_245_q <= '0;
        end
        else
        begin
            redist882_sync_together4364_aunroll_x_in_i_valid_245_q <= redist882_sync_together4364_aunroll_x_in_i_valid_245_delay_0;
        end
    end

    // redist883_sync_together4364_aunroll_x_in_i_valid_247(DELAY,30011)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist883_sync_together4364_aunroll_x_in_i_valid_247_delay_0 <= $unsigned(redist882_sync_together4364_aunroll_x_in_i_valid_245_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist883_sync_together4364_aunroll_x_in_i_valid_247_q <= '0;
        end
        else
        begin
            redist883_sync_together4364_aunroll_x_in_i_valid_247_q <= redist883_sync_together4364_aunroll_x_in_i_valid_247_delay_0;
        end
    end

    // redist884_sync_together4364_aunroll_x_in_i_valid_249(DELAY,30012)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist884_sync_together4364_aunroll_x_in_i_valid_249_delay_0 <= $unsigned(redist883_sync_together4364_aunroll_x_in_i_valid_247_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist884_sync_together4364_aunroll_x_in_i_valid_249_q <= '0;
        end
        else
        begin
            redist884_sync_together4364_aunroll_x_in_i_valid_249_q <= redist884_sync_together4364_aunroll_x_in_i_valid_249_delay_0;
        end
    end

    // redist885_sync_together4364_aunroll_x_in_i_valid_251(DELAY,30013)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist885_sync_together4364_aunroll_x_in_i_valid_251_delay_0 <= $unsigned(redist884_sync_together4364_aunroll_x_in_i_valid_249_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist885_sync_together4364_aunroll_x_in_i_valid_251_q <= '0;
        end
        else
        begin
            redist885_sync_together4364_aunroll_x_in_i_valid_251_q <= redist885_sync_together4364_aunroll_x_in_i_valid_251_delay_0;
        end
    end

    // redist886_sync_together4364_aunroll_x_in_i_valid_253(DELAY,30014)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist886_sync_together4364_aunroll_x_in_i_valid_253_delay_0 <= $unsigned(redist885_sync_together4364_aunroll_x_in_i_valid_251_q);
        end
    end
    always @ (posedge clock)
    begin
        if (!resetn)
        begin
            redist886_sync_together4364_aunroll_x_in_i_valid_253_q <= '0;
        end
        else
        begin
            redist886_sync_together4364_aunroll_x_in_i_valid_253_q <= redist886_sync_together4364_aunroll_x_in_i_valid_253_delay_0;
        end
    end

    // valid_fanout_reg0(REG,13295)@321 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg0_q <= $unsigned(redist886_sync_together4364_aunroll_x_in_i_valid_253_q);
        end
    end

    // redist1_valid_fanout_reg0_q_7(DELAY,29129)
    dspba_delay_ver #( .width(1), .depth(7), .reset_kind("SYNC"), .phase(254), .modulus(2), .reset_high(1'b0) )
    redist1_valid_fanout_reg0_q_7 ( .xin(valid_fanout_reg0_q), .xout(redist1_valid_fanout_reg0_q_7_q), .clk(clock), .aclr(resetn), .ena(1'b1) );

    // i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28(CONSTANT,7421)
    assign i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q = $unsigned(13'b0000000000000);

    // rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x(CONSTANT,15860)
    assign rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = $unsigned(8'b00000000);

    // rightShiftStage2Idx1Rng8_uid23752_dupName_509_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23751)@328
    assign rightShiftStage2Idx1Rng8_uid23752_dupName_509_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23754_dupName_509_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23753)@328
    assign rightShiftStage2Idx1_uid23754_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23752_dupName_509_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x(CONSTANT,15855)
    assign rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = $unsigned(4'b0000);

    // rightShiftStage1Idx1Rng4_uid23747_dupName_509_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23746)@328
    assign rightShiftStage1Idx1Rng4_uid23747_dupName_509_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23749_dupName_509_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23748)@328
    assign rightShiftStage1Idx1_uid23749_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23747_dupName_509_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23742_dupName_509_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23741)@328
    assign rightShiftStage0Idx1Rng1_uid23742_dupName_509_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q[33:1];

    // rightShiftStage0Idx1_uid23744_dupName_509_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23743)@328
    assign rightShiftStage0Idx1_uid23744_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23742_dupName_509_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26592_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(BITSELECT,26591)@327
    assign leftShiftStage2Idx1Rng8_uid26592_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in = leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26592_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26592_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26593_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(BITJOIN,26592)@327
    assign leftShiftStage2Idx1_uid26593_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26592_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26587_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(BITSELECT,26586)@327
    assign leftShiftStage1Idx1Rng4_uid26587_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in = leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26587_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26587_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26588_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(BITJOIN,26587)@327
    assign leftShiftStage1Idx1_uid26588_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26587_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26582_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(BITSELECT,26581)@327
    assign leftShiftStage0Idx1Rng1_uid26582_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26582_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26582_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26583_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(BITJOIN,26582)@327
    assign leftShiftStage0Idx1_uid26583_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26582_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23690_dupName_505_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23689)@326
    assign rightShiftStage2Idx1Rng8_uid23690_dupName_505_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23692_dupName_505_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23691)@326
    assign rightShiftStage2Idx1_uid23692_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23690_dupName_505_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23685_dupName_505_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23684)@326
    assign rightShiftStage1Idx1Rng4_uid23685_dupName_505_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23687_dupName_505_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23686)@326
    assign rightShiftStage1Idx1_uid23687_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23685_dupName_505_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23680_dupName_505_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23679)@326
    assign rightShiftStage0Idx1Rng1_uid23680_dupName_505_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q[33:1];

    // rightShiftStage0Idx1_uid23682_dupName_505_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23681)@326
    assign rightShiftStage0Idx1_uid23682_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23680_dupName_505_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26574_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(BITSELECT,26573)@325
    assign leftShiftStage2Idx1Rng8_uid26574_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in = leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26574_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26574_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26575_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(BITJOIN,26574)@325
    assign leftShiftStage2Idx1_uid26575_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26574_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26569_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(BITSELECT,26568)@325
    assign leftShiftStage1Idx1Rng4_uid26569_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in = leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26569_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26569_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26570_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(BITJOIN,26569)@325
    assign leftShiftStage1Idx1_uid26570_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26569_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26564_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(BITSELECT,26563)@325
    assign leftShiftStage0Idx1Rng1_uid26564_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26564_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26564_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26565_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(BITJOIN,26564)@325
    assign leftShiftStage0Idx1_uid26565_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26564_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23628_dupName_501_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23627)@324
    assign rightShiftStage2Idx1Rng8_uid23628_dupName_501_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23630_dupName_501_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23629)@324
    assign rightShiftStage2Idx1_uid23630_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23628_dupName_501_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23623_dupName_501_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23622)@324
    assign rightShiftStage1Idx1Rng4_uid23623_dupName_501_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23625_dupName_501_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23624)@324
    assign rightShiftStage1Idx1_uid23625_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23623_dupName_501_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23618_dupName_501_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23617)@324
    assign rightShiftStage0Idx1Rng1_uid23618_dupName_501_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q[33:1];

    // rightShiftStage0Idx1_uid23620_dupName_501_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23619)@324
    assign rightShiftStage0Idx1_uid23620_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23618_dupName_501_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26556_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(BITSELECT,26555)@323
    assign leftShiftStage2Idx1Rng8_uid26556_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in = leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26556_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26556_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26557_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(BITJOIN,26556)@323
    assign leftShiftStage2Idx1_uid26557_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26556_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26551_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(BITSELECT,26550)@323
    assign leftShiftStage1Idx1Rng4_uid26551_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in = leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26551_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26551_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26552_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(BITJOIN,26551)@323
    assign leftShiftStage1Idx1_uid26552_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26551_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26546_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(BITSELECT,26545)@323
    assign leftShiftStage0Idx1Rng1_uid26546_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26546_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26546_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26547_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(BITJOIN,26546)@323
    assign leftShiftStage0Idx1_uid26547_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26546_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23566_dupName_497_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23565)@322
    assign rightShiftStage2Idx1Rng8_uid23566_dupName_497_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23568_dupName_497_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23567)@322
    assign rightShiftStage2Idx1_uid23568_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23566_dupName_497_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23561_dupName_497_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23560)@322
    assign rightShiftStage1Idx1Rng4_uid23561_dupName_497_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23563_dupName_497_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23562)@322
    assign rightShiftStage1Idx1_uid23563_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23561_dupName_497_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23556_dupName_497_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23555)@322
    assign rightShiftStage0Idx1Rng1_uid23556_dupName_497_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q[33:1];

    // rightShiftStage0Idx1_uid23558_dupName_497_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23557)@322
    assign rightShiftStage0Idx1_uid23558_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23556_dupName_497_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26538_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(BITSELECT,26537)@321
    assign leftShiftStage2Idx1Rng8_uid26538_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in = leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26538_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26538_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26539_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(BITJOIN,26538)@321
    assign leftShiftStage2Idx1_uid26539_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26538_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26533_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(BITSELECT,26532)@321
    assign leftShiftStage1Idx1Rng4_uid26533_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in = leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26533_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26533_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26534_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(BITJOIN,26533)@321
    assign leftShiftStage1Idx1_uid26534_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26533_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26528_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(BITSELECT,26527)@321
    assign leftShiftStage0Idx1Rng1_uid26528_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26528_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26528_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26529_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(BITJOIN,26528)@321
    assign leftShiftStage0Idx1_uid26529_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26528_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23504_dupName_493_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23503)@320
    assign rightShiftStage2Idx1Rng8_uid23504_dupName_493_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23506_dupName_493_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23505)@320
    assign rightShiftStage2Idx1_uid23506_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23504_dupName_493_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23499_dupName_493_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23498)@320
    assign rightShiftStage1Idx1Rng4_uid23499_dupName_493_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23501_dupName_493_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23500)@320
    assign rightShiftStage1Idx1_uid23501_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23499_dupName_493_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23494_dupName_493_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23493)@320
    assign rightShiftStage0Idx1Rng1_uid23494_dupName_493_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q[33:1];

    // rightShiftStage0Idx1_uid23496_dupName_493_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23495)@320
    assign rightShiftStage0Idx1_uid23496_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23494_dupName_493_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26520_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(BITSELECT,26519)@319
    assign leftShiftStage2Idx1Rng8_uid26520_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in = leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26520_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26520_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26521_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(BITJOIN,26520)@319
    assign leftShiftStage2Idx1_uid26521_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26520_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26515_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(BITSELECT,26514)@319
    assign leftShiftStage1Idx1Rng4_uid26515_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in = leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26515_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26515_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26516_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(BITJOIN,26515)@319
    assign leftShiftStage1Idx1_uid26516_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26515_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26510_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(BITSELECT,26509)@319
    assign leftShiftStage0Idx1Rng1_uid26510_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26510_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26510_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26511_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(BITJOIN,26510)@319
    assign leftShiftStage0Idx1_uid26511_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26510_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23442_dupName_489_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23441)@318
    assign rightShiftStage2Idx1Rng8_uid23442_dupName_489_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23444_dupName_489_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23443)@318
    assign rightShiftStage2Idx1_uid23444_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23442_dupName_489_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23437_dupName_489_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23436)@318
    assign rightShiftStage1Idx1Rng4_uid23437_dupName_489_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23439_dupName_489_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23438)@318
    assign rightShiftStage1Idx1_uid23439_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23437_dupName_489_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23432_dupName_489_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23431)@318
    assign rightShiftStage0Idx1Rng1_uid23432_dupName_489_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q[33:1];

    // rightShiftStage0Idx1_uid23434_dupName_489_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23433)@318
    assign rightShiftStage0Idx1_uid23434_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23432_dupName_489_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26502_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(BITSELECT,26501)@317
    assign leftShiftStage2Idx1Rng8_uid26502_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in = leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26502_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26502_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26503_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(BITJOIN,26502)@317
    assign leftShiftStage2Idx1_uid26503_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26502_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26497_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(BITSELECT,26496)@317
    assign leftShiftStage1Idx1Rng4_uid26497_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in = leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26497_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26497_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26498_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(BITJOIN,26497)@317
    assign leftShiftStage1Idx1_uid26498_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26497_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26492_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(BITSELECT,26491)@317
    assign leftShiftStage0Idx1Rng1_uid26492_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26492_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26492_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26493_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(BITJOIN,26492)@317
    assign leftShiftStage0Idx1_uid26493_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26492_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23380_dupName_485_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23379)@316
    assign rightShiftStage2Idx1Rng8_uid23380_dupName_485_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23382_dupName_485_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23381)@316
    assign rightShiftStage2Idx1_uid23382_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23380_dupName_485_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23375_dupName_485_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23374)@316
    assign rightShiftStage1Idx1Rng4_uid23375_dupName_485_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23377_dupName_485_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23376)@316
    assign rightShiftStage1Idx1_uid23377_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23375_dupName_485_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23370_dupName_485_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23369)@316
    assign rightShiftStage0Idx1Rng1_uid23370_dupName_485_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q[33:1];

    // rightShiftStage0Idx1_uid23372_dupName_485_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23371)@316
    assign rightShiftStage0Idx1_uid23372_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23370_dupName_485_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26484_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(BITSELECT,26483)@315
    assign leftShiftStage2Idx1Rng8_uid26484_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in = leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26484_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26484_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26485_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(BITJOIN,26484)@315
    assign leftShiftStage2Idx1_uid26485_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26484_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26479_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(BITSELECT,26478)@315
    assign leftShiftStage1Idx1Rng4_uid26479_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in = leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26479_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26479_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26480_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(BITJOIN,26479)@315
    assign leftShiftStage1Idx1_uid26480_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26479_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26474_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(BITSELECT,26473)@315
    assign leftShiftStage0Idx1Rng1_uid26474_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26474_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26474_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26475_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(BITJOIN,26474)@315
    assign leftShiftStage0Idx1_uid26475_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26474_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23318_dupName_481_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23317)@314
    assign rightShiftStage2Idx1Rng8_uid23318_dupName_481_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23320_dupName_481_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23319)@314
    assign rightShiftStage2Idx1_uid23320_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23318_dupName_481_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23313_dupName_481_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23312)@314
    assign rightShiftStage1Idx1Rng4_uid23313_dupName_481_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23315_dupName_481_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23314)@314
    assign rightShiftStage1Idx1_uid23315_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23313_dupName_481_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23308_dupName_481_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23307)@314
    assign rightShiftStage0Idx1Rng1_uid23308_dupName_481_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q[33:1];

    // rightShiftStage0Idx1_uid23310_dupName_481_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23309)@314
    assign rightShiftStage0Idx1_uid23310_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23308_dupName_481_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26466_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(BITSELECT,26465)@313
    assign leftShiftStage2Idx1Rng8_uid26466_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in = leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26466_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26466_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26467_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(BITJOIN,26466)@313
    assign leftShiftStage2Idx1_uid26467_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26466_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26461_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(BITSELECT,26460)@313
    assign leftShiftStage1Idx1Rng4_uid26461_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in = leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26461_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26461_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26462_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(BITJOIN,26461)@313
    assign leftShiftStage1Idx1_uid26462_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26461_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26456_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(BITSELECT,26455)@313
    assign leftShiftStage0Idx1Rng1_uid26456_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26456_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26456_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26457_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(BITJOIN,26456)@313
    assign leftShiftStage0Idx1_uid26457_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26456_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23256_dupName_477_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23255)@312
    assign rightShiftStage2Idx1Rng8_uid23256_dupName_477_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23258_dupName_477_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23257)@312
    assign rightShiftStage2Idx1_uid23258_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23256_dupName_477_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23251_dupName_477_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23250)@312
    assign rightShiftStage1Idx1Rng4_uid23251_dupName_477_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23253_dupName_477_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23252)@312
    assign rightShiftStage1Idx1_uid23253_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23251_dupName_477_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23246_dupName_477_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23245)@312
    assign rightShiftStage0Idx1Rng1_uid23246_dupName_477_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q[33:1];

    // rightShiftStage0Idx1_uid23248_dupName_477_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23247)@312
    assign rightShiftStage0Idx1_uid23248_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23246_dupName_477_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26430_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(BITSELECT,26429)@311
    assign leftShiftStage2Idx1Rng8_uid26430_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in = leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26430_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26430_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26431_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(BITJOIN,26430)@311
    assign leftShiftStage2Idx1_uid26431_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26430_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26425_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(BITSELECT,26424)@311
    assign leftShiftStage1Idx1Rng4_uid26425_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in = leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26425_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26425_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26426_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(BITJOIN,26425)@311
    assign leftShiftStage1Idx1_uid26426_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26425_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26420_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(BITSELECT,26419)@311
    assign leftShiftStage0Idx1Rng1_uid26420_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26420_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26420_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26421_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(BITJOIN,26420)@311
    assign leftShiftStage0Idx1_uid26421_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26420_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23194_dupName_473_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23193)@310
    assign rightShiftStage2Idx1Rng8_uid23194_dupName_473_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23196_dupName_473_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23195)@310
    assign rightShiftStage2Idx1_uid23196_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23194_dupName_473_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23189_dupName_473_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23188)@310
    assign rightShiftStage1Idx1Rng4_uid23189_dupName_473_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23191_dupName_473_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23190)@310
    assign rightShiftStage1Idx1_uid23191_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23189_dupName_473_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23184_dupName_473_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23183)@310
    assign rightShiftStage0Idx1Rng1_uid23184_dupName_473_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q[33:1];

    // rightShiftStage0Idx1_uid23186_dupName_473_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23185)@310
    assign rightShiftStage0Idx1_uid23186_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23184_dupName_473_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26412_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(BITSELECT,26411)@309
    assign leftShiftStage2Idx1Rng8_uid26412_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in = leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26412_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26412_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26413_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(BITJOIN,26412)@309
    assign leftShiftStage2Idx1_uid26413_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26412_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26407_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(BITSELECT,26406)@309
    assign leftShiftStage1Idx1Rng4_uid26407_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in = leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26407_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26407_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26408_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(BITJOIN,26407)@309
    assign leftShiftStage1Idx1_uid26408_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26407_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26402_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(BITSELECT,26401)@309
    assign leftShiftStage0Idx1Rng1_uid26402_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26402_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26402_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26403_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(BITJOIN,26402)@309
    assign leftShiftStage0Idx1_uid26403_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26402_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23132_dupName_469_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23131)@308
    assign rightShiftStage2Idx1Rng8_uid23132_dupName_469_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23134_dupName_469_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23133)@308
    assign rightShiftStage2Idx1_uid23134_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23132_dupName_469_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23127_dupName_469_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23126)@308
    assign rightShiftStage1Idx1Rng4_uid23127_dupName_469_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23129_dupName_469_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23128)@308
    assign rightShiftStage1Idx1_uid23129_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23127_dupName_469_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23122_dupName_469_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23121)@308
    assign rightShiftStage0Idx1Rng1_uid23122_dupName_469_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q[33:1];

    // rightShiftStage0Idx1_uid23124_dupName_469_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23123)@308
    assign rightShiftStage0Idx1_uid23124_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23122_dupName_469_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26394_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(BITSELECT,26393)@307
    assign leftShiftStage2Idx1Rng8_uid26394_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in = leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26394_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26394_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26395_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(BITJOIN,26394)@307
    assign leftShiftStage2Idx1_uid26395_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26394_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26389_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(BITSELECT,26388)@307
    assign leftShiftStage1Idx1Rng4_uid26389_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in = leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26389_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26389_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26390_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(BITJOIN,26389)@307
    assign leftShiftStage1Idx1_uid26390_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26389_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26384_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(BITSELECT,26383)@307
    assign leftShiftStage0Idx1Rng1_uid26384_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26384_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26384_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26385_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(BITJOIN,26384)@307
    assign leftShiftStage0Idx1_uid26385_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26384_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23070_dupName_465_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23069)@306
    assign rightShiftStage2Idx1Rng8_uid23070_dupName_465_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23072_dupName_465_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23071)@306
    assign rightShiftStage2Idx1_uid23072_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23070_dupName_465_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23065_dupName_465_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23064)@306
    assign rightShiftStage1Idx1Rng4_uid23065_dupName_465_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23067_dupName_465_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23066)@306
    assign rightShiftStage1Idx1_uid23067_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23065_dupName_465_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23060_dupName_465_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23059)@306
    assign rightShiftStage0Idx1Rng1_uid23060_dupName_465_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q[33:1];

    // rightShiftStage0Idx1_uid23062_dupName_465_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23061)@306
    assign rightShiftStage0Idx1_uid23062_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23060_dupName_465_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26376_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(BITSELECT,26375)@305
    assign leftShiftStage2Idx1Rng8_uid26376_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in = leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26376_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26376_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26377_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(BITJOIN,26376)@305
    assign leftShiftStage2Idx1_uid26377_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26376_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26371_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(BITSELECT,26370)@305
    assign leftShiftStage1Idx1Rng4_uid26371_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in = leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26371_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26371_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26372_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(BITJOIN,26371)@305
    assign leftShiftStage1Idx1_uid26372_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26371_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26366_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(BITSELECT,26365)@305
    assign leftShiftStage0Idx1Rng1_uid26366_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26366_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26366_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26367_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(BITJOIN,26366)@305
    assign leftShiftStage0Idx1_uid26367_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26366_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23008_dupName_461_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23007)@304
    assign rightShiftStage2Idx1Rng8_uid23008_dupName_461_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23010_dupName_461_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23009)@304
    assign rightShiftStage2Idx1_uid23010_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23008_dupName_461_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23003_dupName_461_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23002)@304
    assign rightShiftStage1Idx1Rng4_uid23003_dupName_461_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23005_dupName_461_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23004)@304
    assign rightShiftStage1Idx1_uid23005_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23003_dupName_461_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22998_dupName_461_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22997)@304
    assign rightShiftStage0Idx1Rng1_uid22998_dupName_461_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q[33:1];

    // rightShiftStage0Idx1_uid23000_dupName_461_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22999)@304
    assign rightShiftStage0Idx1_uid23000_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22998_dupName_461_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26358_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(BITSELECT,26357)@303
    assign leftShiftStage2Idx1Rng8_uid26358_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in = leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26358_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26358_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26359_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(BITJOIN,26358)@303
    assign leftShiftStage2Idx1_uid26359_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26358_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26353_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(BITSELECT,26352)@303
    assign leftShiftStage1Idx1Rng4_uid26353_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in = leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26353_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26353_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26354_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(BITJOIN,26353)@303
    assign leftShiftStage1Idx1_uid26354_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26353_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26348_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(BITSELECT,26347)@303
    assign leftShiftStage0Idx1Rng1_uid26348_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26348_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26348_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26349_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(BITJOIN,26348)@303
    assign leftShiftStage0Idx1_uid26349_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26348_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22946_dupName_457_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22945)@302
    assign rightShiftStage2Idx1Rng8_uid22946_dupName_457_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22948_dupName_457_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22947)@302
    assign rightShiftStage2Idx1_uid22948_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22946_dupName_457_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22941_dupName_457_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22940)@302
    assign rightShiftStage1Idx1Rng4_uid22941_dupName_457_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22943_dupName_457_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22942)@302
    assign rightShiftStage1Idx1_uid22943_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22941_dupName_457_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22936_dupName_457_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22935)@302
    assign rightShiftStage0Idx1Rng1_uid22936_dupName_457_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q[33:1];

    // rightShiftStage0Idx1_uid22938_dupName_457_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22937)@302
    assign rightShiftStage0Idx1_uid22938_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22936_dupName_457_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26340_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(BITSELECT,26339)@301
    assign leftShiftStage2Idx1Rng8_uid26340_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in = leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26340_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26340_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26341_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(BITJOIN,26340)@301
    assign leftShiftStage2Idx1_uid26341_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26340_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26335_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(BITSELECT,26334)@301
    assign leftShiftStage1Idx1Rng4_uid26335_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in = leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26335_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26335_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26336_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(BITJOIN,26335)@301
    assign leftShiftStage1Idx1_uid26336_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26335_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26330_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(BITSELECT,26329)@301
    assign leftShiftStage0Idx1Rng1_uid26330_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26330_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26330_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26331_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(BITJOIN,26330)@301
    assign leftShiftStage0Idx1_uid26331_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26330_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22884_dupName_453_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22883)@300
    assign rightShiftStage2Idx1Rng8_uid22884_dupName_453_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22886_dupName_453_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22885)@300
    assign rightShiftStage2Idx1_uid22886_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22884_dupName_453_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22879_dupName_453_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22878)@300
    assign rightShiftStage1Idx1Rng4_uid22879_dupName_453_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22881_dupName_453_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22880)@300
    assign rightShiftStage1Idx1_uid22881_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22879_dupName_453_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22874_dupName_453_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22873)@300
    assign rightShiftStage0Idx1Rng1_uid22874_dupName_453_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q[33:1];

    // rightShiftStage0Idx1_uid22876_dupName_453_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22875)@300
    assign rightShiftStage0Idx1_uid22876_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22874_dupName_453_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26322_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(BITSELECT,26321)@299
    assign leftShiftStage2Idx1Rng8_uid26322_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in = leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26322_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26322_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26323_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(BITJOIN,26322)@299
    assign leftShiftStage2Idx1_uid26323_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26322_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26317_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(BITSELECT,26316)@299
    assign leftShiftStage1Idx1Rng4_uid26317_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in = leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26317_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26317_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26318_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(BITJOIN,26317)@299
    assign leftShiftStage1Idx1_uid26318_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26317_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26312_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(BITSELECT,26311)@299
    assign leftShiftStage0Idx1Rng1_uid26312_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26312_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26312_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26313_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(BITJOIN,26312)@299
    assign leftShiftStage0Idx1_uid26313_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26312_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22822_dupName_449_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22821)@298
    assign rightShiftStage2Idx1Rng8_uid22822_dupName_449_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22824_dupName_449_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22823)@298
    assign rightShiftStage2Idx1_uid22824_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22822_dupName_449_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22817_dupName_449_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22816)@298
    assign rightShiftStage1Idx1Rng4_uid22817_dupName_449_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22819_dupName_449_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22818)@298
    assign rightShiftStage1Idx1_uid22819_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22817_dupName_449_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22812_dupName_449_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22811)@298
    assign rightShiftStage0Idx1Rng1_uid22812_dupName_449_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q[33:1];

    // rightShiftStage0Idx1_uid22814_dupName_449_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22813)@298
    assign rightShiftStage0Idx1_uid22814_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22812_dupName_449_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26304_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(BITSELECT,26303)@297
    assign leftShiftStage2Idx1Rng8_uid26304_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in = leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26304_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26304_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26305_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(BITJOIN,26304)@297
    assign leftShiftStage2Idx1_uid26305_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26304_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26299_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(BITSELECT,26298)@297
    assign leftShiftStage1Idx1Rng4_uid26299_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in = leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26299_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26299_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26300_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(BITJOIN,26299)@297
    assign leftShiftStage1Idx1_uid26300_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26299_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26294_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(BITSELECT,26293)@297
    assign leftShiftStage0Idx1Rng1_uid26294_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26294_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26294_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26295_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(BITJOIN,26294)@297
    assign leftShiftStage0Idx1_uid26295_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26294_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22760_dupName_445_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22759)@296
    assign rightShiftStage2Idx1Rng8_uid22760_dupName_445_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22762_dupName_445_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22761)@296
    assign rightShiftStage2Idx1_uid22762_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22760_dupName_445_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22755_dupName_445_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22754)@296
    assign rightShiftStage1Idx1Rng4_uid22755_dupName_445_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22757_dupName_445_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22756)@296
    assign rightShiftStage1Idx1_uid22757_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22755_dupName_445_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22750_dupName_445_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22749)@296
    assign rightShiftStage0Idx1Rng1_uid22750_dupName_445_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q[33:1];

    // rightShiftStage0Idx1_uid22752_dupName_445_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22751)@296
    assign rightShiftStage0Idx1_uid22752_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22750_dupName_445_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26286_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(BITSELECT,26285)@295
    assign leftShiftStage2Idx1Rng8_uid26286_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in = leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26286_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26286_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26287_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(BITJOIN,26286)@295
    assign leftShiftStage2Idx1_uid26287_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26286_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26281_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(BITSELECT,26280)@295
    assign leftShiftStage1Idx1Rng4_uid26281_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in = leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26281_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26281_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26282_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(BITJOIN,26281)@295
    assign leftShiftStage1Idx1_uid26282_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26281_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26276_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(BITSELECT,26275)@295
    assign leftShiftStage0Idx1Rng1_uid26276_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26276_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26276_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26277_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(BITJOIN,26276)@295
    assign leftShiftStage0Idx1_uid26277_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26276_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22698_dupName_441_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22697)@294
    assign rightShiftStage2Idx1Rng8_uid22698_dupName_441_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22700_dupName_441_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22699)@294
    assign rightShiftStage2Idx1_uid22700_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22698_dupName_441_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22693_dupName_441_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22692)@294
    assign rightShiftStage1Idx1Rng4_uid22693_dupName_441_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22695_dupName_441_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22694)@294
    assign rightShiftStage1Idx1_uid22695_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22693_dupName_441_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22688_dupName_441_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22687)@294
    assign rightShiftStage0Idx1Rng1_uid22688_dupName_441_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q[33:1];

    // rightShiftStage0Idx1_uid22690_dupName_441_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22689)@294
    assign rightShiftStage0Idx1_uid22690_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22688_dupName_441_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26268_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(BITSELECT,26267)@293
    assign leftShiftStage2Idx1Rng8_uid26268_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in = leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26268_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26268_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26269_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(BITJOIN,26268)@293
    assign leftShiftStage2Idx1_uid26269_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26268_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26263_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(BITSELECT,26262)@293
    assign leftShiftStage1Idx1Rng4_uid26263_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in = leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26263_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26263_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26264_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(BITJOIN,26263)@293
    assign leftShiftStage1Idx1_uid26264_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26263_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26258_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(BITSELECT,26257)@293
    assign leftShiftStage0Idx1Rng1_uid26258_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26258_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26258_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26259_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(BITJOIN,26258)@293
    assign leftShiftStage0Idx1_uid26259_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26258_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22636_dupName_437_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22635)@292
    assign rightShiftStage2Idx1Rng8_uid22636_dupName_437_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22638_dupName_437_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22637)@292
    assign rightShiftStage2Idx1_uid22638_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22636_dupName_437_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22631_dupName_437_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22630)@292
    assign rightShiftStage1Idx1Rng4_uid22631_dupName_437_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22633_dupName_437_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22632)@292
    assign rightShiftStage1Idx1_uid22633_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22631_dupName_437_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22626_dupName_437_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22625)@292
    assign rightShiftStage0Idx1Rng1_uid22626_dupName_437_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q[33:1];

    // rightShiftStage0Idx1_uid22628_dupName_437_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22627)@292
    assign rightShiftStage0Idx1_uid22628_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22626_dupName_437_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26232_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(BITSELECT,26231)@291
    assign leftShiftStage2Idx1Rng8_uid26232_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in = leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26232_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26232_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26233_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(BITJOIN,26232)@291
    assign leftShiftStage2Idx1_uid26233_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26232_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26227_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(BITSELECT,26226)@291
    assign leftShiftStage1Idx1Rng4_uid26227_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in = leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26227_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26227_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26228_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(BITJOIN,26227)@291
    assign leftShiftStage1Idx1_uid26228_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26227_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26222_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(BITSELECT,26221)@291
    assign leftShiftStage0Idx1Rng1_uid26222_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26222_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26222_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26223_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(BITJOIN,26222)@291
    assign leftShiftStage0Idx1_uid26223_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26222_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22574_dupName_433_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22573)@290
    assign rightShiftStage2Idx1Rng8_uid22574_dupName_433_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22576_dupName_433_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22575)@290
    assign rightShiftStage2Idx1_uid22576_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22574_dupName_433_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22569_dupName_433_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22568)@290
    assign rightShiftStage1Idx1Rng4_uid22569_dupName_433_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22571_dupName_433_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22570)@290
    assign rightShiftStage1Idx1_uid22571_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22569_dupName_433_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22564_dupName_433_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22563)@290
    assign rightShiftStage0Idx1Rng1_uid22564_dupName_433_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q[33:1];

    // rightShiftStage0Idx1_uid22566_dupName_433_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22565)@290
    assign rightShiftStage0Idx1_uid22566_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22564_dupName_433_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26214_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(BITSELECT,26213)@289
    assign leftShiftStage2Idx1Rng8_uid26214_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in = leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26214_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26214_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26215_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(BITJOIN,26214)@289
    assign leftShiftStage2Idx1_uid26215_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26214_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26209_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(BITSELECT,26208)@289
    assign leftShiftStage1Idx1Rng4_uid26209_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in = leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26209_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26209_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26210_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(BITJOIN,26209)@289
    assign leftShiftStage1Idx1_uid26210_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26209_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26204_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(BITSELECT,26203)@289
    assign leftShiftStage0Idx1Rng1_uid26204_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26204_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26204_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26205_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(BITJOIN,26204)@289
    assign leftShiftStage0Idx1_uid26205_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26204_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22512_dupName_429_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22511)@288
    assign rightShiftStage2Idx1Rng8_uid22512_dupName_429_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22514_dupName_429_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22513)@288
    assign rightShiftStage2Idx1_uid22514_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22512_dupName_429_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22507_dupName_429_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22506)@288
    assign rightShiftStage1Idx1Rng4_uid22507_dupName_429_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22509_dupName_429_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22508)@288
    assign rightShiftStage1Idx1_uid22509_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22507_dupName_429_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22502_dupName_429_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22501)@288
    assign rightShiftStage0Idx1Rng1_uid22502_dupName_429_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q[33:1];

    // rightShiftStage0Idx1_uid22504_dupName_429_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22503)@288
    assign rightShiftStage0Idx1_uid22504_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22502_dupName_429_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26196_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(BITSELECT,26195)@287
    assign leftShiftStage2Idx1Rng8_uid26196_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in = leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26196_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26196_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26197_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(BITJOIN,26196)@287
    assign leftShiftStage2Idx1_uid26197_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26196_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26191_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(BITSELECT,26190)@287
    assign leftShiftStage1Idx1Rng4_uid26191_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in = leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26191_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26191_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26192_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(BITJOIN,26191)@287
    assign leftShiftStage1Idx1_uid26192_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26191_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26186_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(BITSELECT,26185)@287
    assign leftShiftStage0Idx1Rng1_uid26186_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26186_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26186_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26187_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(BITJOIN,26186)@287
    assign leftShiftStage0Idx1_uid26187_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26186_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22450_dupName_425_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22449)@286
    assign rightShiftStage2Idx1Rng8_uid22450_dupName_425_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22452_dupName_425_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22451)@286
    assign rightShiftStage2Idx1_uid22452_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22450_dupName_425_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22445_dupName_425_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22444)@286
    assign rightShiftStage1Idx1Rng4_uid22445_dupName_425_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22447_dupName_425_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22446)@286
    assign rightShiftStage1Idx1_uid22447_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22445_dupName_425_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22440_dupName_425_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22439)@286
    assign rightShiftStage0Idx1Rng1_uid22440_dupName_425_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q[33:1];

    // rightShiftStage0Idx1_uid22442_dupName_425_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22441)@286
    assign rightShiftStage0Idx1_uid22442_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22440_dupName_425_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26178_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(BITSELECT,26177)@285
    assign leftShiftStage2Idx1Rng8_uid26178_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in = leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26178_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26178_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26179_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(BITJOIN,26178)@285
    assign leftShiftStage2Idx1_uid26179_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26178_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26173_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(BITSELECT,26172)@285
    assign leftShiftStage1Idx1Rng4_uid26173_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in = leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26173_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26173_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26174_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(BITJOIN,26173)@285
    assign leftShiftStage1Idx1_uid26174_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26173_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26168_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(BITSELECT,26167)@285
    assign leftShiftStage0Idx1Rng1_uid26168_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26168_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26168_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26169_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(BITJOIN,26168)@285
    assign leftShiftStage0Idx1_uid26169_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26168_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22388_dupName_421_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22387)@284
    assign rightShiftStage2Idx1Rng8_uid22388_dupName_421_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22390_dupName_421_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22389)@284
    assign rightShiftStage2Idx1_uid22390_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22388_dupName_421_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22383_dupName_421_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22382)@284
    assign rightShiftStage1Idx1Rng4_uid22383_dupName_421_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22385_dupName_421_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22384)@284
    assign rightShiftStage1Idx1_uid22385_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22383_dupName_421_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22378_dupName_421_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22377)@284
    assign rightShiftStage0Idx1Rng1_uid22378_dupName_421_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q[33:1];

    // rightShiftStage0Idx1_uid22380_dupName_421_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22379)@284
    assign rightShiftStage0Idx1_uid22380_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22378_dupName_421_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26160_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(BITSELECT,26159)@283
    assign leftShiftStage2Idx1Rng8_uid26160_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in = leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26160_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26160_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26161_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(BITJOIN,26160)@283
    assign leftShiftStage2Idx1_uid26161_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26160_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26155_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(BITSELECT,26154)@283
    assign leftShiftStage1Idx1Rng4_uid26155_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in = leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26155_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26155_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26156_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(BITJOIN,26155)@283
    assign leftShiftStage1Idx1_uid26156_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26155_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26150_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(BITSELECT,26149)@283
    assign leftShiftStage0Idx1Rng1_uid26150_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26150_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26150_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26151_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(BITJOIN,26150)@283
    assign leftShiftStage0Idx1_uid26151_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26150_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22326_dupName_417_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22325)@282
    assign rightShiftStage2Idx1Rng8_uid22326_dupName_417_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22328_dupName_417_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22327)@282
    assign rightShiftStage2Idx1_uid22328_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22326_dupName_417_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22321_dupName_417_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22320)@282
    assign rightShiftStage1Idx1Rng4_uid22321_dupName_417_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22323_dupName_417_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22322)@282
    assign rightShiftStage1Idx1_uid22323_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22321_dupName_417_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22316_dupName_417_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22315)@282
    assign rightShiftStage0Idx1Rng1_uid22316_dupName_417_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q[33:1];

    // rightShiftStage0Idx1_uid22318_dupName_417_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22317)@282
    assign rightShiftStage0Idx1_uid22318_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22316_dupName_417_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26142_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(BITSELECT,26141)@282
    assign leftShiftStage2Idx1Rng8_uid26142_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in = leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26142_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26142_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26143_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(BITJOIN,26142)@282
    assign leftShiftStage2Idx1_uid26143_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26142_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26137_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(BITSELECT,26136)@282
    assign leftShiftStage1Idx1Rng4_uid26137_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in = leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26137_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26137_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26138_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(BITJOIN,26137)@282
    assign leftShiftStage1Idx1_uid26138_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26137_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26132_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(BITSELECT,26131)@282
    assign leftShiftStage0Idx1Rng1_uid26132_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26132_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26132_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26133_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(BITJOIN,26132)@282
    assign leftShiftStage0Idx1_uid26133_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26132_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22264_dupName_413_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22263)@280
    assign rightShiftStage2Idx1Rng8_uid22264_dupName_413_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22266_dupName_413_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22265)@280
    assign rightShiftStage2Idx1_uid22266_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22264_dupName_413_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22259_dupName_413_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22258)@280
    assign rightShiftStage1Idx1Rng4_uid22259_dupName_413_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22261_dupName_413_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22260)@280
    assign rightShiftStage1Idx1_uid22261_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22259_dupName_413_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22254_dupName_413_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22253)@280
    assign rightShiftStage0Idx1Rng1_uid22254_dupName_413_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q[33:1];

    // rightShiftStage0Idx1_uid22256_dupName_413_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22255)@280
    assign rightShiftStage0Idx1_uid22256_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22254_dupName_413_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26124_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(BITSELECT,26123)@280
    assign leftShiftStage2Idx1Rng8_uid26124_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in = leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26124_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26124_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26125_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(BITJOIN,26124)@280
    assign leftShiftStage2Idx1_uid26125_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26124_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26119_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(BITSELECT,26118)@280
    assign leftShiftStage1Idx1Rng4_uid26119_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in = leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26119_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26119_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26120_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(BITJOIN,26119)@280
    assign leftShiftStage1Idx1_uid26120_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26119_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26114_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(BITSELECT,26113)@280
    assign leftShiftStage0Idx1Rng1_uid26114_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26114_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26114_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26115_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(BITJOIN,26114)@280
    assign leftShiftStage0Idx1_uid26115_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26114_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22202_dupName_409_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22201)@278
    assign rightShiftStage2Idx1Rng8_uid22202_dupName_409_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22204_dupName_409_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22203)@278
    assign rightShiftStage2Idx1_uid22204_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22202_dupName_409_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22197_dupName_409_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22196)@278
    assign rightShiftStage1Idx1Rng4_uid22197_dupName_409_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22199_dupName_409_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22198)@278
    assign rightShiftStage1Idx1_uid22199_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22197_dupName_409_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22192_dupName_409_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22191)@278
    assign rightShiftStage0Idx1Rng1_uid22192_dupName_409_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q[33:1];

    // rightShiftStage0Idx1_uid22194_dupName_409_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22193)@278
    assign rightShiftStage0Idx1_uid22194_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22192_dupName_409_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26106_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(BITSELECT,26105)@278
    assign leftShiftStage2Idx1Rng8_uid26106_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in = leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26106_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26106_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26107_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(BITJOIN,26106)@278
    assign leftShiftStage2Idx1_uid26107_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26106_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26101_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(BITSELECT,26100)@278
    assign leftShiftStage1Idx1Rng4_uid26101_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in = leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26101_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26101_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26102_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(BITJOIN,26101)@278
    assign leftShiftStage1Idx1_uid26102_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26101_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26096_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(BITSELECT,26095)@278
    assign leftShiftStage0Idx1Rng1_uid26096_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26096_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26096_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26097_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(BITJOIN,26096)@278
    assign leftShiftStage0Idx1_uid26097_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26096_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22140_dupName_405_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22139)@276
    assign rightShiftStage2Idx1Rng8_uid22140_dupName_405_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22142_dupName_405_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22141)@276
    assign rightShiftStage2Idx1_uid22142_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22140_dupName_405_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22135_dupName_405_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22134)@276
    assign rightShiftStage1Idx1Rng4_uid22135_dupName_405_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22137_dupName_405_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22136)@276
    assign rightShiftStage1Idx1_uid22137_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22135_dupName_405_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22130_dupName_405_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22129)@276
    assign rightShiftStage0Idx1Rng1_uid22130_dupName_405_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q[33:1];

    // rightShiftStage0Idx1_uid22132_dupName_405_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22131)@276
    assign rightShiftStage0Idx1_uid22132_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22130_dupName_405_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26088_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(BITSELECT,26087)@275
    assign leftShiftStage2Idx1Rng8_uid26088_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in = leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26088_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26088_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26089_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(BITJOIN,26088)@275
    assign leftShiftStage2Idx1_uid26089_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26088_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26083_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(BITSELECT,26082)@275
    assign leftShiftStage1Idx1Rng4_uid26083_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in = leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26083_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26083_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26084_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(BITJOIN,26083)@275
    assign leftShiftStage1Idx1_uid26084_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26083_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26078_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(BITSELECT,26077)@275
    assign leftShiftStage0Idx1Rng1_uid26078_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26078_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26078_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26079_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(BITJOIN,26078)@275
    assign leftShiftStage0Idx1_uid26079_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26078_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22078_dupName_401_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22077)@274
    assign rightShiftStage2Idx1Rng8_uid22078_dupName_401_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22080_dupName_401_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22079)@274
    assign rightShiftStage2Idx1_uid22080_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22078_dupName_401_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22073_dupName_401_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22072)@274
    assign rightShiftStage1Idx1Rng4_uid22073_dupName_401_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22075_dupName_401_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22074)@274
    assign rightShiftStage1Idx1_uid22075_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22073_dupName_401_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22068_dupName_401_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22067)@274
    assign rightShiftStage0Idx1Rng1_uid22068_dupName_401_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q[33:1];

    // rightShiftStage0Idx1_uid22070_dupName_401_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22069)@274
    assign rightShiftStage0Idx1_uid22070_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22068_dupName_401_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26070_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(BITSELECT,26069)@273
    assign leftShiftStage2Idx1Rng8_uid26070_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in = leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26070_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26070_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26071_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(BITJOIN,26070)@273
    assign leftShiftStage2Idx1_uid26071_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26070_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26065_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(BITSELECT,26064)@273
    assign leftShiftStage1Idx1Rng4_uid26065_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in = leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26065_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26065_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26066_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(BITJOIN,26065)@273
    assign leftShiftStage1Idx1_uid26066_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26065_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26060_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(BITSELECT,26059)@273
    assign leftShiftStage0Idx1Rng1_uid26060_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26060_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26060_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26061_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(BITJOIN,26060)@273
    assign leftShiftStage0Idx1_uid26061_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26060_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22016_dupName_397_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22015)@272
    assign rightShiftStage2Idx1Rng8_uid22016_dupName_397_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22018_dupName_397_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22017)@272
    assign rightShiftStage2Idx1_uid22018_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22016_dupName_397_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22011_dupName_397_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22010)@272
    assign rightShiftStage1Idx1Rng4_uid22011_dupName_397_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22013_dupName_397_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22012)@272
    assign rightShiftStage1Idx1_uid22013_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22011_dupName_397_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22006_dupName_397_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22005)@272
    assign rightShiftStage0Idx1Rng1_uid22006_dupName_397_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q[33:1];

    // rightShiftStage0Idx1_uid22008_dupName_397_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22007)@272
    assign rightShiftStage0Idx1_uid22008_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22006_dupName_397_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28320_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(BITSELECT,28319)@272
    assign leftShiftStage2Idx1Rng8_uid28320_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in = leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28320_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28320_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28321_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(BITJOIN,28320)@272
    assign leftShiftStage2Idx1_uid28321_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28320_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28315_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(BITSELECT,28314)@272
    assign leftShiftStage1Idx1Rng4_uid28315_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in = leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28315_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28315_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28316_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(BITJOIN,28315)@272
    assign leftShiftStage1Idx1_uid28316_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28315_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28310_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(BITSELECT,28309)@272
    assign leftShiftStage0Idx1Rng1_uid28310_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28310_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28310_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28311_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(BITJOIN,28310)@272
    assign leftShiftStage0Idx1_uid28311_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28310_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21954_dupName_393_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21953)@270
    assign rightShiftStage2Idx1Rng8_uid21954_dupName_393_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21956_dupName_393_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21955)@270
    assign rightShiftStage2Idx1_uid21956_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21954_dupName_393_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21949_dupName_393_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21948)@270
    assign rightShiftStage1Idx1Rng4_uid21949_dupName_393_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21951_dupName_393_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21950)@270
    assign rightShiftStage1Idx1_uid21951_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21949_dupName_393_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21944_dupName_393_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21943)@270
    assign rightShiftStage0Idx1Rng1_uid21944_dupName_393_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q[33:1];

    // rightShiftStage0Idx1_uid21946_dupName_393_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21945)@270
    assign rightShiftStage0Idx1_uid21946_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21944_dupName_393_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28302_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(BITSELECT,28301)@269
    assign leftShiftStage2Idx1Rng8_uid28302_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in = leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28302_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28302_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28303_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(BITJOIN,28302)@269
    assign leftShiftStage2Idx1_uid28303_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28302_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28297_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(BITSELECT,28296)@269
    assign leftShiftStage1Idx1Rng4_uid28297_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in = leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28297_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28297_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28298_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(BITJOIN,28297)@269
    assign leftShiftStage1Idx1_uid28298_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28297_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28292_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(BITSELECT,28291)@269
    assign leftShiftStage0Idx1Rng1_uid28292_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28292_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28292_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28293_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(BITJOIN,28292)@269
    assign leftShiftStage0Idx1_uid28293_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28292_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21892_dupName_389_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21891)@268
    assign rightShiftStage2Idx1Rng8_uid21892_dupName_389_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21894_dupName_389_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21893)@268
    assign rightShiftStage2Idx1_uid21894_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21892_dupName_389_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21887_dupName_389_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21886)@268
    assign rightShiftStage1Idx1Rng4_uid21887_dupName_389_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21889_dupName_389_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21888)@268
    assign rightShiftStage1Idx1_uid21889_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21887_dupName_389_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21882_dupName_389_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21881)@268
    assign rightShiftStage0Idx1Rng1_uid21882_dupName_389_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q[33:1];

    // rightShiftStage0Idx1_uid21884_dupName_389_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21883)@268
    assign rightShiftStage0Idx1_uid21884_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21882_dupName_389_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28284_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(BITSELECT,28283)@267
    assign leftShiftStage2Idx1Rng8_uid28284_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in = leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28284_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28284_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28285_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(BITJOIN,28284)@267
    assign leftShiftStage2Idx1_uid28285_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28284_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28279_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(BITSELECT,28278)@267
    assign leftShiftStage1Idx1Rng4_uid28279_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in = leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28279_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28279_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28280_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(BITJOIN,28279)@267
    assign leftShiftStage1Idx1_uid28280_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28279_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28274_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(BITSELECT,28273)@267
    assign leftShiftStage0Idx1Rng1_uid28274_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28274_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28274_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28275_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(BITJOIN,28274)@267
    assign leftShiftStage0Idx1_uid28275_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28274_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21830_dupName_385_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21829)@266
    assign rightShiftStage2Idx1Rng8_uid21830_dupName_385_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21832_dupName_385_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21831)@266
    assign rightShiftStage2Idx1_uid21832_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21830_dupName_385_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21825_dupName_385_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21824)@266
    assign rightShiftStage1Idx1Rng4_uid21825_dupName_385_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21827_dupName_385_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21826)@266
    assign rightShiftStage1Idx1_uid21827_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21825_dupName_385_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21820_dupName_385_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21819)@266
    assign rightShiftStage0Idx1Rng1_uid21820_dupName_385_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q[33:1];

    // rightShiftStage0Idx1_uid21822_dupName_385_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21821)@266
    assign rightShiftStage0Idx1_uid21822_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21820_dupName_385_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28266_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(BITSELECT,28265)@265
    assign leftShiftStage2Idx1Rng8_uid28266_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in = leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28266_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28266_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28267_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(BITJOIN,28266)@265
    assign leftShiftStage2Idx1_uid28267_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28266_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28261_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(BITSELECT,28260)@265
    assign leftShiftStage1Idx1Rng4_uid28261_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in = leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28261_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28261_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28262_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(BITJOIN,28261)@265
    assign leftShiftStage1Idx1_uid28262_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28261_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28256_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(BITSELECT,28255)@265
    assign leftShiftStage0Idx1Rng1_uid28256_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28256_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28256_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28257_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(BITJOIN,28256)@265
    assign leftShiftStage0Idx1_uid28257_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28256_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21768_dupName_381_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21767)@264
    assign rightShiftStage2Idx1Rng8_uid21768_dupName_381_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21770_dupName_381_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21769)@264
    assign rightShiftStage2Idx1_uid21770_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21768_dupName_381_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21763_dupName_381_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21762)@264
    assign rightShiftStage1Idx1Rng4_uid21763_dupName_381_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21765_dupName_381_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21764)@264
    assign rightShiftStage1Idx1_uid21765_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21763_dupName_381_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21758_dupName_381_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21757)@264
    assign rightShiftStage0Idx1Rng1_uid21758_dupName_381_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q[33:1];

    // rightShiftStage0Idx1_uid21760_dupName_381_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21759)@264
    assign rightShiftStage0Idx1_uid21760_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21758_dupName_381_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28248_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(BITSELECT,28247)@263
    assign leftShiftStage2Idx1Rng8_uid28248_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in = leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28248_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28248_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28249_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(BITJOIN,28248)@263
    assign leftShiftStage2Idx1_uid28249_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28248_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28243_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(BITSELECT,28242)@263
    assign leftShiftStage1Idx1Rng4_uid28243_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in = leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28243_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28243_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28244_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(BITJOIN,28243)@263
    assign leftShiftStage1Idx1_uid28244_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28243_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28238_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(BITSELECT,28237)@263
    assign leftShiftStage0Idx1Rng1_uid28238_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28238_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28238_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28239_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(BITJOIN,28238)@263
    assign leftShiftStage0Idx1_uid28239_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28238_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21706_dupName_377_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21705)@262
    assign rightShiftStage2Idx1Rng8_uid21706_dupName_377_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21708_dupName_377_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21707)@262
    assign rightShiftStage2Idx1_uid21708_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21706_dupName_377_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21701_dupName_377_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21700)@262
    assign rightShiftStage1Idx1Rng4_uid21701_dupName_377_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21703_dupName_377_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21702)@262
    assign rightShiftStage1Idx1_uid21703_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21701_dupName_377_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21696_dupName_377_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21695)@262
    assign rightShiftStage0Idx1Rng1_uid21696_dupName_377_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q[33:1];

    // rightShiftStage0Idx1_uid21698_dupName_377_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21697)@262
    assign rightShiftStage0Idx1_uid21698_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21696_dupName_377_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28230_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(BITSELECT,28229)@261
    assign leftShiftStage2Idx1Rng8_uid28230_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in = leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28230_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28230_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28231_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(BITJOIN,28230)@261
    assign leftShiftStage2Idx1_uid28231_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28230_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28225_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(BITSELECT,28224)@261
    assign leftShiftStage1Idx1Rng4_uid28225_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in = leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28225_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28225_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28226_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(BITJOIN,28225)@261
    assign leftShiftStage1Idx1_uid28226_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28225_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28220_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(BITSELECT,28219)@261
    assign leftShiftStage0Idx1Rng1_uid28220_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28220_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28220_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28221_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(BITJOIN,28220)@261
    assign leftShiftStage0Idx1_uid28221_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28220_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21644_dupName_373_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21643)@260
    assign rightShiftStage2Idx1Rng8_uid21644_dupName_373_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21646_dupName_373_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21645)@260
    assign rightShiftStage2Idx1_uid21646_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21644_dupName_373_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21639_dupName_373_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21638)@260
    assign rightShiftStage1Idx1Rng4_uid21639_dupName_373_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21641_dupName_373_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21640)@260
    assign rightShiftStage1Idx1_uid21641_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21639_dupName_373_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21634_dupName_373_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21633)@260
    assign rightShiftStage0Idx1Rng1_uid21634_dupName_373_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q[33:1];

    // rightShiftStage0Idx1_uid21636_dupName_373_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21635)@260
    assign rightShiftStage0Idx1_uid21636_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21634_dupName_373_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28212_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(BITSELECT,28211)@259
    assign leftShiftStage2Idx1Rng8_uid28212_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in = leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28212_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28212_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28213_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(BITJOIN,28212)@259
    assign leftShiftStage2Idx1_uid28213_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28212_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28207_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(BITSELECT,28206)@259
    assign leftShiftStage1Idx1Rng4_uid28207_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in = leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28207_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28207_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28208_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(BITJOIN,28207)@259
    assign leftShiftStage1Idx1_uid28208_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28207_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28202_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(BITSELECT,28201)@259
    assign leftShiftStage0Idx1Rng1_uid28202_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28202_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28202_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28203_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(BITJOIN,28202)@259
    assign leftShiftStage0Idx1_uid28203_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28202_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21582_dupName_369_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21581)@258
    assign rightShiftStage2Idx1Rng8_uid21582_dupName_369_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21584_dupName_369_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21583)@258
    assign rightShiftStage2Idx1_uid21584_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21582_dupName_369_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21577_dupName_369_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21576)@258
    assign rightShiftStage1Idx1Rng4_uid21577_dupName_369_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21579_dupName_369_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21578)@258
    assign rightShiftStage1Idx1_uid21579_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21577_dupName_369_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21572_dupName_369_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21571)@258
    assign rightShiftStage0Idx1Rng1_uid21572_dupName_369_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q[33:1];

    // rightShiftStage0Idx1_uid21574_dupName_369_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21573)@258
    assign rightShiftStage0Idx1_uid21574_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21572_dupName_369_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28194_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(BITSELECT,28193)@257
    assign leftShiftStage2Idx1Rng8_uid28194_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in = leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28194_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28194_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28195_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(BITJOIN,28194)@257
    assign leftShiftStage2Idx1_uid28195_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28194_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28189_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(BITSELECT,28188)@257
    assign leftShiftStage1Idx1Rng4_uid28189_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in = leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28189_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28189_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28190_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(BITJOIN,28189)@257
    assign leftShiftStage1Idx1_uid28190_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28189_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28184_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(BITSELECT,28183)@257
    assign leftShiftStage0Idx1Rng1_uid28184_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28184_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28184_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28185_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(BITJOIN,28184)@257
    assign leftShiftStage0Idx1_uid28185_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28184_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21520_dupName_365_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21519)@256
    assign rightShiftStage2Idx1Rng8_uid21520_dupName_365_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21522_dupName_365_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21521)@256
    assign rightShiftStage2Idx1_uid21522_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21520_dupName_365_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21515_dupName_365_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21514)@256
    assign rightShiftStage1Idx1Rng4_uid21515_dupName_365_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21517_dupName_365_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21516)@256
    assign rightShiftStage1Idx1_uid21517_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21515_dupName_365_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21510_dupName_365_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21509)@256
    assign rightShiftStage0Idx1Rng1_uid21510_dupName_365_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q[33:1];

    // rightShiftStage0Idx1_uid21512_dupName_365_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21511)@256
    assign rightShiftStage0Idx1_uid21512_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21510_dupName_365_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28176_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(BITSELECT,28175)@255
    assign leftShiftStage2Idx1Rng8_uid28176_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in = leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28176_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28176_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28177_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(BITJOIN,28176)@255
    assign leftShiftStage2Idx1_uid28177_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28176_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28171_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(BITSELECT,28170)@255
    assign leftShiftStage1Idx1Rng4_uid28171_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in = leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28171_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28171_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28172_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(BITJOIN,28171)@255
    assign leftShiftStage1Idx1_uid28172_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28171_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28166_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(BITSELECT,28165)@255
    assign leftShiftStage0Idx1Rng1_uid28166_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28166_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28166_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28167_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(BITJOIN,28166)@255
    assign leftShiftStage0Idx1_uid28167_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28166_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21458_dupName_361_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21457)@254
    assign rightShiftStage2Idx1Rng8_uid21458_dupName_361_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21460_dupName_361_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21459)@254
    assign rightShiftStage2Idx1_uid21460_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21458_dupName_361_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21453_dupName_361_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21452)@254
    assign rightShiftStage1Idx1Rng4_uid21453_dupName_361_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21455_dupName_361_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21454)@254
    assign rightShiftStage1Idx1_uid21455_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21453_dupName_361_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21448_dupName_361_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21447)@254
    assign rightShiftStage0Idx1Rng1_uid21448_dupName_361_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q[33:1];

    // rightShiftStage0Idx1_uid21450_dupName_361_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21449)@254
    assign rightShiftStage0Idx1_uid21450_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21448_dupName_361_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28158_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(BITSELECT,28157)@253
    assign leftShiftStage2Idx1Rng8_uid28158_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in = leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28158_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28158_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28159_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(BITJOIN,28158)@253
    assign leftShiftStage2Idx1_uid28159_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28158_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28153_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(BITSELECT,28152)@253
    assign leftShiftStage1Idx1Rng4_uid28153_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in = leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28153_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28153_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28154_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(BITJOIN,28153)@253
    assign leftShiftStage1Idx1_uid28154_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28153_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28148_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(BITSELECT,28147)@253
    assign leftShiftStage0Idx1Rng1_uid28148_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28148_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28148_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28149_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(BITJOIN,28148)@253
    assign leftShiftStage0Idx1_uid28149_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28148_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21396_dupName_357_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21395)@252
    assign rightShiftStage2Idx1Rng8_uid21396_dupName_357_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21398_dupName_357_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21397)@252
    assign rightShiftStage2Idx1_uid21398_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21396_dupName_357_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21391_dupName_357_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21390)@252
    assign rightShiftStage1Idx1Rng4_uid21391_dupName_357_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21393_dupName_357_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21392)@252
    assign rightShiftStage1Idx1_uid21393_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21391_dupName_357_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21386_dupName_357_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21385)@252
    assign rightShiftStage0Idx1Rng1_uid21386_dupName_357_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q[33:1];

    // rightShiftStage0Idx1_uid21388_dupName_357_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21387)@252
    assign rightShiftStage0Idx1_uid21388_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21386_dupName_357_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28122_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(BITSELECT,28121)@251
    assign leftShiftStage2Idx1Rng8_uid28122_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in = leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28122_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28122_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28123_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(BITJOIN,28122)@251
    assign leftShiftStage2Idx1_uid28123_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28122_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28117_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(BITSELECT,28116)@251
    assign leftShiftStage1Idx1Rng4_uid28117_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in = leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28117_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28117_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28118_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(BITJOIN,28117)@251
    assign leftShiftStage1Idx1_uid28118_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28117_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28112_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(BITSELECT,28111)@251
    assign leftShiftStage0Idx1Rng1_uid28112_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28112_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28112_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28113_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(BITJOIN,28112)@251
    assign leftShiftStage0Idx1_uid28113_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28112_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21334_dupName_353_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21333)@250
    assign rightShiftStage2Idx1Rng8_uid21334_dupName_353_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21336_dupName_353_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21335)@250
    assign rightShiftStage2Idx1_uid21336_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21334_dupName_353_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21329_dupName_353_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21328)@250
    assign rightShiftStage1Idx1Rng4_uid21329_dupName_353_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21331_dupName_353_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21330)@250
    assign rightShiftStage1Idx1_uid21331_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21329_dupName_353_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21324_dupName_353_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21323)@250
    assign rightShiftStage0Idx1Rng1_uid21324_dupName_353_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q[33:1];

    // rightShiftStage0Idx1_uid21326_dupName_353_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21325)@250
    assign rightShiftStage0Idx1_uid21326_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21324_dupName_353_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28104_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(BITSELECT,28103)@249
    assign leftShiftStage2Idx1Rng8_uid28104_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in = leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28104_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28104_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28105_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(BITJOIN,28104)@249
    assign leftShiftStage2Idx1_uid28105_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28104_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28099_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(BITSELECT,28098)@249
    assign leftShiftStage1Idx1Rng4_uid28099_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in = leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28099_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28099_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28100_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(BITJOIN,28099)@249
    assign leftShiftStage1Idx1_uid28100_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28099_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28094_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(BITSELECT,28093)@249
    assign leftShiftStage0Idx1Rng1_uid28094_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28094_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28094_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28095_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(BITJOIN,28094)@249
    assign leftShiftStage0Idx1_uid28095_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28094_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21272_dupName_349_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21271)@248
    assign rightShiftStage2Idx1Rng8_uid21272_dupName_349_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21274_dupName_349_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21273)@248
    assign rightShiftStage2Idx1_uid21274_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21272_dupName_349_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21267_dupName_349_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21266)@248
    assign rightShiftStage1Idx1Rng4_uid21267_dupName_349_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21269_dupName_349_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21268)@248
    assign rightShiftStage1Idx1_uid21269_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21267_dupName_349_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21262_dupName_349_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21261)@248
    assign rightShiftStage0Idx1Rng1_uid21262_dupName_349_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q[33:1];

    // rightShiftStage0Idx1_uid21264_dupName_349_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21263)@248
    assign rightShiftStage0Idx1_uid21264_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21262_dupName_349_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28086_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(BITSELECT,28085)@247
    assign leftShiftStage2Idx1Rng8_uid28086_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in = leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28086_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28086_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28087_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(BITJOIN,28086)@247
    assign leftShiftStage2Idx1_uid28087_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28086_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28081_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(BITSELECT,28080)@247
    assign leftShiftStage1Idx1Rng4_uid28081_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in = leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28081_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28081_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28082_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(BITJOIN,28081)@247
    assign leftShiftStage1Idx1_uid28082_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28081_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28076_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(BITSELECT,28075)@247
    assign leftShiftStage0Idx1Rng1_uid28076_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28076_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28076_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28077_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(BITJOIN,28076)@247
    assign leftShiftStage0Idx1_uid28077_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28076_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21210_dupName_345_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21209)@246
    assign rightShiftStage2Idx1Rng8_uid21210_dupName_345_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21212_dupName_345_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21211)@246
    assign rightShiftStage2Idx1_uid21212_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21210_dupName_345_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21205_dupName_345_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21204)@246
    assign rightShiftStage1Idx1Rng4_uid21205_dupName_345_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21207_dupName_345_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21206)@246
    assign rightShiftStage1Idx1_uid21207_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21205_dupName_345_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21200_dupName_345_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21199)@246
    assign rightShiftStage0Idx1Rng1_uid21200_dupName_345_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q[33:1];

    // rightShiftStage0Idx1_uid21202_dupName_345_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21201)@246
    assign rightShiftStage0Idx1_uid21202_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21200_dupName_345_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28068_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(BITSELECT,28067)@245
    assign leftShiftStage2Idx1Rng8_uid28068_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in = leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28068_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28068_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28069_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(BITJOIN,28068)@245
    assign leftShiftStage2Idx1_uid28069_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28068_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28063_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(BITSELECT,28062)@245
    assign leftShiftStage1Idx1Rng4_uid28063_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in = leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28063_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28063_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28064_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(BITJOIN,28063)@245
    assign leftShiftStage1Idx1_uid28064_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28063_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28058_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(BITSELECT,28057)@245
    assign leftShiftStage0Idx1Rng1_uid28058_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28058_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28058_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28059_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(BITJOIN,28058)@245
    assign leftShiftStage0Idx1_uid28059_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28058_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21148_dupName_341_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21147)@244
    assign rightShiftStage2Idx1Rng8_uid21148_dupName_341_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21150_dupName_341_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21149)@244
    assign rightShiftStage2Idx1_uid21150_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21148_dupName_341_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21143_dupName_341_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21142)@244
    assign rightShiftStage1Idx1Rng4_uid21143_dupName_341_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21145_dupName_341_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21144)@244
    assign rightShiftStage1Idx1_uid21145_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21143_dupName_341_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21138_dupName_341_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21137)@244
    assign rightShiftStage0Idx1Rng1_uid21138_dupName_341_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q[33:1];

    // rightShiftStage0Idx1_uid21140_dupName_341_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21139)@244
    assign rightShiftStage0Idx1_uid21140_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21138_dupName_341_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28050_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(BITSELECT,28049)@243
    assign leftShiftStage2Idx1Rng8_uid28050_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in = leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28050_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28050_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28051_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(BITJOIN,28050)@243
    assign leftShiftStage2Idx1_uid28051_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28050_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28045_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(BITSELECT,28044)@243
    assign leftShiftStage1Idx1Rng4_uid28045_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in = leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28045_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28045_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28046_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(BITJOIN,28045)@243
    assign leftShiftStage1Idx1_uid28046_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28045_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28040_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(BITSELECT,28039)@243
    assign leftShiftStage0Idx1Rng1_uid28040_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28040_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28040_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28041_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(BITJOIN,28040)@243
    assign leftShiftStage0Idx1_uid28041_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28040_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21086_dupName_337_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21085)@242
    assign rightShiftStage2Idx1Rng8_uid21086_dupName_337_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21088_dupName_337_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21087)@242
    assign rightShiftStage2Idx1_uid21088_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21086_dupName_337_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21081_dupName_337_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21080)@242
    assign rightShiftStage1Idx1Rng4_uid21081_dupName_337_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21083_dupName_337_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21082)@242
    assign rightShiftStage1Idx1_uid21083_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21081_dupName_337_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21076_dupName_337_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21075)@242
    assign rightShiftStage0Idx1Rng1_uid21076_dupName_337_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q[33:1];

    // rightShiftStage0Idx1_uid21078_dupName_337_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21077)@242
    assign rightShiftStage0Idx1_uid21078_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21076_dupName_337_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28032_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(BITSELECT,28031)@241
    assign leftShiftStage2Idx1Rng8_uid28032_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in = leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28032_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28032_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28033_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(BITJOIN,28032)@241
    assign leftShiftStage2Idx1_uid28033_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28032_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28027_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(BITSELECT,28026)@241
    assign leftShiftStage1Idx1Rng4_uid28027_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in = leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28027_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28027_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28028_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(BITJOIN,28027)@241
    assign leftShiftStage1Idx1_uid28028_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28027_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28022_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(BITSELECT,28021)@241
    assign leftShiftStage0Idx1Rng1_uid28022_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28022_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28022_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28023_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(BITJOIN,28022)@241
    assign leftShiftStage0Idx1_uid28023_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28022_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21024_dupName_333_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21023)@240
    assign rightShiftStage2Idx1Rng8_uid21024_dupName_333_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21026_dupName_333_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21025)@240
    assign rightShiftStage2Idx1_uid21026_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21024_dupName_333_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21019_dupName_333_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21018)@240
    assign rightShiftStage1Idx1Rng4_uid21019_dupName_333_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21021_dupName_333_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21020)@240
    assign rightShiftStage1Idx1_uid21021_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21019_dupName_333_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21014_dupName_333_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21013)@240
    assign rightShiftStage0Idx1Rng1_uid21014_dupName_333_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q[33:1];

    // rightShiftStage0Idx1_uid21016_dupName_333_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21015)@240
    assign rightShiftStage0Idx1_uid21016_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21014_dupName_333_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28014_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(BITSELECT,28013)@239
    assign leftShiftStage2Idx1Rng8_uid28014_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in = leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28014_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28014_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28015_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(BITJOIN,28014)@239
    assign leftShiftStage2Idx1_uid28015_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28014_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28009_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(BITSELECT,28008)@239
    assign leftShiftStage1Idx1Rng4_uid28009_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in = leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28009_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28009_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28010_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(BITJOIN,28009)@239
    assign leftShiftStage1Idx1_uid28010_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28009_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28004_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(BITSELECT,28003)@239
    assign leftShiftStage0Idx1Rng1_uid28004_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28004_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28004_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28005_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(BITJOIN,28004)@239
    assign leftShiftStage0Idx1_uid28005_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28004_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20962_dupName_329_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20961)@238
    assign rightShiftStage2Idx1Rng8_uid20962_dupName_329_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20964_dupName_329_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20963)@238
    assign rightShiftStage2Idx1_uid20964_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20962_dupName_329_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20957_dupName_329_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20956)@238
    assign rightShiftStage1Idx1Rng4_uid20957_dupName_329_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20959_dupName_329_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20958)@238
    assign rightShiftStage1Idx1_uid20959_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20957_dupName_329_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20952_dupName_329_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20951)@238
    assign rightShiftStage0Idx1Rng1_uid20952_dupName_329_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q[33:1];

    // rightShiftStage0Idx1_uid20954_dupName_329_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20953)@238
    assign rightShiftStage0Idx1_uid20954_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20952_dupName_329_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27996_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(BITSELECT,27995)@237
    assign leftShiftStage2Idx1Rng8_uid27996_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in = leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27996_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27996_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27997_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(BITJOIN,27996)@237
    assign leftShiftStage2Idx1_uid27997_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27996_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27991_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(BITSELECT,27990)@237
    assign leftShiftStage1Idx1Rng4_uid27991_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in = leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27991_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27991_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27992_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(BITJOIN,27991)@237
    assign leftShiftStage1Idx1_uid27992_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27991_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27986_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(BITSELECT,27985)@237
    assign leftShiftStage0Idx1Rng1_uid27986_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27986_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27986_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27987_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(BITJOIN,27986)@237
    assign leftShiftStage0Idx1_uid27987_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27986_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20900_dupName_325_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20899)@236
    assign rightShiftStage2Idx1Rng8_uid20900_dupName_325_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20902_dupName_325_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20901)@236
    assign rightShiftStage2Idx1_uid20902_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20900_dupName_325_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20895_dupName_325_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20894)@236
    assign rightShiftStage1Idx1Rng4_uid20895_dupName_325_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20897_dupName_325_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20896)@236
    assign rightShiftStage1Idx1_uid20897_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20895_dupName_325_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20890_dupName_325_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20889)@236
    assign rightShiftStage0Idx1Rng1_uid20890_dupName_325_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q[33:1];

    // rightShiftStage0Idx1_uid20892_dupName_325_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20891)@236
    assign rightShiftStage0Idx1_uid20892_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20890_dupName_325_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27978_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(BITSELECT,27977)@235
    assign leftShiftStage2Idx1Rng8_uid27978_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in = leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27978_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27978_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27979_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(BITJOIN,27978)@235
    assign leftShiftStage2Idx1_uid27979_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27978_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27973_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(BITSELECT,27972)@235
    assign leftShiftStage1Idx1Rng4_uid27973_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in = leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27973_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27973_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27974_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(BITJOIN,27973)@235
    assign leftShiftStage1Idx1_uid27974_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27973_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27968_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(BITSELECT,27967)@235
    assign leftShiftStage0Idx1Rng1_uid27968_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27968_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27968_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27969_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(BITJOIN,27968)@235
    assign leftShiftStage0Idx1_uid27969_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27968_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20838_dupName_321_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20837)@234
    assign rightShiftStage2Idx1Rng8_uid20838_dupName_321_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20840_dupName_321_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20839)@234
    assign rightShiftStage2Idx1_uid20840_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20838_dupName_321_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20833_dupName_321_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20832)@234
    assign rightShiftStage1Idx1Rng4_uid20833_dupName_321_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20835_dupName_321_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20834)@234
    assign rightShiftStage1Idx1_uid20835_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20833_dupName_321_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20828_dupName_321_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20827)@234
    assign rightShiftStage0Idx1Rng1_uid20828_dupName_321_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q[33:1];

    // rightShiftStage0Idx1_uid20830_dupName_321_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20829)@234
    assign rightShiftStage0Idx1_uid20830_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20828_dupName_321_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27960_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(BITSELECT,27959)@233
    assign leftShiftStage2Idx1Rng8_uid27960_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in = leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27960_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27960_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27961_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(BITJOIN,27960)@233
    assign leftShiftStage2Idx1_uid27961_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27960_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27955_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(BITSELECT,27954)@233
    assign leftShiftStage1Idx1Rng4_uid27955_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in = leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27955_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27955_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27956_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(BITJOIN,27955)@233
    assign leftShiftStage1Idx1_uid27956_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27955_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27950_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(BITSELECT,27949)@233
    assign leftShiftStage0Idx1Rng1_uid27950_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27950_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27950_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27951_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(BITJOIN,27950)@233
    assign leftShiftStage0Idx1_uid27951_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27950_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20776_dupName_317_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20775)@232
    assign rightShiftStage2Idx1Rng8_uid20776_dupName_317_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20778_dupName_317_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20777)@232
    assign rightShiftStage2Idx1_uid20778_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20776_dupName_317_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20771_dupName_317_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20770)@232
    assign rightShiftStage1Idx1Rng4_uid20771_dupName_317_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20773_dupName_317_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20772)@232
    assign rightShiftStage1Idx1_uid20773_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20771_dupName_317_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20766_dupName_317_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20765)@232
    assign rightShiftStage0Idx1Rng1_uid20766_dupName_317_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q[33:1];

    // rightShiftStage0Idx1_uid20768_dupName_317_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20767)@232
    assign rightShiftStage0Idx1_uid20768_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20766_dupName_317_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27924_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(BITSELECT,27923)@231
    assign leftShiftStage2Idx1Rng8_uid27924_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in = leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27924_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27924_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27925_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(BITJOIN,27924)@231
    assign leftShiftStage2Idx1_uid27925_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27924_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27919_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(BITSELECT,27918)@231
    assign leftShiftStage1Idx1Rng4_uid27919_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in = leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27919_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27919_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27920_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(BITJOIN,27919)@231
    assign leftShiftStage1Idx1_uid27920_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27919_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27914_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(BITSELECT,27913)@231
    assign leftShiftStage0Idx1Rng1_uid27914_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27914_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27914_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27915_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(BITJOIN,27914)@231
    assign leftShiftStage0Idx1_uid27915_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27914_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20714_dupName_313_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20713)@230
    assign rightShiftStage2Idx1Rng8_uid20714_dupName_313_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20716_dupName_313_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20715)@230
    assign rightShiftStage2Idx1_uid20716_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20714_dupName_313_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20709_dupName_313_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20708)@230
    assign rightShiftStage1Idx1Rng4_uid20709_dupName_313_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20711_dupName_313_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20710)@230
    assign rightShiftStage1Idx1_uid20711_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20709_dupName_313_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20704_dupName_313_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20703)@230
    assign rightShiftStage0Idx1Rng1_uid20704_dupName_313_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q[33:1];

    // rightShiftStage0Idx1_uid20706_dupName_313_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20705)@230
    assign rightShiftStage0Idx1_uid20706_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20704_dupName_313_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27906_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(BITSELECT,27905)@229
    assign leftShiftStage2Idx1Rng8_uid27906_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in = leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27906_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27906_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27907_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(BITJOIN,27906)@229
    assign leftShiftStage2Idx1_uid27907_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27906_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27901_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(BITSELECT,27900)@229
    assign leftShiftStage1Idx1Rng4_uid27901_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in = leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27901_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27901_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27902_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(BITJOIN,27901)@229
    assign leftShiftStage1Idx1_uid27902_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27901_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27896_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(BITSELECT,27895)@229
    assign leftShiftStage0Idx1Rng1_uid27896_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27896_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27896_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27897_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(BITJOIN,27896)@229
    assign leftShiftStage0Idx1_uid27897_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27896_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20652_dupName_309_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20651)@228
    assign rightShiftStage2Idx1Rng8_uid20652_dupName_309_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20654_dupName_309_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20653)@228
    assign rightShiftStage2Idx1_uid20654_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20652_dupName_309_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20647_dupName_309_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20646)@228
    assign rightShiftStage1Idx1Rng4_uid20647_dupName_309_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20649_dupName_309_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20648)@228
    assign rightShiftStage1Idx1_uid20649_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20647_dupName_309_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20642_dupName_309_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20641)@228
    assign rightShiftStage0Idx1Rng1_uid20642_dupName_309_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q[33:1];

    // rightShiftStage0Idx1_uid20644_dupName_309_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20643)@228
    assign rightShiftStage0Idx1_uid20644_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20642_dupName_309_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27888_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(BITSELECT,27887)@227
    assign leftShiftStage2Idx1Rng8_uid27888_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in = leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27888_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27888_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27889_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(BITJOIN,27888)@227
    assign leftShiftStage2Idx1_uid27889_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27888_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27883_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(BITSELECT,27882)@227
    assign leftShiftStage1Idx1Rng4_uid27883_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in = leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27883_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27883_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27884_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(BITJOIN,27883)@227
    assign leftShiftStage1Idx1_uid27884_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27883_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27878_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(BITSELECT,27877)@227
    assign leftShiftStage0Idx1Rng1_uid27878_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27878_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27878_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27879_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(BITJOIN,27878)@227
    assign leftShiftStage0Idx1_uid27879_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27878_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20590_dupName_305_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20589)@226
    assign rightShiftStage2Idx1Rng8_uid20590_dupName_305_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20592_dupName_305_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20591)@226
    assign rightShiftStage2Idx1_uid20592_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20590_dupName_305_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20585_dupName_305_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20584)@226
    assign rightShiftStage1Idx1Rng4_uid20585_dupName_305_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20587_dupName_305_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20586)@226
    assign rightShiftStage1Idx1_uid20587_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20585_dupName_305_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20580_dupName_305_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20579)@226
    assign rightShiftStage0Idx1Rng1_uid20580_dupName_305_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q[33:1];

    // rightShiftStage0Idx1_uid20582_dupName_305_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20581)@226
    assign rightShiftStage0Idx1_uid20582_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20580_dupName_305_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27870_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(BITSELECT,27869)@225
    assign leftShiftStage2Idx1Rng8_uid27870_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in = leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27870_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27870_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27871_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(BITJOIN,27870)@225
    assign leftShiftStage2Idx1_uid27871_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27870_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27865_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(BITSELECT,27864)@225
    assign leftShiftStage1Idx1Rng4_uid27865_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in = leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27865_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27865_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27866_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(BITJOIN,27865)@225
    assign leftShiftStage1Idx1_uid27866_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27865_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27860_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(BITSELECT,27859)@225
    assign leftShiftStage0Idx1Rng1_uid27860_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27860_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27860_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27861_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(BITJOIN,27860)@225
    assign leftShiftStage0Idx1_uid27861_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27860_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20528_dupName_301_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20527)@224
    assign rightShiftStage2Idx1Rng8_uid20528_dupName_301_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20530_dupName_301_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20529)@224
    assign rightShiftStage2Idx1_uid20530_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20528_dupName_301_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20523_dupName_301_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20522)@224
    assign rightShiftStage1Idx1Rng4_uid20523_dupName_301_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20525_dupName_301_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20524)@224
    assign rightShiftStage1Idx1_uid20525_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20523_dupName_301_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20518_dupName_301_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20517)@224
    assign rightShiftStage0Idx1Rng1_uid20518_dupName_301_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q[33:1];

    // rightShiftStage0Idx1_uid20520_dupName_301_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20519)@224
    assign rightShiftStage0Idx1_uid20520_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20518_dupName_301_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27852_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(BITSELECT,27851)@223
    assign leftShiftStage2Idx1Rng8_uid27852_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in = leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27852_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27852_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27853_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(BITJOIN,27852)@223
    assign leftShiftStage2Idx1_uid27853_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27852_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27847_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(BITSELECT,27846)@223
    assign leftShiftStage1Idx1Rng4_uid27847_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in = leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27847_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27847_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27848_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(BITJOIN,27847)@223
    assign leftShiftStage1Idx1_uid27848_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27847_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27842_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(BITSELECT,27841)@223
    assign leftShiftStage0Idx1Rng1_uid27842_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27842_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27842_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27843_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(BITJOIN,27842)@223
    assign leftShiftStage0Idx1_uid27843_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27842_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20466_dupName_297_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20465)@222
    assign rightShiftStage2Idx1Rng8_uid20466_dupName_297_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20468_dupName_297_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20467)@222
    assign rightShiftStage2Idx1_uid20468_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20466_dupName_297_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20461_dupName_297_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20460)@222
    assign rightShiftStage1Idx1Rng4_uid20461_dupName_297_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20463_dupName_297_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20462)@222
    assign rightShiftStage1Idx1_uid20463_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20461_dupName_297_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20456_dupName_297_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20455)@222
    assign rightShiftStage0Idx1Rng1_uid20456_dupName_297_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q[33:1];

    // rightShiftStage0Idx1_uid20458_dupName_297_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20457)@222
    assign rightShiftStage0Idx1_uid20458_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20456_dupName_297_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27834_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(BITSELECT,27833)@221
    assign leftShiftStage2Idx1Rng8_uid27834_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in = leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27834_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27834_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27835_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(BITJOIN,27834)@221
    assign leftShiftStage2Idx1_uid27835_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27834_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27829_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(BITSELECT,27828)@221
    assign leftShiftStage1Idx1Rng4_uid27829_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in = leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27829_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27829_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27830_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(BITJOIN,27829)@221
    assign leftShiftStage1Idx1_uid27830_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27829_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27824_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(BITSELECT,27823)@221
    assign leftShiftStage0Idx1Rng1_uid27824_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27824_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27824_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27825_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(BITJOIN,27824)@221
    assign leftShiftStage0Idx1_uid27825_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27824_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20404_dupName_293_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20403)@220
    assign rightShiftStage2Idx1Rng8_uid20404_dupName_293_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20406_dupName_293_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20405)@220
    assign rightShiftStage2Idx1_uid20406_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20404_dupName_293_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20399_dupName_293_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20398)@220
    assign rightShiftStage1Idx1Rng4_uid20399_dupName_293_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20401_dupName_293_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20400)@220
    assign rightShiftStage1Idx1_uid20401_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20399_dupName_293_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20394_dupName_293_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20393)@220
    assign rightShiftStage0Idx1Rng1_uid20394_dupName_293_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q[33:1];

    // rightShiftStage0Idx1_uid20396_dupName_293_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20395)@220
    assign rightShiftStage0Idx1_uid20396_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20394_dupName_293_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27816_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(BITSELECT,27815)@219
    assign leftShiftStage2Idx1Rng8_uid27816_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in = leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27816_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27816_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27817_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(BITJOIN,27816)@219
    assign leftShiftStage2Idx1_uid27817_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27816_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27811_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(BITSELECT,27810)@219
    assign leftShiftStage1Idx1Rng4_uid27811_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in = leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27811_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27811_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27812_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(BITJOIN,27811)@219
    assign leftShiftStage1Idx1_uid27812_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27811_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27806_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(BITSELECT,27805)@219
    assign leftShiftStage0Idx1Rng1_uid27806_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27806_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27806_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27807_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(BITJOIN,27806)@219
    assign leftShiftStage0Idx1_uid27807_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27806_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20342_dupName_289_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20341)@218
    assign rightShiftStage2Idx1Rng8_uid20342_dupName_289_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20344_dupName_289_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20343)@218
    assign rightShiftStage2Idx1_uid20344_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20342_dupName_289_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20337_dupName_289_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20336)@218
    assign rightShiftStage1Idx1Rng4_uid20337_dupName_289_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20339_dupName_289_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20338)@218
    assign rightShiftStage1Idx1_uid20339_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20337_dupName_289_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20332_dupName_289_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20331)@218
    assign rightShiftStage0Idx1Rng1_uid20332_dupName_289_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q[33:1];

    // rightShiftStage0Idx1_uid20334_dupName_289_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20333)@218
    assign rightShiftStage0Idx1_uid20334_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20332_dupName_289_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27798_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(BITSELECT,27797)@217
    assign leftShiftStage2Idx1Rng8_uid27798_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in = leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27798_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27798_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27799_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(BITJOIN,27798)@217
    assign leftShiftStage2Idx1_uid27799_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27798_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27793_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(BITSELECT,27792)@217
    assign leftShiftStage1Idx1Rng4_uid27793_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in = leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27793_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27793_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27794_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(BITJOIN,27793)@217
    assign leftShiftStage1Idx1_uid27794_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27793_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27788_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(BITSELECT,27787)@217
    assign leftShiftStage0Idx1Rng1_uid27788_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27788_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27788_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27789_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(BITJOIN,27788)@217
    assign leftShiftStage0Idx1_uid27789_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27788_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20280_dupName_285_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20279)@216
    assign rightShiftStage2Idx1Rng8_uid20280_dupName_285_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20282_dupName_285_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20281)@216
    assign rightShiftStage2Idx1_uid20282_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20280_dupName_285_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20275_dupName_285_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20274)@216
    assign rightShiftStage1Idx1Rng4_uid20275_dupName_285_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20277_dupName_285_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20276)@216
    assign rightShiftStage1Idx1_uid20277_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20275_dupName_285_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20270_dupName_285_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20269)@216
    assign rightShiftStage0Idx1Rng1_uid20270_dupName_285_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q[33:1];

    // rightShiftStage0Idx1_uid20272_dupName_285_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20271)@216
    assign rightShiftStage0Idx1_uid20272_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20270_dupName_285_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27780_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(BITSELECT,27779)@215
    assign leftShiftStage2Idx1Rng8_uid27780_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in = leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27780_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27780_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27781_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(BITJOIN,27780)@215
    assign leftShiftStage2Idx1_uid27781_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27780_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27775_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(BITSELECT,27774)@215
    assign leftShiftStage1Idx1Rng4_uid27775_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in = leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27775_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27775_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27776_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(BITJOIN,27775)@215
    assign leftShiftStage1Idx1_uid27776_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27775_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27770_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(BITSELECT,27769)@215
    assign leftShiftStage0Idx1Rng1_uid27770_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27770_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27770_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27771_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(BITJOIN,27770)@215
    assign leftShiftStage0Idx1_uid27771_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27770_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20218_dupName_281_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20217)@214
    assign rightShiftStage2Idx1Rng8_uid20218_dupName_281_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20220_dupName_281_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20219)@214
    assign rightShiftStage2Idx1_uid20220_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20218_dupName_281_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20213_dupName_281_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20212)@214
    assign rightShiftStage1Idx1Rng4_uid20213_dupName_281_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20215_dupName_281_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20214)@214
    assign rightShiftStage1Idx1_uid20215_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20213_dupName_281_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20208_dupName_281_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20207)@214
    assign rightShiftStage0Idx1Rng1_uid20208_dupName_281_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q[33:1];

    // rightShiftStage0Idx1_uid20210_dupName_281_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20209)@214
    assign rightShiftStage0Idx1_uid20210_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20208_dupName_281_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27762_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(BITSELECT,27761)@213
    assign leftShiftStage2Idx1Rng8_uid27762_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in = leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27762_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27762_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27763_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(BITJOIN,27762)@213
    assign leftShiftStage2Idx1_uid27763_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27762_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27757_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(BITSELECT,27756)@213
    assign leftShiftStage1Idx1Rng4_uid27757_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in = leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27757_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27757_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27758_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(BITJOIN,27757)@213
    assign leftShiftStage1Idx1_uid27758_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27757_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27752_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(BITSELECT,27751)@213
    assign leftShiftStage0Idx1Rng1_uid27752_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27752_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27752_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27753_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(BITJOIN,27752)@213
    assign leftShiftStage0Idx1_uid27753_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27752_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20156_dupName_277_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20155)@212
    assign rightShiftStage2Idx1Rng8_uid20156_dupName_277_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20158_dupName_277_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20157)@212
    assign rightShiftStage2Idx1_uid20158_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20156_dupName_277_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20151_dupName_277_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20150)@212
    assign rightShiftStage1Idx1Rng4_uid20151_dupName_277_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20153_dupName_277_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20152)@212
    assign rightShiftStage1Idx1_uid20153_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20151_dupName_277_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20146_dupName_277_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20145)@212
    assign rightShiftStage0Idx1Rng1_uid20146_dupName_277_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q[33:1];

    // rightShiftStage0Idx1_uid20148_dupName_277_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20147)@212
    assign rightShiftStage0Idx1_uid20148_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20146_dupName_277_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27726_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(BITSELECT,27725)@211
    assign leftShiftStage2Idx1Rng8_uid27726_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in = leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27726_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27726_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27727_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(BITJOIN,27726)@211
    assign leftShiftStage2Idx1_uid27727_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27726_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27721_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(BITSELECT,27720)@211
    assign leftShiftStage1Idx1Rng4_uid27721_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in = leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27721_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27721_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27722_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(BITJOIN,27721)@211
    assign leftShiftStage1Idx1_uid27722_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27721_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27716_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(BITSELECT,27715)@211
    assign leftShiftStage0Idx1Rng1_uid27716_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27716_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27716_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27717_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(BITJOIN,27716)@211
    assign leftShiftStage0Idx1_uid27717_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27716_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20094_dupName_273_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20093)@210
    assign rightShiftStage2Idx1Rng8_uid20094_dupName_273_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20096_dupName_273_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20095)@210
    assign rightShiftStage2Idx1_uid20096_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20094_dupName_273_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20089_dupName_273_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20088)@210
    assign rightShiftStage1Idx1Rng4_uid20089_dupName_273_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20091_dupName_273_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20090)@210
    assign rightShiftStage1Idx1_uid20091_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20089_dupName_273_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20084_dupName_273_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20083)@210
    assign rightShiftStage0Idx1Rng1_uid20084_dupName_273_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q[33:1];

    // rightShiftStage0Idx1_uid20086_dupName_273_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20085)@210
    assign rightShiftStage0Idx1_uid20086_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20084_dupName_273_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27708_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(BITSELECT,27707)@209
    assign leftShiftStage2Idx1Rng8_uid27708_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in = leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27708_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27708_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27709_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(BITJOIN,27708)@209
    assign leftShiftStage2Idx1_uid27709_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27708_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27703_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(BITSELECT,27702)@209
    assign leftShiftStage1Idx1Rng4_uid27703_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in = leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27703_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27703_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27704_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(BITJOIN,27703)@209
    assign leftShiftStage1Idx1_uid27704_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27703_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27698_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(BITSELECT,27697)@209
    assign leftShiftStage0Idx1Rng1_uid27698_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27698_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27698_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27699_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(BITJOIN,27698)@209
    assign leftShiftStage0Idx1_uid27699_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27698_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20032_dupName_269_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20031)@208
    assign rightShiftStage2Idx1Rng8_uid20032_dupName_269_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20034_dupName_269_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20033)@208
    assign rightShiftStage2Idx1_uid20034_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20032_dupName_269_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20027_dupName_269_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20026)@208
    assign rightShiftStage1Idx1Rng4_uid20027_dupName_269_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20029_dupName_269_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20028)@208
    assign rightShiftStage1Idx1_uid20029_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20027_dupName_269_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20022_dupName_269_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20021)@208
    assign rightShiftStage0Idx1Rng1_uid20022_dupName_269_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q[33:1];

    // rightShiftStage0Idx1_uid20024_dupName_269_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20023)@208
    assign rightShiftStage0Idx1_uid20024_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20022_dupName_269_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27690_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(BITSELECT,27689)@207
    assign leftShiftStage2Idx1Rng8_uid27690_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in = leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27690_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27690_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27691_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(BITJOIN,27690)@207
    assign leftShiftStage2Idx1_uid27691_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27690_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27685_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(BITSELECT,27684)@207
    assign leftShiftStage1Idx1Rng4_uid27685_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in = leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27685_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27685_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27686_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(BITJOIN,27685)@207
    assign leftShiftStage1Idx1_uid27686_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27685_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27680_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(BITSELECT,27679)@207
    assign leftShiftStage0Idx1Rng1_uid27680_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27680_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27680_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27681_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(BITJOIN,27680)@207
    assign leftShiftStage0Idx1_uid27681_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27680_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19970_dupName_265_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19969)@206
    assign rightShiftStage2Idx1Rng8_uid19970_dupName_265_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19972_dupName_265_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19971)@206
    assign rightShiftStage2Idx1_uid19972_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19970_dupName_265_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19965_dupName_265_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19964)@206
    assign rightShiftStage1Idx1Rng4_uid19965_dupName_265_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19967_dupName_265_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19966)@206
    assign rightShiftStage1Idx1_uid19967_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19965_dupName_265_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19960_dupName_265_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19959)@206
    assign rightShiftStage0Idx1Rng1_uid19960_dupName_265_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q[33:1];

    // rightShiftStage0Idx1_uid19962_dupName_265_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19961)@206
    assign rightShiftStage0Idx1_uid19962_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19960_dupName_265_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27672_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(BITSELECT,27671)@205
    assign leftShiftStage2Idx1Rng8_uid27672_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in = leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27672_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27672_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27673_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(BITJOIN,27672)@205
    assign leftShiftStage2Idx1_uid27673_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27672_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27667_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(BITSELECT,27666)@205
    assign leftShiftStage1Idx1Rng4_uid27667_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in = leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27667_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27667_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27668_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(BITJOIN,27667)@205
    assign leftShiftStage1Idx1_uid27668_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27667_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27662_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(BITSELECT,27661)@205
    assign leftShiftStage0Idx1Rng1_uid27662_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27662_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27662_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27663_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(BITJOIN,27662)@205
    assign leftShiftStage0Idx1_uid27663_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27662_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19908_dupName_261_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19907)@204
    assign rightShiftStage2Idx1Rng8_uid19908_dupName_261_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19910_dupName_261_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19909)@204
    assign rightShiftStage2Idx1_uid19910_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19908_dupName_261_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19903_dupName_261_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19902)@204
    assign rightShiftStage1Idx1Rng4_uid19903_dupName_261_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19905_dupName_261_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19904)@204
    assign rightShiftStage1Idx1_uid19905_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19903_dupName_261_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19898_dupName_261_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19897)@204
    assign rightShiftStage0Idx1Rng1_uid19898_dupName_261_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q[33:1];

    // rightShiftStage0Idx1_uid19900_dupName_261_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19899)@204
    assign rightShiftStage0Idx1_uid19900_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19898_dupName_261_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27654_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(BITSELECT,27653)@203
    assign leftShiftStage2Idx1Rng8_uid27654_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in = leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27654_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27654_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27655_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(BITJOIN,27654)@203
    assign leftShiftStage2Idx1_uid27655_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27654_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27649_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(BITSELECT,27648)@203
    assign leftShiftStage1Idx1Rng4_uid27649_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in = leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27649_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27649_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27650_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(BITJOIN,27649)@203
    assign leftShiftStage1Idx1_uid27650_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27649_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27644_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(BITSELECT,27643)@203
    assign leftShiftStage0Idx1Rng1_uid27644_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27644_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27644_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27645_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(BITJOIN,27644)@203
    assign leftShiftStage0Idx1_uid27645_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27644_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19846_dupName_257_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19845)@202
    assign rightShiftStage2Idx1Rng8_uid19846_dupName_257_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19848_dupName_257_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19847)@202
    assign rightShiftStage2Idx1_uid19848_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19846_dupName_257_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19841_dupName_257_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19840)@202
    assign rightShiftStage1Idx1Rng4_uid19841_dupName_257_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19843_dupName_257_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19842)@202
    assign rightShiftStage1Idx1_uid19843_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19841_dupName_257_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19836_dupName_257_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19835)@202
    assign rightShiftStage0Idx1Rng1_uid19836_dupName_257_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q[33:1];

    // rightShiftStage0Idx1_uid19838_dupName_257_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19837)@202
    assign rightShiftStage0Idx1_uid19838_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19836_dupName_257_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27636_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(BITSELECT,27635)@201
    assign leftShiftStage2Idx1Rng8_uid27636_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in = leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27636_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27636_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27637_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(BITJOIN,27636)@201
    assign leftShiftStage2Idx1_uid27637_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27636_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27631_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(BITSELECT,27630)@201
    assign leftShiftStage1Idx1Rng4_uid27631_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in = leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27631_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27631_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27632_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(BITJOIN,27631)@201
    assign leftShiftStage1Idx1_uid27632_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27631_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27626_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(BITSELECT,27625)@201
    assign leftShiftStage0Idx1Rng1_uid27626_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27626_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27626_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27627_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(BITJOIN,27626)@201
    assign leftShiftStage0Idx1_uid27627_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27626_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19784_dupName_253_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19783)@200
    assign rightShiftStage2Idx1Rng8_uid19784_dupName_253_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19786_dupName_253_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19785)@200
    assign rightShiftStage2Idx1_uid19786_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19784_dupName_253_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19779_dupName_253_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19778)@200
    assign rightShiftStage1Idx1Rng4_uid19779_dupName_253_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19781_dupName_253_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19780)@200
    assign rightShiftStage1Idx1_uid19781_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19779_dupName_253_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19774_dupName_253_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19773)@200
    assign rightShiftStage0Idx1Rng1_uid19774_dupName_253_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q[33:1];

    // rightShiftStage0Idx1_uid19776_dupName_253_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19775)@200
    assign rightShiftStage0Idx1_uid19776_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19774_dupName_253_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27618_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(BITSELECT,27617)@199
    assign leftShiftStage2Idx1Rng8_uid27618_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in = leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27618_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27618_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27619_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(BITJOIN,27618)@199
    assign leftShiftStage2Idx1_uid27619_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27618_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27613_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(BITSELECT,27612)@199
    assign leftShiftStage1Idx1Rng4_uid27613_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in = leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27613_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27613_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27614_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(BITJOIN,27613)@199
    assign leftShiftStage1Idx1_uid27614_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27613_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27608_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(BITSELECT,27607)@199
    assign leftShiftStage0Idx1Rng1_uid27608_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27608_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27608_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27609_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(BITJOIN,27608)@199
    assign leftShiftStage0Idx1_uid27609_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27608_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19722_dupName_249_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19721)@198
    assign rightShiftStage2Idx1Rng8_uid19722_dupName_249_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19724_dupName_249_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19723)@198
    assign rightShiftStage2Idx1_uid19724_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19722_dupName_249_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19717_dupName_249_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19716)@198
    assign rightShiftStage1Idx1Rng4_uid19717_dupName_249_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19719_dupName_249_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19718)@198
    assign rightShiftStage1Idx1_uid19719_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19717_dupName_249_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19712_dupName_249_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19711)@198
    assign rightShiftStage0Idx1Rng1_uid19712_dupName_249_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q[33:1];

    // rightShiftStage0Idx1_uid19714_dupName_249_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19713)@198
    assign rightShiftStage0Idx1_uid19714_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19712_dupName_249_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27600_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(BITSELECT,27599)@197
    assign leftShiftStage2Idx1Rng8_uid27600_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in = leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27600_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27600_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27601_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(BITJOIN,27600)@197
    assign leftShiftStage2Idx1_uid27601_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27600_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27595_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(BITSELECT,27594)@197
    assign leftShiftStage1Idx1Rng4_uid27595_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in = leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27595_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27595_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27596_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(BITJOIN,27595)@197
    assign leftShiftStage1Idx1_uid27596_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27595_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27590_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(BITSELECT,27589)@197
    assign leftShiftStage0Idx1Rng1_uid27590_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27590_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27590_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27591_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(BITJOIN,27590)@197
    assign leftShiftStage0Idx1_uid27591_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27590_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19660_dupName_245_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19659)@196
    assign rightShiftStage2Idx1Rng8_uid19660_dupName_245_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19662_dupName_245_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19661)@196
    assign rightShiftStage2Idx1_uid19662_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19660_dupName_245_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19655_dupName_245_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19654)@196
    assign rightShiftStage1Idx1Rng4_uid19655_dupName_245_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19657_dupName_245_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19656)@196
    assign rightShiftStage1Idx1_uid19657_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19655_dupName_245_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19650_dupName_245_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19649)@196
    assign rightShiftStage0Idx1Rng1_uid19650_dupName_245_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q[33:1];

    // rightShiftStage0Idx1_uid19652_dupName_245_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19651)@196
    assign rightShiftStage0Idx1_uid19652_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19650_dupName_245_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27582_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(BITSELECT,27581)@195
    assign leftShiftStage2Idx1Rng8_uid27582_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in = leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27582_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27582_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27583_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(BITJOIN,27582)@195
    assign leftShiftStage2Idx1_uid27583_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27582_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27577_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(BITSELECT,27576)@195
    assign leftShiftStage1Idx1Rng4_uid27577_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in = leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27577_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27577_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27578_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(BITJOIN,27577)@195
    assign leftShiftStage1Idx1_uid27578_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27577_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27572_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(BITSELECT,27571)@195
    assign leftShiftStage0Idx1Rng1_uid27572_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27572_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27572_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27573_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(BITJOIN,27572)@195
    assign leftShiftStage0Idx1_uid27573_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27572_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19598_dupName_241_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19597)@194
    assign rightShiftStage2Idx1Rng8_uid19598_dupName_241_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19600_dupName_241_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19599)@194
    assign rightShiftStage2Idx1_uid19600_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19598_dupName_241_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19593_dupName_241_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19592)@194
    assign rightShiftStage1Idx1Rng4_uid19593_dupName_241_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19595_dupName_241_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19594)@194
    assign rightShiftStage1Idx1_uid19595_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19593_dupName_241_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19588_dupName_241_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19587)@194
    assign rightShiftStage0Idx1Rng1_uid19588_dupName_241_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q[33:1];

    // rightShiftStage0Idx1_uid19590_dupName_241_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19589)@194
    assign rightShiftStage0Idx1_uid19590_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19588_dupName_241_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27564_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(BITSELECT,27563)@193
    assign leftShiftStage2Idx1Rng8_uid27564_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in = leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27564_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27564_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27565_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(BITJOIN,27564)@193
    assign leftShiftStage2Idx1_uid27565_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27564_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27559_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(BITSELECT,27558)@193
    assign leftShiftStage1Idx1Rng4_uid27559_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in = leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27559_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27559_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27560_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(BITJOIN,27559)@193
    assign leftShiftStage1Idx1_uid27560_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27559_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27554_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(BITSELECT,27553)@193
    assign leftShiftStage0Idx1Rng1_uid27554_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27554_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27554_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27555_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(BITJOIN,27554)@193
    assign leftShiftStage0Idx1_uid27555_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27554_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19536_dupName_237_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19535)@192
    assign rightShiftStage2Idx1Rng8_uid19536_dupName_237_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19538_dupName_237_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19537)@192
    assign rightShiftStage2Idx1_uid19538_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19536_dupName_237_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19531_dupName_237_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19530)@192
    assign rightShiftStage1Idx1Rng4_uid19531_dupName_237_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19533_dupName_237_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19532)@192
    assign rightShiftStage1Idx1_uid19533_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19531_dupName_237_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19526_dupName_237_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19525)@192
    assign rightShiftStage0Idx1Rng1_uid19526_dupName_237_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q[33:1];

    // rightShiftStage0Idx1_uid19528_dupName_237_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19527)@192
    assign rightShiftStage0Idx1_uid19528_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19526_dupName_237_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27528_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(BITSELECT,27527)@191
    assign leftShiftStage2Idx1Rng8_uid27528_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in = leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27528_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27528_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27529_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(BITJOIN,27528)@191
    assign leftShiftStage2Idx1_uid27529_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27528_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27523_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(BITSELECT,27522)@191
    assign leftShiftStage1Idx1Rng4_uid27523_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in = leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27523_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27523_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27524_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(BITJOIN,27523)@191
    assign leftShiftStage1Idx1_uid27524_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27523_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27518_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(BITSELECT,27517)@191
    assign leftShiftStage0Idx1Rng1_uid27518_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27518_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27518_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27519_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(BITJOIN,27518)@191
    assign leftShiftStage0Idx1_uid27519_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27518_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19474_dupName_233_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19473)@190
    assign rightShiftStage2Idx1Rng8_uid19474_dupName_233_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19476_dupName_233_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19475)@190
    assign rightShiftStage2Idx1_uid19476_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19474_dupName_233_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19469_dupName_233_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19468)@190
    assign rightShiftStage1Idx1Rng4_uid19469_dupName_233_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19471_dupName_233_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19470)@190
    assign rightShiftStage1Idx1_uid19471_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19469_dupName_233_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19464_dupName_233_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19463)@190
    assign rightShiftStage0Idx1Rng1_uid19464_dupName_233_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q[33:1];

    // rightShiftStage0Idx1_uid19466_dupName_233_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19465)@190
    assign rightShiftStage0Idx1_uid19466_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19464_dupName_233_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27510_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(BITSELECT,27509)@189
    assign leftShiftStage2Idx1Rng8_uid27510_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in = leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27510_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27510_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27511_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(BITJOIN,27510)@189
    assign leftShiftStage2Idx1_uid27511_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27510_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27505_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(BITSELECT,27504)@189
    assign leftShiftStage1Idx1Rng4_uid27505_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in = leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27505_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27505_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27506_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(BITJOIN,27505)@189
    assign leftShiftStage1Idx1_uid27506_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27505_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27500_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(BITSELECT,27499)@189
    assign leftShiftStage0Idx1Rng1_uid27500_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27500_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27500_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27501_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(BITJOIN,27500)@189
    assign leftShiftStage0Idx1_uid27501_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27500_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19412_dupName_229_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19411)@188
    assign rightShiftStage2Idx1Rng8_uid19412_dupName_229_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19414_dupName_229_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19413)@188
    assign rightShiftStage2Idx1_uid19414_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19412_dupName_229_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19407_dupName_229_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19406)@188
    assign rightShiftStage1Idx1Rng4_uid19407_dupName_229_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19409_dupName_229_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19408)@188
    assign rightShiftStage1Idx1_uid19409_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19407_dupName_229_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19402_dupName_229_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19401)@188
    assign rightShiftStage0Idx1Rng1_uid19402_dupName_229_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q[33:1];

    // rightShiftStage0Idx1_uid19404_dupName_229_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19403)@188
    assign rightShiftStage0Idx1_uid19404_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19402_dupName_229_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27492_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(BITSELECT,27491)@187
    assign leftShiftStage2Idx1Rng8_uid27492_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in = leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27492_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27492_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27493_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(BITJOIN,27492)@187
    assign leftShiftStage2Idx1_uid27493_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27492_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27487_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(BITSELECT,27486)@187
    assign leftShiftStage1Idx1Rng4_uid27487_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in = leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27487_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27487_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27488_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(BITJOIN,27487)@187
    assign leftShiftStage1Idx1_uid27488_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27487_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27482_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(BITSELECT,27481)@187
    assign leftShiftStage0Idx1Rng1_uid27482_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27482_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27482_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27483_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(BITJOIN,27482)@187
    assign leftShiftStage0Idx1_uid27483_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27482_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19350_dupName_225_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19349)@186
    assign rightShiftStage2Idx1Rng8_uid19350_dupName_225_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19352_dupName_225_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19351)@186
    assign rightShiftStage2Idx1_uid19352_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19350_dupName_225_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19345_dupName_225_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19344)@186
    assign rightShiftStage1Idx1Rng4_uid19345_dupName_225_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19347_dupName_225_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19346)@186
    assign rightShiftStage1Idx1_uid19347_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19345_dupName_225_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19340_dupName_225_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19339)@186
    assign rightShiftStage0Idx1Rng1_uid19340_dupName_225_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q[33:1];

    // rightShiftStage0Idx1_uid19342_dupName_225_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19341)@186
    assign rightShiftStage0Idx1_uid19342_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19340_dupName_225_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27474_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(BITSELECT,27473)@185
    assign leftShiftStage2Idx1Rng8_uid27474_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in = leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27474_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27474_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27475_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(BITJOIN,27474)@185
    assign leftShiftStage2Idx1_uid27475_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27474_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27469_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(BITSELECT,27468)@185
    assign leftShiftStage1Idx1Rng4_uid27469_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in = leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27469_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27469_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27470_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(BITJOIN,27469)@185
    assign leftShiftStage1Idx1_uid27470_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27469_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27464_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(BITSELECT,27463)@185
    assign leftShiftStage0Idx1Rng1_uid27464_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27464_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27464_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27465_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(BITJOIN,27464)@185
    assign leftShiftStage0Idx1_uid27465_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27464_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19288_dupName_221_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19287)@184
    assign rightShiftStage2Idx1Rng8_uid19288_dupName_221_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19290_dupName_221_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19289)@184
    assign rightShiftStage2Idx1_uid19290_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19288_dupName_221_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19283_dupName_221_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19282)@184
    assign rightShiftStage1Idx1Rng4_uid19283_dupName_221_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19285_dupName_221_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19284)@184
    assign rightShiftStage1Idx1_uid19285_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19283_dupName_221_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19278_dupName_221_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19277)@184
    assign rightShiftStage0Idx1Rng1_uid19278_dupName_221_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q[33:1];

    // rightShiftStage0Idx1_uid19280_dupName_221_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19279)@184
    assign rightShiftStage0Idx1_uid19280_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19278_dupName_221_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27456_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(BITSELECT,27455)@183
    assign leftShiftStage2Idx1Rng8_uid27456_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in = leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27456_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27456_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27457_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(BITJOIN,27456)@183
    assign leftShiftStage2Idx1_uid27457_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27456_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27451_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(BITSELECT,27450)@183
    assign leftShiftStage1Idx1Rng4_uid27451_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in = leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27451_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27451_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27452_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(BITJOIN,27451)@183
    assign leftShiftStage1Idx1_uid27452_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27451_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27446_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(BITSELECT,27445)@183
    assign leftShiftStage0Idx1Rng1_uid27446_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27446_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27446_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27447_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(BITJOIN,27446)@183
    assign leftShiftStage0Idx1_uid27447_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27446_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19226_dupName_217_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19225)@182
    assign rightShiftStage2Idx1Rng8_uid19226_dupName_217_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19228_dupName_217_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19227)@182
    assign rightShiftStage2Idx1_uid19228_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19226_dupName_217_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19221_dupName_217_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19220)@182
    assign rightShiftStage1Idx1Rng4_uid19221_dupName_217_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19223_dupName_217_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19222)@182
    assign rightShiftStage1Idx1_uid19223_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19221_dupName_217_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19216_dupName_217_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19215)@182
    assign rightShiftStage0Idx1Rng1_uid19216_dupName_217_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q[33:1];

    // rightShiftStage0Idx1_uid19218_dupName_217_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19217)@182
    assign rightShiftStage0Idx1_uid19218_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19216_dupName_217_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27438_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(BITSELECT,27437)@181
    assign leftShiftStage2Idx1Rng8_uid27438_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in = leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27438_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27438_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27439_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(BITJOIN,27438)@181
    assign leftShiftStage2Idx1_uid27439_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27438_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27433_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(BITSELECT,27432)@181
    assign leftShiftStage1Idx1Rng4_uid27433_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in = leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27433_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27433_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27434_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(BITJOIN,27433)@181
    assign leftShiftStage1Idx1_uid27434_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27433_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27428_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(BITSELECT,27427)@181
    assign leftShiftStage0Idx1Rng1_uid27428_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27428_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27428_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27429_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(BITJOIN,27428)@181
    assign leftShiftStage0Idx1_uid27429_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27428_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19164_dupName_213_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19163)@180
    assign rightShiftStage2Idx1Rng8_uid19164_dupName_213_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19166_dupName_213_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19165)@180
    assign rightShiftStage2Idx1_uid19166_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19164_dupName_213_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19159_dupName_213_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19158)@180
    assign rightShiftStage1Idx1Rng4_uid19159_dupName_213_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19161_dupName_213_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19160)@180
    assign rightShiftStage1Idx1_uid19161_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19159_dupName_213_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19154_dupName_213_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19153)@180
    assign rightShiftStage0Idx1Rng1_uid19154_dupName_213_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q[33:1];

    // rightShiftStage0Idx1_uid19156_dupName_213_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19155)@180
    assign rightShiftStage0Idx1_uid19156_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19154_dupName_213_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27420_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(BITSELECT,27419)@179
    assign leftShiftStage2Idx1Rng8_uid27420_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in = leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27420_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27420_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27421_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(BITJOIN,27420)@179
    assign leftShiftStage2Idx1_uid27421_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27420_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27415_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(BITSELECT,27414)@179
    assign leftShiftStage1Idx1Rng4_uid27415_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in = leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27415_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27415_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27416_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(BITJOIN,27415)@179
    assign leftShiftStage1Idx1_uid27416_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27415_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27410_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(BITSELECT,27409)@179
    assign leftShiftStage0Idx1Rng1_uid27410_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27410_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27410_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27411_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(BITJOIN,27410)@179
    assign leftShiftStage0Idx1_uid27411_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27410_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19102_dupName_209_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19101)@178
    assign rightShiftStage2Idx1Rng8_uid19102_dupName_209_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19104_dupName_209_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19103)@178
    assign rightShiftStage2Idx1_uid19104_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19102_dupName_209_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19097_dupName_209_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19096)@178
    assign rightShiftStage1Idx1Rng4_uid19097_dupName_209_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19099_dupName_209_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19098)@178
    assign rightShiftStage1Idx1_uid19099_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19097_dupName_209_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19092_dupName_209_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19091)@178
    assign rightShiftStage0Idx1Rng1_uid19092_dupName_209_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q[33:1];

    // rightShiftStage0Idx1_uid19094_dupName_209_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19093)@178
    assign rightShiftStage0Idx1_uid19094_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19092_dupName_209_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27402_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(BITSELECT,27401)@177
    assign leftShiftStage2Idx1Rng8_uid27402_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in = leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27402_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27402_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27403_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(BITJOIN,27402)@177
    assign leftShiftStage2Idx1_uid27403_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27402_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27397_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(BITSELECT,27396)@177
    assign leftShiftStage1Idx1Rng4_uid27397_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in = leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27397_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27397_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27398_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(BITJOIN,27397)@177
    assign leftShiftStage1Idx1_uid27398_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27397_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27392_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(BITSELECT,27391)@177
    assign leftShiftStage0Idx1Rng1_uid27392_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27392_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27392_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27393_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(BITJOIN,27392)@177
    assign leftShiftStage0Idx1_uid27393_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27392_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19040_dupName_205_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19039)@176
    assign rightShiftStage2Idx1Rng8_uid19040_dupName_205_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19042_dupName_205_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19041)@176
    assign rightShiftStage2Idx1_uid19042_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19040_dupName_205_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19035_dupName_205_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19034)@176
    assign rightShiftStage1Idx1Rng4_uid19035_dupName_205_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19037_dupName_205_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19036)@176
    assign rightShiftStage1Idx1_uid19037_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19035_dupName_205_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19030_dupName_205_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19029)@176
    assign rightShiftStage0Idx1Rng1_uid19030_dupName_205_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q[33:1];

    // rightShiftStage0Idx1_uid19032_dupName_205_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19031)@176
    assign rightShiftStage0Idx1_uid19032_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19030_dupName_205_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27384_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(BITSELECT,27383)@175
    assign leftShiftStage2Idx1Rng8_uid27384_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in = leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27384_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27384_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27385_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(BITJOIN,27384)@175
    assign leftShiftStage2Idx1_uid27385_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27384_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27379_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(BITSELECT,27378)@175
    assign leftShiftStage1Idx1Rng4_uid27379_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in = leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27379_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27379_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27380_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(BITJOIN,27379)@175
    assign leftShiftStage1Idx1_uid27380_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27379_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27374_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(BITSELECT,27373)@175
    assign leftShiftStage0Idx1Rng1_uid27374_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27374_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27374_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27375_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(BITJOIN,27374)@175
    assign leftShiftStage0Idx1_uid27375_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27374_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18978_dupName_201_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18977)@174
    assign rightShiftStage2Idx1Rng8_uid18978_dupName_201_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18980_dupName_201_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18979)@174
    assign rightShiftStage2Idx1_uid18980_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18978_dupName_201_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18973_dupName_201_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18972)@174
    assign rightShiftStage1Idx1Rng4_uid18973_dupName_201_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18975_dupName_201_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18974)@174
    assign rightShiftStage1Idx1_uid18975_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18973_dupName_201_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18968_dupName_201_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18967)@174
    assign rightShiftStage0Idx1Rng1_uid18968_dupName_201_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q[33:1];

    // rightShiftStage0Idx1_uid18970_dupName_201_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18969)@174
    assign rightShiftStage0Idx1_uid18970_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18968_dupName_201_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27366_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(BITSELECT,27365)@173
    assign leftShiftStage2Idx1Rng8_uid27366_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in = leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27366_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27366_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27367_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(BITJOIN,27366)@173
    assign leftShiftStage2Idx1_uid27367_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27366_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27361_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(BITSELECT,27360)@173
    assign leftShiftStage1Idx1Rng4_uid27361_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in = leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27361_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27361_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27362_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(BITJOIN,27361)@173
    assign leftShiftStage1Idx1_uid27362_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27361_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27356_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(BITSELECT,27355)@173
    assign leftShiftStage0Idx1Rng1_uid27356_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27356_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27356_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27357_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(BITJOIN,27356)@173
    assign leftShiftStage0Idx1_uid27357_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27356_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18916_dupName_197_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18915)@172
    assign rightShiftStage2Idx1Rng8_uid18916_dupName_197_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18918_dupName_197_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18917)@172
    assign rightShiftStage2Idx1_uid18918_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18916_dupName_197_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18911_dupName_197_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18910)@172
    assign rightShiftStage1Idx1Rng4_uid18911_dupName_197_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18913_dupName_197_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18912)@172
    assign rightShiftStage1Idx1_uid18913_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18911_dupName_197_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18906_dupName_197_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18905)@172
    assign rightShiftStage0Idx1Rng1_uid18906_dupName_197_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q[33:1];

    // rightShiftStage0Idx1_uid18908_dupName_197_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18907)@172
    assign rightShiftStage0Idx1_uid18908_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18906_dupName_197_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27330_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(BITSELECT,27329)@171
    assign leftShiftStage2Idx1Rng8_uid27330_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in = leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27330_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27330_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27331_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(BITJOIN,27330)@171
    assign leftShiftStage2Idx1_uid27331_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27330_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27325_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(BITSELECT,27324)@171
    assign leftShiftStage1Idx1Rng4_uid27325_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in = leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27325_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27325_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27326_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(BITJOIN,27325)@171
    assign leftShiftStage1Idx1_uid27326_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27325_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27320_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(BITSELECT,27319)@171
    assign leftShiftStage0Idx1Rng1_uid27320_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27320_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27320_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27321_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(BITJOIN,27320)@171
    assign leftShiftStage0Idx1_uid27321_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27320_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18854_dupName_193_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18853)@170
    assign rightShiftStage2Idx1Rng8_uid18854_dupName_193_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18856_dupName_193_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18855)@170
    assign rightShiftStage2Idx1_uid18856_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18854_dupName_193_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18849_dupName_193_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18848)@170
    assign rightShiftStage1Idx1Rng4_uid18849_dupName_193_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18851_dupName_193_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18850)@170
    assign rightShiftStage1Idx1_uid18851_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18849_dupName_193_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18844_dupName_193_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18843)@170
    assign rightShiftStage0Idx1Rng1_uid18844_dupName_193_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q[33:1];

    // rightShiftStage0Idx1_uid18846_dupName_193_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18845)@170
    assign rightShiftStage0Idx1_uid18846_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18844_dupName_193_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27312_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(BITSELECT,27311)@169
    assign leftShiftStage2Idx1Rng8_uid27312_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in = leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27312_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27312_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27313_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(BITJOIN,27312)@169
    assign leftShiftStage2Idx1_uid27313_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27312_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27307_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(BITSELECT,27306)@169
    assign leftShiftStage1Idx1Rng4_uid27307_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in = leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27307_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27307_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27308_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(BITJOIN,27307)@169
    assign leftShiftStage1Idx1_uid27308_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27307_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27302_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(BITSELECT,27301)@169
    assign leftShiftStage0Idx1Rng1_uid27302_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27302_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27302_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27303_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(BITJOIN,27302)@169
    assign leftShiftStage0Idx1_uid27303_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27302_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18792_dupName_189_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18791)@168
    assign rightShiftStage2Idx1Rng8_uid18792_dupName_189_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18794_dupName_189_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18793)@168
    assign rightShiftStage2Idx1_uid18794_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18792_dupName_189_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18787_dupName_189_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18786)@168
    assign rightShiftStage1Idx1Rng4_uid18787_dupName_189_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18789_dupName_189_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18788)@168
    assign rightShiftStage1Idx1_uid18789_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18787_dupName_189_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18782_dupName_189_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18781)@168
    assign rightShiftStage0Idx1Rng1_uid18782_dupName_189_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q[33:1];

    // rightShiftStage0Idx1_uid18784_dupName_189_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18783)@168
    assign rightShiftStage0Idx1_uid18784_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18782_dupName_189_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27294_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(BITSELECT,27293)@167
    assign leftShiftStage2Idx1Rng8_uid27294_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in = leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27294_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27294_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27295_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(BITJOIN,27294)@167
    assign leftShiftStage2Idx1_uid27295_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27294_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27289_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(BITSELECT,27288)@167
    assign leftShiftStage1Idx1Rng4_uid27289_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in = leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27289_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27289_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27290_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(BITJOIN,27289)@167
    assign leftShiftStage1Idx1_uid27290_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27289_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27284_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(BITSELECT,27283)@167
    assign leftShiftStage0Idx1Rng1_uid27284_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27284_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27284_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27285_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(BITJOIN,27284)@167
    assign leftShiftStage0Idx1_uid27285_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27284_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18730_dupName_185_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18729)@166
    assign rightShiftStage2Idx1Rng8_uid18730_dupName_185_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18732_dupName_185_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18731)@166
    assign rightShiftStage2Idx1_uid18732_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18730_dupName_185_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18725_dupName_185_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18724)@166
    assign rightShiftStage1Idx1Rng4_uid18725_dupName_185_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18727_dupName_185_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18726)@166
    assign rightShiftStage1Idx1_uid18727_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18725_dupName_185_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18720_dupName_185_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18719)@166
    assign rightShiftStage0Idx1Rng1_uid18720_dupName_185_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q[33:1];

    // rightShiftStage0Idx1_uid18722_dupName_185_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18721)@166
    assign rightShiftStage0Idx1_uid18722_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18720_dupName_185_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27276_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(BITSELECT,27275)@165
    assign leftShiftStage2Idx1Rng8_uid27276_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in = leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27276_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27276_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27277_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(BITJOIN,27276)@165
    assign leftShiftStage2Idx1_uid27277_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27276_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27271_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(BITSELECT,27270)@165
    assign leftShiftStage1Idx1Rng4_uid27271_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in = leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27271_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27271_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27272_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(BITJOIN,27271)@165
    assign leftShiftStage1Idx1_uid27272_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27271_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27266_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(BITSELECT,27265)@165
    assign leftShiftStage0Idx1Rng1_uid27266_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27266_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27266_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27267_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(BITJOIN,27266)@165
    assign leftShiftStage0Idx1_uid27267_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27266_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18668_dupName_181_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18667)@164
    assign rightShiftStage2Idx1Rng8_uid18668_dupName_181_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18670_dupName_181_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18669)@164
    assign rightShiftStage2Idx1_uid18670_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18668_dupName_181_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18663_dupName_181_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18662)@164
    assign rightShiftStage1Idx1Rng4_uid18663_dupName_181_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18665_dupName_181_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18664)@164
    assign rightShiftStage1Idx1_uid18665_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18663_dupName_181_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18658_dupName_181_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18657)@164
    assign rightShiftStage0Idx1Rng1_uid18658_dupName_181_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q[33:1];

    // rightShiftStage0Idx1_uid18660_dupName_181_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18659)@164
    assign rightShiftStage0Idx1_uid18660_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18658_dupName_181_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27258_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(BITSELECT,27257)@163
    assign leftShiftStage2Idx1Rng8_uid27258_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in = leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27258_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27258_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27259_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(BITJOIN,27258)@163
    assign leftShiftStage2Idx1_uid27259_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27258_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27253_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(BITSELECT,27252)@163
    assign leftShiftStage1Idx1Rng4_uid27253_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in = leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27253_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27253_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27254_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(BITJOIN,27253)@163
    assign leftShiftStage1Idx1_uid27254_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27253_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27248_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(BITSELECT,27247)@163
    assign leftShiftStage0Idx1Rng1_uid27248_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27248_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27248_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27249_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(BITJOIN,27248)@163
    assign leftShiftStage0Idx1_uid27249_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27248_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18606_dupName_177_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18605)@162
    assign rightShiftStage2Idx1Rng8_uid18606_dupName_177_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18608_dupName_177_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18607)@162
    assign rightShiftStage2Idx1_uid18608_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18606_dupName_177_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18601_dupName_177_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18600)@162
    assign rightShiftStage1Idx1Rng4_uid18601_dupName_177_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18603_dupName_177_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18602)@162
    assign rightShiftStage1Idx1_uid18603_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18601_dupName_177_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18596_dupName_177_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18595)@162
    assign rightShiftStage0Idx1Rng1_uid18596_dupName_177_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q[33:1];

    // rightShiftStage0Idx1_uid18598_dupName_177_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18597)@162
    assign rightShiftStage0Idx1_uid18598_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18596_dupName_177_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27240_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(BITSELECT,27239)@161
    assign leftShiftStage2Idx1Rng8_uid27240_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in = leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27240_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27240_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27241_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(BITJOIN,27240)@161
    assign leftShiftStage2Idx1_uid27241_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27240_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27235_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(BITSELECT,27234)@161
    assign leftShiftStage1Idx1Rng4_uid27235_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in = leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27235_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27235_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27236_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(BITJOIN,27235)@161
    assign leftShiftStage1Idx1_uid27236_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27235_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27230_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(BITSELECT,27229)@161
    assign leftShiftStage0Idx1Rng1_uid27230_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27230_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27230_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27231_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(BITJOIN,27230)@161
    assign leftShiftStage0Idx1_uid27231_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27230_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18544_dupName_173_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18543)@160
    assign rightShiftStage2Idx1Rng8_uid18544_dupName_173_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18546_dupName_173_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18545)@160
    assign rightShiftStage2Idx1_uid18546_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18544_dupName_173_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18539_dupName_173_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18538)@160
    assign rightShiftStage1Idx1Rng4_uid18539_dupName_173_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18541_dupName_173_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18540)@160
    assign rightShiftStage1Idx1_uid18541_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18539_dupName_173_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18534_dupName_173_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18533)@160
    assign rightShiftStage0Idx1Rng1_uid18534_dupName_173_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q[33:1];

    // rightShiftStage0Idx1_uid18536_dupName_173_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18535)@160
    assign rightShiftStage0Idx1_uid18536_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18534_dupName_173_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27222_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(BITSELECT,27221)@159
    assign leftShiftStage2Idx1Rng8_uid27222_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in = leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27222_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27222_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27223_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(BITJOIN,27222)@159
    assign leftShiftStage2Idx1_uid27223_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27222_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27217_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(BITSELECT,27216)@159
    assign leftShiftStage1Idx1Rng4_uid27217_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in = leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27217_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27217_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27218_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(BITJOIN,27217)@159
    assign leftShiftStage1Idx1_uid27218_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27217_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27212_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(BITSELECT,27211)@159
    assign leftShiftStage0Idx1Rng1_uid27212_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27212_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27212_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27213_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(BITJOIN,27212)@159
    assign leftShiftStage0Idx1_uid27213_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27212_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18482_dupName_169_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18481)@158
    assign rightShiftStage2Idx1Rng8_uid18482_dupName_169_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18484_dupName_169_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18483)@158
    assign rightShiftStage2Idx1_uid18484_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18482_dupName_169_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18477_dupName_169_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18476)@158
    assign rightShiftStage1Idx1Rng4_uid18477_dupName_169_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18479_dupName_169_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18478)@158
    assign rightShiftStage1Idx1_uid18479_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18477_dupName_169_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18472_dupName_169_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18471)@158
    assign rightShiftStage0Idx1Rng1_uid18472_dupName_169_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q[33:1];

    // rightShiftStage0Idx1_uid18474_dupName_169_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18473)@158
    assign rightShiftStage0Idx1_uid18474_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18472_dupName_169_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27204_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(BITSELECT,27203)@157
    assign leftShiftStage2Idx1Rng8_uid27204_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in = leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27204_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27204_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27205_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(BITJOIN,27204)@157
    assign leftShiftStage2Idx1_uid27205_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27204_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27199_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(BITSELECT,27198)@157
    assign leftShiftStage1Idx1Rng4_uid27199_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in = leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27199_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27199_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27200_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(BITJOIN,27199)@157
    assign leftShiftStage1Idx1_uid27200_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27199_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27194_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(BITSELECT,27193)@157
    assign leftShiftStage0Idx1Rng1_uid27194_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27194_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27194_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27195_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(BITJOIN,27194)@157
    assign leftShiftStage0Idx1_uid27195_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27194_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18420_dupName_165_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18419)@156
    assign rightShiftStage2Idx1Rng8_uid18420_dupName_165_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18422_dupName_165_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18421)@156
    assign rightShiftStage2Idx1_uid18422_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18420_dupName_165_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18415_dupName_165_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18414)@156
    assign rightShiftStage1Idx1Rng4_uid18415_dupName_165_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18417_dupName_165_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18416)@156
    assign rightShiftStage1Idx1_uid18417_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18415_dupName_165_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18410_dupName_165_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18409)@156
    assign rightShiftStage0Idx1Rng1_uid18410_dupName_165_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q[33:1];

    // rightShiftStage0Idx1_uid18412_dupName_165_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18411)@156
    assign rightShiftStage0Idx1_uid18412_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18410_dupName_165_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27186_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(BITSELECT,27185)@155
    assign leftShiftStage2Idx1Rng8_uid27186_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in = leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27186_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27186_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27187_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(BITJOIN,27186)@155
    assign leftShiftStage2Idx1_uid27187_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27186_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27181_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(BITSELECT,27180)@155
    assign leftShiftStage1Idx1Rng4_uid27181_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in = leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27181_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27181_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27182_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(BITJOIN,27181)@155
    assign leftShiftStage1Idx1_uid27182_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27181_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27176_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(BITSELECT,27175)@155
    assign leftShiftStage0Idx1Rng1_uid27176_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27176_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27176_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27177_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(BITJOIN,27176)@155
    assign leftShiftStage0Idx1_uid27177_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27176_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18358_dupName_161_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18357)@154
    assign rightShiftStage2Idx1Rng8_uid18358_dupName_161_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18360_dupName_161_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18359)@154
    assign rightShiftStage2Idx1_uid18360_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18358_dupName_161_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18353_dupName_161_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18352)@154
    assign rightShiftStage1Idx1Rng4_uid18353_dupName_161_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18355_dupName_161_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18354)@154
    assign rightShiftStage1Idx1_uid18355_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18353_dupName_161_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18348_dupName_161_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18347)@154
    assign rightShiftStage0Idx1Rng1_uid18348_dupName_161_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q[33:1];

    // rightShiftStage0Idx1_uid18350_dupName_161_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18349)@154
    assign rightShiftStage0Idx1_uid18350_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18348_dupName_161_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27168_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(BITSELECT,27167)@153
    assign leftShiftStage2Idx1Rng8_uid27168_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in = leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27168_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27168_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27169_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(BITJOIN,27168)@153
    assign leftShiftStage2Idx1_uid27169_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27168_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27163_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(BITSELECT,27162)@153
    assign leftShiftStage1Idx1Rng4_uid27163_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in = leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27163_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27163_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27164_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(BITJOIN,27163)@153
    assign leftShiftStage1Idx1_uid27164_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27163_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27158_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(BITSELECT,27157)@153
    assign leftShiftStage0Idx1Rng1_uid27158_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27158_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27158_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27159_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(BITJOIN,27158)@153
    assign leftShiftStage0Idx1_uid27159_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27158_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18296_dupName_157_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18295)@152
    assign rightShiftStage2Idx1Rng8_uid18296_dupName_157_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18298_dupName_157_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18297)@152
    assign rightShiftStage2Idx1_uid18298_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18296_dupName_157_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18291_dupName_157_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18290)@152
    assign rightShiftStage1Idx1Rng4_uid18291_dupName_157_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18293_dupName_157_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18292)@152
    assign rightShiftStage1Idx1_uid18293_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18291_dupName_157_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18286_dupName_157_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18285)@152
    assign rightShiftStage0Idx1Rng1_uid18286_dupName_157_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q[33:1];

    // rightShiftStage0Idx1_uid18288_dupName_157_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18287)@152
    assign rightShiftStage0Idx1_uid18288_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18286_dupName_157_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27132_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(BITSELECT,27131)@151
    assign leftShiftStage2Idx1Rng8_uid27132_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in = leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27132_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27132_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27133_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(BITJOIN,27132)@151
    assign leftShiftStage2Idx1_uid27133_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27132_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27127_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(BITSELECT,27126)@151
    assign leftShiftStage1Idx1Rng4_uid27127_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in = leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27127_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27127_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27128_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(BITJOIN,27127)@151
    assign leftShiftStage1Idx1_uid27128_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27127_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27122_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(BITSELECT,27121)@151
    assign leftShiftStage0Idx1Rng1_uid27122_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27122_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27122_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27123_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(BITJOIN,27122)@151
    assign leftShiftStage0Idx1_uid27123_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27122_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18234_dupName_153_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18233)@150
    assign rightShiftStage2Idx1Rng8_uid18234_dupName_153_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18236_dupName_153_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18235)@150
    assign rightShiftStage2Idx1_uid18236_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18234_dupName_153_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18229_dupName_153_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18228)@150
    assign rightShiftStage1Idx1Rng4_uid18229_dupName_153_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18231_dupName_153_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18230)@150
    assign rightShiftStage1Idx1_uid18231_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18229_dupName_153_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18224_dupName_153_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18223)@150
    assign rightShiftStage0Idx1Rng1_uid18224_dupName_153_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q[33:1];

    // rightShiftStage0Idx1_uid18226_dupName_153_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18225)@150
    assign rightShiftStage0Idx1_uid18226_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18224_dupName_153_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27114_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(BITSELECT,27113)@149
    assign leftShiftStage2Idx1Rng8_uid27114_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in = leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27114_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27114_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27115_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(BITJOIN,27114)@149
    assign leftShiftStage2Idx1_uid27115_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27114_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27109_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(BITSELECT,27108)@149
    assign leftShiftStage1Idx1Rng4_uid27109_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in = leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27109_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27109_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27110_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(BITJOIN,27109)@149
    assign leftShiftStage1Idx1_uid27110_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27109_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27104_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(BITSELECT,27103)@149
    assign leftShiftStage0Idx1Rng1_uid27104_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27104_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27104_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27105_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(BITJOIN,27104)@149
    assign leftShiftStage0Idx1_uid27105_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27104_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18172_dupName_149_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18171)@148
    assign rightShiftStage2Idx1Rng8_uid18172_dupName_149_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18174_dupName_149_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18173)@148
    assign rightShiftStage2Idx1_uid18174_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18172_dupName_149_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18167_dupName_149_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18166)@148
    assign rightShiftStage1Idx1Rng4_uid18167_dupName_149_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18169_dupName_149_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18168)@148
    assign rightShiftStage1Idx1_uid18169_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18167_dupName_149_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18162_dupName_149_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18161)@148
    assign rightShiftStage0Idx1Rng1_uid18162_dupName_149_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q[33:1];

    // rightShiftStage0Idx1_uid18164_dupName_149_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18163)@148
    assign rightShiftStage0Idx1_uid18164_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18162_dupName_149_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27096_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(BITSELECT,27095)@147
    assign leftShiftStage2Idx1Rng8_uid27096_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in = leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27096_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27096_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27097_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(BITJOIN,27096)@147
    assign leftShiftStage2Idx1_uid27097_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27096_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27091_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(BITSELECT,27090)@147
    assign leftShiftStage1Idx1Rng4_uid27091_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in = leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27091_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27091_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27092_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(BITJOIN,27091)@147
    assign leftShiftStage1Idx1_uid27092_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27091_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27086_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(BITSELECT,27085)@147
    assign leftShiftStage0Idx1Rng1_uid27086_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27086_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27086_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27087_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(BITJOIN,27086)@147
    assign leftShiftStage0Idx1_uid27087_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27086_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18110_dupName_145_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18109)@146
    assign rightShiftStage2Idx1Rng8_uid18110_dupName_145_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18112_dupName_145_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18111)@146
    assign rightShiftStage2Idx1_uid18112_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18110_dupName_145_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18105_dupName_145_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18104)@146
    assign rightShiftStage1Idx1Rng4_uid18105_dupName_145_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18107_dupName_145_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18106)@146
    assign rightShiftStage1Idx1_uid18107_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18105_dupName_145_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18100_dupName_145_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18099)@146
    assign rightShiftStage0Idx1Rng1_uid18100_dupName_145_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q[33:1];

    // rightShiftStage0Idx1_uid18102_dupName_145_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18101)@146
    assign rightShiftStage0Idx1_uid18102_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18100_dupName_145_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27078_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(BITSELECT,27077)@145
    assign leftShiftStage2Idx1Rng8_uid27078_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in = leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27078_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27078_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27079_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(BITJOIN,27078)@145
    assign leftShiftStage2Idx1_uid27079_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27078_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27073_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(BITSELECT,27072)@145
    assign leftShiftStage1Idx1Rng4_uid27073_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in = leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27073_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27073_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27074_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(BITJOIN,27073)@145
    assign leftShiftStage1Idx1_uid27074_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27073_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27068_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(BITSELECT,27067)@145
    assign leftShiftStage0Idx1Rng1_uid27068_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27068_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27068_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27069_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(BITJOIN,27068)@145
    assign leftShiftStage0Idx1_uid27069_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27068_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18048_dupName_141_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18047)@144
    assign rightShiftStage2Idx1Rng8_uid18048_dupName_141_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18050_dupName_141_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18049)@144
    assign rightShiftStage2Idx1_uid18050_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18048_dupName_141_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18043_dupName_141_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18042)@144
    assign rightShiftStage1Idx1Rng4_uid18043_dupName_141_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18045_dupName_141_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18044)@144
    assign rightShiftStage1Idx1_uid18045_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18043_dupName_141_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18038_dupName_141_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18037)@144
    assign rightShiftStage0Idx1Rng1_uid18038_dupName_141_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q[33:1];

    // rightShiftStage0Idx1_uid18040_dupName_141_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18039)@144
    assign rightShiftStage0Idx1_uid18040_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18038_dupName_141_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27060_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(BITSELECT,27059)@143
    assign leftShiftStage2Idx1Rng8_uid27060_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in = leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27060_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27060_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27061_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(BITJOIN,27060)@143
    assign leftShiftStage2Idx1_uid27061_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27060_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27055_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(BITSELECT,27054)@143
    assign leftShiftStage1Idx1Rng4_uid27055_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in = leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27055_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27055_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27056_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(BITJOIN,27055)@143
    assign leftShiftStage1Idx1_uid27056_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27055_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27050_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(BITSELECT,27049)@143
    assign leftShiftStage0Idx1Rng1_uid27050_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27050_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27050_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27051_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(BITJOIN,27050)@143
    assign leftShiftStage0Idx1_uid27051_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27050_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17986_dupName_137_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17985)@142
    assign rightShiftStage2Idx1Rng8_uid17986_dupName_137_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17988_dupName_137_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17987)@142
    assign rightShiftStage2Idx1_uid17988_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17986_dupName_137_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17981_dupName_137_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17980)@142
    assign rightShiftStage1Idx1Rng4_uid17981_dupName_137_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17983_dupName_137_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17982)@142
    assign rightShiftStage1Idx1_uid17983_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17981_dupName_137_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17976_dupName_137_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17975)@142
    assign rightShiftStage0Idx1Rng1_uid17976_dupName_137_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q[33:1];

    // rightShiftStage0Idx1_uid17978_dupName_137_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17977)@142
    assign rightShiftStage0Idx1_uid17978_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17976_dupName_137_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27042_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(BITSELECT,27041)@141
    assign leftShiftStage2Idx1Rng8_uid27042_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in = leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27042_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27042_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27043_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(BITJOIN,27042)@141
    assign leftShiftStage2Idx1_uid27043_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27042_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27037_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(BITSELECT,27036)@141
    assign leftShiftStage1Idx1Rng4_uid27037_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in = leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27037_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27037_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27038_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(BITJOIN,27037)@141
    assign leftShiftStage1Idx1_uid27038_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27037_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27032_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(BITSELECT,27031)@141
    assign leftShiftStage0Idx1Rng1_uid27032_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27032_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27032_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27033_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(BITJOIN,27032)@141
    assign leftShiftStage0Idx1_uid27033_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27032_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17924_dupName_133_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17923)@140
    assign rightShiftStage2Idx1Rng8_uid17924_dupName_133_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17926_dupName_133_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17925)@140
    assign rightShiftStage2Idx1_uid17926_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17924_dupName_133_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17919_dupName_133_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17918)@140
    assign rightShiftStage1Idx1Rng4_uid17919_dupName_133_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17921_dupName_133_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17920)@140
    assign rightShiftStage1Idx1_uid17921_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17919_dupName_133_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17914_dupName_133_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17913)@140
    assign rightShiftStage0Idx1Rng1_uid17914_dupName_133_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q[33:1];

    // rightShiftStage0Idx1_uid17916_dupName_133_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17915)@140
    assign rightShiftStage0Idx1_uid17916_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17914_dupName_133_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27024_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(BITSELECT,27023)@139
    assign leftShiftStage2Idx1Rng8_uid27024_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in = leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27024_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27024_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27025_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(BITJOIN,27024)@139
    assign leftShiftStage2Idx1_uid27025_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27024_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27019_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(BITSELECT,27018)@139
    assign leftShiftStage1Idx1Rng4_uid27019_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in = leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27019_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27019_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27020_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(BITJOIN,27019)@139
    assign leftShiftStage1Idx1_uid27020_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27019_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27014_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(BITSELECT,27013)@139
    assign leftShiftStage0Idx1Rng1_uid27014_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27014_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27014_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27015_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(BITJOIN,27014)@139
    assign leftShiftStage0Idx1_uid27015_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27014_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17862_dupName_129_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17861)@138
    assign rightShiftStage2Idx1Rng8_uid17862_dupName_129_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17864_dupName_129_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17863)@138
    assign rightShiftStage2Idx1_uid17864_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17862_dupName_129_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17857_dupName_129_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17856)@138
    assign rightShiftStage1Idx1Rng4_uid17857_dupName_129_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17859_dupName_129_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17858)@138
    assign rightShiftStage1Idx1_uid17859_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17857_dupName_129_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17852_dupName_129_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17851)@138
    assign rightShiftStage0Idx1Rng1_uid17852_dupName_129_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q[33:1];

    // rightShiftStage0Idx1_uid17854_dupName_129_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17853)@138
    assign rightShiftStage0Idx1_uid17854_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17852_dupName_129_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27006_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(BITSELECT,27005)@137
    assign leftShiftStage2Idx1Rng8_uid27006_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in = leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27006_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27006_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27007_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(BITJOIN,27006)@137
    assign leftShiftStage2Idx1_uid27007_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27006_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27001_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(BITSELECT,27000)@137
    assign leftShiftStage1Idx1Rng4_uid27001_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in = leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27001_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27001_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27002_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(BITJOIN,27001)@137
    assign leftShiftStage1Idx1_uid27002_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27001_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26996_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(BITSELECT,26995)@137
    assign leftShiftStage0Idx1Rng1_uid26996_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26996_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26996_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26997_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(BITJOIN,26996)@137
    assign leftShiftStage0Idx1_uid26997_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26996_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17800_dupName_125_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17799)@136
    assign rightShiftStage2Idx1Rng8_uid17800_dupName_125_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17802_dupName_125_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17801)@136
    assign rightShiftStage2Idx1_uid17802_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17800_dupName_125_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17795_dupName_125_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17794)@136
    assign rightShiftStage1Idx1Rng4_uid17795_dupName_125_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17797_dupName_125_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17796)@136
    assign rightShiftStage1Idx1_uid17797_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17795_dupName_125_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17790_dupName_125_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17789)@136
    assign rightShiftStage0Idx1Rng1_uid17790_dupName_125_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q[33:1];

    // rightShiftStage0Idx1_uid17792_dupName_125_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17791)@136
    assign rightShiftStage0Idx1_uid17792_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17790_dupName_125_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26988_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(BITSELECT,26987)@135
    assign leftShiftStage2Idx1Rng8_uid26988_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in = leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26988_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26988_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26989_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(BITJOIN,26988)@135
    assign leftShiftStage2Idx1_uid26989_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26988_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26983_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(BITSELECT,26982)@135
    assign leftShiftStage1Idx1Rng4_uid26983_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in = leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26983_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26983_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26984_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(BITJOIN,26983)@135
    assign leftShiftStage1Idx1_uid26984_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26983_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26978_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(BITSELECT,26977)@135
    assign leftShiftStage0Idx1Rng1_uid26978_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26978_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26978_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26979_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(BITJOIN,26978)@135
    assign leftShiftStage0Idx1_uid26979_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26978_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17738_dupName_121_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17737)@134
    assign rightShiftStage2Idx1Rng8_uid17738_dupName_121_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17740_dupName_121_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17739)@134
    assign rightShiftStage2Idx1_uid17740_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17738_dupName_121_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17733_dupName_121_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17732)@134
    assign rightShiftStage1Idx1Rng4_uid17733_dupName_121_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17735_dupName_121_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17734)@134
    assign rightShiftStage1Idx1_uid17735_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17733_dupName_121_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17728_dupName_121_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17727)@134
    assign rightShiftStage0Idx1Rng1_uid17728_dupName_121_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q[33:1];

    // rightShiftStage0Idx1_uid17730_dupName_121_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17729)@134
    assign rightShiftStage0Idx1_uid17730_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17728_dupName_121_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26970_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(BITSELECT,26969)@133
    assign leftShiftStage2Idx1Rng8_uid26970_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in = leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26970_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26970_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26971_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(BITJOIN,26970)@133
    assign leftShiftStage2Idx1_uid26971_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26970_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26965_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(BITSELECT,26964)@133
    assign leftShiftStage1Idx1Rng4_uid26965_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in = leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26965_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26965_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26966_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(BITJOIN,26965)@133
    assign leftShiftStage1Idx1_uid26966_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26965_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26960_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(BITSELECT,26959)@133
    assign leftShiftStage0Idx1Rng1_uid26960_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26960_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26960_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26961_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(BITJOIN,26960)@133
    assign leftShiftStage0Idx1_uid26961_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26960_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17676_dupName_117_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17675)@132
    assign rightShiftStage2Idx1Rng8_uid17676_dupName_117_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17678_dupName_117_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17677)@132
    assign rightShiftStage2Idx1_uid17678_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17676_dupName_117_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17671_dupName_117_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17670)@132
    assign rightShiftStage1Idx1Rng4_uid17671_dupName_117_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17673_dupName_117_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17672)@132
    assign rightShiftStage1Idx1_uid17673_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17671_dupName_117_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17666_dupName_117_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17665)@132
    assign rightShiftStage0Idx1Rng1_uid17666_dupName_117_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q[33:1];

    // rightShiftStage0Idx1_uid17668_dupName_117_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17667)@132
    assign rightShiftStage0Idx1_uid17668_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17666_dupName_117_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26934_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(BITSELECT,26933)@131
    assign leftShiftStage2Idx1Rng8_uid26934_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in = leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26934_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26934_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26935_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(BITJOIN,26934)@131
    assign leftShiftStage2Idx1_uid26935_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26934_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26929_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(BITSELECT,26928)@131
    assign leftShiftStage1Idx1Rng4_uid26929_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in = leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26929_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26929_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26930_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(BITJOIN,26929)@131
    assign leftShiftStage1Idx1_uid26930_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26929_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26924_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(BITSELECT,26923)@131
    assign leftShiftStage0Idx1Rng1_uid26924_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26924_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26924_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26925_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(BITJOIN,26924)@131
    assign leftShiftStage0Idx1_uid26925_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26924_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17614_dupName_113_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17613)@130
    assign rightShiftStage2Idx1Rng8_uid17614_dupName_113_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17616_dupName_113_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17615)@130
    assign rightShiftStage2Idx1_uid17616_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17614_dupName_113_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17609_dupName_113_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17608)@130
    assign rightShiftStage1Idx1Rng4_uid17609_dupName_113_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17611_dupName_113_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17610)@130
    assign rightShiftStage1Idx1_uid17611_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17609_dupName_113_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17604_dupName_113_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17603)@130
    assign rightShiftStage0Idx1Rng1_uid17604_dupName_113_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q[33:1];

    // rightShiftStage0Idx1_uid17606_dupName_113_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17605)@130
    assign rightShiftStage0Idx1_uid17606_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17604_dupName_113_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26916_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(BITSELECT,26915)@129
    assign leftShiftStage2Idx1Rng8_uid26916_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in = leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26916_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26916_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26917_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(BITJOIN,26916)@129
    assign leftShiftStage2Idx1_uid26917_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26916_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26911_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(BITSELECT,26910)@129
    assign leftShiftStage1Idx1Rng4_uid26911_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in = leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26911_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26911_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26912_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(BITJOIN,26911)@129
    assign leftShiftStage1Idx1_uid26912_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26911_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26906_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(BITSELECT,26905)@129
    assign leftShiftStage0Idx1Rng1_uid26906_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26906_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26906_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26907_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(BITJOIN,26906)@129
    assign leftShiftStage0Idx1_uid26907_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26906_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17552_dupName_109_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17551)@128
    assign rightShiftStage2Idx1Rng8_uid17552_dupName_109_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17554_dupName_109_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17553)@128
    assign rightShiftStage2Idx1_uid17554_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17552_dupName_109_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17547_dupName_109_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17546)@128
    assign rightShiftStage1Idx1Rng4_uid17547_dupName_109_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17549_dupName_109_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17548)@128
    assign rightShiftStage1Idx1_uid17549_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17547_dupName_109_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17542_dupName_109_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17541)@128
    assign rightShiftStage0Idx1Rng1_uid17542_dupName_109_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q[33:1];

    // rightShiftStage0Idx1_uid17544_dupName_109_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17543)@128
    assign rightShiftStage0Idx1_uid17544_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17542_dupName_109_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26898_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(BITSELECT,26897)@127
    assign leftShiftStage2Idx1Rng8_uid26898_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in = leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26898_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26898_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26899_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(BITJOIN,26898)@127
    assign leftShiftStage2Idx1_uid26899_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26898_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26893_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(BITSELECT,26892)@127
    assign leftShiftStage1Idx1Rng4_uid26893_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in = leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26893_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26893_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26894_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(BITJOIN,26893)@127
    assign leftShiftStage1Idx1_uid26894_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26893_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26888_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(BITSELECT,26887)@127
    assign leftShiftStage0Idx1Rng1_uid26888_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26888_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26888_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26889_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(BITJOIN,26888)@127
    assign leftShiftStage0Idx1_uid26889_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26888_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17490_dupName_105_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17489)@126
    assign rightShiftStage2Idx1Rng8_uid17490_dupName_105_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17492_dupName_105_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17491)@126
    assign rightShiftStage2Idx1_uid17492_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17490_dupName_105_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17485_dupName_105_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17484)@126
    assign rightShiftStage1Idx1Rng4_uid17485_dupName_105_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17487_dupName_105_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17486)@126
    assign rightShiftStage1Idx1_uid17487_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17485_dupName_105_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17480_dupName_105_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17479)@126
    assign rightShiftStage0Idx1Rng1_uid17480_dupName_105_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q[33:1];

    // rightShiftStage0Idx1_uid17482_dupName_105_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17481)@126
    assign rightShiftStage0Idx1_uid17482_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17480_dupName_105_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26880_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(BITSELECT,26879)@125
    assign leftShiftStage2Idx1Rng8_uid26880_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in = leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26880_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26880_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26881_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(BITJOIN,26880)@125
    assign leftShiftStage2Idx1_uid26881_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26880_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26875_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(BITSELECT,26874)@125
    assign leftShiftStage1Idx1Rng4_uid26875_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in = leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26875_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26875_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26876_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(BITJOIN,26875)@125
    assign leftShiftStage1Idx1_uid26876_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26875_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26870_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(BITSELECT,26869)@125
    assign leftShiftStage0Idx1Rng1_uid26870_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26870_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26870_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26871_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(BITJOIN,26870)@125
    assign leftShiftStage0Idx1_uid26871_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26870_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17428_dupName_101_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17427)@124
    assign rightShiftStage2Idx1Rng8_uid17428_dupName_101_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17430_dupName_101_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17429)@124
    assign rightShiftStage2Idx1_uid17430_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17428_dupName_101_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17423_dupName_101_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17422)@124
    assign rightShiftStage1Idx1Rng4_uid17423_dupName_101_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17425_dupName_101_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17424)@124
    assign rightShiftStage1Idx1_uid17425_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17423_dupName_101_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17418_dupName_101_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17417)@124
    assign rightShiftStage0Idx1Rng1_uid17418_dupName_101_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q[33:1];

    // rightShiftStage0Idx1_uid17420_dupName_101_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17419)@124
    assign rightShiftStage0Idx1_uid17420_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17418_dupName_101_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26862_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(BITSELECT,26861)@123
    assign leftShiftStage2Idx1Rng8_uid26862_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in = leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26862_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26862_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26863_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(BITJOIN,26862)@123
    assign leftShiftStage2Idx1_uid26863_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26862_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26857_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(BITSELECT,26856)@123
    assign leftShiftStage1Idx1Rng4_uid26857_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in = leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26857_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26857_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26858_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(BITJOIN,26857)@123
    assign leftShiftStage1Idx1_uid26858_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26857_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26852_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(BITSELECT,26851)@123
    assign leftShiftStage0Idx1Rng1_uid26852_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26852_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26852_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26853_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(BITJOIN,26852)@123
    assign leftShiftStage0Idx1_uid26853_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26852_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17366_dupName_97_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17365)@122
    assign rightShiftStage2Idx1Rng8_uid17366_dupName_97_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17368_dupName_97_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17367)@122
    assign rightShiftStage2Idx1_uid17368_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17366_dupName_97_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17361_dupName_97_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17360)@122
    assign rightShiftStage1Idx1Rng4_uid17361_dupName_97_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17363_dupName_97_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17362)@122
    assign rightShiftStage1Idx1_uid17363_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17361_dupName_97_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17356_dupName_97_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17355)@122
    assign rightShiftStage0Idx1Rng1_uid17356_dupName_97_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q[33:1];

    // rightShiftStage0Idx1_uid17358_dupName_97_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17357)@122
    assign rightShiftStage0Idx1_uid17358_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17356_dupName_97_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26844_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(BITSELECT,26843)@121
    assign leftShiftStage2Idx1Rng8_uid26844_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in = leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26844_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26844_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26845_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(BITJOIN,26844)@121
    assign leftShiftStage2Idx1_uid26845_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26844_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26839_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(BITSELECT,26838)@121
    assign leftShiftStage1Idx1Rng4_uid26839_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in = leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26839_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26839_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26840_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(BITJOIN,26839)@121
    assign leftShiftStage1Idx1_uid26840_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26839_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26834_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(BITSELECT,26833)@121
    assign leftShiftStage0Idx1Rng1_uid26834_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26834_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26834_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26835_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(BITJOIN,26834)@121
    assign leftShiftStage0Idx1_uid26835_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26834_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17304_dupName_93_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17303)@120
    assign rightShiftStage2Idx1Rng8_uid17304_dupName_93_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17306_dupName_93_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17305)@120
    assign rightShiftStage2Idx1_uid17306_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17304_dupName_93_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17299_dupName_93_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17298)@120
    assign rightShiftStage1Idx1Rng4_uid17299_dupName_93_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17301_dupName_93_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17300)@120
    assign rightShiftStage1Idx1_uid17301_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17299_dupName_93_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17294_dupName_93_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17293)@120
    assign rightShiftStage0Idx1Rng1_uid17294_dupName_93_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q[33:1];

    // rightShiftStage0Idx1_uid17296_dupName_93_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17295)@120
    assign rightShiftStage0Idx1_uid17296_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17294_dupName_93_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26826_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(BITSELECT,26825)@119
    assign leftShiftStage2Idx1Rng8_uid26826_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in = leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26826_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26826_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26827_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(BITJOIN,26826)@119
    assign leftShiftStage2Idx1_uid26827_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26826_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26821_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(BITSELECT,26820)@119
    assign leftShiftStage1Idx1Rng4_uid26821_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in = leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26821_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26821_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26822_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(BITJOIN,26821)@119
    assign leftShiftStage1Idx1_uid26822_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26821_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26816_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(BITSELECT,26815)@119
    assign leftShiftStage0Idx1Rng1_uid26816_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26816_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26816_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26817_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(BITJOIN,26816)@119
    assign leftShiftStage0Idx1_uid26817_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26816_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17242_dupName_89_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17241)@118
    assign rightShiftStage2Idx1Rng8_uid17242_dupName_89_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17244_dupName_89_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17243)@118
    assign rightShiftStage2Idx1_uid17244_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17242_dupName_89_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17237_dupName_89_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17236)@118
    assign rightShiftStage1Idx1Rng4_uid17237_dupName_89_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17239_dupName_89_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17238)@118
    assign rightShiftStage1Idx1_uid17239_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17237_dupName_89_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17232_dupName_89_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17231)@118
    assign rightShiftStage0Idx1Rng1_uid17232_dupName_89_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q[33:1];

    // rightShiftStage0Idx1_uid17234_dupName_89_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17233)@118
    assign rightShiftStage0Idx1_uid17234_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17232_dupName_89_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26808_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(BITSELECT,26807)@117
    assign leftShiftStage2Idx1Rng8_uid26808_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in = leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26808_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26808_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26809_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(BITJOIN,26808)@117
    assign leftShiftStage2Idx1_uid26809_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26808_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26803_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(BITSELECT,26802)@117
    assign leftShiftStage1Idx1Rng4_uid26803_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in = leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26803_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26803_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26804_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(BITJOIN,26803)@117
    assign leftShiftStage1Idx1_uid26804_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26803_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26798_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(BITSELECT,26797)@117
    assign leftShiftStage0Idx1Rng1_uid26798_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26798_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26798_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26799_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(BITJOIN,26798)@117
    assign leftShiftStage0Idx1_uid26799_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26798_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17180_dupName_85_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17179)@116
    assign rightShiftStage2Idx1Rng8_uid17180_dupName_85_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17182_dupName_85_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17181)@116
    assign rightShiftStage2Idx1_uid17182_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17180_dupName_85_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17175_dupName_85_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17174)@116
    assign rightShiftStage1Idx1Rng4_uid17175_dupName_85_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17177_dupName_85_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17176)@116
    assign rightShiftStage1Idx1_uid17177_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17175_dupName_85_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17170_dupName_85_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17169)@116
    assign rightShiftStage0Idx1Rng1_uid17170_dupName_85_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q[33:1];

    // rightShiftStage0Idx1_uid17172_dupName_85_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17171)@116
    assign rightShiftStage0Idx1_uid17172_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17170_dupName_85_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26790_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(BITSELECT,26789)@115
    assign leftShiftStage2Idx1Rng8_uid26790_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in = leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26790_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26790_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26791_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(BITJOIN,26790)@115
    assign leftShiftStage2Idx1_uid26791_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26790_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26785_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(BITSELECT,26784)@115
    assign leftShiftStage1Idx1Rng4_uid26785_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in = leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26785_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26785_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26786_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(BITJOIN,26785)@115
    assign leftShiftStage1Idx1_uid26786_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26785_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26780_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(BITSELECT,26779)@115
    assign leftShiftStage0Idx1Rng1_uid26780_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26780_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26780_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26781_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(BITJOIN,26780)@115
    assign leftShiftStage0Idx1_uid26781_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26780_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17118_dupName_81_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17117)@114
    assign rightShiftStage2Idx1Rng8_uid17118_dupName_81_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17120_dupName_81_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17119)@114
    assign rightShiftStage2Idx1_uid17120_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17118_dupName_81_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17113_dupName_81_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17112)@114
    assign rightShiftStage1Idx1Rng4_uid17113_dupName_81_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17115_dupName_81_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17114)@114
    assign rightShiftStage1Idx1_uid17115_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17113_dupName_81_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17108_dupName_81_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17107)@114
    assign rightShiftStage0Idx1Rng1_uid17108_dupName_81_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q[33:1];

    // rightShiftStage0Idx1_uid17110_dupName_81_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17109)@114
    assign rightShiftStage0Idx1_uid17110_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17108_dupName_81_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26772_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(BITSELECT,26771)@113
    assign leftShiftStage2Idx1Rng8_uid26772_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in = leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26772_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26772_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26773_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(BITJOIN,26772)@113
    assign leftShiftStage2Idx1_uid26773_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26772_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26767_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(BITSELECT,26766)@113
    assign leftShiftStage1Idx1Rng4_uid26767_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in = leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26767_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26767_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26768_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(BITJOIN,26767)@113
    assign leftShiftStage1Idx1_uid26768_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26767_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26762_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(BITSELECT,26761)@113
    assign leftShiftStage0Idx1Rng1_uid26762_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26762_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26762_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26763_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(BITJOIN,26762)@113
    assign leftShiftStage0Idx1_uid26763_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26762_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17056_dupName_77_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17055)@112
    assign rightShiftStage2Idx1Rng8_uid17056_dupName_77_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17058_dupName_77_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17057)@112
    assign rightShiftStage2Idx1_uid17058_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17056_dupName_77_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17051_dupName_77_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17050)@112
    assign rightShiftStage1Idx1Rng4_uid17051_dupName_77_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17053_dupName_77_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17052)@112
    assign rightShiftStage1Idx1_uid17053_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17051_dupName_77_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17046_dupName_77_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17045)@112
    assign rightShiftStage0Idx1Rng1_uid17046_dupName_77_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q[33:1];

    // rightShiftStage0Idx1_uid17048_dupName_77_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17047)@112
    assign rightShiftStage0Idx1_uid17048_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17046_dupName_77_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26736_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(BITSELECT,26735)@111
    assign leftShiftStage2Idx1Rng8_uid26736_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in = leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26736_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26736_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26737_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(BITJOIN,26736)@111
    assign leftShiftStage2Idx1_uid26737_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26736_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26731_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(BITSELECT,26730)@111
    assign leftShiftStage1Idx1Rng4_uid26731_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in = leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26731_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26731_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26732_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(BITJOIN,26731)@111
    assign leftShiftStage1Idx1_uid26732_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26731_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26726_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(BITSELECT,26725)@111
    assign leftShiftStage0Idx1Rng1_uid26726_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26726_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26726_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26727_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(BITJOIN,26726)@111
    assign leftShiftStage0Idx1_uid26727_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26726_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16994_dupName_73_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16993)@110
    assign rightShiftStage2Idx1Rng8_uid16994_dupName_73_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16996_dupName_73_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16995)@110
    assign rightShiftStage2Idx1_uid16996_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16994_dupName_73_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16989_dupName_73_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16988)@110
    assign rightShiftStage1Idx1Rng4_uid16989_dupName_73_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16991_dupName_73_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16990)@110
    assign rightShiftStage1Idx1_uid16991_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16989_dupName_73_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16984_dupName_73_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16983)@110
    assign rightShiftStage0Idx1Rng1_uid16984_dupName_73_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q[33:1];

    // rightShiftStage0Idx1_uid16986_dupName_73_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16985)@110
    assign rightShiftStage0Idx1_uid16986_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16984_dupName_73_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26718_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(BITSELECT,26717)@109
    assign leftShiftStage2Idx1Rng8_uid26718_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in = leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26718_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26718_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26719_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(BITJOIN,26718)@109
    assign leftShiftStage2Idx1_uid26719_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26718_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26713_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(BITSELECT,26712)@109
    assign leftShiftStage1Idx1Rng4_uid26713_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in = leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26713_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26713_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26714_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(BITJOIN,26713)@109
    assign leftShiftStage1Idx1_uid26714_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26713_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26708_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(BITSELECT,26707)@109
    assign leftShiftStage0Idx1Rng1_uid26708_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26708_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26708_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26709_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(BITJOIN,26708)@109
    assign leftShiftStage0Idx1_uid26709_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26708_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16932_dupName_69_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16931)@108
    assign rightShiftStage2Idx1Rng8_uid16932_dupName_69_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16934_dupName_69_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16933)@108
    assign rightShiftStage2Idx1_uid16934_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16932_dupName_69_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16927_dupName_69_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16926)@108
    assign rightShiftStage1Idx1Rng4_uid16927_dupName_69_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16929_dupName_69_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16928)@108
    assign rightShiftStage1Idx1_uid16929_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16927_dupName_69_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16922_dupName_69_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16921)@108
    assign rightShiftStage0Idx1Rng1_uid16922_dupName_69_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q[33:1];

    // rightShiftStage0Idx1_uid16924_dupName_69_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16923)@108
    assign rightShiftStage0Idx1_uid16924_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16922_dupName_69_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26700_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(BITSELECT,26699)@107
    assign leftShiftStage2Idx1Rng8_uid26700_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in = leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26700_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26700_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26701_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(BITJOIN,26700)@107
    assign leftShiftStage2Idx1_uid26701_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26700_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26695_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(BITSELECT,26694)@107
    assign leftShiftStage1Idx1Rng4_uid26695_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in = leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26695_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26695_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26696_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(BITJOIN,26695)@107
    assign leftShiftStage1Idx1_uid26696_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26695_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26690_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(BITSELECT,26689)@107
    assign leftShiftStage0Idx1Rng1_uid26690_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26690_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26690_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26691_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(BITJOIN,26690)@107
    assign leftShiftStage0Idx1_uid26691_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26690_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16870_dupName_65_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16869)@106
    assign rightShiftStage2Idx1Rng8_uid16870_dupName_65_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16872_dupName_65_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16871)@106
    assign rightShiftStage2Idx1_uid16872_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16870_dupName_65_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16865_dupName_65_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16864)@106
    assign rightShiftStage1Idx1Rng4_uid16865_dupName_65_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16867_dupName_65_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16866)@106
    assign rightShiftStage1Idx1_uid16867_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16865_dupName_65_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16860_dupName_65_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16859)@106
    assign rightShiftStage0Idx1Rng1_uid16860_dupName_65_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q[33:1];

    // rightShiftStage0Idx1_uid16862_dupName_65_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16861)@106
    assign rightShiftStage0Idx1_uid16862_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16860_dupName_65_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26682_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(BITSELECT,26681)@105
    assign leftShiftStage2Idx1Rng8_uid26682_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in = leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26682_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26682_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26683_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(BITJOIN,26682)@105
    assign leftShiftStage2Idx1_uid26683_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26682_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26677_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(BITSELECT,26676)@105
    assign leftShiftStage1Idx1Rng4_uid26677_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in = leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26677_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26677_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26678_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(BITJOIN,26677)@105
    assign leftShiftStage1Idx1_uid26678_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26677_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26672_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(BITSELECT,26671)@105
    assign leftShiftStage0Idx1Rng1_uid26672_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26672_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26672_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26673_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(BITJOIN,26672)@105
    assign leftShiftStage0Idx1_uid26673_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26672_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16808_dupName_61_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16807)@104
    assign rightShiftStage2Idx1Rng8_uid16808_dupName_61_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16810_dupName_61_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16809)@104
    assign rightShiftStage2Idx1_uid16810_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16808_dupName_61_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16803_dupName_61_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16802)@104
    assign rightShiftStage1Idx1Rng4_uid16803_dupName_61_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16805_dupName_61_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16804)@104
    assign rightShiftStage1Idx1_uid16805_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16803_dupName_61_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16798_dupName_61_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16797)@104
    assign rightShiftStage0Idx1Rng1_uid16798_dupName_61_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q[33:1];

    // rightShiftStage0Idx1_uid16800_dupName_61_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16799)@104
    assign rightShiftStage0Idx1_uid16800_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16798_dupName_61_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26664_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(BITSELECT,26663)@103
    assign leftShiftStage2Idx1Rng8_uid26664_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in = leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26664_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26664_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26665_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(BITJOIN,26664)@103
    assign leftShiftStage2Idx1_uid26665_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26664_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26659_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(BITSELECT,26658)@103
    assign leftShiftStage1Idx1Rng4_uid26659_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in = leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26659_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26659_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26660_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(BITJOIN,26659)@103
    assign leftShiftStage1Idx1_uid26660_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26659_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26654_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(BITSELECT,26653)@103
    assign leftShiftStage0Idx1Rng1_uid26654_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26654_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26654_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26655_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(BITJOIN,26654)@103
    assign leftShiftStage0Idx1_uid26655_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26654_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16746_dupName_57_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16745)@102
    assign rightShiftStage2Idx1Rng8_uid16746_dupName_57_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16748_dupName_57_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16747)@102
    assign rightShiftStage2Idx1_uid16748_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16746_dupName_57_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16741_dupName_57_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16740)@102
    assign rightShiftStage1Idx1Rng4_uid16741_dupName_57_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16743_dupName_57_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16742)@102
    assign rightShiftStage1Idx1_uid16743_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16741_dupName_57_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16736_dupName_57_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16735)@102
    assign rightShiftStage0Idx1Rng1_uid16736_dupName_57_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q[33:1];

    // rightShiftStage0Idx1_uid16738_dupName_57_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16737)@102
    assign rightShiftStage0Idx1_uid16738_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16736_dupName_57_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26646_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(BITSELECT,26645)@101
    assign leftShiftStage2Idx1Rng8_uid26646_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in = leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26646_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26646_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26647_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(BITJOIN,26646)@101
    assign leftShiftStage2Idx1_uid26647_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26646_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26641_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(BITSELECT,26640)@101
    assign leftShiftStage1Idx1Rng4_uid26641_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in = leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26641_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26641_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26642_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(BITJOIN,26641)@101
    assign leftShiftStage1Idx1_uid26642_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26641_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26636_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(BITSELECT,26635)@101
    assign leftShiftStage0Idx1Rng1_uid26636_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26636_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26636_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26637_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(BITJOIN,26636)@101
    assign leftShiftStage0Idx1_uid26637_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26636_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16684_dupName_53_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16683)@100
    assign rightShiftStage2Idx1Rng8_uid16684_dupName_53_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16686_dupName_53_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16685)@100
    assign rightShiftStage2Idx1_uid16686_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16684_dupName_53_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16679_dupName_53_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16678)@100
    assign rightShiftStage1Idx1Rng4_uid16679_dupName_53_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16681_dupName_53_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16680)@100
    assign rightShiftStage1Idx1_uid16681_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16679_dupName_53_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16674_dupName_53_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16673)@100
    assign rightShiftStage0Idx1Rng1_uid16674_dupName_53_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q[33:1];

    // rightShiftStage0Idx1_uid16676_dupName_53_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16675)@100
    assign rightShiftStage0Idx1_uid16676_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16674_dupName_53_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26628_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(BITSELECT,26627)@99
    assign leftShiftStage2Idx1Rng8_uid26628_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in = leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26628_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26628_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26629_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(BITJOIN,26628)@99
    assign leftShiftStage2Idx1_uid26629_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26628_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26623_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(BITSELECT,26622)@99
    assign leftShiftStage1Idx1Rng4_uid26623_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in = leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26623_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26623_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26624_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(BITJOIN,26623)@99
    assign leftShiftStage1Idx1_uid26624_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26623_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26618_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(BITSELECT,26617)@99
    assign leftShiftStage0Idx1Rng1_uid26618_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26618_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26618_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26619_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(BITJOIN,26618)@99
    assign leftShiftStage0Idx1_uid26619_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26618_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16622_dupName_49_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16621)@98
    assign rightShiftStage2Idx1Rng8_uid16622_dupName_49_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16624_dupName_49_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16623)@98
    assign rightShiftStage2Idx1_uid16624_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16622_dupName_49_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16617_dupName_49_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16616)@98
    assign rightShiftStage1Idx1Rng4_uid16617_dupName_49_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16619_dupName_49_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16618)@98
    assign rightShiftStage1Idx1_uid16619_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16617_dupName_49_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16612_dupName_49_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16611)@98
    assign rightShiftStage0Idx1Rng1_uid16612_dupName_49_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q[33:1];

    // rightShiftStage0Idx1_uid16614_dupName_49_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16613)@98
    assign rightShiftStage0Idx1_uid16614_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16612_dupName_49_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26610_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(BITSELECT,26609)@97
    assign leftShiftStage2Idx1Rng8_uid26610_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in = leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26610_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26610_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26611_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(BITJOIN,26610)@97
    assign leftShiftStage2Idx1_uid26611_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26610_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26605_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(BITSELECT,26604)@97
    assign leftShiftStage1Idx1Rng4_uid26605_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in = leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26605_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26605_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26606_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(BITJOIN,26605)@97
    assign leftShiftStage1Idx1_uid26606_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26605_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26600_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(BITSELECT,26599)@97
    assign leftShiftStage0Idx1Rng1_uid26600_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26600_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26600_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26601_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(BITJOIN,26600)@97
    assign leftShiftStage0Idx1_uid26601_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26600_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16560_dupName_45_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16559)@96
    assign rightShiftStage2Idx1Rng8_uid16560_dupName_45_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16562_dupName_45_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16561)@96
    assign rightShiftStage2Idx1_uid16562_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16560_dupName_45_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16555_dupName_45_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16554)@96
    assign rightShiftStage1Idx1Rng4_uid16555_dupName_45_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16557_dupName_45_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16556)@96
    assign rightShiftStage1Idx1_uid16557_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16555_dupName_45_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16550_dupName_45_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16549)@96
    assign rightShiftStage0Idx1Rng1_uid16550_dupName_45_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q[33:1];

    // rightShiftStage0Idx1_uid16552_dupName_45_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16551)@96
    assign rightShiftStage0Idx1_uid16552_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16550_dupName_45_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26448_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(BITSELECT,26447)@95
    assign leftShiftStage2Idx1Rng8_uid26448_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in = leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26448_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26448_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26449_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(BITJOIN,26448)@95
    assign leftShiftStage2Idx1_uid26449_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26448_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26443_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(BITSELECT,26442)@95
    assign leftShiftStage1Idx1Rng4_uid26443_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in = leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26443_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26443_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26444_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(BITJOIN,26443)@95
    assign leftShiftStage1Idx1_uid26444_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26443_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26438_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(BITSELECT,26437)@95
    assign leftShiftStage0Idx1Rng1_uid26438_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26438_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26438_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26439_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(BITJOIN,26438)@95
    assign leftShiftStage0Idx1_uid26439_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26438_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16498_dupName_41_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16497)@94
    assign rightShiftStage2Idx1Rng8_uid16498_dupName_41_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16500_dupName_41_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16499)@94
    assign rightShiftStage2Idx1_uid16500_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16498_dupName_41_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16493_dupName_41_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16492)@94
    assign rightShiftStage1Idx1Rng4_uid16493_dupName_41_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16495_dupName_41_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16494)@94
    assign rightShiftStage1Idx1_uid16495_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16493_dupName_41_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16488_dupName_41_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16487)@94
    assign rightShiftStage0Idx1Rng1_uid16488_dupName_41_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q[33:1];

    // rightShiftStage0Idx1_uid16490_dupName_41_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16489)@94
    assign rightShiftStage0Idx1_uid16490_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16488_dupName_41_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26250_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(BITSELECT,26249)@94
    assign leftShiftStage2Idx1Rng8_uid26250_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in = leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26250_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26250_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26251_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(BITJOIN,26250)@94
    assign leftShiftStage2Idx1_uid26251_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26250_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26245_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(BITSELECT,26244)@94
    assign leftShiftStage1Idx1Rng4_uid26245_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in = leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26245_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26245_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26246_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(BITJOIN,26245)@94
    assign leftShiftStage1Idx1_uid26246_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26245_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26240_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(BITSELECT,26239)@94
    assign leftShiftStage0Idx1Rng1_uid26240_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26240_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26240_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26241_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(BITJOIN,26240)@94
    assign leftShiftStage0Idx1_uid26241_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26240_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16436_dupName_37_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16435)@92
    assign rightShiftStage2Idx1Rng8_uid16436_dupName_37_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16438_dupName_37_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16437)@92
    assign rightShiftStage2Idx1_uid16438_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16436_dupName_37_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16431_dupName_37_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16430)@92
    assign rightShiftStage1Idx1Rng4_uid16431_dupName_37_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16433_dupName_37_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16432)@92
    assign rightShiftStage1Idx1_uid16433_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16431_dupName_37_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16426_dupName_37_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16425)@92
    assign rightShiftStage0Idx1Rng1_uid16426_dupName_37_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q[33:1];

    // rightShiftStage0Idx1_uid16428_dupName_37_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16427)@92
    assign rightShiftStage0Idx1_uid16428_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16426_dupName_37_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28338_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(BITSELECT,28337)@91
    assign leftShiftStage2Idx1Rng8_uid28338_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in = leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28338_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28338_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28339_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(BITJOIN,28338)@91
    assign leftShiftStage2Idx1_uid28339_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28338_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28333_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(BITSELECT,28332)@91
    assign leftShiftStage1Idx1Rng4_uid28333_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in = leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28333_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28333_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28334_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(BITJOIN,28333)@91
    assign leftShiftStage1Idx1_uid28334_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28333_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28328_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(BITSELECT,28327)@91
    assign leftShiftStage0Idx1Rng1_uid28328_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28328_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28328_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28329_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(BITJOIN,28328)@91
    assign leftShiftStage0Idx1_uid28329_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28328_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16374_dupName_33_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16373)@90
    assign rightShiftStage2Idx1Rng8_uid16374_dupName_33_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16376_dupName_33_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16375)@90
    assign rightShiftStage2Idx1_uid16376_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16374_dupName_33_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16369_dupName_33_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16368)@90
    assign rightShiftStage1Idx1Rng4_uid16369_dupName_33_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16371_dupName_33_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16370)@90
    assign rightShiftStage1Idx1_uid16371_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16369_dupName_33_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16364_dupName_33_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16363)@90
    assign rightShiftStage0Idx1Rng1_uid16364_dupName_33_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q[33:1];

    // rightShiftStage0Idx1_uid16366_dupName_33_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16365)@90
    assign rightShiftStage0Idx1_uid16366_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16364_dupName_33_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid28140_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(BITSELECT,28139)@89
    assign leftShiftStage2Idx1Rng8_uid28140_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in = leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid28140_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid28140_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid28141_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(BITJOIN,28140)@89
    assign leftShiftStage2Idx1_uid28141_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid28140_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid28135_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(BITSELECT,28134)@89
    assign leftShiftStage1Idx1Rng4_uid28135_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in = leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid28135_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid28135_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid28136_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(BITJOIN,28135)@89
    assign leftShiftStage1Idx1_uid28136_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid28135_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid28130_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(BITSELECT,28129)@89
    assign leftShiftStage0Idx1Rng1_uid28130_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid28130_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid28130_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid28131_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(BITJOIN,28130)@89
    assign leftShiftStage0Idx1_uid28131_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid28130_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16312_dupName_29_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16311)@88
    assign rightShiftStage2Idx1Rng8_uid16312_dupName_29_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16314_dupName_29_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16313)@88
    assign rightShiftStage2Idx1_uid16314_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16312_dupName_29_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16307_dupName_29_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16306)@88
    assign rightShiftStage1Idx1Rng4_uid16307_dupName_29_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16309_dupName_29_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16308)@88
    assign rightShiftStage1Idx1_uid16309_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16307_dupName_29_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16302_dupName_29_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16301)@88
    assign rightShiftStage0Idx1Rng1_uid16302_dupName_29_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q[33:1];

    // rightShiftStage0Idx1_uid16304_dupName_29_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16303)@88
    assign rightShiftStage0Idx1_uid16304_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16302_dupName_29_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27942_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(BITSELECT,27941)@87
    assign leftShiftStage2Idx1Rng8_uid27942_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in = leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27942_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27942_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27943_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(BITJOIN,27942)@87
    assign leftShiftStage2Idx1_uid27943_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27942_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27937_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(BITSELECT,27936)@87
    assign leftShiftStage1Idx1Rng4_uid27937_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in = leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27937_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27937_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27938_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(BITJOIN,27937)@87
    assign leftShiftStage1Idx1_uid27938_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27937_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27932_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(BITSELECT,27931)@87
    assign leftShiftStage0Idx1Rng1_uid27932_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27932_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27932_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27933_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(BITJOIN,27932)@87
    assign leftShiftStage0Idx1_uid27933_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27932_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16250_dupName_25_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16249)@86
    assign rightShiftStage2Idx1Rng8_uid16250_dupName_25_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16252_dupName_25_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16251)@86
    assign rightShiftStage2Idx1_uid16252_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16250_dupName_25_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16245_dupName_25_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16244)@86
    assign rightShiftStage1Idx1Rng4_uid16245_dupName_25_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16247_dupName_25_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16246)@86
    assign rightShiftStage1Idx1_uid16247_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16245_dupName_25_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16240_dupName_25_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16239)@86
    assign rightShiftStage0Idx1Rng1_uid16240_dupName_25_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q[33:1];

    // rightShiftStage0Idx1_uid16242_dupName_25_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16241)@86
    assign rightShiftStage0Idx1_uid16242_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16240_dupName_25_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27744_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(BITSELECT,27743)@85
    assign leftShiftStage2Idx1Rng8_uid27744_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in = leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27744_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27744_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27745_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(BITJOIN,27744)@85
    assign leftShiftStage2Idx1_uid27745_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27744_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27739_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(BITSELECT,27738)@85
    assign leftShiftStage1Idx1Rng4_uid27739_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in = leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27739_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27739_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27740_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(BITJOIN,27739)@85
    assign leftShiftStage1Idx1_uid27740_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27739_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27734_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(BITSELECT,27733)@85
    assign leftShiftStage0Idx1Rng1_uid27734_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27734_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27734_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27735_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(BITJOIN,27734)@85
    assign leftShiftStage0Idx1_uid27735_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27734_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16188_dupName_21_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16187)@84
    assign rightShiftStage2Idx1Rng8_uid16188_dupName_21_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16190_dupName_21_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16189)@84
    assign rightShiftStage2Idx1_uid16190_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16188_dupName_21_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16183_dupName_21_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16182)@84
    assign rightShiftStage1Idx1Rng4_uid16183_dupName_21_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16185_dupName_21_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16184)@84
    assign rightShiftStage1Idx1_uid16185_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16183_dupName_21_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16178_dupName_21_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16177)@84
    assign rightShiftStage0Idx1Rng1_uid16178_dupName_21_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q[33:1];

    // rightShiftStage0Idx1_uid16180_dupName_21_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16179)@84
    assign rightShiftStage0Idx1_uid16180_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16178_dupName_21_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27546_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(BITSELECT,27545)@83
    assign leftShiftStage2Idx1Rng8_uid27546_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in = leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27546_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27546_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27547_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(BITJOIN,27546)@83
    assign leftShiftStage2Idx1_uid27547_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27546_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27541_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(BITSELECT,27540)@83
    assign leftShiftStage1Idx1Rng4_uid27541_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in = leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27541_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27541_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27542_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(BITJOIN,27541)@83
    assign leftShiftStage1Idx1_uid27542_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27541_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27536_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(BITSELECT,27535)@83
    assign leftShiftStage0Idx1Rng1_uid27536_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27536_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27536_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27537_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(BITJOIN,27536)@83
    assign leftShiftStage0Idx1_uid27537_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27536_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16126_dupName_17_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16125)@82
    assign rightShiftStage2Idx1Rng8_uid16126_dupName_17_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16128_dupName_17_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16127)@82
    assign rightShiftStage2Idx1_uid16128_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16126_dupName_17_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16121_dupName_17_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16120)@82
    assign rightShiftStage1Idx1Rng4_uid16121_dupName_17_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16123_dupName_17_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16122)@82
    assign rightShiftStage1Idx1_uid16123_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16121_dupName_17_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16116_dupName_17_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16115)@82
    assign rightShiftStage0Idx1Rng1_uid16116_dupName_17_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q[33:1];

    // rightShiftStage0Idx1_uid16118_dupName_17_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16117)@82
    assign rightShiftStage0Idx1_uid16118_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16116_dupName_17_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27348_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(BITSELECT,27347)@81
    assign leftShiftStage2Idx1Rng8_uid27348_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in = leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27348_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27348_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27349_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(BITJOIN,27348)@81
    assign leftShiftStage2Idx1_uid27349_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27348_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27343_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(BITSELECT,27342)@81
    assign leftShiftStage1Idx1Rng4_uid27343_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in = leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27343_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27343_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27344_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(BITJOIN,27343)@81
    assign leftShiftStage1Idx1_uid27344_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27343_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27338_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(BITSELECT,27337)@81
    assign leftShiftStage0Idx1Rng1_uid27338_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27338_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27338_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27339_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(BITJOIN,27338)@81
    assign leftShiftStage0Idx1_uid27339_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27338_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16064_dupName_13_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16063)@80
    assign rightShiftStage2Idx1Rng8_uid16064_dupName_13_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16066_dupName_13_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16065)@80
    assign rightShiftStage2Idx1_uid16066_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16064_dupName_13_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16059_dupName_13_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16058)@80
    assign rightShiftStage1Idx1Rng4_uid16059_dupName_13_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16061_dupName_13_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16060)@80
    assign rightShiftStage1Idx1_uid16061_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16059_dupName_13_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16054_dupName_13_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16053)@80
    assign rightShiftStage0Idx1Rng1_uid16054_dupName_13_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q[33:1];

    // rightShiftStage0Idx1_uid16056_dupName_13_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16055)@80
    assign rightShiftStage0Idx1_uid16056_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16054_dupName_13_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid27150_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(BITSELECT,27149)@79
    assign leftShiftStage2Idx1Rng8_uid27150_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in = leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid27150_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid27150_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid27151_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(BITJOIN,27150)@79
    assign leftShiftStage2Idx1_uid27151_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid27150_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid27145_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(BITSELECT,27144)@79
    assign leftShiftStage1Idx1Rng4_uid27145_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in = leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid27145_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid27145_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid27146_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(BITJOIN,27145)@79
    assign leftShiftStage1Idx1_uid27146_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid27145_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid27140_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(BITSELECT,27139)@79
    assign leftShiftStage0Idx1Rng1_uid27140_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid27140_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid27140_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid27141_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(BITJOIN,27140)@79
    assign leftShiftStage0Idx1_uid27141_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid27140_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16002_dupName_9_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16001)@78
    assign rightShiftStage2Idx1Rng8_uid16002_dupName_9_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16004_dupName_9_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16003)@78
    assign rightShiftStage2Idx1_uid16004_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16002_dupName_9_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15997_dupName_9_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15996)@78
    assign rightShiftStage1Idx1Rng4_uid15997_dupName_9_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15999_dupName_9_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15998)@78
    assign rightShiftStage1Idx1_uid15999_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid15997_dupName_9_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15992_dupName_9_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15991)@78
    assign rightShiftStage0Idx1Rng1_uid15992_dupName_9_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q[33:1];

    // rightShiftStage0Idx1_uid15994_dupName_9_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15993)@78
    assign rightShiftStage0Idx1_uid15994_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15992_dupName_9_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26952_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(BITSELECT,26951)@78
    assign leftShiftStage2Idx1Rng8_uid26952_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in = leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26952_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26952_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26953_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(BITJOIN,26952)@78
    assign leftShiftStage2Idx1_uid26953_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26952_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26947_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(BITSELECT,26946)@78
    assign leftShiftStage1Idx1Rng4_uid26947_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in = leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26947_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26947_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26948_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(BITJOIN,26947)@78
    assign leftShiftStage1Idx1_uid26948_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26947_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26942_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(BITSELECT,26941)@78
    assign leftShiftStage0Idx1Rng1_uid26942_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26942_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26942_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26943_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(BITJOIN,26942)@78
    assign leftShiftStage0Idx1_uid26943_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26942_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15940_dupName_5_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15939)@76
    assign rightShiftStage2Idx1Rng8_uid15940_dupName_5_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15942_dupName_5_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15941)@76
    assign rightShiftStage2Idx1_uid15942_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid15940_dupName_5_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15935_dupName_5_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15934)@76
    assign rightShiftStage1Idx1Rng4_uid15935_dupName_5_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15937_dupName_5_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15936)@76
    assign rightShiftStage1Idx1_uid15937_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid15935_dupName_5_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15930_dupName_5_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15929)@76
    assign rightShiftStage0Idx1Rng1_uid15930_dupName_5_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q[33:1];

    // rightShiftStage0Idx1_uid15932_dupName_5_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15931)@76
    assign rightShiftStage0Idx1_uid15932_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15930_dupName_5_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26754_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(BITSELECT,26753)@75
    assign leftShiftStage2Idx1Rng8_uid26754_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in = leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26754_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26754_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26755_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(BITJOIN,26754)@75
    assign leftShiftStage2Idx1_uid26755_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26754_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26749_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(BITSELECT,26748)@75
    assign leftShiftStage1Idx1Rng4_uid26749_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in = leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26749_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26749_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26750_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(BITJOIN,26749)@75
    assign leftShiftStage1Idx1_uid26750_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26749_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26744_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(BITSELECT,26743)@75
    assign leftShiftStage0Idx1Rng1_uid26744_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26744_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26744_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26745_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(BITJOIN,26744)@75
    assign leftShiftStage0Idx1_uid26745_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26744_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15878_dupName_1_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15877)@75
    assign rightShiftStage2Idx1Rng8_uid15878_dupName_1_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15880_dupName_1_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15879)@75
    assign rightShiftStage2Idx1_uid15880_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid15878_dupName_1_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15873_dupName_1_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15872)@75
    assign rightShiftStage1Idx1Rng4_uid15873_dupName_1_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15875_dupName_1_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15874)@75
    assign rightShiftStage1Idx1_uid15875_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid15873_dupName_1_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15868_dupName_1_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15867)@75
    assign rightShiftStage0Idx1Rng1_uid15868_dupName_1_i_unnamed_c_compmm_m0_shift_x_b = i_conv_i_i_i_i_c_compmm_m276_sel_x_b[33:1];

    // rightShiftStage0Idx1_uid15870_dupName_1_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15869)@75
    assign rightShiftStage0Idx1_uid15870_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15868_dupName_1_i_unnamed_c_compmm_m0_shift_x_b};

    // valid_fanout_reg255(REG,13550)@68 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg255_q <= $unsigned(in_i_valid);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6420_c_compmm_m256(BLACKBOX,8608)@69
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6420_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6420_c_compmm_m256 (
        .in_intel_reserved_ffwd_2_0(in_intel_reserved_ffwd_2_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg255_q),
        .out_dest_data_out_2_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6420_c_compmm_m256_out_dest_data_out_2_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist503_sync_together4364_aunroll_x_in_c1_eni5_1_tpl_1(DELAY,29631)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist503_sync_together4364_aunroll_x_in_c1_eni5_1_tpl_1_q <= $unsigned(in_c1_eni5_1_tpl);
        end
    end

    // redist504_sync_together4364_aunroll_x_in_c1_eni5_2_tpl_1(DELAY,29632)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist504_sync_together4364_aunroll_x_in_c1_eni5_2_tpl_1_q <= $unsigned(in_c1_eni5_2_tpl);
        end
    end

    // valid_fanout_reg256(REG,13551)@68 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg256_q <= $unsigned(in_i_valid);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6419_c_compmm_m257(BLACKBOX,8564)@69
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6419_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6419_c_compmm_m257 (
        .in_intel_reserved_ffwd_1_0(in_intel_reserved_ffwd_1_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg256_q),
        .out_dest_data_out_1_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6419_c_compmm_m257_out_dest_data_out_1_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28999)@69 + 5
    // out q@75
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6419_c_compmm_m257_out_dest_data_out_1_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist503_sync_together4364_aunroll_x_in_c1_eni5_1_tpl_1_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist504_sync_together4364_aunroll_x_in_c1_eni5_2_tpl_1_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6420_c_compmm_m256_out_dest_data_out_2_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_conv_i_i_i_i_c_compmm_m276_sel_x(BITSELECT,3577)@75
    assign i_conv_i_i_i_i_c_compmm_m276_sel_x_b = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32:0]});

    // rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x(MUX,15871)@75
    assign rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_c_compmm_m276_sel_x_b or rightShiftStage0Idx1_uid15870_dupName_1_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_c_compmm_m276_sel_x_b;
            1'b1 : rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15870_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x(MUX,15876)@75
    assign rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15875_dupName_1_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15872_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15875_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x(MUX,15881)@75
    assign rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid15880_dupName_1_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid15877_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid15880_dupName_1_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m277_vt_select_20(BITSELECT,11630)@75
    assign i_unnamed_c_compmm_m277_vt_select_20_b = rightShiftStage2_uid15882_dupName_1_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m277_vt_join(BITJOIN,11629)@75
    assign i_unnamed_c_compmm_m277_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m277_vt_select_20_b};

    // i_conv_i_i_i_i_i_c_compmm_m278_sel_x(BITSELECT,3832)@75
    assign i_conv_i_i_i_i_i_c_compmm_m278_sel_x_b = i_unnamed_c_compmm_m277_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1009_vt_const_15(CONSTANT,10228)
    assign i_unnamed_c_compmm_m1009_vt_const_15_q = $unsigned(15'b000000000000000);

    // i_unnamed_c_compmm_m1007_vt_const_33(CONSTANT,10223)
    assign i_unnamed_c_compmm_m1007_vt_const_33_q = $unsigned(12'b000000000000);

    // rightShiftStage1Idx1Rng8_uid15891_dupName_2_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15890)@75
    assign rightShiftStage1Idx1Rng8_uid15891_dupName_2_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15893_dupName_2_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15892)@75
    assign rightShiftStage1Idx1_uid15893_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid15891_dupName_2_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15886_dupName_2_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15885)@75
    assign rightShiftStage0Idx1Rng4_uid15886_dupName_2_i_unnamed_c_compmm_m0_shift_x_b = i_conv_i_i_i_i_c_compmm_m276_sel_x_b[33:4];

    // rightShiftStage0Idx1_uid15888_dupName_2_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15887)@75
    assign rightShiftStage0Idx1_uid15888_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid15886_dupName_2_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x(MUX,15889)@75
    assign rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_c_compmm_m276_sel_x_b or rightShiftStage0Idx1_uid15888_dupName_2_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_c_compmm_m276_sel_x_b;
            1'b1 : rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15888_dupName_2_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x(MUX,15894)@75
    assign rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15893_dupName_2_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15890_dupName_2_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15893_dupName_2_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m279_vt_select_21(BITSELECT,11647)@75
    assign i_unnamed_c_compmm_m279_vt_select_21_b = rightShiftStage1_uid15895_dupName_2_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m279_vt_join(BITJOIN,11646)@75
    assign i_unnamed_c_compmm_m279_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m279_vt_select_21_b};

    // i_unnamed_c_compmm_m280_sel_x(BITSELECT,6133)@75
    assign i_unnamed_c_compmm_m280_sel_x_b = i_unnamed_c_compmm_m279_vt_join_q[15:0];

    // i_unnamed_c_compmm_m281_BitSelect_for_a(BITSELECT,28620)@75
    assign i_unnamed_c_compmm_m281_BitSelect_for_a_b = i_unnamed_c_compmm_m280_sel_x_b[0:0];

    // i_unnamed_c_compmm_m281_join(BITJOIN,28621)@75
    assign i_unnamed_c_compmm_m281_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m281_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m281_vt_select_0(BITSELECT,11671)@75
    assign i_unnamed_c_compmm_m281_vt_select_0_b = i_unnamed_c_compmm_m281_join_q[0:0];

    // i_unnamed_c_compmm_m281_vt_join(BITJOIN,11670)@75
    assign i_unnamed_c_compmm_m281_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, i_unnamed_c_compmm_m281_vt_select_0_b};

    // i_add_i_i_i_i_i_i_c_compmm_m282(ADD,7287)@75
    assign i_add_i_i_i_i_i_i_c_compmm_m282_a = {1'b0, i_unnamed_c_compmm_m281_vt_join_q};
    assign i_add_i_i_i_i_i_i_c_compmm_m282_b = {1'b0, i_conv_i_i_i_i_i_c_compmm_m278_sel_x_b};
    assign i_add_i_i_i_i_i_i_c_compmm_m282_o = $unsigned(i_add_i_i_i_i_i_i_c_compmm_m282_a) + $unsigned(i_add_i_i_i_i_i_i_c_compmm_m282_b);
    assign i_add_i_i_i_i_i_i_c_compmm_m282_q = i_add_i_i_i_i_i_i_c_compmm_m282_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_c_compmm_m282_sel_x(BITSELECT,2301)@75
    assign bgTrunc_i_add_i_i_i_i_i_i_c_compmm_m282_sel_x_b = i_add_i_i_i_i_i_i_c_compmm_m282_q[15:0];

    // i_conv_i_i_i_i_i_i246_1_c_compmm_m302_sel_x(BITSELECT,3871)@75
    assign i_conv_i_i_i_i_i_i246_1_c_compmm_m302_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_c_compmm_m282_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_select_15(BITSELECT,8211)@75
    assign i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_select_15_b = i_conv_i_i_i_i_i_i246_1_c_compmm_m302_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_join(BITJOIN,8210)@75
    assign i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_select_15_b};

    // leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(MUX,26746)@75
    assign leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_join_q or leftShiftStage0Idx1_uid26745_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_1_c_compmm_m302_vt_join_q;
            1'b1 : leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26745_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(MUX,26751)@75
    assign leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s or leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26750_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = leftShiftStage0_uid26747_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26750_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x(MUX,26756)@75
    assign leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s or leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26755_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = leftShiftStage1_uid26752_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26755_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28(BITSELECT,9955)@75
    assign i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28_b = leftShiftStage2_uid26757_i_shl_i_i_i_i_i_i_1_c_compmm_m0_shift_x_q[28:13];

    // redist341_i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28_b_1(DELAY,29469)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist341_i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_join(BITJOIN,9954)@76
    assign i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_join_q = {redist341_i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg253(REG,13548)@69 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg253_q <= $unsigned(redist760_sync_together4364_aunroll_x_in_i_valid_1_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6422_c_compmm_m254(BLACKBOX,8696)@70
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6422_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6422_c_compmm_m254 (
        .in_intel_reserved_ffwd_4_0(in_intel_reserved_ffwd_4_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg253_q),
        .out_dest_data_out_4_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6422_c_compmm_m254_out_dest_data_out_4_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2(DELAY,29633)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2_delay_0 <= $unsigned(in_c1_eni5_3_tpl);
            redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2_q <= redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2_delay_0;
        end
    end

    // redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2(DELAY,29634)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2_delay_0 <= $unsigned(in_c1_eni5_4_tpl);
            redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2_q <= redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2_delay_0;
        end
    end

    // valid_fanout_reg254(REG,13549)@69 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg254_q <= $unsigned(redist760_sync_together4364_aunroll_x_in_i_valid_1_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6421_c_compmm_m255(BLACKBOX,8652)@70
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6421_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6421_c_compmm_m255 (
        .in_intel_reserved_ffwd_3_0(in_intel_reserved_ffwd_3_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg254_q),
        .out_dest_data_out_3_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6421_c_compmm_m255_out_dest_data_out_3_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28872)@70 + 5
    // out q@76
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6421_c_compmm_m255_out_dest_data_out_3_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6422_c_compmm_m254_out_dest_data_out_4_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304(ADD,8985)@76
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod287_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_b = $unsigned({{5{i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_1_c_compmm_m303_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_o[33:0];

    // rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x(MUX,15933)@76
    assign rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q or rightShiftStage0Idx1_uid15932_dupName_5_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q;
            1'b1 : rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15932_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x(MUX,15938)@76
    assign rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15937_dupName_5_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15934_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15937_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x(MUX,15943)@76
    assign rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid15942_dupName_5_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid15939_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid15942_dupName_5_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m305_vt_select_20(BITSELECT,11872)@76
    assign i_unnamed_c_compmm_m305_vt_select_20_b = rightShiftStage2_uid15944_dupName_5_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m305_vt_join(BITJOIN,11871)@76
    assign i_unnamed_c_compmm_m305_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m305_vt_select_20_b};

    // i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x(BITSELECT,3743)@76
    assign i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x_b = i_unnamed_c_compmm_m305_vt_join_q[15:0];

    // redist975_i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x_b_1(DELAY,30103)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist975_i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15953_dupName_6_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15952)@76
    assign rightShiftStage1Idx1Rng8_uid15953_dupName_6_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15955_dupName_6_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15954)@76
    assign rightShiftStage1Idx1_uid15955_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid15953_dupName_6_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15948_dupName_6_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15947)@76
    assign rightShiftStage0Idx1Rng4_uid15948_dupName_6_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q[33:4];

    // rightShiftStage0Idx1_uid15950_dupName_6_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15949)@76
    assign rightShiftStage0Idx1_uid15950_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid15948_dupName_6_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x(MUX,15951)@76
    assign rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q or rightShiftStage0Idx1_uid15950_dupName_6_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_1_i_c_compmm_m304_q;
            1'b1 : rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15950_dupName_6_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x(MUX,15956)@76
    assign rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15955_dupName_6_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15952_dupName_6_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15955_dupName_6_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m307_vt_select_21(BITSELECT,11886)@76
    assign i_unnamed_c_compmm_m307_vt_select_21_b = rightShiftStage1_uid15957_dupName_6_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m307_vt_join(BITJOIN,11885)@76
    assign i_unnamed_c_compmm_m307_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m307_vt_select_21_b};

    // i_unnamed_c_compmm_m308_sel_x(BITSELECT,6155)@76
    assign i_unnamed_c_compmm_m308_sel_x_b = i_unnamed_c_compmm_m307_vt_join_q[15:0];

    // i_unnamed_c_compmm_m309_BitSelect_for_a(BITSELECT,28664)@76
    assign i_unnamed_c_compmm_m309_BitSelect_for_a_b = i_unnamed_c_compmm_m308_sel_x_b[0:0];

    // i_unnamed_c_compmm_m309_join(BITJOIN,28665)@76
    assign i_unnamed_c_compmm_m309_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m309_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m309_vt_select_0(BITSELECT,11913)@76
    assign i_unnamed_c_compmm_m309_vt_select_0_b = i_unnamed_c_compmm_m309_join_q[0:0];

    // redist103_i_unnamed_c_compmm_m309_vt_select_0_b_1(DELAY,29231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist103_i_unnamed_c_compmm_m309_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m309_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m309_vt_join(BITJOIN,11912)@77
    assign i_unnamed_c_compmm_m309_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist103_i_unnamed_c_compmm_m309_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_1_c_compmm_m310(ADD,7198)@77
    assign i_add_i_i_i_i_i_i_1_c_compmm_m310_a = {1'b0, i_unnamed_c_compmm_m309_vt_join_q};
    assign i_add_i_i_i_i_i_i_1_c_compmm_m310_b = {1'b0, redist975_i_conv_i_i_i_i_i_1_c_compmm_m306_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_1_c_compmm_m310_o = $unsigned(i_add_i_i_i_i_i_i_1_c_compmm_m310_a) + $unsigned(i_add_i_i_i_i_i_i_1_c_compmm_m310_b);
    assign i_add_i_i_i_i_i_i_1_c_compmm_m310_q = i_add_i_i_i_i_i_i_1_c_compmm_m310_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x(BITSELECT,2212)@77
    assign bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x_b = i_add_i_i_i_i_i_i_1_c_compmm_m310_q[15:0];

    // redist1143_bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x_b_1(DELAY,30271)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1143_bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x_b_1_q <= $unsigned(bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x_b);
        end
    end

    // i_conv_i_i_i_i_i_i246_2_c_compmm_m330_sel_x(BITSELECT,3882)@78
    assign i_conv_i_i_i_i_i_i246_2_c_compmm_m330_sel_x_b = {13'b0000000000000, redist1143_bgTrunc_i_add_i_i_i_i_i_i_1_c_compmm_m310_sel_x_b_1_q[15:0]};

    // i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_select_15(BITSELECT,8255)@78
    assign i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_select_15_b = i_conv_i_i_i_i_i_i246_2_c_compmm_m330_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_join(BITJOIN,8254)@78
    assign i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_select_15_b};

    // leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(MUX,26944)@78
    assign leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_join_q or leftShiftStage0Idx1_uid26943_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_2_c_compmm_m330_vt_join_q;
            1'b1 : leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26943_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(MUX,26949)@78
    assign leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s or leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26948_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = leftShiftStage0_uid26945_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26948_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x(MUX,26954)@78
    assign leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s or leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26953_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = leftShiftStage1_uid26950_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26953_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_select_28(BITSELECT,9988)@78
    assign i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_select_28_b = leftShiftStage2_uid26955_i_shl_i_i_i_i_i_i_2_c_compmm_m0_shift_x_q[28:13];

    // i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_join(BITJOIN,9987)@78
    assign i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_join_q = {i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_select_28_b, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg251(REG,13546)@71 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg251_q <= $unsigned(redist761_sync_together4364_aunroll_x_in_i_valid_3_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6424_c_compmm_m252(BLACKBOX,8784)@72
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6424_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6424_c_compmm_m252 (
        .in_intel_reserved_ffwd_6_0(in_intel_reserved_ffwd_6_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg251_q),
        .out_dest_data_out_6_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6424_c_compmm_m252_out_dest_data_out_6_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_inputreg0(DELAY,30337)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_inputreg0_q <= $unsigned(in_c1_eni5_5_tpl);
        end
    end

    // redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4(DELAY,29635)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_delay_0 <= $unsigned(redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_inputreg0_q);
            redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_delay_1 <= redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_delay_0;
            redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_q <= redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_delay_1;
        end
    end

    // redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_inputreg0(DELAY,30338)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_inputreg0_q <= $unsigned(in_c1_eni5_6_tpl);
        end
    end

    // redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4(DELAY,29636)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_delay_0 <= $unsigned(redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_inputreg0_q);
            redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_delay_1 <= redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_delay_0;
            redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_q <= redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_delay_1;
        end
    end

    // valid_fanout_reg252(REG,13547)@71 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg252_q <= $unsigned(redist761_sync_together4364_aunroll_x_in_i_valid_3_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6423_c_compmm_m253(BLACKBOX,8740)@72
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6423_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6423_c_compmm_m253 (
        .in_intel_reserved_ffwd_5_0(in_intel_reserved_ffwd_5_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg252_q),
        .out_dest_data_out_5_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6423_c_compmm_m253_out_dest_data_out_5_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28873)@72 + 5
    // out q@78
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6423_c_compmm_m253_out_dest_data_out_5_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6424_c_compmm_m252_out_dest_data_out_6_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332(ADD,8996)@78
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod292_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_b = $unsigned({{5{i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_2_c_compmm_m331_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_o[33:0];

    // rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x(MUX,15995)@78
    assign rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q or rightShiftStage0Idx1_uid15994_dupName_9_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q;
            1'b1 : rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15994_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x(MUX,16000)@78
    assign rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15999_dupName_9_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15996_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15999_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x(MUX,16005)@78
    assign rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16004_dupName_9_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16001_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16004_dupName_9_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m333_vt_select_20(BITSELECT,12114)@78
    assign i_unnamed_c_compmm_m333_vt_select_20_b = rightShiftStage2_uid16006_dupName_9_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m333_vt_join(BITJOIN,12113)@78
    assign i_unnamed_c_compmm_m333_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m333_vt_select_20_b};

    // i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x(BITSELECT,3754)@78
    assign i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x_b = i_unnamed_c_compmm_m333_vt_join_q[15:0];

    // redist964_i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x_b_1(DELAY,30092)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist964_i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16015_dupName_10_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16014)@78
    assign rightShiftStage1Idx1Rng8_uid16015_dupName_10_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16017_dupName_10_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16016)@78
    assign rightShiftStage1Idx1_uid16017_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16015_dupName_10_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16010_dupName_10_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16009)@78
    assign rightShiftStage0Idx1Rng4_uid16010_dupName_10_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q[33:4];

    // rightShiftStage0Idx1_uid16012_dupName_10_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16011)@78
    assign rightShiftStage0Idx1_uid16012_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16010_dupName_10_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x(MUX,16013)@78
    assign rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q or rightShiftStage0Idx1_uid16012_dupName_10_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_2_i_c_compmm_m332_q;
            1'b1 : rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16012_dupName_10_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x(MUX,16018)@78
    assign rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16017_dupName_10_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16014_dupName_10_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16017_dupName_10_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m335_vt_select_21(BITSELECT,12128)@78
    assign i_unnamed_c_compmm_m335_vt_select_21_b = rightShiftStage1_uid16019_dupName_10_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m335_vt_join(BITJOIN,12127)@78
    assign i_unnamed_c_compmm_m335_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m335_vt_select_21_b};

    // i_unnamed_c_compmm_m336_sel_x(BITSELECT,6177)@78
    assign i_unnamed_c_compmm_m336_sel_x_b = i_unnamed_c_compmm_m335_vt_join_q[15:0];

    // i_unnamed_c_compmm_m337_BitSelect_for_a(BITSELECT,28708)@78
    assign i_unnamed_c_compmm_m337_BitSelect_for_a_b = i_unnamed_c_compmm_m336_sel_x_b[0:0];

    // i_unnamed_c_compmm_m337_join(BITJOIN,28709)@78
    assign i_unnamed_c_compmm_m337_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m337_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m337_vt_select_0(BITSELECT,12155)@78
    assign i_unnamed_c_compmm_m337_vt_select_0_b = i_unnamed_c_compmm_m337_join_q[0:0];

    // redist82_i_unnamed_c_compmm_m337_vt_select_0_b_1(DELAY,29210)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist82_i_unnamed_c_compmm_m337_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m337_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m337_vt_join(BITJOIN,12154)@79
    assign i_unnamed_c_compmm_m337_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist82_i_unnamed_c_compmm_m337_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_2_c_compmm_m338(ADD,7209)@79
    assign i_add_i_i_i_i_i_i_2_c_compmm_m338_a = {1'b0, i_unnamed_c_compmm_m337_vt_join_q};
    assign i_add_i_i_i_i_i_i_2_c_compmm_m338_b = {1'b0, redist964_i_conv_i_i_i_i_i_2_c_compmm_m334_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_2_c_compmm_m338_o = $unsigned(i_add_i_i_i_i_i_i_2_c_compmm_m338_a) + $unsigned(i_add_i_i_i_i_i_i_2_c_compmm_m338_b);
    assign i_add_i_i_i_i_i_i_2_c_compmm_m338_q = i_add_i_i_i_i_i_i_2_c_compmm_m338_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_2_c_compmm_m338_sel_x(BITSELECT,2223)@79
    assign bgTrunc_i_add_i_i_i_i_i_i_2_c_compmm_m338_sel_x_b = i_add_i_i_i_i_i_i_2_c_compmm_m338_q[15:0];

    // i_conv_i_i_i_i_i_i246_3_c_compmm_m358_sel_x(BITSELECT,3893)@79
    assign i_conv_i_i_i_i_i_i246_3_c_compmm_m358_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_2_c_compmm_m338_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_select_15(BITSELECT,8299)@79
    assign i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_select_15_b = i_conv_i_i_i_i_i_i246_3_c_compmm_m358_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_join(BITJOIN,8298)@79
    assign i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_select_15_b};

    // leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(MUX,27142)@79
    assign leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_join_q or leftShiftStage0Idx1_uid27141_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_3_c_compmm_m358_vt_join_q;
            1'b1 : leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27141_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(MUX,27147)@79
    assign leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s or leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27146_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = leftShiftStage0_uid27143_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27146_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x(MUX,27152)@79
    assign leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s or leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27151_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = leftShiftStage1_uid27148_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27151_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28(BITSELECT,10021)@79
    assign i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28_b = leftShiftStage2_uid27153_i_shl_i_i_i_i_i_i_3_c_compmm_m0_shift_x_q[28:13];

    // redist320_i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28_b_1(DELAY,29448)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist320_i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_join(BITJOIN,10020)@80
    assign i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_join_q = {redist320_i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg249(REG,13544)@73 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg249_q <= $unsigned(redist762_sync_together4364_aunroll_x_in_i_valid_5_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6426_c_compmm_m250(BLACKBOX,8808)@74
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6426_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6426_c_compmm_m250 (
        .in_intel_reserved_ffwd_8_0(in_intel_reserved_ffwd_8_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg249_q),
        .out_dest_data_out_8_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6426_c_compmm_m250_out_dest_data_out_8_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_offset(CONSTANT,30343)
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_offset_q = $unsigned(2'b11);

    // redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt(ADD,30344)
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_a = {1'b0, redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_q};
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_b = {1'b0, redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_o <= $unsigned(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_a) + $unsigned(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_b);
        end
    end
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_q = redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_o[2:0];

    // redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_inputreg0(DELAY,30339)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_inputreg0_q <= $unsigned(in_c1_eni5_7_tpl);
        end
    end

    // redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr(COUNTER,30342)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_i <= $unsigned(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_q = redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_i[1:0];

    // redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem(DUALMEM,30341)
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_ia = $unsigned(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_inputreg0_q);
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_aa = redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_wraddr_q;
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_ab = redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_aa),
        .data_a(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_ab),
        .q_b(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_q = redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_iq[15:0];

    // redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_outputreg0(DELAY,30340)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_outputreg0_q <= $unsigned(redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_mem_q);
        end
    end

    // redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt(ADD,30350)
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_a = {1'b0, redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_q};
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_b = {1'b0, redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_o <= $unsigned(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_a) + $unsigned(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_b);
        end
    end
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_q = redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_o[2:0];

    // redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_inputreg0(DELAY,30345)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_inputreg0_q <= $unsigned(in_c1_eni5_8_tpl);
        end
    end

    // redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr(COUNTER,30348)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_i <= $unsigned(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_q = redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_i[1:0];

    // redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem(DUALMEM,30347)
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_ia = $unsigned(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_inputreg0_q);
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_aa = redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_wraddr_q;
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_ab = redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_aa),
        .data_a(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_ab),
        .q_b(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_q = redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_iq[15:0];

    // redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_outputreg0(DELAY,30346)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_outputreg0_q <= $unsigned(redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_mem_q);
        end
    end

    // valid_fanout_reg250(REG,13545)@73 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg250_q <= $unsigned(redist762_sync_together4364_aunroll_x_in_i_valid_5_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6425_c_compmm_m251(BLACKBOX,8804)@74
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6425_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6425_c_compmm_m251 (
        .in_intel_reserved_ffwd_7_0(in_intel_reserved_ffwd_7_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg250_q),
        .out_dest_data_out_7_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6425_c_compmm_m251_out_dest_data_out_7_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28874)@74 + 5
    // out q@80
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6425_c_compmm_m251_out_dest_data_out_7_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6426_c_compmm_m250_out_dest_data_out_8_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360(ADD,9007)@80
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod297_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_b = $unsigned({{5{i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_3_c_compmm_m359_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_o[33:0];

    // rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x(MUX,16057)@80
    assign rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q or rightShiftStage0Idx1_uid16056_dupName_13_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q;
            1'b1 : rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16056_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x(MUX,16062)@80
    assign rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16061_dupName_13_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16058_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16061_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x(MUX,16067)@80
    assign rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16066_dupName_13_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16063_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16066_dupName_13_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m361_vt_select_20(BITSELECT,12356)@80
    assign i_unnamed_c_compmm_m361_vt_select_20_b = rightShiftStage2_uid16068_dupName_13_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m361_vt_join(BITJOIN,12355)@80
    assign i_unnamed_c_compmm_m361_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m361_vt_select_20_b};

    // i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x(BITSELECT,3765)@80
    assign i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x_b = i_unnamed_c_compmm_m361_vt_join_q[15:0];

    // redist953_i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x_b_1(DELAY,30081)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist953_i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16077_dupName_14_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16076)@80
    assign rightShiftStage1Idx1Rng8_uid16077_dupName_14_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16079_dupName_14_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16078)@80
    assign rightShiftStage1Idx1_uid16079_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16077_dupName_14_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16072_dupName_14_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16071)@80
    assign rightShiftStage0Idx1Rng4_uid16072_dupName_14_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q[33:4];

    // rightShiftStage0Idx1_uid16074_dupName_14_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16073)@80
    assign rightShiftStage0Idx1_uid16074_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16072_dupName_14_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x(MUX,16075)@80
    assign rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q or rightShiftStage0Idx1_uid16074_dupName_14_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_3_i_c_compmm_m360_q;
            1'b1 : rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16074_dupName_14_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x(MUX,16080)@80
    assign rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16079_dupName_14_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16076_dupName_14_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16079_dupName_14_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m363_vt_select_21(BITSELECT,12370)@80
    assign i_unnamed_c_compmm_m363_vt_select_21_b = rightShiftStage1_uid16081_dupName_14_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m363_vt_join(BITJOIN,12369)@80
    assign i_unnamed_c_compmm_m363_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m363_vt_select_21_b};

    // i_unnamed_c_compmm_m364_sel_x(BITSELECT,6199)@80
    assign i_unnamed_c_compmm_m364_sel_x_b = i_unnamed_c_compmm_m363_vt_join_q[15:0];

    // i_unnamed_c_compmm_m365_BitSelect_for_a(BITSELECT,28752)@80
    assign i_unnamed_c_compmm_m365_BitSelect_for_a_b = i_unnamed_c_compmm_m364_sel_x_b[0:0];

    // i_unnamed_c_compmm_m365_join(BITJOIN,28753)@80
    assign i_unnamed_c_compmm_m365_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m365_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m365_vt_select_0(BITSELECT,12397)@80
    assign i_unnamed_c_compmm_m365_vt_select_0_b = i_unnamed_c_compmm_m365_join_q[0:0];

    // redist60_i_unnamed_c_compmm_m365_vt_select_0_b_1(DELAY,29188)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist60_i_unnamed_c_compmm_m365_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m365_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m365_vt_join(BITJOIN,12396)@81
    assign i_unnamed_c_compmm_m365_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist60_i_unnamed_c_compmm_m365_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_3_c_compmm_m366(ADD,7220)@81
    assign i_add_i_i_i_i_i_i_3_c_compmm_m366_a = {1'b0, i_unnamed_c_compmm_m365_vt_join_q};
    assign i_add_i_i_i_i_i_i_3_c_compmm_m366_b = {1'b0, redist953_i_conv_i_i_i_i_i_3_c_compmm_m362_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_3_c_compmm_m366_o = $unsigned(i_add_i_i_i_i_i_i_3_c_compmm_m366_a) + $unsigned(i_add_i_i_i_i_i_i_3_c_compmm_m366_b);
    assign i_add_i_i_i_i_i_i_3_c_compmm_m366_q = i_add_i_i_i_i_i_i_3_c_compmm_m366_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_3_c_compmm_m366_sel_x(BITSELECT,2234)@81
    assign bgTrunc_i_add_i_i_i_i_i_i_3_c_compmm_m366_sel_x_b = i_add_i_i_i_i_i_i_3_c_compmm_m366_q[15:0];

    // i_conv_i_i_i_i_i_i246_4_c_compmm_m386_sel_x(BITSELECT,3904)@81
    assign i_conv_i_i_i_i_i_i246_4_c_compmm_m386_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_3_c_compmm_m366_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_select_15(BITSELECT,8343)@81
    assign i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_select_15_b = i_conv_i_i_i_i_i_i246_4_c_compmm_m386_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_join(BITJOIN,8342)@81
    assign i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_select_15_b};

    // leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(MUX,27340)@81
    assign leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_join_q or leftShiftStage0Idx1_uid27339_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_4_c_compmm_m386_vt_join_q;
            1'b1 : leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27339_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(MUX,27345)@81
    assign leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s or leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27344_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = leftShiftStage0_uid27341_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27344_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x(MUX,27350)@81
    assign leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s or leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27349_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = leftShiftStage1_uid27346_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27349_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28(BITSELECT,10054)@81
    assign i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28_b = leftShiftStage2_uid27351_i_shl_i_i_i_i_i_i_4_c_compmm_m0_shift_x_q[28:13];

    // redist309_i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28_b_1(DELAY,29437)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist309_i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_join(BITJOIN,10053)@82
    assign i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_join_q = {redist309_i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg247(REG,13542)@75 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg247_q <= $unsigned(redist763_sync_together4364_aunroll_x_in_i_valid_7_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6428_c_compmm_m248(BLACKBOX,8816)@76
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6428_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6428_c_compmm_m248 (
        .in_intel_reserved_ffwd_10_0(in_intel_reserved_ffwd_10_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg247_q),
        .out_dest_data_out_10_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6428_c_compmm_m248_out_dest_data_out_10_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_offset(CONSTANT,30355)
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_offset_q = $unsigned(3'b101);

    // redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt(ADD,30356)
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_a = {1'b0, redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_q};
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_b = {1'b0, redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_o <= $unsigned(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_a) + $unsigned(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_b);
        end
    end
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_q = redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_o[3:0];

    // redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_inputreg0(DELAY,30351)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_inputreg0_q <= $unsigned(in_c1_eni5_9_tpl);
        end
    end

    // redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr(COUNTER,30354)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_i <= $unsigned(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_q = redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_i[2:0];

    // redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem(DUALMEM,30353)
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_ia = $unsigned(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_inputreg0_q);
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_aa = redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_wraddr_q;
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_ab = redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_aa),
        .data_a(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_ab),
        .q_b(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_q = redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_iq[15:0];

    // redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_outputreg0(DELAY,30352)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_outputreg0_q <= $unsigned(redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_mem_q);
        end
    end

    // redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt(ADD,30362)
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_a = {1'b0, redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_q};
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_b = {1'b0, redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_o <= $unsigned(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_a) + $unsigned(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_b);
        end
    end
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_q = redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_o[3:0];

    // redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_inputreg0(DELAY,30357)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_inputreg0_q <= $unsigned(in_c1_eni5_10_tpl);
        end
    end

    // redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr(COUNTER,30360)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_i <= $unsigned(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_q = redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_i[2:0];

    // redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem(DUALMEM,30359)
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_ia = $unsigned(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_inputreg0_q);
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_aa = redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_wraddr_q;
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_ab = redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_aa),
        .data_a(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_ab),
        .q_b(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_q = redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_iq[15:0];

    // redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_outputreg0(DELAY,30358)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_outputreg0_q <= $unsigned(redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_mem_q);
        end
    end

    // valid_fanout_reg248(REG,13543)@75 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg248_q <= $unsigned(redist763_sync_together4364_aunroll_x_in_i_valid_7_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6427_c_compmm_m249(BLACKBOX,8812)@76
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6427_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6427_c_compmm_m249 (
        .in_intel_reserved_ffwd_9_0(in_intel_reserved_ffwd_9_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg248_q),
        .out_dest_data_out_9_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6427_c_compmm_m249_out_dest_data_out_9_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28875)@76 + 5
    // out q@82
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6427_c_compmm_m249_out_dest_data_out_9_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6428_c_compmm_m248_out_dest_data_out_10_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388(ADD,9018)@82
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod302_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_b = $unsigned({{5{i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_4_c_compmm_m387_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_o[33:0];

    // rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x(MUX,16119)@82
    assign rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q or rightShiftStage0Idx1_uid16118_dupName_17_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q;
            1'b1 : rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16118_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x(MUX,16124)@82
    assign rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16123_dupName_17_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16120_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16123_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x(MUX,16129)@82
    assign rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16128_dupName_17_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16125_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16128_dupName_17_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m389_vt_select_20(BITSELECT,12554)@82
    assign i_unnamed_c_compmm_m389_vt_select_20_b = rightShiftStage2_uid16130_dupName_17_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m389_vt_join(BITJOIN,12553)@82
    assign i_unnamed_c_compmm_m389_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m389_vt_select_20_b};

    // i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x(BITSELECT,3776)@82
    assign i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x_b = i_unnamed_c_compmm_m389_vt_join_q[15:0];

    // redist942_i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x_b_1(DELAY,30070)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist942_i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16139_dupName_18_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16138)@82
    assign rightShiftStage1Idx1Rng8_uid16139_dupName_18_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16141_dupName_18_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16140)@82
    assign rightShiftStage1Idx1_uid16141_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16139_dupName_18_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16134_dupName_18_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16133)@82
    assign rightShiftStage0Idx1Rng4_uid16134_dupName_18_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q[33:4];

    // rightShiftStage0Idx1_uid16136_dupName_18_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16135)@82
    assign rightShiftStage0Idx1_uid16136_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16134_dupName_18_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x(MUX,16137)@82
    assign rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q or rightShiftStage0Idx1_uid16136_dupName_18_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_4_i_c_compmm_m388_q;
            1'b1 : rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16136_dupName_18_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x(MUX,16142)@82
    assign rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16141_dupName_18_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16138_dupName_18_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16141_dupName_18_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m391_vt_select_21(BITSELECT,12557)@82
    assign i_unnamed_c_compmm_m391_vt_select_21_b = rightShiftStage1_uid16143_dupName_18_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m391_vt_join(BITJOIN,12556)@82
    assign i_unnamed_c_compmm_m391_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m391_vt_select_21_b};

    // i_unnamed_c_compmm_m392_sel_x(BITSELECT,6216)@82
    assign i_unnamed_c_compmm_m392_sel_x_b = i_unnamed_c_compmm_m391_vt_join_q[15:0];

    // i_unnamed_c_compmm_m393_BitSelect_for_a(BITSELECT,28784)@82
    assign i_unnamed_c_compmm_m393_BitSelect_for_a_b = i_unnamed_c_compmm_m392_sel_x_b[0:0];

    // i_unnamed_c_compmm_m393_join(BITJOIN,28785)@82
    assign i_unnamed_c_compmm_m393_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m393_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m393_vt_select_0(BITSELECT,12562)@82
    assign i_unnamed_c_compmm_m393_vt_select_0_b = i_unnamed_c_compmm_m393_join_q[0:0];

    // redist45_i_unnamed_c_compmm_m393_vt_select_0_b_1(DELAY,29173)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist45_i_unnamed_c_compmm_m393_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m393_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m393_vt_join(BITJOIN,12561)@83
    assign i_unnamed_c_compmm_m393_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist45_i_unnamed_c_compmm_m393_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_4_c_compmm_m394(ADD,7231)@83
    assign i_add_i_i_i_i_i_i_4_c_compmm_m394_a = {1'b0, i_unnamed_c_compmm_m393_vt_join_q};
    assign i_add_i_i_i_i_i_i_4_c_compmm_m394_b = {1'b0, redist942_i_conv_i_i_i_i_i_4_c_compmm_m390_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_4_c_compmm_m394_o = $unsigned(i_add_i_i_i_i_i_i_4_c_compmm_m394_a) + $unsigned(i_add_i_i_i_i_i_i_4_c_compmm_m394_b);
    assign i_add_i_i_i_i_i_i_4_c_compmm_m394_q = i_add_i_i_i_i_i_i_4_c_compmm_m394_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_4_c_compmm_m394_sel_x(BITSELECT,2245)@83
    assign bgTrunc_i_add_i_i_i_i_i_i_4_c_compmm_m394_sel_x_b = i_add_i_i_i_i_i_i_4_c_compmm_m394_q[15:0];

    // i_conv_i_i_i_i_i_i246_5_c_compmm_m414_sel_x(BITSELECT,3915)@83
    assign i_conv_i_i_i_i_i_i246_5_c_compmm_m414_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_4_c_compmm_m394_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_select_15(BITSELECT,8387)@83
    assign i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_select_15_b = i_conv_i_i_i_i_i_i246_5_c_compmm_m414_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_join(BITJOIN,8386)@83
    assign i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_select_15_b};

    // leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(MUX,27538)@83
    assign leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_join_q or leftShiftStage0Idx1_uid27537_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_5_c_compmm_m414_vt_join_q;
            1'b1 : leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27537_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(MUX,27543)@83
    assign leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s or leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27542_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = leftShiftStage0_uid27539_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27542_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x(MUX,27548)@83
    assign leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s or leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27547_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = leftShiftStage1_uid27544_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27547_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28(BITSELECT,10087)@83
    assign i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28_b = leftShiftStage2_uid27549_i_shl_i_i_i_i_i_i_5_c_compmm_m0_shift_x_q[28:13];

    // redist298_i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28_b_1(DELAY,29426)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist298_i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_join(BITJOIN,10086)@84
    assign i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_join_q = {redist298_i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg245(REG,13540)@77 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg245_q <= $unsigned(redist764_sync_together4364_aunroll_x_in_i_valid_9_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6430_c_compmm_m246(BLACKBOX,8572)@78
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6430_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6430_c_compmm_m246 (
        .in_intel_reserved_ffwd_12_0(in_intel_reserved_ffwd_12_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg245_q),
        .out_dest_data_out_12_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6430_c_compmm_m246_out_dest_data_out_12_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_offset(CONSTANT,30367)
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_offset_q = $unsigned(3'b011);

    // redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt(ADD,30368)
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_a = {1'b0, redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_q};
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_b = {1'b0, redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_o <= $unsigned(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_a) + $unsigned(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_b);
        end
    end
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_q = redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_o[3:0];

    // redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_inputreg0(DELAY,30363)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_inputreg0_q <= $unsigned(in_c1_eni5_11_tpl);
        end
    end

    // redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr(COUNTER,30366)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_i <= $unsigned(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_q = redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_i[2:0];

    // redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem(DUALMEM,30365)
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_ia = $unsigned(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_inputreg0_q);
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_aa = redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_wraddr_q;
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_ab = redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_aa),
        .data_a(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_ab),
        .q_b(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_q = redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_iq[15:0];

    // redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_outputreg0(DELAY,30364)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_outputreg0_q <= $unsigned(redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_mem_q);
        end
    end

    // redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt(ADD,30374)
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_a = {1'b0, redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_q};
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_b = {1'b0, redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_o <= $unsigned(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_a) + $unsigned(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_b);
        end
    end
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_q = redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_o[3:0];

    // redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_inputreg0(DELAY,30369)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_inputreg0_q <= $unsigned(in_c1_eni5_12_tpl);
        end
    end

    // redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr(COUNTER,30372)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_i <= $unsigned(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_q = redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_i[2:0];

    // redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem(DUALMEM,30371)
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_ia = $unsigned(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_inputreg0_q);
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_aa = redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_wraddr_q;
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_ab = redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_aa),
        .data_a(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_ab),
        .q_b(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_q = redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_iq[15:0];

    // redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_outputreg0(DELAY,30370)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_outputreg0_q <= $unsigned(redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_mem_q);
        end
    end

    // valid_fanout_reg246(REG,13541)@77 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg246_q <= $unsigned(redist764_sync_together4364_aunroll_x_in_i_valid_9_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6429_c_compmm_m247(BLACKBOX,8568)@78
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6429_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6429_c_compmm_m247 (
        .in_intel_reserved_ffwd_11_0(in_intel_reserved_ffwd_11_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg246_q),
        .out_dest_data_out_11_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6429_c_compmm_m247_out_dest_data_out_11_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28876)@78 + 5
    // out q@84
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6429_c_compmm_m247_out_dest_data_out_11_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6430_c_compmm_m246_out_dest_data_out_12_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416(ADD,9029)@84
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod307_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_b = $unsigned({{5{i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_5_c_compmm_m415_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_o[33:0];

    // rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x(MUX,16181)@84
    assign rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q or rightShiftStage0Idx1_uid16180_dupName_21_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q;
            1'b1 : rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16180_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x(MUX,16186)@84
    assign rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16185_dupName_21_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16182_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16185_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x(MUX,16191)@84
    assign rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16190_dupName_21_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16187_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16190_dupName_21_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m417_vt_select_20(BITSELECT,12576)@84
    assign i_unnamed_c_compmm_m417_vt_select_20_b = rightShiftStage2_uid16192_dupName_21_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m417_vt_join(BITJOIN,12575)@84
    assign i_unnamed_c_compmm_m417_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m417_vt_select_20_b};

    // i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x(BITSELECT,3787)@84
    assign i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x_b = i_unnamed_c_compmm_m417_vt_join_q[15:0];

    // redist931_i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x_b_1(DELAY,30059)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist931_i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16201_dupName_22_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16200)@84
    assign rightShiftStage1Idx1Rng8_uid16201_dupName_22_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16203_dupName_22_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16202)@84
    assign rightShiftStage1Idx1_uid16203_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16201_dupName_22_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16196_dupName_22_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16195)@84
    assign rightShiftStage0Idx1Rng4_uid16196_dupName_22_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q[33:4];

    // rightShiftStage0Idx1_uid16198_dupName_22_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16197)@84
    assign rightShiftStage0Idx1_uid16198_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16196_dupName_22_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x(MUX,16199)@84
    assign rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q or rightShiftStage0Idx1_uid16198_dupName_22_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_5_i_c_compmm_m416_q;
            1'b1 : rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16198_dupName_22_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x(MUX,16204)@84
    assign rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16203_dupName_22_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16200_dupName_22_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16203_dupName_22_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m419_vt_select_21(BITSELECT,12579)@84
    assign i_unnamed_c_compmm_m419_vt_select_21_b = rightShiftStage1_uid16205_dupName_22_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m419_vt_join(BITJOIN,12578)@84
    assign i_unnamed_c_compmm_m419_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m419_vt_select_21_b};

    // i_unnamed_c_compmm_m420_sel_x(BITSELECT,6218)@84
    assign i_unnamed_c_compmm_m420_sel_x_b = i_unnamed_c_compmm_m419_vt_join_q[15:0];

    // i_unnamed_c_compmm_m421_BitSelect_for_a(BITSELECT,28788)@84
    assign i_unnamed_c_compmm_m421_BitSelect_for_a_b = i_unnamed_c_compmm_m420_sel_x_b[0:0];

    // i_unnamed_c_compmm_m421_join(BITJOIN,28789)@84
    assign i_unnamed_c_compmm_m421_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m421_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m421_vt_select_0(BITSELECT,12584)@84
    assign i_unnamed_c_compmm_m421_vt_select_0_b = i_unnamed_c_compmm_m421_join_q[0:0];

    // redist43_i_unnamed_c_compmm_m421_vt_select_0_b_1(DELAY,29171)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist43_i_unnamed_c_compmm_m421_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m421_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m421_vt_join(BITJOIN,12583)@85
    assign i_unnamed_c_compmm_m421_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist43_i_unnamed_c_compmm_m421_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_5_c_compmm_m422(ADD,7242)@85
    assign i_add_i_i_i_i_i_i_5_c_compmm_m422_a = {1'b0, i_unnamed_c_compmm_m421_vt_join_q};
    assign i_add_i_i_i_i_i_i_5_c_compmm_m422_b = {1'b0, redist931_i_conv_i_i_i_i_i_5_c_compmm_m418_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_5_c_compmm_m422_o = $unsigned(i_add_i_i_i_i_i_i_5_c_compmm_m422_a) + $unsigned(i_add_i_i_i_i_i_i_5_c_compmm_m422_b);
    assign i_add_i_i_i_i_i_i_5_c_compmm_m422_q = i_add_i_i_i_i_i_i_5_c_compmm_m422_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_5_c_compmm_m422_sel_x(BITSELECT,2256)@85
    assign bgTrunc_i_add_i_i_i_i_i_i_5_c_compmm_m422_sel_x_b = i_add_i_i_i_i_i_i_5_c_compmm_m422_q[15:0];

    // i_conv_i_i_i_i_i_i246_6_c_compmm_m442_sel_x(BITSELECT,3926)@85
    assign i_conv_i_i_i_i_i_i246_6_c_compmm_m442_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_5_c_compmm_m422_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_select_15(BITSELECT,8431)@85
    assign i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_select_15_b = i_conv_i_i_i_i_i_i246_6_c_compmm_m442_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_join(BITJOIN,8430)@85
    assign i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_select_15_b};

    // leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(MUX,27736)@85
    assign leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_join_q or leftShiftStage0Idx1_uid27735_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_6_c_compmm_m442_vt_join_q;
            1'b1 : leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27735_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(MUX,27741)@85
    assign leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s or leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27740_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = leftShiftStage0_uid27737_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27740_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x(MUX,27746)@85
    assign leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s or leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27745_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = leftShiftStage1_uid27742_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27745_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28(BITSELECT,10120)@85
    assign i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28_b = leftShiftStage2_uid27747_i_shl_i_i_i_i_i_i_6_c_compmm_m0_shift_x_q[28:13];

    // redist287_i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28_b_1(DELAY,29415)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist287_i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_join(BITJOIN,10119)@86
    assign i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_join_q = {redist287_i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg243(REG,13538)@79 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg243_q <= $unsigned(redist765_sync_together4364_aunroll_x_in_i_valid_11_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6432_c_compmm_m244(BLACKBOX,8580)@80
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6432_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6432_c_compmm_m244 (
        .in_intel_reserved_ffwd_14_0(in_intel_reserved_ffwd_14_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg243_q),
        .out_dest_data_out_14_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6432_c_compmm_m244_out_dest_data_out_14_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_offset(CONSTANT,30379)
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_offset_q = $unsigned(4'b1001);

    // redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt(ADD,30380)
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_a = {1'b0, redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_q};
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_b = {1'b0, redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_o <= $unsigned(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_a) + $unsigned(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_b);
        end
    end
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_q = redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_o[4:0];

    // redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_inputreg0(DELAY,30375)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_inputreg0_q <= $unsigned(in_c1_eni5_13_tpl);
        end
    end

    // redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr(COUNTER,30378)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_i <= $unsigned(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_q = redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_i[3:0];

    // redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem(DUALMEM,30377)
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_ia = $unsigned(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_inputreg0_q);
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_aa = redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_wraddr_q;
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_ab = redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_aa),
        .data_a(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_ab),
        .q_b(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_q = redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_iq[15:0];

    // redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_outputreg0(DELAY,30376)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_outputreg0_q <= $unsigned(redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_mem_q);
        end
    end

    // redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt(ADD,30386)
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_a = {1'b0, redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_q};
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_b = {1'b0, redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_o <= $unsigned(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_a) + $unsigned(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_b);
        end
    end
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_q = redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_o[4:0];

    // redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_inputreg0(DELAY,30381)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_inputreg0_q <= $unsigned(in_c1_eni5_14_tpl);
        end
    end

    // redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr(COUNTER,30384)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_i <= $unsigned(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_q = redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_i[3:0];

    // redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem(DUALMEM,30383)
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_ia = $unsigned(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_inputreg0_q);
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_aa = redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_wraddr_q;
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_ab = redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_aa),
        .data_a(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_ab),
        .q_b(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_q = redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_iq[15:0];

    // redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_outputreg0(DELAY,30382)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_outputreg0_q <= $unsigned(redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_mem_q);
        end
    end

    // valid_fanout_reg244(REG,13539)@79 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg244_q <= $unsigned(redist765_sync_together4364_aunroll_x_in_i_valid_11_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6431_c_compmm_m245(BLACKBOX,8576)@80
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6431_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6431_c_compmm_m245 (
        .in_intel_reserved_ffwd_13_0(in_intel_reserved_ffwd_13_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg244_q),
        .out_dest_data_out_13_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6431_c_compmm_m245_out_dest_data_out_13_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28877)@80 + 5
    // out q@86
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6431_c_compmm_m245_out_dest_data_out_13_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6432_c_compmm_m244_out_dest_data_out_14_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444(ADD,9040)@86
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod312_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_b = $unsigned({{5{i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_6_c_compmm_m443_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_o[33:0];

    // rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x(MUX,16243)@86
    assign rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q or rightShiftStage0Idx1_uid16242_dupName_25_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q;
            1'b1 : rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16242_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x(MUX,16248)@86
    assign rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16247_dupName_25_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16244_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16247_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x(MUX,16253)@86
    assign rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16252_dupName_25_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16249_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16252_dupName_25_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m445_vt_select_20(BITSELECT,12598)@86
    assign i_unnamed_c_compmm_m445_vt_select_20_b = rightShiftStage2_uid16254_dupName_25_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m445_vt_join(BITJOIN,12597)@86
    assign i_unnamed_c_compmm_m445_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m445_vt_select_20_b};

    // i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x(BITSELECT,3798)@86
    assign i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x_b = i_unnamed_c_compmm_m445_vt_join_q[15:0];

    // redist920_i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x_b_1(DELAY,30048)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist920_i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16263_dupName_26_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16262)@86
    assign rightShiftStage1Idx1Rng8_uid16263_dupName_26_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16265_dupName_26_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16264)@86
    assign rightShiftStage1Idx1_uid16265_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16263_dupName_26_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16258_dupName_26_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16257)@86
    assign rightShiftStage0Idx1Rng4_uid16258_dupName_26_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q[33:4];

    // rightShiftStage0Idx1_uid16260_dupName_26_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16259)@86
    assign rightShiftStage0Idx1_uid16260_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16258_dupName_26_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x(MUX,16261)@86
    assign rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q or rightShiftStage0Idx1_uid16260_dupName_26_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_6_i_c_compmm_m444_q;
            1'b1 : rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16260_dupName_26_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x(MUX,16266)@86
    assign rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16265_dupName_26_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16262_dupName_26_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16265_dupName_26_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m447_vt_select_21(BITSELECT,12601)@86
    assign i_unnamed_c_compmm_m447_vt_select_21_b = rightShiftStage1_uid16267_dupName_26_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m447_vt_join(BITJOIN,12600)@86
    assign i_unnamed_c_compmm_m447_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m447_vt_select_21_b};

    // i_unnamed_c_compmm_m448_sel_x(BITSELECT,6220)@86
    assign i_unnamed_c_compmm_m448_sel_x_b = i_unnamed_c_compmm_m447_vt_join_q[15:0];

    // i_unnamed_c_compmm_m449_BitSelect_for_a(BITSELECT,28792)@86
    assign i_unnamed_c_compmm_m449_BitSelect_for_a_b = i_unnamed_c_compmm_m448_sel_x_b[0:0];

    // i_unnamed_c_compmm_m449_join(BITJOIN,28793)@86
    assign i_unnamed_c_compmm_m449_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m449_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m449_vt_select_0(BITSELECT,12606)@86
    assign i_unnamed_c_compmm_m449_vt_select_0_b = i_unnamed_c_compmm_m449_join_q[0:0];

    // redist41_i_unnamed_c_compmm_m449_vt_select_0_b_1(DELAY,29169)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist41_i_unnamed_c_compmm_m449_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m449_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m449_vt_join(BITJOIN,12605)@87
    assign i_unnamed_c_compmm_m449_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist41_i_unnamed_c_compmm_m449_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_6_c_compmm_m450(ADD,7253)@87
    assign i_add_i_i_i_i_i_i_6_c_compmm_m450_a = {1'b0, i_unnamed_c_compmm_m449_vt_join_q};
    assign i_add_i_i_i_i_i_i_6_c_compmm_m450_b = {1'b0, redist920_i_conv_i_i_i_i_i_6_c_compmm_m446_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_6_c_compmm_m450_o = $unsigned(i_add_i_i_i_i_i_i_6_c_compmm_m450_a) + $unsigned(i_add_i_i_i_i_i_i_6_c_compmm_m450_b);
    assign i_add_i_i_i_i_i_i_6_c_compmm_m450_q = i_add_i_i_i_i_i_i_6_c_compmm_m450_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_6_c_compmm_m450_sel_x(BITSELECT,2267)@87
    assign bgTrunc_i_add_i_i_i_i_i_i_6_c_compmm_m450_sel_x_b = i_add_i_i_i_i_i_i_6_c_compmm_m450_q[15:0];

    // i_conv_i_i_i_i_i_i246_7_c_compmm_m470_sel_x(BITSELECT,3937)@87
    assign i_conv_i_i_i_i_i_i246_7_c_compmm_m470_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_6_c_compmm_m450_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_select_15(BITSELECT,8475)@87
    assign i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_select_15_b = i_conv_i_i_i_i_i_i246_7_c_compmm_m470_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_join(BITJOIN,8474)@87
    assign i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_select_15_b};

    // leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(MUX,27934)@87
    assign leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_join_q or leftShiftStage0Idx1_uid27933_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_7_c_compmm_m470_vt_join_q;
            1'b1 : leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27933_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(MUX,27939)@87
    assign leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s or leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27938_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = leftShiftStage0_uid27935_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27938_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x(MUX,27944)@87
    assign leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s or leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27943_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = leftShiftStage1_uid27940_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27943_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28(BITSELECT,10153)@87
    assign i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28_b = leftShiftStage2_uid27945_i_shl_i_i_i_i_i_i_7_c_compmm_m0_shift_x_q[28:13];

    // redist276_i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28_b_1(DELAY,29404)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist276_i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_join(BITJOIN,10152)@88
    assign i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_join_q = {redist276_i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg241(REG,13536)@81 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg241_q <= $unsigned(redist766_sync_together4364_aunroll_x_in_i_valid_13_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6434_c_compmm_m242(BLACKBOX,8588)@82
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6434_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6434_c_compmm_m242 (
        .in_intel_reserved_ffwd_16_0(in_intel_reserved_ffwd_16_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg241_q),
        .out_dest_data_out_16_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6434_c_compmm_m242_out_dest_data_out_16_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_offset(CONSTANT,30391)
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_offset_q = $unsigned(4'b0111);

    // redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt(ADD,30392)
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_a = {1'b0, redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_q};
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_b = {1'b0, redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_o <= $unsigned(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_a) + $unsigned(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_b);
        end
    end
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_q = redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_o[4:0];

    // redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_inputreg0(DELAY,30387)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_inputreg0_q <= $unsigned(in_c1_eni5_15_tpl);
        end
    end

    // redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr(COUNTER,30390)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_i <= $unsigned(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_q = redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_i[3:0];

    // redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem(DUALMEM,30389)
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_ia = $unsigned(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_inputreg0_q);
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_aa = redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_wraddr_q;
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_ab = redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_aa),
        .data_a(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_ab),
        .q_b(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_q = redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_iq[15:0];

    // redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_outputreg0(DELAY,30388)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_outputreg0_q <= $unsigned(redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_mem_q);
        end
    end

    // redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt(ADD,30398)
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_a = {1'b0, redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_q};
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_b = {1'b0, redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_o <= $unsigned(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_a) + $unsigned(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_b);
        end
    end
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_q = redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_o[4:0];

    // redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_inputreg0(DELAY,30393)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_inputreg0_q <= $unsigned(in_c1_eni5_16_tpl);
        end
    end

    // redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr(COUNTER,30396)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_i <= $unsigned(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_q = redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_i[3:0];

    // redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem(DUALMEM,30395)
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_ia = $unsigned(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_inputreg0_q);
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_aa = redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_wraddr_q;
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_ab = redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_aa),
        .data_a(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_ab),
        .q_b(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_q = redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_iq[15:0];

    // redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_outputreg0(DELAY,30394)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_outputreg0_q <= $unsigned(redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_mem_q);
        end
    end

    // valid_fanout_reg242(REG,13537)@81 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg242_q <= $unsigned(redist766_sync_together4364_aunroll_x_in_i_valid_13_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6433_c_compmm_m243(BLACKBOX,8584)@82
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6433_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6433_c_compmm_m243 (
        .in_intel_reserved_ffwd_15_0(in_intel_reserved_ffwd_15_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg242_q),
        .out_dest_data_out_15_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6433_c_compmm_m243_out_dest_data_out_15_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28878)@82 + 5
    // out q@88
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6433_c_compmm_m243_out_dest_data_out_15_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6434_c_compmm_m242_out_dest_data_out_16_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472(ADD,9051)@88
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod317_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_b = $unsigned({{5{i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_7_c_compmm_m471_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_o[33:0];

    // rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x(MUX,16305)@88
    assign rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q or rightShiftStage0Idx1_uid16304_dupName_29_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q;
            1'b1 : rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16304_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x(MUX,16310)@88
    assign rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16309_dupName_29_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16306_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16309_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x(MUX,16315)@88
    assign rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16314_dupName_29_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16311_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16314_dupName_29_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m473_vt_select_20(BITSELECT,12620)@88
    assign i_unnamed_c_compmm_m473_vt_select_20_b = rightShiftStage2_uid16316_dupName_29_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m473_vt_join(BITJOIN,12619)@88
    assign i_unnamed_c_compmm_m473_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m473_vt_select_20_b};

    // i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x(BITSELECT,3809)@88
    assign i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x_b = i_unnamed_c_compmm_m473_vt_join_q[15:0];

    // redist909_i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x_b_1(DELAY,30037)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist909_i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16325_dupName_30_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16324)@88
    assign rightShiftStage1Idx1Rng8_uid16325_dupName_30_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16327_dupName_30_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16326)@88
    assign rightShiftStage1Idx1_uid16327_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16325_dupName_30_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16320_dupName_30_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16319)@88
    assign rightShiftStage0Idx1Rng4_uid16320_dupName_30_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q[33:4];

    // rightShiftStage0Idx1_uid16322_dupName_30_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16321)@88
    assign rightShiftStage0Idx1_uid16322_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16320_dupName_30_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x(MUX,16323)@88
    assign rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q or rightShiftStage0Idx1_uid16322_dupName_30_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_7_i_c_compmm_m472_q;
            1'b1 : rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16322_dupName_30_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x(MUX,16328)@88
    assign rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16327_dupName_30_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16324_dupName_30_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16327_dupName_30_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m475_vt_select_21(BITSELECT,12623)@88
    assign i_unnamed_c_compmm_m475_vt_select_21_b = rightShiftStage1_uid16329_dupName_30_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m475_vt_join(BITJOIN,12622)@88
    assign i_unnamed_c_compmm_m475_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m475_vt_select_21_b};

    // i_unnamed_c_compmm_m476_sel_x(BITSELECT,6222)@88
    assign i_unnamed_c_compmm_m476_sel_x_b = i_unnamed_c_compmm_m475_vt_join_q[15:0];

    // i_unnamed_c_compmm_m477_BitSelect_for_a(BITSELECT,28796)@88
    assign i_unnamed_c_compmm_m477_BitSelect_for_a_b = i_unnamed_c_compmm_m476_sel_x_b[0:0];

    // i_unnamed_c_compmm_m477_join(BITJOIN,28797)@88
    assign i_unnamed_c_compmm_m477_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m477_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m477_vt_select_0(BITSELECT,12628)@88
    assign i_unnamed_c_compmm_m477_vt_select_0_b = i_unnamed_c_compmm_m477_join_q[0:0];

    // redist39_i_unnamed_c_compmm_m477_vt_select_0_b_1(DELAY,29167)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist39_i_unnamed_c_compmm_m477_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m477_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m477_vt_join(BITJOIN,12627)@89
    assign i_unnamed_c_compmm_m477_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist39_i_unnamed_c_compmm_m477_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_7_c_compmm_m478(ADD,7264)@89
    assign i_add_i_i_i_i_i_i_7_c_compmm_m478_a = {1'b0, i_unnamed_c_compmm_m477_vt_join_q};
    assign i_add_i_i_i_i_i_i_7_c_compmm_m478_b = {1'b0, redist909_i_conv_i_i_i_i_i_7_c_compmm_m474_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_7_c_compmm_m478_o = $unsigned(i_add_i_i_i_i_i_i_7_c_compmm_m478_a) + $unsigned(i_add_i_i_i_i_i_i_7_c_compmm_m478_b);
    assign i_add_i_i_i_i_i_i_7_c_compmm_m478_q = i_add_i_i_i_i_i_i_7_c_compmm_m478_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_7_c_compmm_m478_sel_x(BITSELECT,2278)@89
    assign bgTrunc_i_add_i_i_i_i_i_i_7_c_compmm_m478_sel_x_b = i_add_i_i_i_i_i_i_7_c_compmm_m478_q[15:0];

    // i_conv_i_i_i_i_i_i246_8_c_compmm_m498_sel_x(BITSELECT,3948)@89
    assign i_conv_i_i_i_i_i_i246_8_c_compmm_m498_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_7_c_compmm_m478_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_select_15(BITSELECT,8519)@89
    assign i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_select_15_b = i_conv_i_i_i_i_i_i246_8_c_compmm_m498_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_join(BITJOIN,8518)@89
    assign i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_select_15_b};

    // leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(MUX,28132)@89
    assign leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_join_q or leftShiftStage0Idx1_uid28131_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_8_c_compmm_m498_vt_join_q;
            1'b1 : leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28131_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(MUX,28137)@89
    assign leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s or leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28136_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = leftShiftStage0_uid28133_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28136_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x(MUX,28142)@89
    assign leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s or leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28141_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = leftShiftStage1_uid28138_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28141_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28(BITSELECT,10186)@89
    assign i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28_b = leftShiftStage2_uid28143_i_shl_i_i_i_i_i_i_8_c_compmm_m0_shift_x_q[28:13];

    // redist265_i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28_b_1(DELAY,29393)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist265_i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_join(BITJOIN,10185)@90
    assign i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_join_q = {redist265_i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg239(REG,13534)@83 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg239_q <= $unsigned(redist767_sync_together4364_aunroll_x_in_i_valid_15_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_6436_c_compmm_m240(BLACKBOX,8596)@84
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6436_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_6436_c_compmm_m240 (
        .in_intel_reserved_ffwd_18_0(in_intel_reserved_ffwd_18_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg239_q),
        .out_dest_data_out_18_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_6436_c_compmm_m240_out_dest_data_out_18_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_offset(CONSTANT,30403)
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_offset_q = $unsigned(4'b0101);

    // redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt(ADD,30404)
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_a = {1'b0, redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_q};
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_b = {1'b0, redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_o <= $unsigned(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_a) + $unsigned(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_b);
        end
    end
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_q = redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_o[4:0];

    // redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_inputreg0(DELAY,30399)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_inputreg0_q <= $unsigned(in_c1_eni5_17_tpl);
        end
    end

    // redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr(COUNTER,30402)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_i <= $unsigned(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_q = redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_i[3:0];

    // redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem(DUALMEM,30401)
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_ia = $unsigned(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_inputreg0_q);
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_aa = redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_wraddr_q;
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_ab = redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_aa),
        .data_a(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_ab),
        .q_b(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_q = redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_iq[15:0];

    // redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_outputreg0(DELAY,30400)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_outputreg0_q <= $unsigned(redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_mem_q);
        end
    end

    // redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt(ADD,30410)
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_a = {1'b0, redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_q};
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_b = {1'b0, redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_o <= $unsigned(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_a) + $unsigned(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_b);
        end
    end
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_q = redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_o[4:0];

    // redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_inputreg0(DELAY,30405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_inputreg0_q <= $unsigned(in_c1_eni5_18_tpl);
        end
    end

    // redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr(COUNTER,30408)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_i <= $unsigned(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_q = redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_i[3:0];

    // redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem(DUALMEM,30407)
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_ia = $unsigned(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_inputreg0_q);
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_aa = redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_wraddr_q;
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_ab = redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_aa),
        .data_a(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_ab),
        .q_b(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_q = redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_iq[15:0];

    // redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_outputreg0(DELAY,30406)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_outputreg0_q <= $unsigned(redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_mem_q);
        end
    end

    // valid_fanout_reg240(REG,13535)@83 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg240_q <= $unsigned(redist767_sync_together4364_aunroll_x_in_i_valid_15_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6435_c_compmm_m241(BLACKBOX,8592)@84
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6435_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6435_c_compmm_m241 (
        .in_intel_reserved_ffwd_17_0(in_intel_reserved_ffwd_17_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg240_q),
        .out_dest_data_out_17_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6435_c_compmm_m241_out_dest_data_out_17_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28879)@84 + 5
    // out q@90
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6435_c_compmm_m241_out_dest_data_out_17_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_6436_c_compmm_m240_out_dest_data_out_18_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500(ADD,9062)@90
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod322_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_b = $unsigned({{5{i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_8_c_compmm_m499_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_o[33:0];

    // rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x(MUX,16367)@90
    assign rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q or rightShiftStage0Idx1_uid16366_dupName_33_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q;
            1'b1 : rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16366_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x(MUX,16372)@90
    assign rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16371_dupName_33_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16368_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16371_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x(MUX,16377)@90
    assign rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16376_dupName_33_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16373_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16376_dupName_33_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m501_vt_select_20(BITSELECT,12642)@90
    assign i_unnamed_c_compmm_m501_vt_select_20_b = rightShiftStage2_uid16378_dupName_33_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m501_vt_join(BITJOIN,12641)@90
    assign i_unnamed_c_compmm_m501_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m501_vt_select_20_b};

    // i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x(BITSELECT,3820)@90
    assign i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x_b = i_unnamed_c_compmm_m501_vt_join_q[15:0];

    // redist898_i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x_b_1(DELAY,30026)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist898_i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16387_dupName_34_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16386)@90
    assign rightShiftStage1Idx1Rng8_uid16387_dupName_34_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16389_dupName_34_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16388)@90
    assign rightShiftStage1Idx1_uid16389_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16387_dupName_34_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16382_dupName_34_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16381)@90
    assign rightShiftStage0Idx1Rng4_uid16382_dupName_34_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q[33:4];

    // rightShiftStage0Idx1_uid16384_dupName_34_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16383)@90
    assign rightShiftStage0Idx1_uid16384_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16382_dupName_34_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x(MUX,16385)@90
    assign rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q or rightShiftStage0Idx1_uid16384_dupName_34_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_8_i_c_compmm_m500_q;
            1'b1 : rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16384_dupName_34_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x(MUX,16390)@90
    assign rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16389_dupName_34_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16386_dupName_34_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16389_dupName_34_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m503_vt_select_21(BITSELECT,12645)@90
    assign i_unnamed_c_compmm_m503_vt_select_21_b = rightShiftStage1_uid16391_dupName_34_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m503_vt_join(BITJOIN,12644)@90
    assign i_unnamed_c_compmm_m503_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m503_vt_select_21_b};

    // i_unnamed_c_compmm_m504_sel_x(BITSELECT,6224)@90
    assign i_unnamed_c_compmm_m504_sel_x_b = i_unnamed_c_compmm_m503_vt_join_q[15:0];

    // i_unnamed_c_compmm_m505_BitSelect_for_a(BITSELECT,28800)@90
    assign i_unnamed_c_compmm_m505_BitSelect_for_a_b = i_unnamed_c_compmm_m504_sel_x_b[0:0];

    // i_unnamed_c_compmm_m505_join(BITJOIN,28801)@90
    assign i_unnamed_c_compmm_m505_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m505_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m505_vt_select_0(BITSELECT,12650)@90
    assign i_unnamed_c_compmm_m505_vt_select_0_b = i_unnamed_c_compmm_m505_join_q[0:0];

    // redist37_i_unnamed_c_compmm_m505_vt_select_0_b_1(DELAY,29165)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist37_i_unnamed_c_compmm_m505_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m505_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m505_vt_join(BITJOIN,12649)@91
    assign i_unnamed_c_compmm_m505_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist37_i_unnamed_c_compmm_m505_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_8_c_compmm_m506(ADD,7275)@91
    assign i_add_i_i_i_i_i_i_8_c_compmm_m506_a = {1'b0, i_unnamed_c_compmm_m505_vt_join_q};
    assign i_add_i_i_i_i_i_i_8_c_compmm_m506_b = {1'b0, redist898_i_conv_i_i_i_i_i_8_c_compmm_m502_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_8_c_compmm_m506_o = $unsigned(i_add_i_i_i_i_i_i_8_c_compmm_m506_a) + $unsigned(i_add_i_i_i_i_i_i_8_c_compmm_m506_b);
    assign i_add_i_i_i_i_i_i_8_c_compmm_m506_q = i_add_i_i_i_i_i_i_8_c_compmm_m506_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_8_c_compmm_m506_sel_x(BITSELECT,2289)@91
    assign bgTrunc_i_add_i_i_i_i_i_i_8_c_compmm_m506_sel_x_b = i_add_i_i_i_i_i_i_8_c_compmm_m506_q[15:0];

    // i_conv_i_i_i_i_i_i246_9_c_compmm_m526_sel_x(BITSELECT,3959)@91
    assign i_conv_i_i_i_i_i_i246_9_c_compmm_m526_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_8_c_compmm_m506_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_select_15(BITSELECT,8563)@91
    assign i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_select_15_b = i_conv_i_i_i_i_i_i246_9_c_compmm_m526_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_join(BITJOIN,8562)@91
    assign i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_select_15_b};

    // leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(MUX,28330)@91
    assign leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_join_q or leftShiftStage0Idx1_uid28329_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_9_c_compmm_m526_vt_join_q;
            1'b1 : leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28329_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(MUX,28335)@91
    assign leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s or leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28334_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = leftShiftStage0_uid28331_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28334_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x(MUX,28340)@91
    assign leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s or leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28339_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = leftShiftStage1_uid28336_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28339_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28(BITSELECT,10219)@91
    assign i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28_b = leftShiftStage2_uid28341_i_shl_i_i_i_i_i_i_9_c_compmm_m0_shift_x_q[28:13];

    // redist255_i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28_b_1(DELAY,29383)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist255_i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_join(BITJOIN,10218)@92
    assign i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_join_q = {redist255_i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg237(REG,13532)@85 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg237_q <= $unsigned(redist768_sync_together4364_aunroll_x_in_i_valid_17_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_6438_c_compmm_m238(BLACKBOX,8604)@86
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6438_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_6438_c_compmm_m238 (
        .in_intel_reserved_ffwd_20_0(in_intel_reserved_ffwd_20_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg237_q),
        .out_dest_data_out_20_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_6438_c_compmm_m238_out_dest_data_out_20_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_offset(CONSTANT,30415)
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_offset_q = $unsigned(4'b0011);

    // redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt(ADD,30416)
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_a = {1'b0, redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_q};
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_b = {1'b0, redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_o <= $unsigned(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_a) + $unsigned(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_b);
        end
    end
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_q = redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_o[4:0];

    // redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_inputreg0(DELAY,30411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_inputreg0_q <= $unsigned(in_c1_eni5_19_tpl);
        end
    end

    // redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr(COUNTER,30414)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_i <= $unsigned(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_q = redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_i[3:0];

    // redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem(DUALMEM,30413)
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_ia = $unsigned(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_inputreg0_q);
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_aa = redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_wraddr_q;
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_ab = redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_aa),
        .data_a(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_ab),
        .q_b(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_q = redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_iq[15:0];

    // redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_outputreg0(DELAY,30412)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_outputreg0_q <= $unsigned(redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_mem_q);
        end
    end

    // redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt(ADD,30422)
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_a = {1'b0, redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_q};
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_b = {1'b0, redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_o <= $unsigned(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_a) + $unsigned(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_b);
        end
    end
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_q = redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_o[4:0];

    // redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_inputreg0(DELAY,30417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_inputreg0_q <= $unsigned(in_c1_eni5_20_tpl);
        end
    end

    // redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr(COUNTER,30420)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_i <= $unsigned(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_q = redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_i[3:0];

    // redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem(DUALMEM,30419)
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_ia = $unsigned(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_inputreg0_q);
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_aa = redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_wraddr_q;
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_ab = redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_aa),
        .data_a(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_ab),
        .q_b(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_q = redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_iq[15:0];

    // redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_outputreg0(DELAY,30418)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_outputreg0_q <= $unsigned(redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_mem_q);
        end
    end

    // valid_fanout_reg238(REG,13533)@85 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg238_q <= $unsigned(redist768_sync_together4364_aunroll_x_in_i_valid_17_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_6437_c_compmm_m239(BLACKBOX,8600)@86
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6437_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_6437_c_compmm_m239 (
        .in_intel_reserved_ffwd_19_0(in_intel_reserved_ffwd_19_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg238_q),
        .out_dest_data_out_19_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_6437_c_compmm_m239_out_dest_data_out_19_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28880)@86 + 5
    // out q@92
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_6437_c_compmm_m239_out_dest_data_out_19_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_6438_c_compmm_m238_out_dest_data_out_20_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528(ADD,9073)@92
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod327_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_b = $unsigned({{5{i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_9_c_compmm_m527_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_o[33:0];

    // rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x(MUX,16429)@92
    assign rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q or rightShiftStage0Idx1_uid16428_dupName_37_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q;
            1'b1 : rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16428_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x(MUX,16434)@92
    assign rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16433_dupName_37_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16430_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16433_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x(MUX,16439)@92
    assign rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16438_dupName_37_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16435_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16438_dupName_37_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m529_vt_select_20(BITSELECT,12664)@92
    assign i_unnamed_c_compmm_m529_vt_select_20_b = rightShiftStage2_uid16440_dupName_37_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m529_vt_join(BITJOIN,12663)@92
    assign i_unnamed_c_compmm_m529_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m529_vt_select_20_b};

    // i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x(BITSELECT,3831)@92
    assign i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x_b = i_unnamed_c_compmm_m529_vt_join_q[15:0];

    // redist887_i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x_b_1(DELAY,30015)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist887_i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16449_dupName_38_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16448)@92
    assign rightShiftStage1Idx1Rng8_uid16449_dupName_38_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16451_dupName_38_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16450)@92
    assign rightShiftStage1Idx1_uid16451_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16449_dupName_38_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16444_dupName_38_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16443)@92
    assign rightShiftStage0Idx1Rng4_uid16444_dupName_38_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q[33:4];

    // rightShiftStage0Idx1_uid16446_dupName_38_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16445)@92
    assign rightShiftStage0Idx1_uid16446_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16444_dupName_38_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x(MUX,16447)@92
    assign rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q or rightShiftStage0Idx1_uid16446_dupName_38_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_9_i_c_compmm_m528_q;
            1'b1 : rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16446_dupName_38_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x(MUX,16452)@92
    assign rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16451_dupName_38_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16448_dupName_38_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16451_dupName_38_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m531_vt_select_21(BITSELECT,12667)@92
    assign i_unnamed_c_compmm_m531_vt_select_21_b = rightShiftStage1_uid16453_dupName_38_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m531_vt_join(BITJOIN,12666)@92
    assign i_unnamed_c_compmm_m531_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m531_vt_select_21_b};

    // i_unnamed_c_compmm_m532_sel_x(BITSELECT,6226)@92
    assign i_unnamed_c_compmm_m532_sel_x_b = i_unnamed_c_compmm_m531_vt_join_q[15:0];

    // i_unnamed_c_compmm_m533_BitSelect_for_a(BITSELECT,28804)@92
    assign i_unnamed_c_compmm_m533_BitSelect_for_a_b = i_unnamed_c_compmm_m532_sel_x_b[0:0];

    // i_unnamed_c_compmm_m533_join(BITJOIN,28805)@92
    assign i_unnamed_c_compmm_m533_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m533_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m533_vt_select_0(BITSELECT,12672)@92
    assign i_unnamed_c_compmm_m533_vt_select_0_b = i_unnamed_c_compmm_m533_join_q[0:0];

    // redist35_i_unnamed_c_compmm_m533_vt_select_0_b_1(DELAY,29163)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist35_i_unnamed_c_compmm_m533_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m533_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m533_vt_join(BITJOIN,12671)@93
    assign i_unnamed_c_compmm_m533_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist35_i_unnamed_c_compmm_m533_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_9_c_compmm_m534(ADD,7286)@93
    assign i_add_i_i_i_i_i_i_9_c_compmm_m534_a = {1'b0, i_unnamed_c_compmm_m533_vt_join_q};
    assign i_add_i_i_i_i_i_i_9_c_compmm_m534_b = {1'b0, redist887_i_conv_i_i_i_i_i_9_c_compmm_m530_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_9_c_compmm_m534_o = $unsigned(i_add_i_i_i_i_i_i_9_c_compmm_m534_a) + $unsigned(i_add_i_i_i_i_i_i_9_c_compmm_m534_b);
    assign i_add_i_i_i_i_i_i_9_c_compmm_m534_q = i_add_i_i_i_i_i_i_9_c_compmm_m534_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x(BITSELECT,2300)@93
    assign bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x_b = i_add_i_i_i_i_i_i_9_c_compmm_m534_q[15:0];

    // redist1141_bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x_b_1(DELAY,30269)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1141_bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x_b_1_q <= $unsigned(bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x_b);
        end
    end

    // i_conv_i_i_i_i_i_i246_10_c_compmm_m554_sel_x(BITSELECT,3843)@94
    assign i_conv_i_i_i_i_i_i246_10_c_compmm_m554_sel_x_b = {13'b0000000000000, redist1141_bgTrunc_i_add_i_i_i_i_i_i_9_c_compmm_m534_sel_x_b_1_q[15:0]};

    // i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_select_15(BITSELECT,8099)@94
    assign i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_select_15_b = i_conv_i_i_i_i_i_i246_10_c_compmm_m554_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_join(BITJOIN,8098)@94
    assign i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_select_15_b};

    // leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(MUX,26242)@94
    assign leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_join_q or leftShiftStage0Idx1_uid26241_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_10_c_compmm_m554_vt_join_q;
            1'b1 : leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26241_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(MUX,26247)@94
    assign leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s or leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26246_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = leftShiftStage0_uid26243_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26246_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x(MUX,26252)@94
    assign leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s or leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26251_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = leftShiftStage1_uid26248_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26251_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_select_28(BITSELECT,9871)@94
    assign i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_select_28_b = leftShiftStage2_uid26253_i_shl_i_i_i_i_i_i_10_c_compmm_m0_shift_x_q[28:13];

    // i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_join(BITJOIN,9870)@94
    assign i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_join_q = {i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_select_28_b, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg235(REG,13530)@87 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg235_q <= $unsigned(redist769_sync_together4364_aunroll_x_in_i_valid_19_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_6440_c_compmm_m236(BLACKBOX,8616)@88
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6440_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_6440_c_compmm_m236 (
        .in_intel_reserved_ffwd_22_0(in_intel_reserved_ffwd_22_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg235_q),
        .out_dest_data_out_22_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_6440_c_compmm_m236_out_dest_data_out_22_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_offset(CONSTANT,30427)
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_offset_q = $unsigned(5'b10001);

    // redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt(ADD,30428)
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_a = {1'b0, redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_q};
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_b = {1'b0, redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_o <= $unsigned(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_a) + $unsigned(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_b);
        end
    end
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_q = redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_o[5:0];

    // redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_inputreg0(DELAY,30423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_inputreg0_q <= $unsigned(in_c1_eni5_21_tpl);
        end
    end

    // redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr(COUNTER,30426)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_i <= $unsigned(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_q = redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_i[4:0];

    // redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem(DUALMEM,30425)
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_ia = $unsigned(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_inputreg0_q);
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_aa = redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_wraddr_q;
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_ab = redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_aa),
        .data_a(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_ab),
        .q_b(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_q = redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_iq[15:0];

    // redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_outputreg0(DELAY,30424)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_outputreg0_q <= $unsigned(redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_mem_q);
        end
    end

    // redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt(ADD,30434)
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_a = {1'b0, redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_q};
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_b = {1'b0, redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_o <= $unsigned(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_a) + $unsigned(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_b);
        end
    end
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_q = redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_o[5:0];

    // redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_inputreg0(DELAY,30429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_inputreg0_q <= $unsigned(in_c1_eni5_22_tpl);
        end
    end

    // redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr(COUNTER,30432)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_i <= $unsigned(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_q = redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_i[4:0];

    // redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem(DUALMEM,30431)
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_ia = $unsigned(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_inputreg0_q);
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_aa = redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_wraddr_q;
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_ab = redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_aa),
        .data_a(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_ab),
        .q_b(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_q = redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_iq[15:0];

    // redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_outputreg0(DELAY,30430)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_outputreg0_q <= $unsigned(redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_mem_q);
        end
    end

    // valid_fanout_reg236(REG,13531)@87 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg236_q <= $unsigned(redist769_sync_together4364_aunroll_x_in_i_valid_19_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_6439_c_compmm_m237(BLACKBOX,8612)@88
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6439_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_6439_c_compmm_m237 (
        .in_intel_reserved_ffwd_21_0(in_intel_reserved_ffwd_21_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg236_q),
        .out_dest_data_out_21_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_6439_c_compmm_m237_out_dest_data_out_21_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28881)@88 + 5
    // out q@94
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_6439_c_compmm_m237_out_dest_data_out_21_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_6440_c_compmm_m236_out_dest_data_out_22_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556(ADD,8957)@94
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod332_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_b = $unsigned({{5{i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_10_c_compmm_m555_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_o[33:0];

    // rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x(MUX,16491)@94
    assign rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q or rightShiftStage0Idx1_uid16490_dupName_41_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q;
            1'b1 : rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16490_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x(MUX,16496)@94
    assign rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16495_dupName_41_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16492_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16495_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x(MUX,16501)@94
    assign rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16500_dupName_41_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16497_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16500_dupName_41_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m557_vt_select_20(BITSELECT,12686)@94
    assign i_unnamed_c_compmm_m557_vt_select_20_b = rightShiftStage2_uid16502_dupName_41_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m557_vt_join(BITJOIN,12685)@94
    assign i_unnamed_c_compmm_m557_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m557_vt_select_20_b};

    // i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x(BITSELECT,3715)@94
    assign i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x_b = i_unnamed_c_compmm_m557_vt_join_q[15:0];

    // redist1003_i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x_b_1(DELAY,30131)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1003_i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16511_dupName_42_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16510)@94
    assign rightShiftStage1Idx1Rng8_uid16511_dupName_42_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16513_dupName_42_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16512)@94
    assign rightShiftStage1Idx1_uid16513_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16511_dupName_42_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16506_dupName_42_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16505)@94
    assign rightShiftStage0Idx1Rng4_uid16506_dupName_42_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q[33:4];

    // rightShiftStage0Idx1_uid16508_dupName_42_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16507)@94
    assign rightShiftStage0Idx1_uid16508_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16506_dupName_42_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x(MUX,16509)@94
    assign rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q or rightShiftStage0Idx1_uid16508_dupName_42_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_10_i_c_compmm_m556_q;
            1'b1 : rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16508_dupName_42_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x(MUX,16514)@94
    assign rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16513_dupName_42_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16510_dupName_42_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16513_dupName_42_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m559_vt_select_21(BITSELECT,12689)@94
    assign i_unnamed_c_compmm_m559_vt_select_21_b = rightShiftStage1_uid16515_dupName_42_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m559_vt_join(BITJOIN,12688)@94
    assign i_unnamed_c_compmm_m559_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m559_vt_select_21_b};

    // i_unnamed_c_compmm_m560_sel_x(BITSELECT,6228)@94
    assign i_unnamed_c_compmm_m560_sel_x_b = i_unnamed_c_compmm_m559_vt_join_q[15:0];

    // i_unnamed_c_compmm_m561_BitSelect_for_a(BITSELECT,28808)@94
    assign i_unnamed_c_compmm_m561_BitSelect_for_a_b = i_unnamed_c_compmm_m560_sel_x_b[0:0];

    // i_unnamed_c_compmm_m561_join(BITJOIN,28809)@94
    assign i_unnamed_c_compmm_m561_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m561_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m561_vt_select_0(BITSELECT,12694)@94
    assign i_unnamed_c_compmm_m561_vt_select_0_b = i_unnamed_c_compmm_m561_join_q[0:0];

    // redist33_i_unnamed_c_compmm_m561_vt_select_0_b_1(DELAY,29161)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist33_i_unnamed_c_compmm_m561_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m561_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m561_vt_join(BITJOIN,12693)@95
    assign i_unnamed_c_compmm_m561_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist33_i_unnamed_c_compmm_m561_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_10_c_compmm_m562(ADD,7170)@95
    assign i_add_i_i_i_i_i_i_10_c_compmm_m562_a = {1'b0, i_unnamed_c_compmm_m561_vt_join_q};
    assign i_add_i_i_i_i_i_i_10_c_compmm_m562_b = {1'b0, redist1003_i_conv_i_i_i_i_i_10_c_compmm_m558_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_10_c_compmm_m562_o = $unsigned(i_add_i_i_i_i_i_i_10_c_compmm_m562_a) + $unsigned(i_add_i_i_i_i_i_i_10_c_compmm_m562_b);
    assign i_add_i_i_i_i_i_i_10_c_compmm_m562_q = i_add_i_i_i_i_i_i_10_c_compmm_m562_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_10_c_compmm_m562_sel_x(BITSELECT,2184)@95
    assign bgTrunc_i_add_i_i_i_i_i_i_10_c_compmm_m562_sel_x_b = i_add_i_i_i_i_i_i_10_c_compmm_m562_q[15:0];

    // i_conv_i_i_i_i_i_i246_11_c_compmm_m582_sel_x(BITSELECT,3854)@95
    assign i_conv_i_i_i_i_i_i246_11_c_compmm_m582_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_10_c_compmm_m562_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_select_15(BITSELECT,8143)@95
    assign i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_select_15_b = i_conv_i_i_i_i_i_i246_11_c_compmm_m582_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_join(BITJOIN,8142)@95
    assign i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_select_15_b};

    // leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(MUX,26440)@95
    assign leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_join_q or leftShiftStage0Idx1_uid26439_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_11_c_compmm_m582_vt_join_q;
            1'b1 : leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26439_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(MUX,26445)@95
    assign leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s or leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26444_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = leftShiftStage0_uid26441_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26444_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x(MUX,26450)@95
    assign leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s or leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26449_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = leftShiftStage1_uid26446_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26449_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28(BITSELECT,9904)@95
    assign i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28_b = leftShiftStage2_uid26451_i_shl_i_i_i_i_i_i_11_c_compmm_m0_shift_x_q[28:13];

    // redist358_i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28_b_1(DELAY,29486)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist358_i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_join(BITJOIN,9903)@96
    assign i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_join_q = {redist358_i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg233(REG,13528)@89 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg233_q <= $unsigned(redist770_sync_together4364_aunroll_x_in_i_valid_21_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_6442_c_compmm_m234(BLACKBOX,8624)@90
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6442_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_6442_c_compmm_m234 (
        .in_intel_reserved_ffwd_24_0(in_intel_reserved_ffwd_24_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg233_q),
        .out_dest_data_out_24_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_6442_c_compmm_m234_out_dest_data_out_24_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_offset(CONSTANT,30439)
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_offset_q = $unsigned(5'b01111);

    // redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt(ADD,30440)
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_a = {1'b0, redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_q};
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_b = {1'b0, redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_o <= $unsigned(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_a) + $unsigned(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_b);
        end
    end
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_q = redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_o[5:0];

    // redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_inputreg0(DELAY,30435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_inputreg0_q <= $unsigned(in_c1_eni5_23_tpl);
        end
    end

    // redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr(COUNTER,30438)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_i <= $unsigned(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_q = redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_i[4:0];

    // redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem(DUALMEM,30437)
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_ia = $unsigned(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_inputreg0_q);
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_aa = redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_wraddr_q;
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_ab = redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_aa),
        .data_a(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_ab),
        .q_b(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_q = redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_iq[15:0];

    // redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_outputreg0(DELAY,30436)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_outputreg0_q <= $unsigned(redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_mem_q);
        end
    end

    // redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt(ADD,30446)
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_a = {1'b0, redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_q};
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_b = {1'b0, redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_o <= $unsigned(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_a) + $unsigned(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_b);
        end
    end
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_q = redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_o[5:0];

    // redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_inputreg0(DELAY,30441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_inputreg0_q <= $unsigned(in_c1_eni5_24_tpl);
        end
    end

    // redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr(COUNTER,30444)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_i <= $unsigned(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_q = redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_i[4:0];

    // redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem(DUALMEM,30443)
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_ia = $unsigned(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_inputreg0_q);
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_aa = redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_wraddr_q;
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_ab = redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_aa),
        .data_a(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_ab),
        .q_b(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_q = redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_iq[15:0];

    // redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_outputreg0(DELAY,30442)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_outputreg0_q <= $unsigned(redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_mem_q);
        end
    end

    // valid_fanout_reg234(REG,13529)@89 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg234_q <= $unsigned(redist770_sync_together4364_aunroll_x_in_i_valid_21_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_6441_c_compmm_m235(BLACKBOX,8620)@90
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6441_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_6441_c_compmm_m235 (
        .in_intel_reserved_ffwd_23_0(in_intel_reserved_ffwd_23_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg234_q),
        .out_dest_data_out_23_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_6441_c_compmm_m235_out_dest_data_out_23_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28882)@90 + 5
    // out q@96
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_6441_c_compmm_m235_out_dest_data_out_23_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_6442_c_compmm_m234_out_dest_data_out_24_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584(ADD,8968)@96
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod337_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_b = $unsigned({{5{i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_11_c_compmm_m583_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_o[33:0];

    // rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x(MUX,16553)@96
    assign rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q or rightShiftStage0Idx1_uid16552_dupName_45_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q;
            1'b1 : rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16552_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x(MUX,16558)@96
    assign rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16557_dupName_45_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16554_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16557_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x(MUX,16563)@96
    assign rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16562_dupName_45_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16559_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16562_dupName_45_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m585_vt_select_20(BITSELECT,12708)@96
    assign i_unnamed_c_compmm_m585_vt_select_20_b = rightShiftStage2_uid16564_dupName_45_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m585_vt_join(BITJOIN,12707)@96
    assign i_unnamed_c_compmm_m585_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m585_vt_select_20_b};

    // i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x(BITSELECT,3726)@96
    assign i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x_b = i_unnamed_c_compmm_m585_vt_join_q[15:0];

    // redist992_i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x_b_1(DELAY,30120)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist992_i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16573_dupName_46_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16572)@96
    assign rightShiftStage1Idx1Rng8_uid16573_dupName_46_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16575_dupName_46_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16574)@96
    assign rightShiftStage1Idx1_uid16575_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16573_dupName_46_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16568_dupName_46_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16567)@96
    assign rightShiftStage0Idx1Rng4_uid16568_dupName_46_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q[33:4];

    // rightShiftStage0Idx1_uid16570_dupName_46_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16569)@96
    assign rightShiftStage0Idx1_uid16570_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16568_dupName_46_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x(MUX,16571)@96
    assign rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q or rightShiftStage0Idx1_uid16570_dupName_46_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_11_i_c_compmm_m584_q;
            1'b1 : rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16570_dupName_46_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x(MUX,16576)@96
    assign rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16575_dupName_46_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16572_dupName_46_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16575_dupName_46_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m587_vt_select_21(BITSELECT,12711)@96
    assign i_unnamed_c_compmm_m587_vt_select_21_b = rightShiftStage1_uid16577_dupName_46_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m587_vt_join(BITJOIN,12710)@96
    assign i_unnamed_c_compmm_m587_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m587_vt_select_21_b};

    // i_unnamed_c_compmm_m588_sel_x(BITSELECT,6230)@96
    assign i_unnamed_c_compmm_m588_sel_x_b = i_unnamed_c_compmm_m587_vt_join_q[15:0];

    // i_unnamed_c_compmm_m589_BitSelect_for_a(BITSELECT,28812)@96
    assign i_unnamed_c_compmm_m589_BitSelect_for_a_b = i_unnamed_c_compmm_m588_sel_x_b[0:0];

    // i_unnamed_c_compmm_m589_join(BITJOIN,28813)@96
    assign i_unnamed_c_compmm_m589_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m589_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m589_vt_select_0(BITSELECT,12716)@96
    assign i_unnamed_c_compmm_m589_vt_select_0_b = i_unnamed_c_compmm_m589_join_q[0:0];

    // redist31_i_unnamed_c_compmm_m589_vt_select_0_b_1(DELAY,29159)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist31_i_unnamed_c_compmm_m589_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m589_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m589_vt_join(BITJOIN,12715)@97
    assign i_unnamed_c_compmm_m589_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist31_i_unnamed_c_compmm_m589_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_11_c_compmm_m590(ADD,7181)@97
    assign i_add_i_i_i_i_i_i_11_c_compmm_m590_a = {1'b0, i_unnamed_c_compmm_m589_vt_join_q};
    assign i_add_i_i_i_i_i_i_11_c_compmm_m590_b = {1'b0, redist992_i_conv_i_i_i_i_i_11_c_compmm_m586_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_11_c_compmm_m590_o = $unsigned(i_add_i_i_i_i_i_i_11_c_compmm_m590_a) + $unsigned(i_add_i_i_i_i_i_i_11_c_compmm_m590_b);
    assign i_add_i_i_i_i_i_i_11_c_compmm_m590_q = i_add_i_i_i_i_i_i_11_c_compmm_m590_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_11_c_compmm_m590_sel_x(BITSELECT,2195)@97
    assign bgTrunc_i_add_i_i_i_i_i_i_11_c_compmm_m590_sel_x_b = i_add_i_i_i_i_i_i_11_c_compmm_m590_q[15:0];

    // i_conv_i_i_i_i_i_i246_12_c_compmm_m610_sel_x(BITSELECT,3863)@97
    assign i_conv_i_i_i_i_i_i246_12_c_compmm_m610_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_11_c_compmm_m590_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_select_15(BITSELECT,8179)@97
    assign i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_select_15_b = i_conv_i_i_i_i_i_i246_12_c_compmm_m610_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_join(BITJOIN,8178)@97
    assign i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_select_15_b};

    // leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(MUX,26602)@97
    assign leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_join_q or leftShiftStage0Idx1_uid26601_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_12_c_compmm_m610_vt_join_q;
            1'b1 : leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26601_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(MUX,26607)@97
    assign leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s or leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26606_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = leftShiftStage0_uid26603_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26606_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x(MUX,26612)@97
    assign leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s or leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26611_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = leftShiftStage1_uid26608_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26611_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28(BITSELECT,9931)@97
    assign i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28_b = leftShiftStage2_uid26613_i_shl_i_i_i_i_i_i_12_c_compmm_m0_shift_x_q[28:13];

    // redist349_i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28_b_1(DELAY,29477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist349_i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_join(BITJOIN,9930)@98
    assign i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_join_q = {redist349_i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg231(REG,13526)@91 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg231_q <= $unsigned(redist771_sync_together4364_aunroll_x_in_i_valid_23_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_6444_c_compmm_m232(BLACKBOX,8632)@92
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6444_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_6444_c_compmm_m232 (
        .in_intel_reserved_ffwd_26_0(in_intel_reserved_ffwd_26_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg231_q),
        .out_dest_data_out_26_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_6444_c_compmm_m232_out_dest_data_out_26_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_offset(CONSTANT,30451)
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_offset_q = $unsigned(5'b01101);

    // redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt(ADD,30452)
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_a = {1'b0, redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_q};
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_b = {1'b0, redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_o <= $unsigned(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_a) + $unsigned(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_b);
        end
    end
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_q = redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_o[5:0];

    // redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_inputreg0(DELAY,30447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_inputreg0_q <= $unsigned(in_c1_eni5_25_tpl);
        end
    end

    // redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr(COUNTER,30450)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_i <= $unsigned(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_q = redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_i[4:0];

    // redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem(DUALMEM,30449)
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_ia = $unsigned(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_inputreg0_q);
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_aa = redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_wraddr_q;
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_ab = redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_aa),
        .data_a(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_ab),
        .q_b(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_q = redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_iq[15:0];

    // redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_outputreg0(DELAY,30448)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_outputreg0_q <= $unsigned(redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_mem_q);
        end
    end

    // redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt(ADD,30458)
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_a = {1'b0, redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_q};
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_b = {1'b0, redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_o <= $unsigned(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_a) + $unsigned(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_b);
        end
    end
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_q = redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_o[5:0];

    // redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_inputreg0(DELAY,30453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_inputreg0_q <= $unsigned(in_c1_eni5_26_tpl);
        end
    end

    // redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr(COUNTER,30456)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_i <= $unsigned(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_q = redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_i[4:0];

    // redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem(DUALMEM,30455)
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_ia = $unsigned(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_inputreg0_q);
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_aa = redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_wraddr_q;
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_ab = redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_aa),
        .data_a(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_ab),
        .q_b(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_q = redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_iq[15:0];

    // redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_outputreg0(DELAY,30454)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_outputreg0_q <= $unsigned(redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_mem_q);
        end
    end

    // valid_fanout_reg232(REG,13527)@91 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg232_q <= $unsigned(redist771_sync_together4364_aunroll_x_in_i_valid_23_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_6443_c_compmm_m233(BLACKBOX,8628)@92
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6443_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_6443_c_compmm_m233 (
        .in_intel_reserved_ffwd_25_0(in_intel_reserved_ffwd_25_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg232_q),
        .out_dest_data_out_25_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_6443_c_compmm_m233_out_dest_data_out_25_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28883)@92 + 5
    // out q@98
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_6443_c_compmm_m233_out_dest_data_out_25_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_6444_c_compmm_m232_out_dest_data_out_26_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612(ADD,8977)@98
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod342_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_b = $unsigned({{5{i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_12_c_compmm_m611_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_o[33:0];

    // rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x(MUX,16615)@98
    assign rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q or rightShiftStage0Idx1_uid16614_dupName_49_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q;
            1'b1 : rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16614_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x(MUX,16620)@98
    assign rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16619_dupName_49_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16616_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16619_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x(MUX,16625)@98
    assign rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16624_dupName_49_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16621_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16624_dupName_49_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m613_vt_select_20(BITSELECT,12730)@98
    assign i_unnamed_c_compmm_m613_vt_select_20_b = rightShiftStage2_uid16626_dupName_49_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m613_vt_join(BITJOIN,12729)@98
    assign i_unnamed_c_compmm_m613_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m613_vt_select_20_b};

    // i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x(BITSELECT,3735)@98
    assign i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x_b = i_unnamed_c_compmm_m613_vt_join_q[15:0];

    // redist983_i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x_b_1(DELAY,30111)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist983_i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16635_dupName_50_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16634)@98
    assign rightShiftStage1Idx1Rng8_uid16635_dupName_50_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16637_dupName_50_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16636)@98
    assign rightShiftStage1Idx1_uid16637_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16635_dupName_50_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16630_dupName_50_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16629)@98
    assign rightShiftStage0Idx1Rng4_uid16630_dupName_50_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q[33:4];

    // rightShiftStage0Idx1_uid16632_dupName_50_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16631)@98
    assign rightShiftStage0Idx1_uid16632_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16630_dupName_50_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x(MUX,16633)@98
    assign rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q or rightShiftStage0Idx1_uid16632_dupName_50_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_12_i_c_compmm_m612_q;
            1'b1 : rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16632_dupName_50_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x(MUX,16638)@98
    assign rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16637_dupName_50_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16634_dupName_50_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16637_dupName_50_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m615_vt_select_21(BITSELECT,12733)@98
    assign i_unnamed_c_compmm_m615_vt_select_21_b = rightShiftStage1_uid16639_dupName_50_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m615_vt_join(BITJOIN,12732)@98
    assign i_unnamed_c_compmm_m615_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m615_vt_select_21_b};

    // i_unnamed_c_compmm_m616_sel_x(BITSELECT,6232)@98
    assign i_unnamed_c_compmm_m616_sel_x_b = i_unnamed_c_compmm_m615_vt_join_q[15:0];

    // i_unnamed_c_compmm_m617_BitSelect_for_a(BITSELECT,28816)@98
    assign i_unnamed_c_compmm_m617_BitSelect_for_a_b = i_unnamed_c_compmm_m616_sel_x_b[0:0];

    // i_unnamed_c_compmm_m617_join(BITJOIN,28817)@98
    assign i_unnamed_c_compmm_m617_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m617_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m617_vt_select_0(BITSELECT,12738)@98
    assign i_unnamed_c_compmm_m617_vt_select_0_b = i_unnamed_c_compmm_m617_join_q[0:0];

    // redist29_i_unnamed_c_compmm_m617_vt_select_0_b_1(DELAY,29157)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist29_i_unnamed_c_compmm_m617_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m617_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m617_vt_join(BITJOIN,12737)@99
    assign i_unnamed_c_compmm_m617_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist29_i_unnamed_c_compmm_m617_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_12_c_compmm_m618(ADD,7190)@99
    assign i_add_i_i_i_i_i_i_12_c_compmm_m618_a = {1'b0, i_unnamed_c_compmm_m617_vt_join_q};
    assign i_add_i_i_i_i_i_i_12_c_compmm_m618_b = {1'b0, redist983_i_conv_i_i_i_i_i_12_c_compmm_m614_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_12_c_compmm_m618_o = $unsigned(i_add_i_i_i_i_i_i_12_c_compmm_m618_a) + $unsigned(i_add_i_i_i_i_i_i_12_c_compmm_m618_b);
    assign i_add_i_i_i_i_i_i_12_c_compmm_m618_q = i_add_i_i_i_i_i_i_12_c_compmm_m618_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_12_c_compmm_m618_sel_x(BITSELECT,2204)@99
    assign bgTrunc_i_add_i_i_i_i_i_i_12_c_compmm_m618_sel_x_b = i_add_i_i_i_i_i_i_12_c_compmm_m618_q[15:0];

    // i_conv_i_i_i_i_i_i246_13_c_compmm_m638_sel_x(BITSELECT,3864)@99
    assign i_conv_i_i_i_i_i_i246_13_c_compmm_m638_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_12_c_compmm_m618_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_select_15(BITSELECT,8183)@99
    assign i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_select_15_b = i_conv_i_i_i_i_i_i246_13_c_compmm_m638_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_join(BITJOIN,8182)@99
    assign i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_select_15_b};

    // leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(MUX,26620)@99
    assign leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_join_q or leftShiftStage0Idx1_uid26619_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_13_c_compmm_m638_vt_join_q;
            1'b1 : leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26619_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(MUX,26625)@99
    assign leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s or leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26624_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = leftShiftStage0_uid26621_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26624_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x(MUX,26630)@99
    assign leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s or leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26629_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = leftShiftStage1_uid26626_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26629_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28(BITSELECT,9934)@99
    assign i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28_b = leftShiftStage2_uid26631_i_shl_i_i_i_i_i_i_13_c_compmm_m0_shift_x_q[28:13];

    // redist348_i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28_b_1(DELAY,29476)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist348_i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_join(BITJOIN,9933)@100
    assign i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_join_q = {redist348_i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg229(REG,13524)@93 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg229_q <= $unsigned(redist772_sync_together4364_aunroll_x_in_i_valid_25_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_6446_c_compmm_m230(BLACKBOX,8640)@94
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6446_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_6446_c_compmm_m230 (
        .in_intel_reserved_ffwd_28_0(in_intel_reserved_ffwd_28_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg229_q),
        .out_dest_data_out_28_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_6446_c_compmm_m230_out_dest_data_out_28_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_offset(CONSTANT,30463)
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_offset_q = $unsigned(5'b01011);

    // redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt(ADD,30464)
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_a = {1'b0, redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_q};
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_b = {1'b0, redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_o <= $unsigned(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_a) + $unsigned(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_b);
        end
    end
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_q = redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_o[5:0];

    // redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_inputreg0(DELAY,30459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_inputreg0_q <= $unsigned(in_c1_eni5_27_tpl);
        end
    end

    // redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr(COUNTER,30462)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_i <= $unsigned(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_q = redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_i[4:0];

    // redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem(DUALMEM,30461)
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_ia = $unsigned(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_inputreg0_q);
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_aa = redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_wraddr_q;
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_ab = redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_aa),
        .data_a(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_ab),
        .q_b(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_q = redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_iq[15:0];

    // redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_outputreg0(DELAY,30460)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_outputreg0_q <= $unsigned(redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_mem_q);
        end
    end

    // redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt(ADD,30470)
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_a = {1'b0, redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_q};
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_b = {1'b0, redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_o <= $unsigned(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_a) + $unsigned(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_b);
        end
    end
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_q = redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_o[5:0];

    // redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_inputreg0(DELAY,30465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_inputreg0_q <= $unsigned(in_c1_eni5_28_tpl);
        end
    end

    // redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr(COUNTER,30468)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_i <= $unsigned(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_q = redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_i[4:0];

    // redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem(DUALMEM,30467)
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_ia = $unsigned(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_inputreg0_q);
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_aa = redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_wraddr_q;
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_ab = redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_aa),
        .data_a(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_ab),
        .q_b(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_q = redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_iq[15:0];

    // redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_outputreg0(DELAY,30466)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_outputreg0_q <= $unsigned(redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_mem_q);
        end
    end

    // valid_fanout_reg230(REG,13525)@93 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg230_q <= $unsigned(redist772_sync_together4364_aunroll_x_in_i_valid_25_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_6445_c_compmm_m231(BLACKBOX,8636)@94
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6445_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_6445_c_compmm_m231 (
        .in_intel_reserved_ffwd_27_0(in_intel_reserved_ffwd_27_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg230_q),
        .out_dest_data_out_27_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_6445_c_compmm_m231_out_dest_data_out_27_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28884)@94 + 5
    // out q@100
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_6445_c_compmm_m231_out_dest_data_out_27_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_6446_c_compmm_m230_out_dest_data_out_28_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640(ADD,8978)@100
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod347_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_b = $unsigned({{5{i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_13_c_compmm_m639_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_o[33:0];

    // rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x(MUX,16677)@100
    assign rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q or rightShiftStage0Idx1_uid16676_dupName_53_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q;
            1'b1 : rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16676_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x(MUX,16682)@100
    assign rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16681_dupName_53_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16678_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16681_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x(MUX,16687)@100
    assign rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16686_dupName_53_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16683_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16686_dupName_53_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m641_vt_select_20(BITSELECT,12752)@100
    assign i_unnamed_c_compmm_m641_vt_select_20_b = rightShiftStage2_uid16688_dupName_53_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m641_vt_join(BITJOIN,12751)@100
    assign i_unnamed_c_compmm_m641_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m641_vt_select_20_b};

    // i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x(BITSELECT,3736)@100
    assign i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x_b = i_unnamed_c_compmm_m641_vt_join_q[15:0];

    // redist982_i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x_b_1(DELAY,30110)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist982_i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16697_dupName_54_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16696)@100
    assign rightShiftStage1Idx1Rng8_uid16697_dupName_54_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16699_dupName_54_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16698)@100
    assign rightShiftStage1Idx1_uid16699_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16697_dupName_54_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16692_dupName_54_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16691)@100
    assign rightShiftStage0Idx1Rng4_uid16692_dupName_54_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q[33:4];

    // rightShiftStage0Idx1_uid16694_dupName_54_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16693)@100
    assign rightShiftStage0Idx1_uid16694_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16692_dupName_54_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x(MUX,16695)@100
    assign rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q or rightShiftStage0Idx1_uid16694_dupName_54_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_13_i_c_compmm_m640_q;
            1'b1 : rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16694_dupName_54_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x(MUX,16700)@100
    assign rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16699_dupName_54_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16696_dupName_54_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16699_dupName_54_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m643_vt_select_21(BITSELECT,12755)@100
    assign i_unnamed_c_compmm_m643_vt_select_21_b = rightShiftStage1_uid16701_dupName_54_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m643_vt_join(BITJOIN,12754)@100
    assign i_unnamed_c_compmm_m643_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m643_vt_select_21_b};

    // i_unnamed_c_compmm_m644_sel_x(BITSELECT,6234)@100
    assign i_unnamed_c_compmm_m644_sel_x_b = i_unnamed_c_compmm_m643_vt_join_q[15:0];

    // i_unnamed_c_compmm_m645_BitSelect_for_a(BITSELECT,28820)@100
    assign i_unnamed_c_compmm_m645_BitSelect_for_a_b = i_unnamed_c_compmm_m644_sel_x_b[0:0];

    // i_unnamed_c_compmm_m645_join(BITJOIN,28821)@100
    assign i_unnamed_c_compmm_m645_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m645_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m645_vt_select_0(BITSELECT,12760)@100
    assign i_unnamed_c_compmm_m645_vt_select_0_b = i_unnamed_c_compmm_m645_join_q[0:0];

    // redist27_i_unnamed_c_compmm_m645_vt_select_0_b_1(DELAY,29155)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist27_i_unnamed_c_compmm_m645_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m645_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m645_vt_join(BITJOIN,12759)@101
    assign i_unnamed_c_compmm_m645_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist27_i_unnamed_c_compmm_m645_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_13_c_compmm_m646(ADD,7191)@101
    assign i_add_i_i_i_i_i_i_13_c_compmm_m646_a = {1'b0, i_unnamed_c_compmm_m645_vt_join_q};
    assign i_add_i_i_i_i_i_i_13_c_compmm_m646_b = {1'b0, redist982_i_conv_i_i_i_i_i_13_c_compmm_m642_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_13_c_compmm_m646_o = $unsigned(i_add_i_i_i_i_i_i_13_c_compmm_m646_a) + $unsigned(i_add_i_i_i_i_i_i_13_c_compmm_m646_b);
    assign i_add_i_i_i_i_i_i_13_c_compmm_m646_q = i_add_i_i_i_i_i_i_13_c_compmm_m646_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_13_c_compmm_m646_sel_x(BITSELECT,2205)@101
    assign bgTrunc_i_add_i_i_i_i_i_i_13_c_compmm_m646_sel_x_b = i_add_i_i_i_i_i_i_13_c_compmm_m646_q[15:0];

    // i_conv_i_i_i_i_i_i246_14_c_compmm_m666_sel_x(BITSELECT,3865)@101
    assign i_conv_i_i_i_i_i_i246_14_c_compmm_m666_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_13_c_compmm_m646_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_select_15(BITSELECT,8187)@101
    assign i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_select_15_b = i_conv_i_i_i_i_i_i246_14_c_compmm_m666_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_join(BITJOIN,8186)@101
    assign i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_select_15_b};

    // leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(MUX,26638)@101
    assign leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_join_q or leftShiftStage0Idx1_uid26637_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_14_c_compmm_m666_vt_join_q;
            1'b1 : leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26637_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(MUX,26643)@101
    assign leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s or leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26642_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = leftShiftStage0_uid26639_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26642_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x(MUX,26648)@101
    assign leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s or leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26647_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = leftShiftStage1_uid26644_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26647_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28(BITSELECT,9937)@101
    assign i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28_b = leftShiftStage2_uid26649_i_shl_i_i_i_i_i_i_14_c_compmm_m0_shift_x_q[28:13];

    // redist347_i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28_b_1(DELAY,29475)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist347_i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_join(BITJOIN,9936)@102
    assign i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_join_q = {redist347_i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg227(REG,13522)@95 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg227_q <= $unsigned(redist773_sync_together4364_aunroll_x_in_i_valid_27_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_6448_c_compmm_m228(BLACKBOX,8648)@96
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6448_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_6448_c_compmm_m228 (
        .in_intel_reserved_ffwd_30_0(in_intel_reserved_ffwd_30_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg227_q),
        .out_dest_data_out_30_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_6448_c_compmm_m228_out_dest_data_out_30_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_offset(CONSTANT,30475)
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_offset_q = $unsigned(5'b01001);

    // redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt(ADD,30476)
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_a = {1'b0, redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_q};
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_b = {1'b0, redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_o <= $unsigned(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_a) + $unsigned(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_b);
        end
    end
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_q = redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_o[5:0];

    // redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_inputreg0(DELAY,30471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_inputreg0_q <= $unsigned(in_c1_eni5_29_tpl);
        end
    end

    // redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr(COUNTER,30474)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_i <= $unsigned(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_q = redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_i[4:0];

    // redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem(DUALMEM,30473)
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_ia = $unsigned(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_inputreg0_q);
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_aa = redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_wraddr_q;
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_ab = redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_aa),
        .data_a(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_ab),
        .q_b(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_q = redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_iq[15:0];

    // redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_outputreg0(DELAY,30472)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_outputreg0_q <= $unsigned(redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_mem_q);
        end
    end

    // redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt(ADD,30482)
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_a = {1'b0, redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_q};
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_b = {1'b0, redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_o <= $unsigned(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_a) + $unsigned(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_b);
        end
    end
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_q = redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_o[5:0];

    // redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_inputreg0(DELAY,30477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_inputreg0_q <= $unsigned(in_c1_eni5_30_tpl);
        end
    end

    // redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr(COUNTER,30480)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_i <= $unsigned(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_q = redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_i[4:0];

    // redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem(DUALMEM,30479)
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_ia = $unsigned(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_inputreg0_q);
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_aa = redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_wraddr_q;
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_ab = redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_aa),
        .data_a(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_ab),
        .q_b(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_q = redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_iq[15:0];

    // redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_outputreg0(DELAY,30478)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_outputreg0_q <= $unsigned(redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_mem_q);
        end
    end

    // valid_fanout_reg228(REG,13523)@95 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg228_q <= $unsigned(redist773_sync_together4364_aunroll_x_in_i_valid_27_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_6447_c_compmm_m229(BLACKBOX,8644)@96
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6447_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_6447_c_compmm_m229 (
        .in_intel_reserved_ffwd_29_0(in_intel_reserved_ffwd_29_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg228_q),
        .out_dest_data_out_29_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_6447_c_compmm_m229_out_dest_data_out_29_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28885)@96 + 5
    // out q@102
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_6447_c_compmm_m229_out_dest_data_out_29_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_6448_c_compmm_m228_out_dest_data_out_30_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668(ADD,8979)@102
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod352_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_b = $unsigned({{5{i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_14_c_compmm_m667_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_o[33:0];

    // rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x(MUX,16739)@102
    assign rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q or rightShiftStage0Idx1_uid16738_dupName_57_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q;
            1'b1 : rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16738_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x(MUX,16744)@102
    assign rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16743_dupName_57_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16740_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16743_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x(MUX,16749)@102
    assign rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16748_dupName_57_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16745_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16748_dupName_57_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m669_vt_select_20(BITSELECT,12774)@102
    assign i_unnamed_c_compmm_m669_vt_select_20_b = rightShiftStage2_uid16750_dupName_57_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m669_vt_join(BITJOIN,12773)@102
    assign i_unnamed_c_compmm_m669_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m669_vt_select_20_b};

    // i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x(BITSELECT,3737)@102
    assign i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x_b = i_unnamed_c_compmm_m669_vt_join_q[15:0];

    // redist981_i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x_b_1(DELAY,30109)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist981_i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16759_dupName_58_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16758)@102
    assign rightShiftStage1Idx1Rng8_uid16759_dupName_58_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16761_dupName_58_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16760)@102
    assign rightShiftStage1Idx1_uid16761_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16759_dupName_58_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16754_dupName_58_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16753)@102
    assign rightShiftStage0Idx1Rng4_uid16754_dupName_58_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q[33:4];

    // rightShiftStage0Idx1_uid16756_dupName_58_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16755)@102
    assign rightShiftStage0Idx1_uid16756_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16754_dupName_58_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x(MUX,16757)@102
    assign rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q or rightShiftStage0Idx1_uid16756_dupName_58_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_14_i_c_compmm_m668_q;
            1'b1 : rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16756_dupName_58_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x(MUX,16762)@102
    assign rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16761_dupName_58_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16758_dupName_58_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16761_dupName_58_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m671_vt_select_21(BITSELECT,12777)@102
    assign i_unnamed_c_compmm_m671_vt_select_21_b = rightShiftStage1_uid16763_dupName_58_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m671_vt_join(BITJOIN,12776)@102
    assign i_unnamed_c_compmm_m671_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m671_vt_select_21_b};

    // i_unnamed_c_compmm_m672_sel_x(BITSELECT,6236)@102
    assign i_unnamed_c_compmm_m672_sel_x_b = i_unnamed_c_compmm_m671_vt_join_q[15:0];

    // i_unnamed_c_compmm_m673_BitSelect_for_a(BITSELECT,28824)@102
    assign i_unnamed_c_compmm_m673_BitSelect_for_a_b = i_unnamed_c_compmm_m672_sel_x_b[0:0];

    // i_unnamed_c_compmm_m673_join(BITJOIN,28825)@102
    assign i_unnamed_c_compmm_m673_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m673_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m673_vt_select_0(BITSELECT,12782)@102
    assign i_unnamed_c_compmm_m673_vt_select_0_b = i_unnamed_c_compmm_m673_join_q[0:0];

    // redist25_i_unnamed_c_compmm_m673_vt_select_0_b_1(DELAY,29153)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist25_i_unnamed_c_compmm_m673_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m673_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m673_vt_join(BITJOIN,12781)@103
    assign i_unnamed_c_compmm_m673_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist25_i_unnamed_c_compmm_m673_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_14_c_compmm_m674(ADD,7192)@103
    assign i_add_i_i_i_i_i_i_14_c_compmm_m674_a = {1'b0, i_unnamed_c_compmm_m673_vt_join_q};
    assign i_add_i_i_i_i_i_i_14_c_compmm_m674_b = {1'b0, redist981_i_conv_i_i_i_i_i_14_c_compmm_m670_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_14_c_compmm_m674_o = $unsigned(i_add_i_i_i_i_i_i_14_c_compmm_m674_a) + $unsigned(i_add_i_i_i_i_i_i_14_c_compmm_m674_b);
    assign i_add_i_i_i_i_i_i_14_c_compmm_m674_q = i_add_i_i_i_i_i_i_14_c_compmm_m674_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_14_c_compmm_m674_sel_x(BITSELECT,2206)@103
    assign bgTrunc_i_add_i_i_i_i_i_i_14_c_compmm_m674_sel_x_b = i_add_i_i_i_i_i_i_14_c_compmm_m674_q[15:0];

    // i_conv_i_i_i_i_i_i246_15_c_compmm_m694_sel_x(BITSELECT,3866)@103
    assign i_conv_i_i_i_i_i_i246_15_c_compmm_m694_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_14_c_compmm_m674_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_select_15(BITSELECT,8191)@103
    assign i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_select_15_b = i_conv_i_i_i_i_i_i246_15_c_compmm_m694_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_join(BITJOIN,8190)@103
    assign i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_select_15_b};

    // leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(MUX,26656)@103
    assign leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_join_q or leftShiftStage0Idx1_uid26655_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_15_c_compmm_m694_vt_join_q;
            1'b1 : leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26655_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(MUX,26661)@103
    assign leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s or leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26660_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = leftShiftStage0_uid26657_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26660_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x(MUX,26666)@103
    assign leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s or leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26665_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = leftShiftStage1_uid26662_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26665_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28(BITSELECT,9940)@103
    assign i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28_b = leftShiftStage2_uid26667_i_shl_i_i_i_i_i_i_15_c_compmm_m0_shift_x_q[28:13];

    // redist346_i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28_b_1(DELAY,29474)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist346_i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_join(BITJOIN,9939)@104
    assign i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_join_q = {redist346_i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg225(REG,13520)@97 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg225_q <= $unsigned(redist774_sync_together4364_aunroll_x_in_i_valid_29_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_6450_c_compmm_m226(BLACKBOX,8660)@98
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6450_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_6450_c_compmm_m226 (
        .in_intel_reserved_ffwd_32_0(in_intel_reserved_ffwd_32_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg225_q),
        .out_dest_data_out_32_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_6450_c_compmm_m226_out_dest_data_out_32_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_offset(CONSTANT,30487)
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_offset_q = $unsigned(5'b00111);

    // redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt(ADD,30488)
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_a = {1'b0, redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_q};
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_b = {1'b0, redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_o <= $unsigned(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_a) + $unsigned(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_b);
        end
    end
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_q = redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_o[5:0];

    // redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_inputreg0(DELAY,30483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_inputreg0_q <= $unsigned(in_c1_eni5_31_tpl);
        end
    end

    // redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr(COUNTER,30486)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_i <= $unsigned(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_q = redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_i[4:0];

    // redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem(DUALMEM,30485)
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_ia = $unsigned(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_inputreg0_q);
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_aa = redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_wraddr_q;
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_ab = redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_aa),
        .data_a(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_ab),
        .q_b(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_q = redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_iq[15:0];

    // redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_outputreg0(DELAY,30484)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_outputreg0_q <= $unsigned(redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_mem_q);
        end
    end

    // redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt(ADD,30494)
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_a = {1'b0, redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_q};
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_b = {1'b0, redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_o <= $unsigned(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_a) + $unsigned(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_b);
        end
    end
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_q = redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_o[5:0];

    // redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_inputreg0(DELAY,30489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_inputreg0_q <= $unsigned(in_c1_eni5_32_tpl);
        end
    end

    // redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr(COUNTER,30492)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_i <= $unsigned(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_q = redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_i[4:0];

    // redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem(DUALMEM,30491)
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_ia = $unsigned(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_inputreg0_q);
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_aa = redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_wraddr_q;
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_ab = redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_aa),
        .data_a(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_ab),
        .q_b(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_q = redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_iq[15:0];

    // redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_outputreg0(DELAY,30490)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_outputreg0_q <= $unsigned(redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_mem_q);
        end
    end

    // valid_fanout_reg226(REG,13521)@97 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg226_q <= $unsigned(redist774_sync_together4364_aunroll_x_in_i_valid_29_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_6449_c_compmm_m227(BLACKBOX,8656)@98
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6449_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_6449_c_compmm_m227 (
        .in_intel_reserved_ffwd_31_0(in_intel_reserved_ffwd_31_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg226_q),
        .out_dest_data_out_31_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_6449_c_compmm_m227_out_dest_data_out_31_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28886)@98 + 5
    // out q@104
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_6449_c_compmm_m227_out_dest_data_out_31_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_6450_c_compmm_m226_out_dest_data_out_32_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696(ADD,8980)@104
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod357_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_b = $unsigned({{5{i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_15_c_compmm_m695_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_o[33:0];

    // rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x(MUX,16801)@104
    assign rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q or rightShiftStage0Idx1_uid16800_dupName_61_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q;
            1'b1 : rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16800_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x(MUX,16806)@104
    assign rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16805_dupName_61_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16802_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16805_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x(MUX,16811)@104
    assign rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16810_dupName_61_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16807_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16810_dupName_61_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m697_vt_select_20(BITSELECT,12796)@104
    assign i_unnamed_c_compmm_m697_vt_select_20_b = rightShiftStage2_uid16812_dupName_61_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m697_vt_join(BITJOIN,12795)@104
    assign i_unnamed_c_compmm_m697_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m697_vt_select_20_b};

    // i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x(BITSELECT,3738)@104
    assign i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x_b = i_unnamed_c_compmm_m697_vt_join_q[15:0];

    // redist980_i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x_b_1(DELAY,30108)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist980_i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16821_dupName_62_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16820)@104
    assign rightShiftStage1Idx1Rng8_uid16821_dupName_62_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16823_dupName_62_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16822)@104
    assign rightShiftStage1Idx1_uid16823_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16821_dupName_62_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16816_dupName_62_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16815)@104
    assign rightShiftStage0Idx1Rng4_uid16816_dupName_62_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q[33:4];

    // rightShiftStage0Idx1_uid16818_dupName_62_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16817)@104
    assign rightShiftStage0Idx1_uid16818_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16816_dupName_62_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x(MUX,16819)@104
    assign rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q or rightShiftStage0Idx1_uid16818_dupName_62_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_15_i_c_compmm_m696_q;
            1'b1 : rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16818_dupName_62_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x(MUX,16824)@104
    assign rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16823_dupName_62_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16820_dupName_62_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16823_dupName_62_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m699_vt_select_21(BITSELECT,12799)@104
    assign i_unnamed_c_compmm_m699_vt_select_21_b = rightShiftStage1_uid16825_dupName_62_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m699_vt_join(BITJOIN,12798)@104
    assign i_unnamed_c_compmm_m699_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m699_vt_select_21_b};

    // i_unnamed_c_compmm_m700_sel_x(BITSELECT,6238)@104
    assign i_unnamed_c_compmm_m700_sel_x_b = i_unnamed_c_compmm_m699_vt_join_q[15:0];

    // i_unnamed_c_compmm_m701_BitSelect_for_a(BITSELECT,28828)@104
    assign i_unnamed_c_compmm_m701_BitSelect_for_a_b = i_unnamed_c_compmm_m700_sel_x_b[0:0];

    // i_unnamed_c_compmm_m701_join(BITJOIN,28829)@104
    assign i_unnamed_c_compmm_m701_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m701_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m701_vt_select_0(BITSELECT,12804)@104
    assign i_unnamed_c_compmm_m701_vt_select_0_b = i_unnamed_c_compmm_m701_join_q[0:0];

    // redist23_i_unnamed_c_compmm_m701_vt_select_0_b_1(DELAY,29151)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist23_i_unnamed_c_compmm_m701_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m701_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m701_vt_join(BITJOIN,12803)@105
    assign i_unnamed_c_compmm_m701_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist23_i_unnamed_c_compmm_m701_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_15_c_compmm_m702(ADD,7193)@105
    assign i_add_i_i_i_i_i_i_15_c_compmm_m702_a = {1'b0, i_unnamed_c_compmm_m701_vt_join_q};
    assign i_add_i_i_i_i_i_i_15_c_compmm_m702_b = {1'b0, redist980_i_conv_i_i_i_i_i_15_c_compmm_m698_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_15_c_compmm_m702_o = $unsigned(i_add_i_i_i_i_i_i_15_c_compmm_m702_a) + $unsigned(i_add_i_i_i_i_i_i_15_c_compmm_m702_b);
    assign i_add_i_i_i_i_i_i_15_c_compmm_m702_q = i_add_i_i_i_i_i_i_15_c_compmm_m702_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_15_c_compmm_m702_sel_x(BITSELECT,2207)@105
    assign bgTrunc_i_add_i_i_i_i_i_i_15_c_compmm_m702_sel_x_b = i_add_i_i_i_i_i_i_15_c_compmm_m702_q[15:0];

    // i_conv_i_i_i_i_i_i246_16_c_compmm_m722_sel_x(BITSELECT,3867)@105
    assign i_conv_i_i_i_i_i_i246_16_c_compmm_m722_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_15_c_compmm_m702_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_select_15(BITSELECT,8195)@105
    assign i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_select_15_b = i_conv_i_i_i_i_i_i246_16_c_compmm_m722_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_join(BITJOIN,8194)@105
    assign i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_select_15_b};

    // leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(MUX,26674)@105
    assign leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_join_q or leftShiftStage0Idx1_uid26673_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_16_c_compmm_m722_vt_join_q;
            1'b1 : leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26673_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(MUX,26679)@105
    assign leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s or leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26678_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = leftShiftStage0_uid26675_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26678_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x(MUX,26684)@105
    assign leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s or leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26683_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = leftShiftStage1_uid26680_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26683_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28(BITSELECT,9943)@105
    assign i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28_b = leftShiftStage2_uid26685_i_shl_i_i_i_i_i_i_16_c_compmm_m0_shift_x_q[28:13];

    // redist345_i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28_b_1(DELAY,29473)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist345_i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_join(BITJOIN,9942)@106
    assign i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_join_q = {redist345_i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg223(REG,13518)@99 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg223_q <= $unsigned(redist775_sync_together4364_aunroll_x_in_i_valid_31_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_6452_c_compmm_m224(BLACKBOX,8668)@100
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6452_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_6452_c_compmm_m224 (
        .in_intel_reserved_ffwd_34_0(in_intel_reserved_ffwd_34_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg223_q),
        .out_dest_data_out_34_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_6452_c_compmm_m224_out_dest_data_out_34_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_offset(CONSTANT,30499)
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_offset_q = $unsigned(5'b00101);

    // redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt(ADD,30500)
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_a = {1'b0, redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_q};
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_b = {1'b0, redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_o <= $unsigned(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_a) + $unsigned(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_b);
        end
    end
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_q = redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_o[5:0];

    // redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_inputreg0(DELAY,30495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_inputreg0_q <= $unsigned(in_c1_eni5_33_tpl);
        end
    end

    // redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr(COUNTER,30498)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_i <= $unsigned(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_q = redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_i[4:0];

    // redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem(DUALMEM,30497)
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_ia = $unsigned(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_inputreg0_q);
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_aa = redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_wraddr_q;
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_ab = redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_aa),
        .data_a(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_ab),
        .q_b(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_q = redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_iq[15:0];

    // redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_outputreg0(DELAY,30496)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_outputreg0_q <= $unsigned(redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_mem_q);
        end
    end

    // redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt(ADD,30506)
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_a = {1'b0, redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_q};
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_b = {1'b0, redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_o <= $unsigned(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_a) + $unsigned(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_b);
        end
    end
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_q = redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_o[5:0];

    // redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_inputreg0(DELAY,30501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_inputreg0_q <= $unsigned(in_c1_eni5_34_tpl);
        end
    end

    // redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr(COUNTER,30504)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_i <= $unsigned(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_q = redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_i[4:0];

    // redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem(DUALMEM,30503)
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_ia = $unsigned(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_inputreg0_q);
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_aa = redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_wraddr_q;
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_ab = redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_aa),
        .data_a(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_ab),
        .q_b(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_q = redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_iq[15:0];

    // redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_outputreg0(DELAY,30502)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_outputreg0_q <= $unsigned(redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_mem_q);
        end
    end

    // valid_fanout_reg224(REG,13519)@99 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg224_q <= $unsigned(redist775_sync_together4364_aunroll_x_in_i_valid_31_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_6451_c_compmm_m225(BLACKBOX,8664)@100
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6451_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_6451_c_compmm_m225 (
        .in_intel_reserved_ffwd_33_0(in_intel_reserved_ffwd_33_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg224_q),
        .out_dest_data_out_33_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_6451_c_compmm_m225_out_dest_data_out_33_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28887)@100 + 5
    // out q@106
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_6451_c_compmm_m225_out_dest_data_out_33_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_6452_c_compmm_m224_out_dest_data_out_34_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724(ADD,8981)@106
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod362_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_b = $unsigned({{5{i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_16_c_compmm_m723_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_o[33:0];

    // rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x(MUX,16863)@106
    assign rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q or rightShiftStage0Idx1_uid16862_dupName_65_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q;
            1'b1 : rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16862_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x(MUX,16868)@106
    assign rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16867_dupName_65_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16864_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16867_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x(MUX,16873)@106
    assign rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16872_dupName_65_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16869_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16872_dupName_65_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m725_vt_select_20(BITSELECT,12818)@106
    assign i_unnamed_c_compmm_m725_vt_select_20_b = rightShiftStage2_uid16874_dupName_65_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m725_vt_join(BITJOIN,12817)@106
    assign i_unnamed_c_compmm_m725_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m725_vt_select_20_b};

    // i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x(BITSELECT,3739)@106
    assign i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x_b = i_unnamed_c_compmm_m725_vt_join_q[15:0];

    // redist979_i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x_b_1(DELAY,30107)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist979_i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16883_dupName_66_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16882)@106
    assign rightShiftStage1Idx1Rng8_uid16883_dupName_66_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16885_dupName_66_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16884)@106
    assign rightShiftStage1Idx1_uid16885_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16883_dupName_66_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16878_dupName_66_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16877)@106
    assign rightShiftStage0Idx1Rng4_uid16878_dupName_66_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q[33:4];

    // rightShiftStage0Idx1_uid16880_dupName_66_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16879)@106
    assign rightShiftStage0Idx1_uid16880_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16878_dupName_66_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x(MUX,16881)@106
    assign rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q or rightShiftStage0Idx1_uid16880_dupName_66_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_16_i_c_compmm_m724_q;
            1'b1 : rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16880_dupName_66_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x(MUX,16886)@106
    assign rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16885_dupName_66_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16882_dupName_66_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16885_dupName_66_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m727_vt_select_21(BITSELECT,12821)@106
    assign i_unnamed_c_compmm_m727_vt_select_21_b = rightShiftStage1_uid16887_dupName_66_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m727_vt_join(BITJOIN,12820)@106
    assign i_unnamed_c_compmm_m727_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m727_vt_select_21_b};

    // i_unnamed_c_compmm_m728_sel_x(BITSELECT,6240)@106
    assign i_unnamed_c_compmm_m728_sel_x_b = i_unnamed_c_compmm_m727_vt_join_q[15:0];

    // i_unnamed_c_compmm_m729_BitSelect_for_a(BITSELECT,28832)@106
    assign i_unnamed_c_compmm_m729_BitSelect_for_a_b = i_unnamed_c_compmm_m728_sel_x_b[0:0];

    // i_unnamed_c_compmm_m729_join(BITJOIN,28833)@106
    assign i_unnamed_c_compmm_m729_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m729_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m729_vt_select_0(BITSELECT,12826)@106
    assign i_unnamed_c_compmm_m729_vt_select_0_b = i_unnamed_c_compmm_m729_join_q[0:0];

    // redist21_i_unnamed_c_compmm_m729_vt_select_0_b_1(DELAY,29149)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist21_i_unnamed_c_compmm_m729_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m729_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m729_vt_join(BITJOIN,12825)@107
    assign i_unnamed_c_compmm_m729_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist21_i_unnamed_c_compmm_m729_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_16_c_compmm_m730(ADD,7194)@107
    assign i_add_i_i_i_i_i_i_16_c_compmm_m730_a = {1'b0, i_unnamed_c_compmm_m729_vt_join_q};
    assign i_add_i_i_i_i_i_i_16_c_compmm_m730_b = {1'b0, redist979_i_conv_i_i_i_i_i_16_c_compmm_m726_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_16_c_compmm_m730_o = $unsigned(i_add_i_i_i_i_i_i_16_c_compmm_m730_a) + $unsigned(i_add_i_i_i_i_i_i_16_c_compmm_m730_b);
    assign i_add_i_i_i_i_i_i_16_c_compmm_m730_q = i_add_i_i_i_i_i_i_16_c_compmm_m730_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_16_c_compmm_m730_sel_x(BITSELECT,2208)@107
    assign bgTrunc_i_add_i_i_i_i_i_i_16_c_compmm_m730_sel_x_b = i_add_i_i_i_i_i_i_16_c_compmm_m730_q[15:0];

    // i_conv_i_i_i_i_i_i246_17_c_compmm_m750_sel_x(BITSELECT,3868)@107
    assign i_conv_i_i_i_i_i_i246_17_c_compmm_m750_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_16_c_compmm_m730_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_select_15(BITSELECT,8199)@107
    assign i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_select_15_b = i_conv_i_i_i_i_i_i246_17_c_compmm_m750_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_join(BITJOIN,8198)@107
    assign i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_select_15_b};

    // leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(MUX,26692)@107
    assign leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_join_q or leftShiftStage0Idx1_uid26691_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_17_c_compmm_m750_vt_join_q;
            1'b1 : leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26691_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(MUX,26697)@107
    assign leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s or leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26696_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = leftShiftStage0_uid26693_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26696_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x(MUX,26702)@107
    assign leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s or leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26701_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = leftShiftStage1_uid26698_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26701_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28(BITSELECT,9946)@107
    assign i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28_b = leftShiftStage2_uid26703_i_shl_i_i_i_i_i_i_17_c_compmm_m0_shift_x_q[28:13];

    // redist344_i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28_b_1(DELAY,29472)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist344_i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_join(BITJOIN,9945)@108
    assign i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_join_q = {redist344_i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg221(REG,13516)@101 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg221_q <= $unsigned(redist776_sync_together4364_aunroll_x_in_i_valid_33_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_6454_c_compmm_m222(BLACKBOX,8676)@102
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6454_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_6454_c_compmm_m222 (
        .in_intel_reserved_ffwd_36_0(in_intel_reserved_ffwd_36_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg221_q),
        .out_dest_data_out_36_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_6454_c_compmm_m222_out_dest_data_out_36_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset(CONSTANT,30671)
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q = $unsigned(5'b00100);

    // redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt(ADD,31800)
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_a = {1'b0, redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_q};
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_o <= $unsigned(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_a) + $unsigned(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_b);
        end
    end
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_q = redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_o[5:0];

    // redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_inputreg0(DELAY,31795)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_inputreg0_q <= $unsigned(in_c1_eni5_35_tpl);
        end
    end

    // redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr(COUNTER,31798)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_i <= $unsigned(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_q = redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_i[4:0];

    // redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem(DUALMEM,31797)
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_ia = $unsigned(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_inputreg0_q);
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_aa = redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_wraddr_q;
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_ab = redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_aa),
        .data_a(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_ab),
        .q_b(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_q = redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_iq[15:0];

    // redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_outputreg0(DELAY,31796)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_outputreg0_q <= $unsigned(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_mem_q);
        end
    end

    // redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34(DELAY,29665)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_q <= $unsigned(redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_split_0_outputreg0_q);
        end
    end

    // redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt(ADD,31806)
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_a = {1'b0, redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_q};
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_o <= $unsigned(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_a) + $unsigned(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_b);
        end
    end
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_q = redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_o[5:0];

    // redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_inputreg0(DELAY,31801)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_inputreg0_q <= $unsigned(in_c1_eni5_36_tpl);
        end
    end

    // redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr(COUNTER,31804)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_i <= $unsigned(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_q = redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_i[4:0];

    // redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem(DUALMEM,31803)
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_ia = $unsigned(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_inputreg0_q);
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_aa = redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_wraddr_q;
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_ab = redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_aa),
        .data_a(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_ab),
        .q_b(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_q = redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_iq[15:0];

    // redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_outputreg0(DELAY,31802)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_outputreg0_q <= $unsigned(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_mem_q);
        end
    end

    // redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34(DELAY,29666)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_q <= $unsigned(redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_split_0_outputreg0_q);
        end
    end

    // valid_fanout_reg222(REG,13517)@101 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg222_q <= $unsigned(redist776_sync_together4364_aunroll_x_in_i_valid_33_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_6453_c_compmm_m223(BLACKBOX,8672)@102
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6453_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_6453_c_compmm_m223 (
        .in_intel_reserved_ffwd_35_0(in_intel_reserved_ffwd_35_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg222_q),
        .out_dest_data_out_35_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_6453_c_compmm_m223_out_dest_data_out_35_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28888)@102 + 5
    // out q@108
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_6453_c_compmm_m223_out_dest_data_out_35_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_6454_c_compmm_m222_out_dest_data_out_36_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752(ADD,8982)@108
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod367_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_b = $unsigned({{5{i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_17_c_compmm_m751_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_o[33:0];

    // rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x(MUX,16925)@108
    assign rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q or rightShiftStage0Idx1_uid16924_dupName_69_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q;
            1'b1 : rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16924_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x(MUX,16930)@108
    assign rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16929_dupName_69_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16926_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16929_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x(MUX,16935)@108
    assign rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16934_dupName_69_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16931_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16934_dupName_69_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m753_vt_select_20(BITSELECT,12840)@108
    assign i_unnamed_c_compmm_m753_vt_select_20_b = rightShiftStage2_uid16936_dupName_69_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m753_vt_join(BITJOIN,12839)@108
    assign i_unnamed_c_compmm_m753_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m753_vt_select_20_b};

    // i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x(BITSELECT,3740)@108
    assign i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x_b = i_unnamed_c_compmm_m753_vt_join_q[15:0];

    // redist978_i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x_b_1(DELAY,30106)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist978_i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16945_dupName_70_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16944)@108
    assign rightShiftStage1Idx1Rng8_uid16945_dupName_70_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16947_dupName_70_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16946)@108
    assign rightShiftStage1Idx1_uid16947_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16945_dupName_70_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16940_dupName_70_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16939)@108
    assign rightShiftStage0Idx1Rng4_uid16940_dupName_70_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q[33:4];

    // rightShiftStage0Idx1_uid16942_dupName_70_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16941)@108
    assign rightShiftStage0Idx1_uid16942_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16940_dupName_70_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x(MUX,16943)@108
    assign rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q or rightShiftStage0Idx1_uid16942_dupName_70_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_17_i_c_compmm_m752_q;
            1'b1 : rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16942_dupName_70_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x(MUX,16948)@108
    assign rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16947_dupName_70_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16944_dupName_70_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16947_dupName_70_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m755_vt_select_21(BITSELECT,12843)@108
    assign i_unnamed_c_compmm_m755_vt_select_21_b = rightShiftStage1_uid16949_dupName_70_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m755_vt_join(BITJOIN,12842)@108
    assign i_unnamed_c_compmm_m755_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m755_vt_select_21_b};

    // i_unnamed_c_compmm_m756_sel_x(BITSELECT,6242)@108
    assign i_unnamed_c_compmm_m756_sel_x_b = i_unnamed_c_compmm_m755_vt_join_q[15:0];

    // i_unnamed_c_compmm_m757_BitSelect_for_a(BITSELECT,28836)@108
    assign i_unnamed_c_compmm_m757_BitSelect_for_a_b = i_unnamed_c_compmm_m756_sel_x_b[0:0];

    // i_unnamed_c_compmm_m757_join(BITJOIN,28837)@108
    assign i_unnamed_c_compmm_m757_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m757_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m757_vt_select_0(BITSELECT,12848)@108
    assign i_unnamed_c_compmm_m757_vt_select_0_b = i_unnamed_c_compmm_m757_join_q[0:0];

    // redist19_i_unnamed_c_compmm_m757_vt_select_0_b_1(DELAY,29147)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist19_i_unnamed_c_compmm_m757_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m757_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m757_vt_join(BITJOIN,12847)@109
    assign i_unnamed_c_compmm_m757_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist19_i_unnamed_c_compmm_m757_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_17_c_compmm_m758(ADD,7195)@109
    assign i_add_i_i_i_i_i_i_17_c_compmm_m758_a = {1'b0, i_unnamed_c_compmm_m757_vt_join_q};
    assign i_add_i_i_i_i_i_i_17_c_compmm_m758_b = {1'b0, redist978_i_conv_i_i_i_i_i_17_c_compmm_m754_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_17_c_compmm_m758_o = $unsigned(i_add_i_i_i_i_i_i_17_c_compmm_m758_a) + $unsigned(i_add_i_i_i_i_i_i_17_c_compmm_m758_b);
    assign i_add_i_i_i_i_i_i_17_c_compmm_m758_q = i_add_i_i_i_i_i_i_17_c_compmm_m758_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_17_c_compmm_m758_sel_x(BITSELECT,2209)@109
    assign bgTrunc_i_add_i_i_i_i_i_i_17_c_compmm_m758_sel_x_b = i_add_i_i_i_i_i_i_17_c_compmm_m758_q[15:0];

    // i_conv_i_i_i_i_i_i246_18_c_compmm_m778_sel_x(BITSELECT,3869)@109
    assign i_conv_i_i_i_i_i_i246_18_c_compmm_m778_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_17_c_compmm_m758_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_select_15(BITSELECT,8203)@109
    assign i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_select_15_b = i_conv_i_i_i_i_i_i246_18_c_compmm_m778_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_join(BITJOIN,8202)@109
    assign i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_select_15_b};

    // leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(MUX,26710)@109
    assign leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_join_q or leftShiftStage0Idx1_uid26709_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_18_c_compmm_m778_vt_join_q;
            1'b1 : leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26709_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(MUX,26715)@109
    assign leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s or leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26714_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = leftShiftStage0_uid26711_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26714_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x(MUX,26720)@109
    assign leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s or leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26719_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = leftShiftStage1_uid26716_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26719_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28(BITSELECT,9949)@109
    assign i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28_b = leftShiftStage2_uid26721_i_shl_i_i_i_i_i_i_18_c_compmm_m0_shift_x_q[28:13];

    // redist343_i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28_b_1(DELAY,29471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist343_i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_join(BITJOIN,9948)@110
    assign i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_join_q = {redist343_i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg219(REG,13514)@103 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg219_q <= $unsigned(redist777_sync_together4364_aunroll_x_in_i_valid_35_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_6456_c_compmm_m220(BLACKBOX,8684)@104
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6456_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_6456_c_compmm_m220 (
        .in_intel_reserved_ffwd_38_0(in_intel_reserved_ffwd_38_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg219_q),
        .out_dest_data_out_38_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_6456_c_compmm_m220_out_dest_data_out_38_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt(ADD,31812)
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_a = {1'b0, redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_q};
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_o <= $unsigned(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_a) + $unsigned(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_b);
        end
    end
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_q = redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_o[5:0];

    // redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_inputreg0(DELAY,31807)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_inputreg0_q <= $unsigned(in_c1_eni5_37_tpl);
        end
    end

    // redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr(COUNTER,31810)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_i <= $unsigned(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_q = redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_i[4:0];

    // redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem(DUALMEM,31809)
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_ia = $unsigned(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_inputreg0_q);
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_aa = redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_wraddr_q;
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_ab = redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_aa),
        .data_a(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_ab),
        .q_b(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_q = redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_iq[15:0];

    // redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_outputreg0(DELAY,31808)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_outputreg0_q <= $unsigned(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_mem_q);
        end
    end

    // redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36(DELAY,29667)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_delay_0 <= $unsigned(redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_split_0_outputreg0_q);
            redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_delay_1 <= redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_delay_0;
            redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_q <= redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_delay_1;
        end
    end

    // redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt(ADD,31818)
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_a = {1'b0, redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_q};
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_o <= $unsigned(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_a) + $unsigned(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_b);
        end
    end
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_q = redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_o[5:0];

    // redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_inputreg0(DELAY,31813)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_inputreg0_q <= $unsigned(in_c1_eni5_38_tpl);
        end
    end

    // redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr(COUNTER,31816)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_i <= $unsigned(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_q = redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_i[4:0];

    // redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem(DUALMEM,31815)
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_ia = $unsigned(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_inputreg0_q);
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_aa = redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_wraddr_q;
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_ab = redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_aa),
        .data_a(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_ab),
        .q_b(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_q = redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_iq[15:0];

    // redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_outputreg0(DELAY,31814)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_outputreg0_q <= $unsigned(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_mem_q);
        end
    end

    // redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36(DELAY,29668)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_delay_0 <= $unsigned(redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_split_0_outputreg0_q);
            redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_delay_1 <= redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_delay_0;
            redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_q <= redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_delay_1;
        end
    end

    // valid_fanout_reg220(REG,13515)@103 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg220_q <= $unsigned(redist777_sync_together4364_aunroll_x_in_i_valid_35_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_6455_c_compmm_m221(BLACKBOX,8680)@104
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6455_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_6455_c_compmm_m221 (
        .in_intel_reserved_ffwd_37_0(in_intel_reserved_ffwd_37_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg220_q),
        .out_dest_data_out_37_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_6455_c_compmm_m221_out_dest_data_out_37_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28889)@104 + 5
    // out q@110
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_6455_c_compmm_m221_out_dest_data_out_37_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_6456_c_compmm_m220_out_dest_data_out_38_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780(ADD,8983)@110
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod372_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_b = $unsigned({{5{i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_18_c_compmm_m779_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_o[33:0];

    // rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x(MUX,16987)@110
    assign rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q or rightShiftStage0Idx1_uid16986_dupName_73_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q;
            1'b1 : rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16986_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x(MUX,16992)@110
    assign rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16991_dupName_73_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16988_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16991_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x(MUX,16997)@110
    assign rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16996_dupName_73_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16993_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16996_dupName_73_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m781_vt_select_20(BITSELECT,12862)@110
    assign i_unnamed_c_compmm_m781_vt_select_20_b = rightShiftStage2_uid16998_dupName_73_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m781_vt_join(BITJOIN,12861)@110
    assign i_unnamed_c_compmm_m781_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m781_vt_select_20_b};

    // i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x(BITSELECT,3741)@110
    assign i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x_b = i_unnamed_c_compmm_m781_vt_join_q[15:0];

    // redist977_i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x_b_1(DELAY,30105)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist977_i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17007_dupName_74_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17006)@110
    assign rightShiftStage1Idx1Rng8_uid17007_dupName_74_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17009_dupName_74_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17008)@110
    assign rightShiftStage1Idx1_uid17009_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17007_dupName_74_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17002_dupName_74_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17001)@110
    assign rightShiftStage0Idx1Rng4_uid17002_dupName_74_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q[33:4];

    // rightShiftStage0Idx1_uid17004_dupName_74_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17003)@110
    assign rightShiftStage0Idx1_uid17004_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17002_dupName_74_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x(MUX,17005)@110
    assign rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q or rightShiftStage0Idx1_uid17004_dupName_74_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_18_i_c_compmm_m780_q;
            1'b1 : rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17004_dupName_74_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x(MUX,17010)@110
    assign rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17009_dupName_74_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17006_dupName_74_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17009_dupName_74_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m783_vt_select_21(BITSELECT,12865)@110
    assign i_unnamed_c_compmm_m783_vt_select_21_b = rightShiftStage1_uid17011_dupName_74_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m783_vt_join(BITJOIN,12864)@110
    assign i_unnamed_c_compmm_m783_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m783_vt_select_21_b};

    // i_unnamed_c_compmm_m784_sel_x(BITSELECT,6244)@110
    assign i_unnamed_c_compmm_m784_sel_x_b = i_unnamed_c_compmm_m783_vt_join_q[15:0];

    // i_unnamed_c_compmm_m785_BitSelect_for_a(BITSELECT,28840)@110
    assign i_unnamed_c_compmm_m785_BitSelect_for_a_b = i_unnamed_c_compmm_m784_sel_x_b[0:0];

    // i_unnamed_c_compmm_m785_join(BITJOIN,28841)@110
    assign i_unnamed_c_compmm_m785_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m785_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m785_vt_select_0(BITSELECT,12870)@110
    assign i_unnamed_c_compmm_m785_vt_select_0_b = i_unnamed_c_compmm_m785_join_q[0:0];

    // redist17_i_unnamed_c_compmm_m785_vt_select_0_b_1(DELAY,29145)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist17_i_unnamed_c_compmm_m785_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m785_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m785_vt_join(BITJOIN,12869)@111
    assign i_unnamed_c_compmm_m785_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist17_i_unnamed_c_compmm_m785_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_18_c_compmm_m786(ADD,7196)@111
    assign i_add_i_i_i_i_i_i_18_c_compmm_m786_a = {1'b0, i_unnamed_c_compmm_m785_vt_join_q};
    assign i_add_i_i_i_i_i_i_18_c_compmm_m786_b = {1'b0, redist977_i_conv_i_i_i_i_i_18_c_compmm_m782_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_18_c_compmm_m786_o = $unsigned(i_add_i_i_i_i_i_i_18_c_compmm_m786_a) + $unsigned(i_add_i_i_i_i_i_i_18_c_compmm_m786_b);
    assign i_add_i_i_i_i_i_i_18_c_compmm_m786_q = i_add_i_i_i_i_i_i_18_c_compmm_m786_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_18_c_compmm_m786_sel_x(BITSELECT,2210)@111
    assign bgTrunc_i_add_i_i_i_i_i_i_18_c_compmm_m786_sel_x_b = i_add_i_i_i_i_i_i_18_c_compmm_m786_q[15:0];

    // i_conv_i_i_i_i_i_i246_19_c_compmm_m806_sel_x(BITSELECT,3870)@111
    assign i_conv_i_i_i_i_i_i246_19_c_compmm_m806_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_18_c_compmm_m786_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_select_15(BITSELECT,8207)@111
    assign i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_select_15_b = i_conv_i_i_i_i_i_i246_19_c_compmm_m806_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_join(BITJOIN,8206)@111
    assign i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_select_15_b};

    // leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(MUX,26728)@111
    assign leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_join_q or leftShiftStage0Idx1_uid26727_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_19_c_compmm_m806_vt_join_q;
            1'b1 : leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26727_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(MUX,26733)@111
    assign leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s or leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26732_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = leftShiftStage0_uid26729_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26732_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x(MUX,26738)@111
    assign leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s or leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26737_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = leftShiftStage1_uid26734_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26737_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28(BITSELECT,9952)@111
    assign i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28_b = leftShiftStage2_uid26739_i_shl_i_i_i_i_i_i_19_c_compmm_m0_shift_x_q[28:13];

    // redist342_i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28_b_1(DELAY,29470)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist342_i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_join(BITJOIN,9951)@112
    assign i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_join_q = {redist342_i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg217(REG,13512)@105 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg217_q <= $unsigned(redist778_sync_together4364_aunroll_x_in_i_valid_37_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_6458_c_compmm_m218(BLACKBOX,8692)@106
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6458_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_6458_c_compmm_m218 (
        .in_intel_reserved_ffwd_40_0(in_intel_reserved_ffwd_40_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg217_q),
        .out_dest_data_out_40_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_6458_c_compmm_m218_out_dest_data_out_40_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt(ADD,31824)
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_a = {1'b0, redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_q};
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_o <= $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_a) + $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_b);
        end
    end
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_q = redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_o[5:0];

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_inputreg0(DELAY,31819)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_inputreg0_q <= $unsigned(in_c1_eni5_39_tpl);
        end
    end

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr(COUNTER,31822)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_i <= $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_q = redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_i[4:0];

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem(DUALMEM,31821)
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_ia = $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_inputreg0_q);
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_aa = redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_wraddr_q;
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_ab = redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_aa),
        .data_a(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_ab),
        .q_b(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_q = redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_iq[15:0];

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_outputreg0(DELAY,31820)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_outputreg0_q <= $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_mem_q);
        end
    end

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_inputreg0(DELAY,30507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_inputreg0_q <= $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_split_0_outputreg0_q);
        end
    end

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38(DELAY,29669)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_delay_0 <= $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_inputreg0_q);
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_delay_1 <= redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_delay_0;
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_q <= redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_delay_1;
        end
    end

    // redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_outputreg0(DELAY,30508)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_outputreg0_q <= $unsigned(redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_q);
        end
    end

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt(ADD,31830)
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_a = {1'b0, redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_q};
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_o <= $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_a) + $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_b);
        end
    end
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_q = redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_o[5:0];

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_inputreg0(DELAY,31825)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_inputreg0_q <= $unsigned(in_c1_eni5_40_tpl);
        end
    end

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr(COUNTER,31828)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_i <= $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_q = redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_i[4:0];

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem(DUALMEM,31827)
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_ia = $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_inputreg0_q);
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_aa = redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_wraddr_q;
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_ab = redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_aa),
        .data_a(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_ab),
        .q_b(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_q = redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_iq[15:0];

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_outputreg0(DELAY,31826)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_outputreg0_q <= $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_mem_q);
        end
    end

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_inputreg0(DELAY,30509)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_inputreg0_q <= $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_split_0_outputreg0_q);
        end
    end

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38(DELAY,29670)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_delay_0 <= $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_inputreg0_q);
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_delay_1 <= redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_delay_0;
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_q <= redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_delay_1;
        end
    end

    // redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_outputreg0(DELAY,30510)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_outputreg0_q <= $unsigned(redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_q);
        end
    end

    // valid_fanout_reg218(REG,13513)@105 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg218_q <= $unsigned(redist778_sync_together4364_aunroll_x_in_i_valid_37_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_6457_c_compmm_m219(BLACKBOX,8688)@106
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6457_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_6457_c_compmm_m219 (
        .in_intel_reserved_ffwd_39_0(in_intel_reserved_ffwd_39_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg218_q),
        .out_dest_data_out_39_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_6457_c_compmm_m219_out_dest_data_out_39_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28890)@106 + 5
    // out q@112
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_6457_c_compmm_m219_out_dest_data_out_39_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_6458_c_compmm_m218_out_dest_data_out_40_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808(ADD,8984)@112
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod377_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_b = $unsigned({{5{i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_19_c_compmm_m807_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_o[33:0];

    // rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x(MUX,17049)@112
    assign rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q or rightShiftStage0Idx1_uid17048_dupName_77_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q;
            1'b1 : rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17048_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x(MUX,17054)@112
    assign rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17053_dupName_77_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17050_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17053_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x(MUX,17059)@112
    assign rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17058_dupName_77_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17055_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17058_dupName_77_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m809_vt_select_20(BITSELECT,12884)@112
    assign i_unnamed_c_compmm_m809_vt_select_20_b = rightShiftStage2_uid17060_dupName_77_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m809_vt_join(BITJOIN,12883)@112
    assign i_unnamed_c_compmm_m809_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m809_vt_select_20_b};

    // i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x(BITSELECT,3742)@112
    assign i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x_b = i_unnamed_c_compmm_m809_vt_join_q[15:0];

    // redist976_i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x_b_1(DELAY,30104)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist976_i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17069_dupName_78_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17068)@112
    assign rightShiftStage1Idx1Rng8_uid17069_dupName_78_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17071_dupName_78_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17070)@112
    assign rightShiftStage1Idx1_uid17071_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17069_dupName_78_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17064_dupName_78_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17063)@112
    assign rightShiftStage0Idx1Rng4_uid17064_dupName_78_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q[33:4];

    // rightShiftStage0Idx1_uid17066_dupName_78_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17065)@112
    assign rightShiftStage0Idx1_uid17066_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17064_dupName_78_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x(MUX,17067)@112
    assign rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q or rightShiftStage0Idx1_uid17066_dupName_78_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_19_i_c_compmm_m808_q;
            1'b1 : rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17066_dupName_78_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x(MUX,17072)@112
    assign rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17071_dupName_78_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17068_dupName_78_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17071_dupName_78_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m811_vt_select_21(BITSELECT,12887)@112
    assign i_unnamed_c_compmm_m811_vt_select_21_b = rightShiftStage1_uid17073_dupName_78_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m811_vt_join(BITJOIN,12886)@112
    assign i_unnamed_c_compmm_m811_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m811_vt_select_21_b};

    // i_unnamed_c_compmm_m812_sel_x(BITSELECT,6246)@112
    assign i_unnamed_c_compmm_m812_sel_x_b = i_unnamed_c_compmm_m811_vt_join_q[15:0];

    // i_unnamed_c_compmm_m813_BitSelect_for_a(BITSELECT,28844)@112
    assign i_unnamed_c_compmm_m813_BitSelect_for_a_b = i_unnamed_c_compmm_m812_sel_x_b[0:0];

    // i_unnamed_c_compmm_m813_join(BITJOIN,28845)@112
    assign i_unnamed_c_compmm_m813_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m813_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m813_vt_select_0(BITSELECT,12892)@112
    assign i_unnamed_c_compmm_m813_vt_select_0_b = i_unnamed_c_compmm_m813_join_q[0:0];

    // redist15_i_unnamed_c_compmm_m813_vt_select_0_b_1(DELAY,29143)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist15_i_unnamed_c_compmm_m813_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m813_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m813_vt_join(BITJOIN,12891)@113
    assign i_unnamed_c_compmm_m813_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist15_i_unnamed_c_compmm_m813_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_19_c_compmm_m814(ADD,7197)@113
    assign i_add_i_i_i_i_i_i_19_c_compmm_m814_a = {1'b0, i_unnamed_c_compmm_m813_vt_join_q};
    assign i_add_i_i_i_i_i_i_19_c_compmm_m814_b = {1'b0, redist976_i_conv_i_i_i_i_i_19_c_compmm_m810_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_19_c_compmm_m814_o = $unsigned(i_add_i_i_i_i_i_i_19_c_compmm_m814_a) + $unsigned(i_add_i_i_i_i_i_i_19_c_compmm_m814_b);
    assign i_add_i_i_i_i_i_i_19_c_compmm_m814_q = i_add_i_i_i_i_i_i_19_c_compmm_m814_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_19_c_compmm_m814_sel_x(BITSELECT,2211)@113
    assign bgTrunc_i_add_i_i_i_i_i_i_19_c_compmm_m814_sel_x_b = i_add_i_i_i_i_i_i_19_c_compmm_m814_q[15:0];

    // i_conv_i_i_i_i_i_i246_20_c_compmm_m834_sel_x(BITSELECT,3872)@113
    assign i_conv_i_i_i_i_i_i246_20_c_compmm_m834_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_19_c_compmm_m814_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_select_15(BITSELECT,8215)@113
    assign i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_select_15_b = i_conv_i_i_i_i_i_i246_20_c_compmm_m834_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_join(BITJOIN,8214)@113
    assign i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_select_15_b};

    // leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(MUX,26764)@113
    assign leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_join_q or leftShiftStage0Idx1_uid26763_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_20_c_compmm_m834_vt_join_q;
            1'b1 : leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26763_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(MUX,26769)@113
    assign leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s or leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26768_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = leftShiftStage0_uid26765_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26768_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x(MUX,26774)@113
    assign leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s or leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26773_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = leftShiftStage1_uid26770_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26773_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28(BITSELECT,9958)@113
    assign i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28_b = leftShiftStage2_uid26775_i_shl_i_i_i_i_i_i_20_c_compmm_m0_shift_x_q[28:13];

    // redist340_i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28_b_1(DELAY,29468)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist340_i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_join(BITJOIN,9957)@114
    assign i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_join_q = {redist340_i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg215(REG,13510)@107 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg215_q <= $unsigned(redist779_sync_together4364_aunroll_x_in_i_valid_39_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_6460_c_compmm_m216(BLACKBOX,8704)@108
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6460_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_6460_c_compmm_m216 (
        .in_intel_reserved_ffwd_42_0(in_intel_reserved_ffwd_42_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg215_q),
        .out_dest_data_out_42_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_6460_c_compmm_m216_out_dest_data_out_42_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_offset(CONSTANT,30515)
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_offset_q = $unsigned(2'b10);

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt(ADD,30516)
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_a = {1'b0, redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_q};
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_b = {1'b0, redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_o <= $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_a) + $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_b);
        end
    end
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_q = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_o[2:0];

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt(ADD,31836)
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_a = {1'b0, redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_q};
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_o <= $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_a) + $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_b);
        end
    end
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_q = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_o[5:0];

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_inputreg0(DELAY,31831)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_inputreg0_q <= $unsigned(in_c1_eni5_41_tpl);
        end
    end

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr(COUNTER,31834)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_i <= $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_q = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_i[4:0];

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem(DUALMEM,31833)
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_ia = $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_inputreg0_q);
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_aa = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_wraddr_q;
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_ab = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_aa),
        .data_a(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_ab),
        .q_b(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_q = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_iq[15:0];

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_outputreg0(DELAY,31832)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_outputreg0_q <= $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_mem_q);
        end
    end

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_inputreg0(DELAY,30511)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_inputreg0_q <= $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_split_0_outputreg0_q);
        end
    end

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr(COUNTER,30514)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_i <= $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_q = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_i[1:0];

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem(DUALMEM,30513)
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_ia = $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_inputreg0_q);
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_aa = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_wraddr_q;
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_ab = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_aa),
        .data_a(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_ab),
        .q_b(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_q = redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_iq[15:0];

    // redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_outputreg0(DELAY,30512)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_outputreg0_q <= $unsigned(redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_mem_q);
        end
    end

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt(ADD,30522)
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_a = {1'b0, redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_q};
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_b = {1'b0, redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_o <= $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_a) + $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_b);
        end
    end
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_q = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_o[2:0];

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt(ADD,31842)
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_a = {1'b0, redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_q};
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_o <= $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_a) + $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_b);
        end
    end
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_q = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_o[5:0];

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_inputreg0(DELAY,31837)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_inputreg0_q <= $unsigned(in_c1_eni5_42_tpl);
        end
    end

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr(COUNTER,31840)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_i <= $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_q = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_i[4:0];

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem(DUALMEM,31839)
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_ia = $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_inputreg0_q);
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_aa = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_wraddr_q;
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_ab = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_aa),
        .data_a(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_ab),
        .q_b(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_q = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_iq[15:0];

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_outputreg0(DELAY,31838)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_outputreg0_q <= $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_mem_q);
        end
    end

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_inputreg0(DELAY,30517)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_inputreg0_q <= $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_split_0_outputreg0_q);
        end
    end

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr(COUNTER,30520)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_i <= $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_q = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_i[1:0];

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem(DUALMEM,30519)
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_ia = $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_inputreg0_q);
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_aa = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_wraddr_q;
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_ab = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_aa),
        .data_a(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_ab),
        .q_b(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_q = redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_iq[15:0];

    // redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_outputreg0(DELAY,30518)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_outputreg0_q <= $unsigned(redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_mem_q);
        end
    end

    // valid_fanout_reg216(REG,13511)@107 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg216_q <= $unsigned(redist779_sync_together4364_aunroll_x_in_i_valid_39_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_6459_c_compmm_m217(BLACKBOX,8700)@108
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6459_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_6459_c_compmm_m217 (
        .in_intel_reserved_ffwd_41_0(in_intel_reserved_ffwd_41_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg216_q),
        .out_dest_data_out_41_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_6459_c_compmm_m217_out_dest_data_out_41_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28891)@108 + 5
    // out q@114
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_6459_c_compmm_m217_out_dest_data_out_41_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_6460_c_compmm_m216_out_dest_data_out_42_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836(ADD,8986)@114
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod382_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_b = $unsigned({{5{i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_20_c_compmm_m835_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_o[33:0];

    // rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x(MUX,17111)@114
    assign rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q or rightShiftStage0Idx1_uid17110_dupName_81_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q;
            1'b1 : rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17110_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x(MUX,17116)@114
    assign rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17115_dupName_81_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17112_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17115_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x(MUX,17121)@114
    assign rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17120_dupName_81_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17117_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17120_dupName_81_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m837_vt_select_20(BITSELECT,12906)@114
    assign i_unnamed_c_compmm_m837_vt_select_20_b = rightShiftStage2_uid17122_dupName_81_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m837_vt_join(BITJOIN,12905)@114
    assign i_unnamed_c_compmm_m837_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m837_vt_select_20_b};

    // i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x(BITSELECT,3744)@114
    assign i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x_b = i_unnamed_c_compmm_m837_vt_join_q[15:0];

    // redist974_i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x_b_1(DELAY,30102)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist974_i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17131_dupName_82_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17130)@114
    assign rightShiftStage1Idx1Rng8_uid17131_dupName_82_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17133_dupName_82_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17132)@114
    assign rightShiftStage1Idx1_uid17133_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17131_dupName_82_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17126_dupName_82_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17125)@114
    assign rightShiftStage0Idx1Rng4_uid17126_dupName_82_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q[33:4];

    // rightShiftStage0Idx1_uid17128_dupName_82_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17127)@114
    assign rightShiftStage0Idx1_uid17128_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17126_dupName_82_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x(MUX,17129)@114
    assign rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q or rightShiftStage0Idx1_uid17128_dupName_82_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_20_i_c_compmm_m836_q;
            1'b1 : rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17128_dupName_82_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x(MUX,17134)@114
    assign rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17133_dupName_82_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17130_dupName_82_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17133_dupName_82_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m839_vt_select_21(BITSELECT,12909)@114
    assign i_unnamed_c_compmm_m839_vt_select_21_b = rightShiftStage1_uid17135_dupName_82_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m839_vt_join(BITJOIN,12908)@114
    assign i_unnamed_c_compmm_m839_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m839_vt_select_21_b};

    // i_unnamed_c_compmm_m840_sel_x(BITSELECT,6248)@114
    assign i_unnamed_c_compmm_m840_sel_x_b = i_unnamed_c_compmm_m839_vt_join_q[15:0];

    // i_unnamed_c_compmm_m841_BitSelect_for_a(BITSELECT,28848)@114
    assign i_unnamed_c_compmm_m841_BitSelect_for_a_b = i_unnamed_c_compmm_m840_sel_x_b[0:0];

    // i_unnamed_c_compmm_m841_join(BITJOIN,28849)@114
    assign i_unnamed_c_compmm_m841_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m841_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m841_vt_select_0(BITSELECT,12914)@114
    assign i_unnamed_c_compmm_m841_vt_select_0_b = i_unnamed_c_compmm_m841_join_q[0:0];

    // redist13_i_unnamed_c_compmm_m841_vt_select_0_b_1(DELAY,29141)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist13_i_unnamed_c_compmm_m841_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m841_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m841_vt_join(BITJOIN,12913)@115
    assign i_unnamed_c_compmm_m841_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist13_i_unnamed_c_compmm_m841_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_20_c_compmm_m842(ADD,7199)@115
    assign i_add_i_i_i_i_i_i_20_c_compmm_m842_a = {1'b0, i_unnamed_c_compmm_m841_vt_join_q};
    assign i_add_i_i_i_i_i_i_20_c_compmm_m842_b = {1'b0, redist974_i_conv_i_i_i_i_i_20_c_compmm_m838_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_20_c_compmm_m842_o = $unsigned(i_add_i_i_i_i_i_i_20_c_compmm_m842_a) + $unsigned(i_add_i_i_i_i_i_i_20_c_compmm_m842_b);
    assign i_add_i_i_i_i_i_i_20_c_compmm_m842_q = i_add_i_i_i_i_i_i_20_c_compmm_m842_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_20_c_compmm_m842_sel_x(BITSELECT,2213)@115
    assign bgTrunc_i_add_i_i_i_i_i_i_20_c_compmm_m842_sel_x_b = i_add_i_i_i_i_i_i_20_c_compmm_m842_q[15:0];

    // i_conv_i_i_i_i_i_i246_21_c_compmm_m862_sel_x(BITSELECT,3873)@115
    assign i_conv_i_i_i_i_i_i246_21_c_compmm_m862_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_20_c_compmm_m842_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_select_15(BITSELECT,8219)@115
    assign i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_select_15_b = i_conv_i_i_i_i_i_i246_21_c_compmm_m862_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_join(BITJOIN,8218)@115
    assign i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_select_15_b};

    // leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(MUX,26782)@115
    assign leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_join_q or leftShiftStage0Idx1_uid26781_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_21_c_compmm_m862_vt_join_q;
            1'b1 : leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26781_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(MUX,26787)@115
    assign leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s or leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26786_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = leftShiftStage0_uid26783_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26786_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x(MUX,26792)@115
    assign leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s or leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26791_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = leftShiftStage1_uid26788_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26791_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28(BITSELECT,9961)@115
    assign i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28_b = leftShiftStage2_uid26793_i_shl_i_i_i_i_i_i_21_c_compmm_m0_shift_x_q[28:13];

    // redist339_i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28_b_1(DELAY,29467)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist339_i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_join(BITJOIN,9960)@116
    assign i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_join_q = {redist339_i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg213(REG,13508)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg213_q <= $unsigned(redist780_sync_together4364_aunroll_x_in_i_valid_41_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_6462_c_compmm_m214(BLACKBOX,8712)@110
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6462_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_6462_c_compmm_m214 (
        .in_intel_reserved_ffwd_44_0(in_intel_reserved_ffwd_44_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg213_q),
        .out_dest_data_out_44_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_6462_c_compmm_m214_out_dest_data_out_44_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_offset(CONSTANT,30527)
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_offset_q = $unsigned(3'b100);

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt(ADD,30528)
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_a = {1'b0, redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_q};
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_b = {1'b0, redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_o <= $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_a) + $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_b);
        end
    end
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_q = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_o[3:0];

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt(ADD,31848)
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_a = {1'b0, redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_q};
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_o <= $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_a) + $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_b);
        end
    end
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_q = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_o[5:0];

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_inputreg0(DELAY,31843)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_inputreg0_q <= $unsigned(in_c1_eni5_43_tpl);
        end
    end

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr(COUNTER,31846)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_i <= $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_q = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_i[4:0];

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem(DUALMEM,31845)
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_ia = $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_inputreg0_q);
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_aa = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_wraddr_q;
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_ab = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_aa),
        .data_a(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_ab),
        .q_b(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_q = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_iq[15:0];

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_outputreg0(DELAY,31844)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_outputreg0_q <= $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_mem_q);
        end
    end

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_inputreg0(DELAY,30523)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_inputreg0_q <= $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_split_0_outputreg0_q);
        end
    end

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr(COUNTER,30526)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_i <= $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_q = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_i[2:0];

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem(DUALMEM,30525)
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_ia = $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_inputreg0_q);
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_aa = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_wraddr_q;
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_ab = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_aa),
        .data_a(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_ab),
        .q_b(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_q = redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_iq[15:0];

    // redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_outputreg0(DELAY,30524)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_outputreg0_q <= $unsigned(redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_mem_q);
        end
    end

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt(ADD,30534)
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_a = {1'b0, redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_q};
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_b = {1'b0, redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_o <= $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_a) + $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_b);
        end
    end
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_q = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_o[3:0];

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt(ADD,31854)
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_a = {1'b0, redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_q};
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_o <= $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_a) + $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_b);
        end
    end
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_q = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_o[5:0];

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_inputreg0(DELAY,31849)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_inputreg0_q <= $unsigned(in_c1_eni5_44_tpl);
        end
    end

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr(COUNTER,31852)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_i <= $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_q = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_i[4:0];

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem(DUALMEM,31851)
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_ia = $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_inputreg0_q);
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_aa = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_wraddr_q;
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_ab = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_aa),
        .data_a(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_ab),
        .q_b(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_q = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_iq[15:0];

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_outputreg0(DELAY,31850)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_outputreg0_q <= $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_mem_q);
        end
    end

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_inputreg0(DELAY,30529)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_inputreg0_q <= $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_split_0_outputreg0_q);
        end
    end

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr(COUNTER,30532)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_i <= $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_q = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_i[2:0];

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem(DUALMEM,30531)
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_ia = $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_inputreg0_q);
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_aa = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_wraddr_q;
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_ab = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_aa),
        .data_a(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_ab),
        .q_b(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_q = redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_iq[15:0];

    // redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_outputreg0(DELAY,30530)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_outputreg0_q <= $unsigned(redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_mem_q);
        end
    end

    // valid_fanout_reg214(REG,13509)@109 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg214_q <= $unsigned(redist780_sync_together4364_aunroll_x_in_i_valid_41_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_6461_c_compmm_m215(BLACKBOX,8708)@110
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6461_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_6461_c_compmm_m215 (
        .in_intel_reserved_ffwd_43_0(in_intel_reserved_ffwd_43_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg214_q),
        .out_dest_data_out_43_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_6461_c_compmm_m215_out_dest_data_out_43_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28892)@110 + 5
    // out q@116
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_6461_c_compmm_m215_out_dest_data_out_43_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_6462_c_compmm_m214_out_dest_data_out_44_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864(ADD,8987)@116
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod387_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_b = $unsigned({{5{i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_21_c_compmm_m863_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_o[33:0];

    // rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x(MUX,17173)@116
    assign rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q or rightShiftStage0Idx1_uid17172_dupName_85_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q;
            1'b1 : rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17172_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x(MUX,17178)@116
    assign rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17177_dupName_85_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17174_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17177_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x(MUX,17183)@116
    assign rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17182_dupName_85_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17179_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17182_dupName_85_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m865_vt_select_20(BITSELECT,12928)@116
    assign i_unnamed_c_compmm_m865_vt_select_20_b = rightShiftStage2_uid17184_dupName_85_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m865_vt_join(BITJOIN,12927)@116
    assign i_unnamed_c_compmm_m865_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m865_vt_select_20_b};

    // i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x(BITSELECT,3745)@116
    assign i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x_b = i_unnamed_c_compmm_m865_vt_join_q[15:0];

    // redist973_i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x_b_1(DELAY,30101)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist973_i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17193_dupName_86_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17192)@116
    assign rightShiftStage1Idx1Rng8_uid17193_dupName_86_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17195_dupName_86_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17194)@116
    assign rightShiftStage1Idx1_uid17195_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17193_dupName_86_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17188_dupName_86_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17187)@116
    assign rightShiftStage0Idx1Rng4_uid17188_dupName_86_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q[33:4];

    // rightShiftStage0Idx1_uid17190_dupName_86_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17189)@116
    assign rightShiftStage0Idx1_uid17190_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17188_dupName_86_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x(MUX,17191)@116
    assign rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q or rightShiftStage0Idx1_uid17190_dupName_86_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_21_i_c_compmm_m864_q;
            1'b1 : rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17190_dupName_86_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x(MUX,17196)@116
    assign rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17195_dupName_86_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17192_dupName_86_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17195_dupName_86_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m867_vt_select_21(BITSELECT,12931)@116
    assign i_unnamed_c_compmm_m867_vt_select_21_b = rightShiftStage1_uid17197_dupName_86_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m867_vt_join(BITJOIN,12930)@116
    assign i_unnamed_c_compmm_m867_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m867_vt_select_21_b};

    // i_unnamed_c_compmm_m868_sel_x(BITSELECT,6250)@116
    assign i_unnamed_c_compmm_m868_sel_x_b = i_unnamed_c_compmm_m867_vt_join_q[15:0];

    // i_unnamed_c_compmm_m869_BitSelect_for_a(BITSELECT,28852)@116
    assign i_unnamed_c_compmm_m869_BitSelect_for_a_b = i_unnamed_c_compmm_m868_sel_x_b[0:0];

    // i_unnamed_c_compmm_m869_join(BITJOIN,28853)@116
    assign i_unnamed_c_compmm_m869_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m869_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m869_vt_select_0(BITSELECT,12936)@116
    assign i_unnamed_c_compmm_m869_vt_select_0_b = i_unnamed_c_compmm_m869_join_q[0:0];

    // redist11_i_unnamed_c_compmm_m869_vt_select_0_b_1(DELAY,29139)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist11_i_unnamed_c_compmm_m869_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m869_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m869_vt_join(BITJOIN,12935)@117
    assign i_unnamed_c_compmm_m869_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist11_i_unnamed_c_compmm_m869_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_21_c_compmm_m870(ADD,7200)@117
    assign i_add_i_i_i_i_i_i_21_c_compmm_m870_a = {1'b0, i_unnamed_c_compmm_m869_vt_join_q};
    assign i_add_i_i_i_i_i_i_21_c_compmm_m870_b = {1'b0, redist973_i_conv_i_i_i_i_i_21_c_compmm_m866_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_21_c_compmm_m870_o = $unsigned(i_add_i_i_i_i_i_i_21_c_compmm_m870_a) + $unsigned(i_add_i_i_i_i_i_i_21_c_compmm_m870_b);
    assign i_add_i_i_i_i_i_i_21_c_compmm_m870_q = i_add_i_i_i_i_i_i_21_c_compmm_m870_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_21_c_compmm_m870_sel_x(BITSELECT,2214)@117
    assign bgTrunc_i_add_i_i_i_i_i_i_21_c_compmm_m870_sel_x_b = i_add_i_i_i_i_i_i_21_c_compmm_m870_q[15:0];

    // i_conv_i_i_i_i_i_i246_22_c_compmm_m890_sel_x(BITSELECT,3874)@117
    assign i_conv_i_i_i_i_i_i246_22_c_compmm_m890_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_21_c_compmm_m870_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_select_15(BITSELECT,8223)@117
    assign i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_select_15_b = i_conv_i_i_i_i_i_i246_22_c_compmm_m890_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_join(BITJOIN,8222)@117
    assign i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_select_15_b};

    // leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(MUX,26800)@117
    assign leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_join_q or leftShiftStage0Idx1_uid26799_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_22_c_compmm_m890_vt_join_q;
            1'b1 : leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26799_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(MUX,26805)@117
    assign leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s or leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26804_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = leftShiftStage0_uid26801_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26804_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x(MUX,26810)@117
    assign leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s or leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26809_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = leftShiftStage1_uid26806_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26809_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28(BITSELECT,9964)@117
    assign i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28_b = leftShiftStage2_uid26811_i_shl_i_i_i_i_i_i_22_c_compmm_m0_shift_x_q[28:13];

    // redist338_i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28_b_1(DELAY,29466)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist338_i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_join(BITJOIN,9963)@118
    assign i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_join_q = {redist338_i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg211(REG,13506)@111 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg211_q <= $unsigned(redist781_sync_together4364_aunroll_x_in_i_valid_43_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_6464_c_compmm_m212(BLACKBOX,8720)@112
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6464_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_6464_c_compmm_m212 (
        .in_intel_reserved_ffwd_46_0(in_intel_reserved_ffwd_46_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg211_q),
        .out_dest_data_out_46_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_6464_c_compmm_m212_out_dest_data_out_46_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_offset(CONSTANT,30539)
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_offset_q = $unsigned(3'b010);

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt(ADD,30540)
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_a = {1'b0, redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_q};
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_b = {1'b0, redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_o <= $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_a) + $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_b);
        end
    end
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_q = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_o[3:0];

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt(ADD,31860)
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_a = {1'b0, redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_q};
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_o <= $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_a) + $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_b);
        end
    end
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_q = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_o[5:0];

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_inputreg0(DELAY,31855)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_inputreg0_q <= $unsigned(in_c1_eni5_45_tpl);
        end
    end

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr(COUNTER,31858)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_i <= $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_q = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_i[4:0];

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem(DUALMEM,31857)
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_ia = $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_inputreg0_q);
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_aa = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_wraddr_q;
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_ab = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_aa),
        .data_a(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_ab),
        .q_b(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_q = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_iq[15:0];

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_outputreg0(DELAY,31856)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_outputreg0_q <= $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_mem_q);
        end
    end

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_inputreg0(DELAY,30535)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_inputreg0_q <= $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_split_0_outputreg0_q);
        end
    end

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr(COUNTER,30538)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_i <= $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_q = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_i[2:0];

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem(DUALMEM,30537)
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_ia = $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_inputreg0_q);
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_aa = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_wraddr_q;
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_ab = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_aa),
        .data_a(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_ab),
        .q_b(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_q = redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_iq[15:0];

    // redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_outputreg0(DELAY,30536)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_outputreg0_q <= $unsigned(redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_mem_q);
        end
    end

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt(ADD,30546)
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_a = {1'b0, redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_q};
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_b = {1'b0, redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_o <= $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_a) + $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_b);
        end
    end
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_q = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_o[3:0];

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt(ADD,31866)
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_a = {1'b0, redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_q};
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_o <= $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_a) + $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_b);
        end
    end
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_q = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_o[5:0];

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_inputreg0(DELAY,31861)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_inputreg0_q <= $unsigned(in_c1_eni5_46_tpl);
        end
    end

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr(COUNTER,31864)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_i <= $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_q = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_i[4:0];

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem(DUALMEM,31863)
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_ia = $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_inputreg0_q);
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_aa = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_wraddr_q;
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_ab = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_aa),
        .data_a(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_ab),
        .q_b(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_q = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_iq[15:0];

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_outputreg0(DELAY,31862)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_outputreg0_q <= $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_mem_q);
        end
    end

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_inputreg0(DELAY,30541)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_inputreg0_q <= $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_split_0_outputreg0_q);
        end
    end

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr(COUNTER,30544)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_i <= $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_q = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_i[2:0];

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem(DUALMEM,30543)
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_ia = $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_inputreg0_q);
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_aa = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_wraddr_q;
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_ab = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_aa),
        .data_a(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_ab),
        .q_b(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_q = redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_iq[15:0];

    // redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_outputreg0(DELAY,30542)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_outputreg0_q <= $unsigned(redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_mem_q);
        end
    end

    // valid_fanout_reg212(REG,13507)@111 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg212_q <= $unsigned(redist781_sync_together4364_aunroll_x_in_i_valid_43_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_6463_c_compmm_m213(BLACKBOX,8716)@112
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6463_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_6463_c_compmm_m213 (
        .in_intel_reserved_ffwd_45_0(in_intel_reserved_ffwd_45_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg212_q),
        .out_dest_data_out_45_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_6463_c_compmm_m213_out_dest_data_out_45_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28893)@112 + 5
    // out q@118
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_6463_c_compmm_m213_out_dest_data_out_45_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_6464_c_compmm_m212_out_dest_data_out_46_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892(ADD,8988)@118
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod392_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_b = $unsigned({{5{i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_22_c_compmm_m891_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_o[33:0];

    // rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x(MUX,17235)@118
    assign rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q or rightShiftStage0Idx1_uid17234_dupName_89_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q;
            1'b1 : rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17234_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x(MUX,17240)@118
    assign rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17239_dupName_89_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17236_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17239_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x(MUX,17245)@118
    assign rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17244_dupName_89_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17241_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17244_dupName_89_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m893_vt_select_20(BITSELECT,12950)@118
    assign i_unnamed_c_compmm_m893_vt_select_20_b = rightShiftStage2_uid17246_dupName_89_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m893_vt_join(BITJOIN,12949)@118
    assign i_unnamed_c_compmm_m893_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m893_vt_select_20_b};

    // i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x(BITSELECT,3746)@118
    assign i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x_b = i_unnamed_c_compmm_m893_vt_join_q[15:0];

    // redist972_i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x_b_1(DELAY,30100)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist972_i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17255_dupName_90_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17254)@118
    assign rightShiftStage1Idx1Rng8_uid17255_dupName_90_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17257_dupName_90_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17256)@118
    assign rightShiftStage1Idx1_uid17257_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17255_dupName_90_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17250_dupName_90_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17249)@118
    assign rightShiftStage0Idx1Rng4_uid17250_dupName_90_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q[33:4];

    // rightShiftStage0Idx1_uid17252_dupName_90_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17251)@118
    assign rightShiftStage0Idx1_uid17252_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17250_dupName_90_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x(MUX,17253)@118
    assign rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q or rightShiftStage0Idx1_uid17252_dupName_90_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_22_i_c_compmm_m892_q;
            1'b1 : rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17252_dupName_90_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x(MUX,17258)@118
    assign rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17257_dupName_90_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17254_dupName_90_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17257_dupName_90_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m895_vt_select_21(BITSELECT,12953)@118
    assign i_unnamed_c_compmm_m895_vt_select_21_b = rightShiftStage1_uid17259_dupName_90_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m895_vt_join(BITJOIN,12952)@118
    assign i_unnamed_c_compmm_m895_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m895_vt_select_21_b};

    // i_unnamed_c_compmm_m896_sel_x(BITSELECT,6252)@118
    assign i_unnamed_c_compmm_m896_sel_x_b = i_unnamed_c_compmm_m895_vt_join_q[15:0];

    // i_unnamed_c_compmm_m897_BitSelect_for_a(BITSELECT,28856)@118
    assign i_unnamed_c_compmm_m897_BitSelect_for_a_b = i_unnamed_c_compmm_m896_sel_x_b[0:0];

    // i_unnamed_c_compmm_m897_join(BITJOIN,28857)@118
    assign i_unnamed_c_compmm_m897_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m897_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m897_vt_select_0(BITSELECT,12958)@118
    assign i_unnamed_c_compmm_m897_vt_select_0_b = i_unnamed_c_compmm_m897_join_q[0:0];

    // redist9_i_unnamed_c_compmm_m897_vt_select_0_b_1(DELAY,29137)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist9_i_unnamed_c_compmm_m897_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m897_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m897_vt_join(BITJOIN,12957)@119
    assign i_unnamed_c_compmm_m897_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist9_i_unnamed_c_compmm_m897_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_22_c_compmm_m898(ADD,7201)@119
    assign i_add_i_i_i_i_i_i_22_c_compmm_m898_a = {1'b0, i_unnamed_c_compmm_m897_vt_join_q};
    assign i_add_i_i_i_i_i_i_22_c_compmm_m898_b = {1'b0, redist972_i_conv_i_i_i_i_i_22_c_compmm_m894_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_22_c_compmm_m898_o = $unsigned(i_add_i_i_i_i_i_i_22_c_compmm_m898_a) + $unsigned(i_add_i_i_i_i_i_i_22_c_compmm_m898_b);
    assign i_add_i_i_i_i_i_i_22_c_compmm_m898_q = i_add_i_i_i_i_i_i_22_c_compmm_m898_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_22_c_compmm_m898_sel_x(BITSELECT,2215)@119
    assign bgTrunc_i_add_i_i_i_i_i_i_22_c_compmm_m898_sel_x_b = i_add_i_i_i_i_i_i_22_c_compmm_m898_q[15:0];

    // i_conv_i_i_i_i_i_i246_23_c_compmm_m918_sel_x(BITSELECT,3875)@119
    assign i_conv_i_i_i_i_i_i246_23_c_compmm_m918_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_22_c_compmm_m898_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_select_15(BITSELECT,8227)@119
    assign i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_select_15_b = i_conv_i_i_i_i_i_i246_23_c_compmm_m918_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_join(BITJOIN,8226)@119
    assign i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_select_15_b};

    // leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(MUX,26818)@119
    assign leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_join_q or leftShiftStage0Idx1_uid26817_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_23_c_compmm_m918_vt_join_q;
            1'b1 : leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26817_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(MUX,26823)@119
    assign leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s or leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26822_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = leftShiftStage0_uid26819_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26822_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x(MUX,26828)@119
    assign leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s or leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26827_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = leftShiftStage1_uid26824_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26827_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28(BITSELECT,9967)@119
    assign i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28_b = leftShiftStage2_uid26829_i_shl_i_i_i_i_i_i_23_c_compmm_m0_shift_x_q[28:13];

    // redist337_i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28_b_1(DELAY,29465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist337_i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_join(BITJOIN,9966)@120
    assign i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_join_q = {redist337_i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg209(REG,13504)@113 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg209_q <= $unsigned(redist782_sync_together4364_aunroll_x_in_i_valid_45_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_6466_c_compmm_m210(BLACKBOX,8728)@114
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6466_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_6466_c_compmm_m210 (
        .in_intel_reserved_ffwd_48_0(in_intel_reserved_ffwd_48_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg209_q),
        .out_dest_data_out_48_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_6466_c_compmm_m210_out_dest_data_out_48_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_offset(CONSTANT,30551)
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_offset_q = $unsigned(4'b1000);

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt(ADD,30552)
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_a = {1'b0, redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_q};
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_b = {1'b0, redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_o <= $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_a) + $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_b);
        end
    end
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_q = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_o[4:0];

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt(ADD,31872)
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_a = {1'b0, redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_q};
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_o <= $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_a) + $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_b);
        end
    end
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_q = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_o[5:0];

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_inputreg0(DELAY,31867)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_inputreg0_q <= $unsigned(in_c1_eni5_47_tpl);
        end
    end

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr(COUNTER,31870)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_i <= $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_q = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_i[4:0];

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem(DUALMEM,31869)
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_ia = $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_inputreg0_q);
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_aa = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_wraddr_q;
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_ab = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_aa),
        .data_a(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_ab),
        .q_b(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_q = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_iq[15:0];

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_outputreg0(DELAY,31868)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_outputreg0_q <= $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_mem_q);
        end
    end

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_inputreg0(DELAY,30547)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_inputreg0_q <= $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_split_0_outputreg0_q);
        end
    end

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr(COUNTER,30550)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_i <= $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_q = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_i[3:0];

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem(DUALMEM,30549)
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_ia = $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_inputreg0_q);
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_aa = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_wraddr_q;
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_ab = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_aa),
        .data_a(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_ab),
        .q_b(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_q = redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_iq[15:0];

    // redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_outputreg0(DELAY,30548)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_outputreg0_q <= $unsigned(redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_mem_q);
        end
    end

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt(ADD,30558)
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_a = {1'b0, redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_q};
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_b = {1'b0, redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_o <= $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_a) + $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_b);
        end
    end
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_q = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_o[4:0];

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt(ADD,31878)
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_a = {1'b0, redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_q};
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_o <= $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_a) + $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_b);
        end
    end
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_q = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_o[5:0];

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_inputreg0(DELAY,31873)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_inputreg0_q <= $unsigned(in_c1_eni5_48_tpl);
        end
    end

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr(COUNTER,31876)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_i <= $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_q = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_i[4:0];

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem(DUALMEM,31875)
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_ia = $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_inputreg0_q);
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_aa = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_wraddr_q;
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_ab = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_aa),
        .data_a(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_ab),
        .q_b(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_q = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_iq[15:0];

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_outputreg0(DELAY,31874)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_outputreg0_q <= $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_mem_q);
        end
    end

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_inputreg0(DELAY,30553)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_inputreg0_q <= $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_split_0_outputreg0_q);
        end
    end

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr(COUNTER,30556)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_i <= $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_q = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_i[3:0];

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem(DUALMEM,30555)
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_ia = $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_inputreg0_q);
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_aa = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_wraddr_q;
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_ab = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_aa),
        .data_a(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_ab),
        .q_b(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_q = redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_iq[15:0];

    // redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_outputreg0(DELAY,30554)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_outputreg0_q <= $unsigned(redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_mem_q);
        end
    end

    // valid_fanout_reg210(REG,13505)@113 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg210_q <= $unsigned(redist782_sync_together4364_aunroll_x_in_i_valid_45_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_6465_c_compmm_m211(BLACKBOX,8724)@114
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6465_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_6465_c_compmm_m211 (
        .in_intel_reserved_ffwd_47_0(in_intel_reserved_ffwd_47_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg210_q),
        .out_dest_data_out_47_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_6465_c_compmm_m211_out_dest_data_out_47_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28894)@114 + 5
    // out q@120
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_6465_c_compmm_m211_out_dest_data_out_47_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_6466_c_compmm_m210_out_dest_data_out_48_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920(ADD,8989)@120
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod397_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_b = $unsigned({{5{i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_23_c_compmm_m919_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_o[33:0];

    // rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x(MUX,17297)@120
    assign rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q or rightShiftStage0Idx1_uid17296_dupName_93_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q;
            1'b1 : rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17296_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x(MUX,17302)@120
    assign rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17301_dupName_93_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17298_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17301_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x(MUX,17307)@120
    assign rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17306_dupName_93_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17303_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17306_dupName_93_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m921_vt_select_20(BITSELECT,12972)@120
    assign i_unnamed_c_compmm_m921_vt_select_20_b = rightShiftStage2_uid17308_dupName_93_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m921_vt_join(BITJOIN,12971)@120
    assign i_unnamed_c_compmm_m921_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m921_vt_select_20_b};

    // i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x(BITSELECT,3747)@120
    assign i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x_b = i_unnamed_c_compmm_m921_vt_join_q[15:0];

    // redist971_i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x_b_1(DELAY,30099)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist971_i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17317_dupName_94_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17316)@120
    assign rightShiftStage1Idx1Rng8_uid17317_dupName_94_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17319_dupName_94_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17318)@120
    assign rightShiftStage1Idx1_uid17319_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17317_dupName_94_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17312_dupName_94_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17311)@120
    assign rightShiftStage0Idx1Rng4_uid17312_dupName_94_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q[33:4];

    // rightShiftStage0Idx1_uid17314_dupName_94_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17313)@120
    assign rightShiftStage0Idx1_uid17314_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17312_dupName_94_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x(MUX,17315)@120
    assign rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q or rightShiftStage0Idx1_uid17314_dupName_94_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_23_i_c_compmm_m920_q;
            1'b1 : rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17314_dupName_94_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x(MUX,17320)@120
    assign rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17319_dupName_94_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17316_dupName_94_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17319_dupName_94_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m923_vt_select_21(BITSELECT,12975)@120
    assign i_unnamed_c_compmm_m923_vt_select_21_b = rightShiftStage1_uid17321_dupName_94_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m923_vt_join(BITJOIN,12974)@120
    assign i_unnamed_c_compmm_m923_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m923_vt_select_21_b};

    // i_unnamed_c_compmm_m924_sel_x(BITSELECT,6254)@120
    assign i_unnamed_c_compmm_m924_sel_x_b = i_unnamed_c_compmm_m923_vt_join_q[15:0];

    // i_unnamed_c_compmm_m925_BitSelect_for_a(BITSELECT,28860)@120
    assign i_unnamed_c_compmm_m925_BitSelect_for_a_b = i_unnamed_c_compmm_m924_sel_x_b[0:0];

    // i_unnamed_c_compmm_m925_join(BITJOIN,28861)@120
    assign i_unnamed_c_compmm_m925_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m925_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m925_vt_select_0(BITSELECT,12980)@120
    assign i_unnamed_c_compmm_m925_vt_select_0_b = i_unnamed_c_compmm_m925_join_q[0:0];

    // redist7_i_unnamed_c_compmm_m925_vt_select_0_b_1(DELAY,29135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist7_i_unnamed_c_compmm_m925_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m925_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m925_vt_join(BITJOIN,12979)@121
    assign i_unnamed_c_compmm_m925_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist7_i_unnamed_c_compmm_m925_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_23_c_compmm_m926(ADD,7202)@121
    assign i_add_i_i_i_i_i_i_23_c_compmm_m926_a = {1'b0, i_unnamed_c_compmm_m925_vt_join_q};
    assign i_add_i_i_i_i_i_i_23_c_compmm_m926_b = {1'b0, redist971_i_conv_i_i_i_i_i_23_c_compmm_m922_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_23_c_compmm_m926_o = $unsigned(i_add_i_i_i_i_i_i_23_c_compmm_m926_a) + $unsigned(i_add_i_i_i_i_i_i_23_c_compmm_m926_b);
    assign i_add_i_i_i_i_i_i_23_c_compmm_m926_q = i_add_i_i_i_i_i_i_23_c_compmm_m926_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_23_c_compmm_m926_sel_x(BITSELECT,2216)@121
    assign bgTrunc_i_add_i_i_i_i_i_i_23_c_compmm_m926_sel_x_b = i_add_i_i_i_i_i_i_23_c_compmm_m926_q[15:0];

    // i_conv_i_i_i_i_i_i246_24_c_compmm_m946_sel_x(BITSELECT,3876)@121
    assign i_conv_i_i_i_i_i_i246_24_c_compmm_m946_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_23_c_compmm_m926_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_select_15(BITSELECT,8231)@121
    assign i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_select_15_b = i_conv_i_i_i_i_i_i246_24_c_compmm_m946_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_join(BITJOIN,8230)@121
    assign i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_select_15_b};

    // leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(MUX,26836)@121
    assign leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_join_q or leftShiftStage0Idx1_uid26835_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_24_c_compmm_m946_vt_join_q;
            1'b1 : leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26835_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(MUX,26841)@121
    assign leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s or leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26840_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = leftShiftStage0_uid26837_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26840_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x(MUX,26846)@121
    assign leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s or leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26845_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = leftShiftStage1_uid26842_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26845_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28(BITSELECT,9970)@121
    assign i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28_b = leftShiftStage2_uid26847_i_shl_i_i_i_i_i_i_24_c_compmm_m0_shift_x_q[28:13];

    // redist336_i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28_b_1(DELAY,29464)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist336_i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_join(BITJOIN,9969)@122
    assign i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_join_q = {redist336_i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg207(REG,13502)@115 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg207_q <= $unsigned(redist783_sync_together4364_aunroll_x_in_i_valid_47_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_6468_c_compmm_m208(BLACKBOX,8736)@116
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6468_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_6468_c_compmm_m208 (
        .in_intel_reserved_ffwd_50_0(in_intel_reserved_ffwd_50_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg207_q),
        .out_dest_data_out_50_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_6468_c_compmm_m208_out_dest_data_out_50_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_offset(CONSTANT,30563)
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_offset_q = $unsigned(4'b0110);

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt(ADD,30564)
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_a = {1'b0, redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_q};
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_b = {1'b0, redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_o <= $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_a) + $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_b);
        end
    end
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_q = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_o[4:0];

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt(ADD,31884)
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_a = {1'b0, redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_q};
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_o <= $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_a) + $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_b);
        end
    end
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_q = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_o[5:0];

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_inputreg0(DELAY,31879)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_inputreg0_q <= $unsigned(in_c1_eni5_49_tpl);
        end
    end

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr(COUNTER,31882)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_i <= $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_q = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_i[4:0];

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem(DUALMEM,31881)
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_ia = $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_inputreg0_q);
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_aa = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_wraddr_q;
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_ab = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_aa),
        .data_a(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_ab),
        .q_b(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_q = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_iq[15:0];

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_outputreg0(DELAY,31880)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_outputreg0_q <= $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_mem_q);
        end
    end

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_inputreg0(DELAY,30559)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_inputreg0_q <= $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_split_0_outputreg0_q);
        end
    end

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr(COUNTER,30562)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_i <= $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_q = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_i[3:0];

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem(DUALMEM,30561)
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_ia = $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_inputreg0_q);
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_aa = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_wraddr_q;
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_ab = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_aa),
        .data_a(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_ab),
        .q_b(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_q = redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_iq[15:0];

    // redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_outputreg0(DELAY,30560)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_outputreg0_q <= $unsigned(redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_mem_q);
        end
    end

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt(ADD,30570)
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_a = {1'b0, redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_q};
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_b = {1'b0, redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_o <= $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_a) + $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_b);
        end
    end
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_q = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_o[4:0];

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt(ADD,31890)
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_a = {1'b0, redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_q};
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_o <= $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_a) + $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_b);
        end
    end
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_q = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_o[5:0];

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_inputreg0(DELAY,31885)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_inputreg0_q <= $unsigned(in_c1_eni5_50_tpl);
        end
    end

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr(COUNTER,31888)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_i <= $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_q = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_i[4:0];

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem(DUALMEM,31887)
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_ia = $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_inputreg0_q);
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_aa = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_wraddr_q;
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_ab = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_aa),
        .data_a(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_ab),
        .q_b(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_q = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_iq[15:0];

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_outputreg0(DELAY,31886)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_outputreg0_q <= $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_mem_q);
        end
    end

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_inputreg0(DELAY,30565)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_inputreg0_q <= $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_split_0_outputreg0_q);
        end
    end

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr(COUNTER,30568)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_i <= $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_q = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_i[3:0];

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem(DUALMEM,30567)
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_ia = $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_inputreg0_q);
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_aa = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_wraddr_q;
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_ab = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_aa),
        .data_a(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_ab),
        .q_b(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_q = redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_iq[15:0];

    // redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_outputreg0(DELAY,30566)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_outputreg0_q <= $unsigned(redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_mem_q);
        end
    end

    // valid_fanout_reg208(REG,13503)@115 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg208_q <= $unsigned(redist783_sync_together4364_aunroll_x_in_i_valid_47_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_6467_c_compmm_m209(BLACKBOX,8732)@116
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6467_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_6467_c_compmm_m209 (
        .in_intel_reserved_ffwd_49_0(in_intel_reserved_ffwd_49_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg208_q),
        .out_dest_data_out_49_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_6467_c_compmm_m209_out_dest_data_out_49_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28895)@116 + 5
    // out q@122
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_6467_c_compmm_m209_out_dest_data_out_49_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_6468_c_compmm_m208_out_dest_data_out_50_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948(ADD,8990)@122
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod402_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_b = $unsigned({{5{i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_24_c_compmm_m947_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_o[33:0];

    // rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x(MUX,17359)@122
    assign rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q or rightShiftStage0Idx1_uid17358_dupName_97_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q;
            1'b1 : rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17358_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x(MUX,17364)@122
    assign rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17363_dupName_97_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17360_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17363_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x(MUX,17369)@122
    assign rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17368_dupName_97_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17365_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17368_dupName_97_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m949_vt_select_20(BITSELECT,12994)@122
    assign i_unnamed_c_compmm_m949_vt_select_20_b = rightShiftStage2_uid17370_dupName_97_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m949_vt_join(BITJOIN,12993)@122
    assign i_unnamed_c_compmm_m949_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m949_vt_select_20_b};

    // i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x(BITSELECT,3748)@122
    assign i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x_b = i_unnamed_c_compmm_m949_vt_join_q[15:0];

    // redist970_i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x_b_1(DELAY,30098)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist970_i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17379_dupName_98_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17378)@122
    assign rightShiftStage1Idx1Rng8_uid17379_dupName_98_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17381_dupName_98_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17380)@122
    assign rightShiftStage1Idx1_uid17381_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17379_dupName_98_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17374_dupName_98_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17373)@122
    assign rightShiftStage0Idx1Rng4_uid17374_dupName_98_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q[33:4];

    // rightShiftStage0Idx1_uid17376_dupName_98_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17375)@122
    assign rightShiftStage0Idx1_uid17376_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17374_dupName_98_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x(MUX,17377)@122
    assign rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q or rightShiftStage0Idx1_uid17376_dupName_98_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_24_i_c_compmm_m948_q;
            1'b1 : rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17376_dupName_98_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x(MUX,17382)@122
    assign rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17381_dupName_98_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17378_dupName_98_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17381_dupName_98_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m951_vt_select_21(BITSELECT,12997)@122
    assign i_unnamed_c_compmm_m951_vt_select_21_b = rightShiftStage1_uid17383_dupName_98_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m951_vt_join(BITJOIN,12996)@122
    assign i_unnamed_c_compmm_m951_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m951_vt_select_21_b};

    // i_unnamed_c_compmm_m952_sel_x(BITSELECT,6256)@122
    assign i_unnamed_c_compmm_m952_sel_x_b = i_unnamed_c_compmm_m951_vt_join_q[15:0];

    // i_unnamed_c_compmm_m953_BitSelect_for_a(BITSELECT,28864)@122
    assign i_unnamed_c_compmm_m953_BitSelect_for_a_b = i_unnamed_c_compmm_m952_sel_x_b[0:0];

    // i_unnamed_c_compmm_m953_join(BITJOIN,28865)@122
    assign i_unnamed_c_compmm_m953_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m953_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m953_vt_select_0(BITSELECT,13002)@122
    assign i_unnamed_c_compmm_m953_vt_select_0_b = i_unnamed_c_compmm_m953_join_q[0:0];

    // redist5_i_unnamed_c_compmm_m953_vt_select_0_b_1(DELAY,29133)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist5_i_unnamed_c_compmm_m953_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m953_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m953_vt_join(BITJOIN,13001)@123
    assign i_unnamed_c_compmm_m953_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist5_i_unnamed_c_compmm_m953_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_24_c_compmm_m954(ADD,7203)@123
    assign i_add_i_i_i_i_i_i_24_c_compmm_m954_a = {1'b0, i_unnamed_c_compmm_m953_vt_join_q};
    assign i_add_i_i_i_i_i_i_24_c_compmm_m954_b = {1'b0, redist970_i_conv_i_i_i_i_i_24_c_compmm_m950_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_24_c_compmm_m954_o = $unsigned(i_add_i_i_i_i_i_i_24_c_compmm_m954_a) + $unsigned(i_add_i_i_i_i_i_i_24_c_compmm_m954_b);
    assign i_add_i_i_i_i_i_i_24_c_compmm_m954_q = i_add_i_i_i_i_i_i_24_c_compmm_m954_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_24_c_compmm_m954_sel_x(BITSELECT,2217)@123
    assign bgTrunc_i_add_i_i_i_i_i_i_24_c_compmm_m954_sel_x_b = i_add_i_i_i_i_i_i_24_c_compmm_m954_q[15:0];

    // i_conv_i_i_i_i_i_i246_25_c_compmm_m974_sel_x(BITSELECT,3877)@123
    assign i_conv_i_i_i_i_i_i246_25_c_compmm_m974_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_24_c_compmm_m954_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_select_15(BITSELECT,8235)@123
    assign i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_select_15_b = i_conv_i_i_i_i_i_i246_25_c_compmm_m974_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_join(BITJOIN,8234)@123
    assign i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_select_15_b};

    // leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(MUX,26854)@123
    assign leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_join_q or leftShiftStage0Idx1_uid26853_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_25_c_compmm_m974_vt_join_q;
            1'b1 : leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26853_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(MUX,26859)@123
    assign leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s or leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26858_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = leftShiftStage0_uid26855_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26858_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x(MUX,26864)@123
    assign leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s or leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26863_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = leftShiftStage1_uid26860_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26863_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28(BITSELECT,9973)@123
    assign i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28_b = leftShiftStage2_uid26865_i_shl_i_i_i_i_i_i_25_c_compmm_m0_shift_x_q[28:13];

    // redist335_i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28_b_1(DELAY,29463)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist335_i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_join(BITJOIN,9972)@124
    assign i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_join_q = {redist335_i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg205(REG,13500)@117 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg205_q <= $unsigned(redist784_sync_together4364_aunroll_x_in_i_valid_49_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_6470_c_compmm_m206(BLACKBOX,8748)@118
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6470_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_6470_c_compmm_m206 (
        .in_intel_reserved_ffwd_52_0(in_intel_reserved_ffwd_52_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg205_q),
        .out_dest_data_out_52_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_6470_c_compmm_m206_out_dest_data_out_52_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_offset(CONSTANT,30575)
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_offset_q = $unsigned(4'b0100);

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt(ADD,30576)
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_a = {1'b0, redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_q};
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_b = {1'b0, redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_o <= $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_a) + $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_b);
        end
    end
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_q = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_o[4:0];

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt(ADD,31896)
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_a = {1'b0, redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_q};
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_o <= $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_a) + $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_b);
        end
    end
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_q = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_o[5:0];

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_inputreg0(DELAY,31891)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_inputreg0_q <= $unsigned(in_c1_eni5_51_tpl);
        end
    end

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr(COUNTER,31894)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_i <= $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_q = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_i[4:0];

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem(DUALMEM,31893)
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_ia = $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_inputreg0_q);
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_aa = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_wraddr_q;
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_ab = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_aa),
        .data_a(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_ab),
        .q_b(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_q = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_iq[15:0];

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_outputreg0(DELAY,31892)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_outputreg0_q <= $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_mem_q);
        end
    end

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_inputreg0(DELAY,30571)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_inputreg0_q <= $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_split_0_outputreg0_q);
        end
    end

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr(COUNTER,30574)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_i <= $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_q = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_i[3:0];

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem(DUALMEM,30573)
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_ia = $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_inputreg0_q);
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_aa = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_wraddr_q;
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_ab = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_aa),
        .data_a(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_ab),
        .q_b(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_q = redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_iq[15:0];

    // redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_outputreg0(DELAY,30572)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_outputreg0_q <= $unsigned(redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_mem_q);
        end
    end

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt(ADD,30582)
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_a = {1'b0, redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_q};
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_b = {1'b0, redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_o <= $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_a) + $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_b);
        end
    end
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_q = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_o[4:0];

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt(ADD,31902)
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_a = {1'b0, redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_q};
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_o <= $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_a) + $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_b);
        end
    end
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_q = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_o[5:0];

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_inputreg0(DELAY,31897)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_inputreg0_q <= $unsigned(in_c1_eni5_52_tpl);
        end
    end

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr(COUNTER,31900)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_i <= $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_q = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_i[4:0];

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem(DUALMEM,31899)
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_ia = $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_inputreg0_q);
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_aa = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_wraddr_q;
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_ab = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_aa),
        .data_a(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_ab),
        .q_b(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_q = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_iq[15:0];

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_outputreg0(DELAY,31898)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_outputreg0_q <= $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_mem_q);
        end
    end

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_inputreg0(DELAY,30577)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_inputreg0_q <= $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_split_0_outputreg0_q);
        end
    end

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr(COUNTER,30580)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_i <= $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_q = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_i[3:0];

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem(DUALMEM,30579)
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_ia = $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_inputreg0_q);
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_aa = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_wraddr_q;
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_ab = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_aa),
        .data_a(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_ab),
        .q_b(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_q = redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_iq[15:0];

    // redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_outputreg0(DELAY,30578)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_outputreg0_q <= $unsigned(redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_mem_q);
        end
    end

    // valid_fanout_reg206(REG,13501)@117 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg206_q <= $unsigned(redist784_sync_together4364_aunroll_x_in_i_valid_49_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_6469_c_compmm_m207(BLACKBOX,8744)@118
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6469_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_6469_c_compmm_m207 (
        .in_intel_reserved_ffwd_51_0(in_intel_reserved_ffwd_51_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg206_q),
        .out_dest_data_out_51_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_6469_c_compmm_m207_out_dest_data_out_51_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28896)@118 + 5
    // out q@124
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_6469_c_compmm_m207_out_dest_data_out_51_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_6470_c_compmm_m206_out_dest_data_out_52_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976(ADD,8991)@124
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod407_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_b = $unsigned({{5{i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_25_c_compmm_m975_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_o[33:0];

    // rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x(MUX,17421)@124
    assign rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q or rightShiftStage0Idx1_uid17420_dupName_101_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q;
            1'b1 : rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17420_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x(MUX,17426)@124
    assign rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17425_dupName_101_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17422_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17425_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x(MUX,17431)@124
    assign rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17430_dupName_101_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17427_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17430_dupName_101_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m977_vt_select_20(BITSELECT,13016)@124
    assign i_unnamed_c_compmm_m977_vt_select_20_b = rightShiftStage2_uid17432_dupName_101_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m977_vt_join(BITJOIN,13015)@124
    assign i_unnamed_c_compmm_m977_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m977_vt_select_20_b};

    // i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x(BITSELECT,3749)@124
    assign i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x_b = i_unnamed_c_compmm_m977_vt_join_q[15:0];

    // redist969_i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x_b_1(DELAY,30097)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist969_i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17441_dupName_102_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17440)@124
    assign rightShiftStage1Idx1Rng8_uid17441_dupName_102_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17443_dupName_102_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17442)@124
    assign rightShiftStage1Idx1_uid17443_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17441_dupName_102_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17436_dupName_102_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17435)@124
    assign rightShiftStage0Idx1Rng4_uid17436_dupName_102_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q[33:4];

    // rightShiftStage0Idx1_uid17438_dupName_102_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17437)@124
    assign rightShiftStage0Idx1_uid17438_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17436_dupName_102_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x(MUX,17439)@124
    assign rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q or rightShiftStage0Idx1_uid17438_dupName_102_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_25_i_c_compmm_m976_q;
            1'b1 : rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17438_dupName_102_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x(MUX,17444)@124
    assign rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17443_dupName_102_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17440_dupName_102_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17443_dupName_102_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m979_vt_select_21(BITSELECT,13019)@124
    assign i_unnamed_c_compmm_m979_vt_select_21_b = rightShiftStage1_uid17445_dupName_102_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m979_vt_join(BITJOIN,13018)@124
    assign i_unnamed_c_compmm_m979_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m979_vt_select_21_b};

    // i_unnamed_c_compmm_m980_sel_x(BITSELECT,6258)@124
    assign i_unnamed_c_compmm_m980_sel_x_b = i_unnamed_c_compmm_m979_vt_join_q[15:0];

    // i_unnamed_c_compmm_m981_BitSelect_for_a(BITSELECT,28868)@124
    assign i_unnamed_c_compmm_m981_BitSelect_for_a_b = i_unnamed_c_compmm_m980_sel_x_b[0:0];

    // i_unnamed_c_compmm_m981_join(BITJOIN,28869)@124
    assign i_unnamed_c_compmm_m981_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m981_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m981_vt_select_0(BITSELECT,13024)@124
    assign i_unnamed_c_compmm_m981_vt_select_0_b = i_unnamed_c_compmm_m981_join_q[0:0];

    // redist3_i_unnamed_c_compmm_m981_vt_select_0_b_1(DELAY,29131)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist3_i_unnamed_c_compmm_m981_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m981_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m981_vt_join(BITJOIN,13023)@125
    assign i_unnamed_c_compmm_m981_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist3_i_unnamed_c_compmm_m981_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_25_c_compmm_m982(ADD,7204)@125
    assign i_add_i_i_i_i_i_i_25_c_compmm_m982_a = {1'b0, i_unnamed_c_compmm_m981_vt_join_q};
    assign i_add_i_i_i_i_i_i_25_c_compmm_m982_b = {1'b0, redist969_i_conv_i_i_i_i_i_25_c_compmm_m978_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_25_c_compmm_m982_o = $unsigned(i_add_i_i_i_i_i_i_25_c_compmm_m982_a) + $unsigned(i_add_i_i_i_i_i_i_25_c_compmm_m982_b);
    assign i_add_i_i_i_i_i_i_25_c_compmm_m982_q = i_add_i_i_i_i_i_i_25_c_compmm_m982_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_25_c_compmm_m982_sel_x(BITSELECT,2218)@125
    assign bgTrunc_i_add_i_i_i_i_i_i_25_c_compmm_m982_sel_x_b = i_add_i_i_i_i_i_i_25_c_compmm_m982_q[15:0];

    // i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_sel_x(BITSELECT,3878)@125
    assign i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_25_c_compmm_m982_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_select_15(BITSELECT,8239)@125
    assign i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_select_15_b = i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_join(BITJOIN,8238)@125
    assign i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_select_15_b};

    // leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(MUX,26872)@125
    assign leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_join_q or leftShiftStage0Idx1_uid26871_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_26_c_compmm_m1002_vt_join_q;
            1'b1 : leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26871_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(MUX,26877)@125
    assign leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s or leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26876_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = leftShiftStage0_uid26873_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26876_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x(MUX,26882)@125
    assign leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s or leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26881_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = leftShiftStage1_uid26878_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26881_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28(BITSELECT,9976)@125
    assign i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28_b = leftShiftStage2_uid26883_i_shl_i_i_i_i_i_i_26_c_compmm_m0_shift_x_q[28:13];

    // redist334_i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28_b_1(DELAY,29462)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist334_i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_join(BITJOIN,9975)@126
    assign i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_join_q = {redist334_i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg203(REG,13498)@119 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg203_q <= $unsigned(redist785_sync_together4364_aunroll_x_in_i_valid_51_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_6472_c_compmm_m204(BLACKBOX,8756)@120
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6472_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_6472_c_compmm_m204 (
        .in_intel_reserved_ffwd_54_0(in_intel_reserved_ffwd_54_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg203_q),
        .out_dest_data_out_54_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_6472_c_compmm_m204_out_dest_data_out_54_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_offset(CONSTANT,30587)
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_offset_q = $unsigned(4'b0010);

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt(ADD,30588)
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_a = {1'b0, redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_q};
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_b = {1'b0, redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_o <= $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_a) + $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_b);
        end
    end
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_q = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_o[4:0];

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt(ADD,31908)
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_a = {1'b0, redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_q};
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_o <= $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_a) + $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_b);
        end
    end
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_q = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_o[5:0];

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_inputreg0(DELAY,31903)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_inputreg0_q <= $unsigned(in_c1_eni5_53_tpl);
        end
    end

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr(COUNTER,31906)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_i <= $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_q = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_i[4:0];

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem(DUALMEM,31905)
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_ia = $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_inputreg0_q);
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_aa = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_wraddr_q;
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_ab = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_aa),
        .data_a(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_ab),
        .q_b(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_q = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_iq[15:0];

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_outputreg0(DELAY,31904)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_outputreg0_q <= $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_mem_q);
        end
    end

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_inputreg0(DELAY,30583)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_inputreg0_q <= $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_split_0_outputreg0_q);
        end
    end

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr(COUNTER,30586)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_i <= $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_q = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_i[3:0];

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem(DUALMEM,30585)
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_ia = $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_inputreg0_q);
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_aa = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_wraddr_q;
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_ab = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_aa),
        .data_a(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_ab),
        .q_b(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_q = redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_iq[15:0];

    // redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_outputreg0(DELAY,30584)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_outputreg0_q <= $unsigned(redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_mem_q);
        end
    end

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt(ADD,30594)
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_a = {1'b0, redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_q};
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_b = {1'b0, redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_o <= $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_a) + $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_b);
        end
    end
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_q = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_o[4:0];

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt(ADD,31914)
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_a = {1'b0, redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_q};
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_o <= $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_a) + $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_b);
        end
    end
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_q = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_o[5:0];

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_inputreg0(DELAY,31909)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_inputreg0_q <= $unsigned(in_c1_eni5_54_tpl);
        end
    end

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr(COUNTER,31912)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_i <= $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_q = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_i[4:0];

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem(DUALMEM,31911)
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_ia = $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_inputreg0_q);
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_aa = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_wraddr_q;
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_ab = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_aa),
        .data_a(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_ab),
        .q_b(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_q = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_iq[15:0];

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_outputreg0(DELAY,31910)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_outputreg0_q <= $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_mem_q);
        end
    end

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_inputreg0(DELAY,30589)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_inputreg0_q <= $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_split_0_outputreg0_q);
        end
    end

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr(COUNTER,30592)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_i <= $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_q = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_i[3:0];

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem(DUALMEM,30591)
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_ia = $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_inputreg0_q);
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_aa = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_wraddr_q;
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_ab = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_aa),
        .data_a(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_ab),
        .q_b(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_q = redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_iq[15:0];

    // redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_outputreg0(DELAY,30590)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_outputreg0_q <= $unsigned(redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_mem_q);
        end
    end

    // valid_fanout_reg204(REG,13499)@119 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg204_q <= $unsigned(redist785_sync_together4364_aunroll_x_in_i_valid_51_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_6471_c_compmm_m205(BLACKBOX,8752)@120
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6471_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_6471_c_compmm_m205 (
        .in_intel_reserved_ffwd_53_0(in_intel_reserved_ffwd_53_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg204_q),
        .out_dest_data_out_53_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_6471_c_compmm_m205_out_dest_data_out_53_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28897)@120 + 5
    // out q@126
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_6471_c_compmm_m205_out_dest_data_out_53_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_6472_c_compmm_m204_out_dest_data_out_54_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004(ADD,8992)@126
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod412_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_b = $unsigned({{5{i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_26_c_compmm_m1003_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_o[33:0];

    // rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x(MUX,17483)@126
    assign rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q or rightShiftStage0Idx1_uid17482_dupName_105_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q;
            1'b1 : rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17482_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x(MUX,17488)@126
    assign rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17487_dupName_105_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17484_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17487_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x(MUX,17493)@126
    assign rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17492_dupName_105_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17489_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17492_dupName_105_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1005_vt_select_20(BITSELECT,10222)@126
    assign i_unnamed_c_compmm_m1005_vt_select_20_b = rightShiftStage2_uid17494_dupName_105_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1005_vt_join(BITJOIN,10221)@126
    assign i_unnamed_c_compmm_m1005_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1005_vt_select_20_b};

    // i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x(BITSELECT,3750)@126
    assign i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x_b = i_unnamed_c_compmm_m1005_vt_join_q[15:0];

    // redist968_i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x_b_1(DELAY,30096)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist968_i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17503_dupName_106_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17502)@126
    assign rightShiftStage1Idx1Rng8_uid17503_dupName_106_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17505_dupName_106_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17504)@126
    assign rightShiftStage1Idx1_uid17505_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17503_dupName_106_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17498_dupName_106_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17497)@126
    assign rightShiftStage0Idx1Rng4_uid17498_dupName_106_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q[33:4];

    // rightShiftStage0Idx1_uid17500_dupName_106_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17499)@126
    assign rightShiftStage0Idx1_uid17500_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17498_dupName_106_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x(MUX,17501)@126
    assign rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q or rightShiftStage0Idx1_uid17500_dupName_106_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_26_i_c_compmm_m1004_q;
            1'b1 : rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17500_dupName_106_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x(MUX,17506)@126
    assign rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17505_dupName_106_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17502_dupName_106_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17505_dupName_106_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1007_vt_select_21(BITSELECT,10225)@126
    assign i_unnamed_c_compmm_m1007_vt_select_21_b = rightShiftStage1_uid17507_dupName_106_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1007_vt_join(BITJOIN,10224)@126
    assign i_unnamed_c_compmm_m1007_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1007_vt_select_21_b};

    // i_unnamed_c_compmm_m1008_sel_x(BITSELECT,6004)@126
    assign i_unnamed_c_compmm_m1008_sel_x_b = i_unnamed_c_compmm_m1007_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1009_BitSelect_for_a(BITSELECT,28360)@126
    assign i_unnamed_c_compmm_m1009_BitSelect_for_a_b = i_unnamed_c_compmm_m1008_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1009_join(BITJOIN,28361)@126
    assign i_unnamed_c_compmm_m1009_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1009_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1009_vt_select_0(BITSELECT,10230)@126
    assign i_unnamed_c_compmm_m1009_vt_select_0_b = i_unnamed_c_compmm_m1009_join_q[0:0];

    // redist254_i_unnamed_c_compmm_m1009_vt_select_0_b_1(DELAY,29382)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist254_i_unnamed_c_compmm_m1009_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1009_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1009_vt_join(BITJOIN,10229)@127
    assign i_unnamed_c_compmm_m1009_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist254_i_unnamed_c_compmm_m1009_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_26_c_compmm_m1010(ADD,7205)@127
    assign i_add_i_i_i_i_i_i_26_c_compmm_m1010_a = {1'b0, i_unnamed_c_compmm_m1009_vt_join_q};
    assign i_add_i_i_i_i_i_i_26_c_compmm_m1010_b = {1'b0, redist968_i_conv_i_i_i_i_i_26_c_compmm_m1006_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_26_c_compmm_m1010_o = $unsigned(i_add_i_i_i_i_i_i_26_c_compmm_m1010_a) + $unsigned(i_add_i_i_i_i_i_i_26_c_compmm_m1010_b);
    assign i_add_i_i_i_i_i_i_26_c_compmm_m1010_q = i_add_i_i_i_i_i_i_26_c_compmm_m1010_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_26_c_compmm_m1010_sel_x(BITSELECT,2219)@127
    assign bgTrunc_i_add_i_i_i_i_i_i_26_c_compmm_m1010_sel_x_b = i_add_i_i_i_i_i_i_26_c_compmm_m1010_q[15:0];

    // i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_sel_x(BITSELECT,3879)@127
    assign i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_26_c_compmm_m1010_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_select_15(BITSELECT,8243)@127
    assign i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_select_15_b = i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_join(BITJOIN,8242)@127
    assign i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_select_15_b};

    // leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(MUX,26890)@127
    assign leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_join_q or leftShiftStage0Idx1_uid26889_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_27_c_compmm_m1030_vt_join_q;
            1'b1 : leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26889_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(MUX,26895)@127
    assign leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s or leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26894_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = leftShiftStage0_uid26891_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26894_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x(MUX,26900)@127
    assign leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s or leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26899_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = leftShiftStage1_uid26896_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26899_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28(BITSELECT,9979)@127
    assign i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28_b = leftShiftStage2_uid26901_i_shl_i_i_i_i_i_i_27_c_compmm_m0_shift_x_q[28:13];

    // redist333_i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28_b_1(DELAY,29461)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist333_i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_join(BITJOIN,9978)@128
    assign i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_join_q = {redist333_i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg201(REG,13496)@121 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg201_q <= $unsigned(redist786_sync_together4364_aunroll_x_in_i_valid_53_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_6474_c_compmm_m202(BLACKBOX,8764)@122
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6474_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_6474_c_compmm_m202 (
        .in_intel_reserved_ffwd_56_0(in_intel_reserved_ffwd_56_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg201_q),
        .out_dest_data_out_56_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_6474_c_compmm_m202_out_dest_data_out_56_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_offset(CONSTANT,30599)
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_offset_q = $unsigned(5'b10000);

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt(ADD,30600)
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_a = {1'b0, redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_q};
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_b = {1'b0, redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_o <= $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_a) + $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_b);
        end
    end
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_q = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_o[5:0];

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt(ADD,31920)
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_a = {1'b0, redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_q};
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_o <= $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_a) + $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_b);
        end
    end
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_q = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_o[5:0];

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_inputreg0(DELAY,31915)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_inputreg0_q <= $unsigned(in_c1_eni5_55_tpl);
        end
    end

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem(DUALMEM,31917)
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_ia = $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_inputreg0_q);
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_aa = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_q;
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_ab = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_aa),
        .data_a(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_ab),
        .q_b(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_q = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_iq[15:0];

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_outputreg0(DELAY,31916)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_outputreg0_q <= $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_mem_q);
        end
    end

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_inputreg0(DELAY,30595)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_inputreg0_q <= $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_split_0_outputreg0_q);
        end
    end

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr(COUNTER,30598)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_i <= $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_q = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_i[4:0];

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem(DUALMEM,30597)
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_ia = $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_inputreg0_q);
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_aa = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_wraddr_q;
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_ab = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_aa),
        .data_a(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_ab),
        .q_b(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_q = redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_iq[15:0];

    // redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_outputreg0(DELAY,30596)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_outputreg0_q <= $unsigned(redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_mem_q);
        end
    end

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt(ADD,30606)
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_a = {1'b0, redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_q};
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_b = {1'b0, redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_o <= $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_a) + $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_b);
        end
    end
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_q = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_o[5:0];

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt(ADD,31926)
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_a = {1'b0, redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_q};
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_o <= $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_a) + $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_b);
        end
    end
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_q = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_o[5:0];

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_inputreg0(DELAY,31921)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_inputreg0_q <= $unsigned(in_c1_eni5_56_tpl);
        end
    end

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem(DUALMEM,31923)
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_ia = $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_inputreg0_q);
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_aa = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_q;
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_ab = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_aa),
        .data_a(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_ab),
        .q_b(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_q = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_iq[15:0];

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_outputreg0(DELAY,31922)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_outputreg0_q <= $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_mem_q);
        end
    end

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_inputreg0(DELAY,30601)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_inputreg0_q <= $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_split_0_outputreg0_q);
        end
    end

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr(COUNTER,30604)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_i <= $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_q = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_i[4:0];

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem(DUALMEM,30603)
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_ia = $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_inputreg0_q);
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_aa = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_wraddr_q;
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_ab = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_aa),
        .data_a(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_ab),
        .q_b(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_q = redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_iq[15:0];

    // redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_outputreg0(DELAY,30602)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_outputreg0_q <= $unsigned(redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_mem_q);
        end
    end

    // valid_fanout_reg202(REG,13497)@121 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg202_q <= $unsigned(redist786_sync_together4364_aunroll_x_in_i_valid_53_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_6473_c_compmm_m203(BLACKBOX,8760)@122
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6473_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_6473_c_compmm_m203 (
        .in_intel_reserved_ffwd_55_0(in_intel_reserved_ffwd_55_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg202_q),
        .out_dest_data_out_55_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_6473_c_compmm_m203_out_dest_data_out_55_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28898)@122 + 5
    // out q@128
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_6473_c_compmm_m203_out_dest_data_out_55_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_6474_c_compmm_m202_out_dest_data_out_56_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032(ADD,8993)@128
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod417_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_b = $unsigned({{5{i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_27_c_compmm_m1031_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_o[33:0];

    // rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x(MUX,17545)@128
    assign rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q or rightShiftStage0Idx1_uid17544_dupName_109_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q;
            1'b1 : rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17544_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x(MUX,17550)@128
    assign rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17549_dupName_109_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17546_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17549_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x(MUX,17555)@128
    assign rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17554_dupName_109_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17551_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17554_dupName_109_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1033_vt_select_20(BITSELECT,10244)@128
    assign i_unnamed_c_compmm_m1033_vt_select_20_b = rightShiftStage2_uid17556_dupName_109_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1033_vt_join(BITJOIN,10243)@128
    assign i_unnamed_c_compmm_m1033_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1033_vt_select_20_b};

    // i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x(BITSELECT,3751)@128
    assign i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x_b = i_unnamed_c_compmm_m1033_vt_join_q[15:0];

    // redist967_i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x_b_1(DELAY,30095)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist967_i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17565_dupName_110_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17564)@128
    assign rightShiftStage1Idx1Rng8_uid17565_dupName_110_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17567_dupName_110_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17566)@128
    assign rightShiftStage1Idx1_uid17567_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17565_dupName_110_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17560_dupName_110_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17559)@128
    assign rightShiftStage0Idx1Rng4_uid17560_dupName_110_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q[33:4];

    // rightShiftStage0Idx1_uid17562_dupName_110_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17561)@128
    assign rightShiftStage0Idx1_uid17562_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17560_dupName_110_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x(MUX,17563)@128
    assign rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q or rightShiftStage0Idx1_uid17562_dupName_110_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_27_i_c_compmm_m1032_q;
            1'b1 : rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17562_dupName_110_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x(MUX,17568)@128
    assign rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17567_dupName_110_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17564_dupName_110_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17567_dupName_110_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1035_vt_select_21(BITSELECT,10247)@128
    assign i_unnamed_c_compmm_m1035_vt_select_21_b = rightShiftStage1_uid17569_dupName_110_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1035_vt_join(BITJOIN,10246)@128
    assign i_unnamed_c_compmm_m1035_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1035_vt_select_21_b};

    // i_unnamed_c_compmm_m1036_sel_x(BITSELECT,6006)@128
    assign i_unnamed_c_compmm_m1036_sel_x_b = i_unnamed_c_compmm_m1035_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1037_BitSelect_for_a(BITSELECT,28364)@128
    assign i_unnamed_c_compmm_m1037_BitSelect_for_a_b = i_unnamed_c_compmm_m1036_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1037_join(BITJOIN,28365)@128
    assign i_unnamed_c_compmm_m1037_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1037_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1037_vt_select_0(BITSELECT,10252)@128
    assign i_unnamed_c_compmm_m1037_vt_select_0_b = i_unnamed_c_compmm_m1037_join_q[0:0];

    // redist252_i_unnamed_c_compmm_m1037_vt_select_0_b_1(DELAY,29380)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist252_i_unnamed_c_compmm_m1037_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1037_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1037_vt_join(BITJOIN,10251)@129
    assign i_unnamed_c_compmm_m1037_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist252_i_unnamed_c_compmm_m1037_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_27_c_compmm_m1038(ADD,7206)@129
    assign i_add_i_i_i_i_i_i_27_c_compmm_m1038_a = {1'b0, i_unnamed_c_compmm_m1037_vt_join_q};
    assign i_add_i_i_i_i_i_i_27_c_compmm_m1038_b = {1'b0, redist967_i_conv_i_i_i_i_i_27_c_compmm_m1034_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_27_c_compmm_m1038_o = $unsigned(i_add_i_i_i_i_i_i_27_c_compmm_m1038_a) + $unsigned(i_add_i_i_i_i_i_i_27_c_compmm_m1038_b);
    assign i_add_i_i_i_i_i_i_27_c_compmm_m1038_q = i_add_i_i_i_i_i_i_27_c_compmm_m1038_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_27_c_compmm_m1038_sel_x(BITSELECT,2220)@129
    assign bgTrunc_i_add_i_i_i_i_i_i_27_c_compmm_m1038_sel_x_b = i_add_i_i_i_i_i_i_27_c_compmm_m1038_q[15:0];

    // i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_sel_x(BITSELECT,3880)@129
    assign i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_27_c_compmm_m1038_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_select_15(BITSELECT,8247)@129
    assign i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_select_15_b = i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_join(BITJOIN,8246)@129
    assign i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_select_15_b};

    // leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(MUX,26908)@129
    assign leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_join_q or leftShiftStage0Idx1_uid26907_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_28_c_compmm_m1058_vt_join_q;
            1'b1 : leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26907_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(MUX,26913)@129
    assign leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s or leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26912_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = leftShiftStage0_uid26909_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26912_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x(MUX,26918)@129
    assign leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s or leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26917_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = leftShiftStage1_uid26914_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26917_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28(BITSELECT,9982)@129
    assign i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28_b = leftShiftStage2_uid26919_i_shl_i_i_i_i_i_i_28_c_compmm_m0_shift_x_q[28:13];

    // redist332_i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28_b_1(DELAY,29460)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist332_i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_join(BITJOIN,9981)@130
    assign i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_join_q = {redist332_i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg199(REG,13494)@123 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg199_q <= $unsigned(redist787_sync_together4364_aunroll_x_in_i_valid_55_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_6476_c_compmm_m200(BLACKBOX,8772)@124
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6476_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_6476_c_compmm_m200 (
        .in_intel_reserved_ffwd_58_0(in_intel_reserved_ffwd_58_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg199_q),
        .out_dest_data_out_58_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_6476_c_compmm_m200_out_dest_data_out_58_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_offset(CONSTANT,30611)
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_offset_q = $unsigned(5'b01110);

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt(ADD,30612)
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_a = {1'b0, redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_q};
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_b = {1'b0, redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_o <= $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_a) + $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_b);
        end
    end
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_q = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_o[5:0];

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt(ADD,31932)
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_a = {1'b0, redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_q};
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_o <= $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_a) + $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_b);
        end
    end
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_q = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_o[5:0];

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_inputreg0(DELAY,31927)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_inputreg0_q <= $unsigned(in_c1_eni5_57_tpl);
        end
    end

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem(DUALMEM,31929)
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_ia = $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_inputreg0_q);
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_aa = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_q;
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_ab = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_aa),
        .data_a(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_ab),
        .q_b(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_q = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_iq[15:0];

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_outputreg0(DELAY,31928)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_outputreg0_q <= $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_mem_q);
        end
    end

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_inputreg0(DELAY,30607)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_inputreg0_q <= $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_split_0_outputreg0_q);
        end
    end

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr(COUNTER,30610)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_i <= $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_q = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_i[4:0];

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem(DUALMEM,30609)
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_ia = $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_inputreg0_q);
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_aa = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_wraddr_q;
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_ab = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_aa),
        .data_a(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_ab),
        .q_b(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_q = redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_iq[15:0];

    // redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_outputreg0(DELAY,30608)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_outputreg0_q <= $unsigned(redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_mem_q);
        end
    end

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt(ADD,30618)
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_a = {1'b0, redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_q};
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_b = {1'b0, redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_o <= $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_a) + $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_b);
        end
    end
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_q = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_o[5:0];

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt(ADD,31938)
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_a = {1'b0, redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_q};
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_o <= $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_a) + $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_b);
        end
    end
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_q = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_o[5:0];

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_inputreg0(DELAY,31933)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_inputreg0_q <= $unsigned(in_c1_eni5_58_tpl);
        end
    end

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem(DUALMEM,31935)
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_ia = $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_inputreg0_q);
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_aa = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_q;
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_ab = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_aa),
        .data_a(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_ab),
        .q_b(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_q = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_iq[15:0];

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_outputreg0(DELAY,31934)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_outputreg0_q <= $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_mem_q);
        end
    end

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_inputreg0(DELAY,30613)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_inputreg0_q <= $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_split_0_outputreg0_q);
        end
    end

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr(COUNTER,30616)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_i <= $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_q = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_i[4:0];

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem(DUALMEM,30615)
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_ia = $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_inputreg0_q);
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_aa = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_wraddr_q;
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_ab = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_aa),
        .data_a(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_ab),
        .q_b(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_q = redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_iq[15:0];

    // redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_outputreg0(DELAY,30614)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_outputreg0_q <= $unsigned(redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_mem_q);
        end
    end

    // valid_fanout_reg200(REG,13495)@123 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg200_q <= $unsigned(redist787_sync_together4364_aunroll_x_in_i_valid_55_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_6475_c_compmm_m201(BLACKBOX,8768)@124
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6475_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_6475_c_compmm_m201 (
        .in_intel_reserved_ffwd_57_0(in_intel_reserved_ffwd_57_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg200_q),
        .out_dest_data_out_57_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_6475_c_compmm_m201_out_dest_data_out_57_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28899)@124 + 5
    // out q@130
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_6475_c_compmm_m201_out_dest_data_out_57_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_6476_c_compmm_m200_out_dest_data_out_58_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060(ADD,8994)@130
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod422_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_b = $unsigned({{5{i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_28_c_compmm_m1059_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_o[33:0];

    // rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x(MUX,17607)@130
    assign rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q or rightShiftStage0Idx1_uid17606_dupName_113_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q;
            1'b1 : rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17606_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x(MUX,17612)@130
    assign rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17611_dupName_113_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17608_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17611_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x(MUX,17617)@130
    assign rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17616_dupName_113_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17613_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17616_dupName_113_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1061_vt_select_20(BITSELECT,10266)@130
    assign i_unnamed_c_compmm_m1061_vt_select_20_b = rightShiftStage2_uid17618_dupName_113_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1061_vt_join(BITJOIN,10265)@130
    assign i_unnamed_c_compmm_m1061_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1061_vt_select_20_b};

    // i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x(BITSELECT,3752)@130
    assign i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x_b = i_unnamed_c_compmm_m1061_vt_join_q[15:0];

    // redist966_i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x_b_1(DELAY,30094)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist966_i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17627_dupName_114_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17626)@130
    assign rightShiftStage1Idx1Rng8_uid17627_dupName_114_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17629_dupName_114_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17628)@130
    assign rightShiftStage1Idx1_uid17629_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17627_dupName_114_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17622_dupName_114_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17621)@130
    assign rightShiftStage0Idx1Rng4_uid17622_dupName_114_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q[33:4];

    // rightShiftStage0Idx1_uid17624_dupName_114_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17623)@130
    assign rightShiftStage0Idx1_uid17624_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17622_dupName_114_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x(MUX,17625)@130
    assign rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q or rightShiftStage0Idx1_uid17624_dupName_114_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_28_i_c_compmm_m1060_q;
            1'b1 : rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17624_dupName_114_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x(MUX,17630)@130
    assign rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17629_dupName_114_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17626_dupName_114_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17629_dupName_114_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1063_vt_select_21(BITSELECT,10269)@130
    assign i_unnamed_c_compmm_m1063_vt_select_21_b = rightShiftStage1_uid17631_dupName_114_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1063_vt_join(BITJOIN,10268)@130
    assign i_unnamed_c_compmm_m1063_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1063_vt_select_21_b};

    // i_unnamed_c_compmm_m1064_sel_x(BITSELECT,6008)@130
    assign i_unnamed_c_compmm_m1064_sel_x_b = i_unnamed_c_compmm_m1063_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1065_BitSelect_for_a(BITSELECT,28368)@130
    assign i_unnamed_c_compmm_m1065_BitSelect_for_a_b = i_unnamed_c_compmm_m1064_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1065_join(BITJOIN,28369)@130
    assign i_unnamed_c_compmm_m1065_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1065_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1065_vt_select_0(BITSELECT,10274)@130
    assign i_unnamed_c_compmm_m1065_vt_select_0_b = i_unnamed_c_compmm_m1065_join_q[0:0];

    // redist250_i_unnamed_c_compmm_m1065_vt_select_0_b_1(DELAY,29378)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist250_i_unnamed_c_compmm_m1065_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1065_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1065_vt_join(BITJOIN,10273)@131
    assign i_unnamed_c_compmm_m1065_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist250_i_unnamed_c_compmm_m1065_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_28_c_compmm_m1066(ADD,7207)@131
    assign i_add_i_i_i_i_i_i_28_c_compmm_m1066_a = {1'b0, i_unnamed_c_compmm_m1065_vt_join_q};
    assign i_add_i_i_i_i_i_i_28_c_compmm_m1066_b = {1'b0, redist966_i_conv_i_i_i_i_i_28_c_compmm_m1062_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_28_c_compmm_m1066_o = $unsigned(i_add_i_i_i_i_i_i_28_c_compmm_m1066_a) + $unsigned(i_add_i_i_i_i_i_i_28_c_compmm_m1066_b);
    assign i_add_i_i_i_i_i_i_28_c_compmm_m1066_q = i_add_i_i_i_i_i_i_28_c_compmm_m1066_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_28_c_compmm_m1066_sel_x(BITSELECT,2221)@131
    assign bgTrunc_i_add_i_i_i_i_i_i_28_c_compmm_m1066_sel_x_b = i_add_i_i_i_i_i_i_28_c_compmm_m1066_q[15:0];

    // i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_sel_x(BITSELECT,3881)@131
    assign i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_28_c_compmm_m1066_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_select_15(BITSELECT,8251)@131
    assign i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_select_15_b = i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_join(BITJOIN,8250)@131
    assign i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_select_15_b};

    // leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(MUX,26926)@131
    assign leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_join_q or leftShiftStage0Idx1_uid26925_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_29_c_compmm_m1086_vt_join_q;
            1'b1 : leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26925_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(MUX,26931)@131
    assign leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s or leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26930_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = leftShiftStage0_uid26927_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26930_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x(MUX,26936)@131
    assign leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s or leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26935_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = leftShiftStage1_uid26932_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26935_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28(BITSELECT,9985)@131
    assign i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28_b = leftShiftStage2_uid26937_i_shl_i_i_i_i_i_i_29_c_compmm_m0_shift_x_q[28:13];

    // redist331_i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28_b_1(DELAY,29459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist331_i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_join(BITJOIN,9984)@132
    assign i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_join_q = {redist331_i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg197(REG,13492)@125 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg197_q <= $unsigned(redist788_sync_together4364_aunroll_x_in_i_valid_57_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_6478_c_compmm_m198(BLACKBOX,8780)@126
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6478_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_6478_c_compmm_m198 (
        .in_intel_reserved_ffwd_60_0(in_intel_reserved_ffwd_60_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg197_q),
        .out_dest_data_out_60_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_6478_c_compmm_m198_out_dest_data_out_60_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_offset(CONSTANT,30623)
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_offset_q = $unsigned(5'b01100);

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt(ADD,30624)
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_a = {1'b0, redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_q};
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_b = {1'b0, redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_o <= $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_a) + $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_b);
        end
    end
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_q = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_o[5:0];

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt(ADD,31944)
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_a = {1'b0, redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_q};
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_o <= $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_a) + $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_b);
        end
    end
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_q = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_o[5:0];

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_inputreg0(DELAY,31939)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_inputreg0_q <= $unsigned(in_c1_eni5_59_tpl);
        end
    end

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem(DUALMEM,31941)
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_ia = $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_inputreg0_q);
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_aa = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_q;
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_ab = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_aa),
        .data_a(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_ab),
        .q_b(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_q = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_iq[15:0];

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_outputreg0(DELAY,31940)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_outputreg0_q <= $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_mem_q);
        end
    end

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_inputreg0(DELAY,30619)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_inputreg0_q <= $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_split_0_outputreg0_q);
        end
    end

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr(COUNTER,30622)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_i <= $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_q = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_i[4:0];

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem(DUALMEM,30621)
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_ia = $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_inputreg0_q);
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_aa = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_wraddr_q;
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_ab = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_aa),
        .data_a(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_ab),
        .q_b(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_q = redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_iq[15:0];

    // redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_outputreg0(DELAY,30620)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_outputreg0_q <= $unsigned(redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_mem_q);
        end
    end

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt(ADD,30630)
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_a = {1'b0, redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_q};
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_b = {1'b0, redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_o <= $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_a) + $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_b);
        end
    end
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_q = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_o[5:0];

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt(ADD,31950)
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_a = {1'b0, redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_q};
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_o <= $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_a) + $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_b);
        end
    end
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_q = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_o[5:0];

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_inputreg0(DELAY,31945)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_inputreg0_q <= $unsigned(in_c1_eni5_60_tpl);
        end
    end

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem(DUALMEM,31947)
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_ia = $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_inputreg0_q);
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_aa = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_q;
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_ab = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_aa),
        .data_a(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_ab),
        .q_b(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_q = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_iq[15:0];

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_outputreg0(DELAY,31946)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_outputreg0_q <= $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_mem_q);
        end
    end

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_inputreg0(DELAY,30625)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_inputreg0_q <= $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_split_0_outputreg0_q);
        end
    end

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr(COUNTER,30628)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_i <= $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_q = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_i[4:0];

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem(DUALMEM,30627)
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_ia = $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_inputreg0_q);
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_aa = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_wraddr_q;
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_ab = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_aa),
        .data_a(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_ab),
        .q_b(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_q = redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_iq[15:0];

    // redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_outputreg0(DELAY,30626)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_outputreg0_q <= $unsigned(redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_mem_q);
        end
    end

    // valid_fanout_reg198(REG,13493)@125 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg198_q <= $unsigned(redist788_sync_together4364_aunroll_x_in_i_valid_57_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_6477_c_compmm_m199(BLACKBOX,8776)@126
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6477_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_6477_c_compmm_m199 (
        .in_intel_reserved_ffwd_59_0(in_intel_reserved_ffwd_59_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg198_q),
        .out_dest_data_out_59_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_6477_c_compmm_m199_out_dest_data_out_59_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28900)@126 + 5
    // out q@132
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_6477_c_compmm_m199_out_dest_data_out_59_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_6478_c_compmm_m198_out_dest_data_out_60_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088(ADD,8995)@132
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod427_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_b = $unsigned({{5{i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_29_c_compmm_m1087_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_o[33:0];

    // rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x(MUX,17669)@132
    assign rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q or rightShiftStage0Idx1_uid17668_dupName_117_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q;
            1'b1 : rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17668_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x(MUX,17674)@132
    assign rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17673_dupName_117_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17670_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17673_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x(MUX,17679)@132
    assign rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17678_dupName_117_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17675_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17678_dupName_117_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1089_vt_select_20(BITSELECT,10288)@132
    assign i_unnamed_c_compmm_m1089_vt_select_20_b = rightShiftStage2_uid17680_dupName_117_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1089_vt_join(BITJOIN,10287)@132
    assign i_unnamed_c_compmm_m1089_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1089_vt_select_20_b};

    // i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x(BITSELECT,3753)@132
    assign i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x_b = i_unnamed_c_compmm_m1089_vt_join_q[15:0];

    // redist965_i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x_b_1(DELAY,30093)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist965_i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17689_dupName_118_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17688)@132
    assign rightShiftStage1Idx1Rng8_uid17689_dupName_118_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17691_dupName_118_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17690)@132
    assign rightShiftStage1Idx1_uid17691_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17689_dupName_118_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17684_dupName_118_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17683)@132
    assign rightShiftStage0Idx1Rng4_uid17684_dupName_118_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q[33:4];

    // rightShiftStage0Idx1_uid17686_dupName_118_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17685)@132
    assign rightShiftStage0Idx1_uid17686_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17684_dupName_118_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x(MUX,17687)@132
    assign rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q or rightShiftStage0Idx1_uid17686_dupName_118_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_29_i_c_compmm_m1088_q;
            1'b1 : rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17686_dupName_118_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x(MUX,17692)@132
    assign rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17691_dupName_118_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17688_dupName_118_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17691_dupName_118_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1091_vt_select_21(BITSELECT,10291)@132
    assign i_unnamed_c_compmm_m1091_vt_select_21_b = rightShiftStage1_uid17693_dupName_118_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1091_vt_join(BITJOIN,10290)@132
    assign i_unnamed_c_compmm_m1091_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1091_vt_select_21_b};

    // i_unnamed_c_compmm_m1092_sel_x(BITSELECT,6010)@132
    assign i_unnamed_c_compmm_m1092_sel_x_b = i_unnamed_c_compmm_m1091_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1093_BitSelect_for_a(BITSELECT,28372)@132
    assign i_unnamed_c_compmm_m1093_BitSelect_for_a_b = i_unnamed_c_compmm_m1092_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1093_join(BITJOIN,28373)@132
    assign i_unnamed_c_compmm_m1093_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1093_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1093_vt_select_0(BITSELECT,10296)@132
    assign i_unnamed_c_compmm_m1093_vt_select_0_b = i_unnamed_c_compmm_m1093_join_q[0:0];

    // redist248_i_unnamed_c_compmm_m1093_vt_select_0_b_1(DELAY,29376)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist248_i_unnamed_c_compmm_m1093_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1093_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1093_vt_join(BITJOIN,10295)@133
    assign i_unnamed_c_compmm_m1093_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist248_i_unnamed_c_compmm_m1093_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_29_c_compmm_m1094(ADD,7208)@133
    assign i_add_i_i_i_i_i_i_29_c_compmm_m1094_a = {1'b0, i_unnamed_c_compmm_m1093_vt_join_q};
    assign i_add_i_i_i_i_i_i_29_c_compmm_m1094_b = {1'b0, redist965_i_conv_i_i_i_i_i_29_c_compmm_m1090_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_29_c_compmm_m1094_o = $unsigned(i_add_i_i_i_i_i_i_29_c_compmm_m1094_a) + $unsigned(i_add_i_i_i_i_i_i_29_c_compmm_m1094_b);
    assign i_add_i_i_i_i_i_i_29_c_compmm_m1094_q = i_add_i_i_i_i_i_i_29_c_compmm_m1094_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_29_c_compmm_m1094_sel_x(BITSELECT,2222)@133
    assign bgTrunc_i_add_i_i_i_i_i_i_29_c_compmm_m1094_sel_x_b = i_add_i_i_i_i_i_i_29_c_compmm_m1094_q[15:0];

    // i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_sel_x(BITSELECT,3883)@133
    assign i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_29_c_compmm_m1094_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_select_15(BITSELECT,8259)@133
    assign i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_select_15_b = i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_join(BITJOIN,8258)@133
    assign i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_select_15_b};

    // leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(MUX,26962)@133
    assign leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_join_q or leftShiftStage0Idx1_uid26961_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_30_c_compmm_m1114_vt_join_q;
            1'b1 : leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26961_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(MUX,26967)@133
    assign leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s or leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26966_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = leftShiftStage0_uid26963_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26966_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x(MUX,26972)@133
    assign leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s or leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26971_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = leftShiftStage1_uid26968_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26971_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28(BITSELECT,9991)@133
    assign i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28_b = leftShiftStage2_uid26973_i_shl_i_i_i_i_i_i_30_c_compmm_m0_shift_x_q[28:13];

    // redist330_i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28_b_1(DELAY,29458)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist330_i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_join(BITJOIN,9990)@134
    assign i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_join_q = {redist330_i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg195(REG,13490)@127 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg195_q <= $unsigned(redist789_sync_together4364_aunroll_x_in_i_valid_59_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_6480_c_compmm_m196(BLACKBOX,8792)@128
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6480_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_6480_c_compmm_m196 (
        .in_intel_reserved_ffwd_62_0(in_intel_reserved_ffwd_62_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg195_q),
        .out_dest_data_out_62_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_6480_c_compmm_m196_out_dest_data_out_62_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_offset(CONSTANT,30635)
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_offset_q = $unsigned(5'b01010);

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt(ADD,30636)
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_a = {1'b0, redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_q};
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_b = {1'b0, redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_o <= $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_a) + $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_b);
        end
    end
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_q = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_o[5:0];

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt(ADD,31956)
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_a = {1'b0, redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_q};
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_o <= $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_a) + $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_b);
        end
    end
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_q = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_o[5:0];

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_inputreg0(DELAY,31951)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_inputreg0_q <= $unsigned(in_c1_eni5_61_tpl);
        end
    end

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem(DUALMEM,31953)
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_ia = $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_inputreg0_q);
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_aa = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_q;
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_ab = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_aa),
        .data_a(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_ab),
        .q_b(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_q = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_iq[15:0];

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_outputreg0(DELAY,31952)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_outputreg0_q <= $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_mem_q);
        end
    end

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_inputreg0(DELAY,30631)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_inputreg0_q <= $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_split_0_outputreg0_q);
        end
    end

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr(COUNTER,30634)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_i <= $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_q = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_i[4:0];

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem(DUALMEM,30633)
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_ia = $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_inputreg0_q);
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_aa = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_wraddr_q;
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_ab = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_aa),
        .data_a(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_ab),
        .q_b(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_q = redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_iq[15:0];

    // redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_outputreg0(DELAY,30632)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_outputreg0_q <= $unsigned(redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_mem_q);
        end
    end

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt(ADD,30642)
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_a = {1'b0, redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_q};
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_b = {1'b0, redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_o <= $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_a) + $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_b);
        end
    end
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_q = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_o[5:0];

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt(ADD,31962)
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_a = {1'b0, redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_q};
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_o <= $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_a) + $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_b);
        end
    end
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_q = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_o[5:0];

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_inputreg0(DELAY,31957)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_inputreg0_q <= $unsigned(in_c1_eni5_62_tpl);
        end
    end

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem(DUALMEM,31959)
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_ia = $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_inputreg0_q);
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_aa = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_q;
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_ab = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_aa),
        .data_a(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_ab),
        .q_b(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_q = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_iq[15:0];

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_outputreg0(DELAY,31958)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_outputreg0_q <= $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_mem_q);
        end
    end

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_inputreg0(DELAY,30637)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_inputreg0_q <= $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_split_0_outputreg0_q);
        end
    end

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr(COUNTER,30640)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_i <= $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_q = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_i[4:0];

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem(DUALMEM,30639)
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_ia = $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_inputreg0_q);
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_aa = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_wraddr_q;
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_ab = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_aa),
        .data_a(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_ab),
        .q_b(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_q = redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_iq[15:0];

    // redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_outputreg0(DELAY,30638)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_outputreg0_q <= $unsigned(redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_mem_q);
        end
    end

    // valid_fanout_reg196(REG,13491)@127 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg196_q <= $unsigned(redist789_sync_together4364_aunroll_x_in_i_valid_59_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_6479_c_compmm_m197(BLACKBOX,8788)@128
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6479_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_6479_c_compmm_m197 (
        .in_intel_reserved_ffwd_61_0(in_intel_reserved_ffwd_61_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg196_q),
        .out_dest_data_out_61_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_6479_c_compmm_m197_out_dest_data_out_61_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28901)@128 + 5
    // out q@134
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_6479_c_compmm_m197_out_dest_data_out_61_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_6480_c_compmm_m196_out_dest_data_out_62_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116(ADD,8997)@134
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod432_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_b = $unsigned({{5{i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_30_c_compmm_m1115_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_o[33:0];

    // rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x(MUX,17731)@134
    assign rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q or rightShiftStage0Idx1_uid17730_dupName_121_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q;
            1'b1 : rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17730_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x(MUX,17736)@134
    assign rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17735_dupName_121_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17732_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17735_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x(MUX,17741)@134
    assign rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17740_dupName_121_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17737_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17740_dupName_121_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1117_vt_select_20(BITSELECT,10310)@134
    assign i_unnamed_c_compmm_m1117_vt_select_20_b = rightShiftStage2_uid17742_dupName_121_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1117_vt_join(BITJOIN,10309)@134
    assign i_unnamed_c_compmm_m1117_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1117_vt_select_20_b};

    // i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x(BITSELECT,3755)@134
    assign i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x_b = i_unnamed_c_compmm_m1117_vt_join_q[15:0];

    // redist963_i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x_b_1(DELAY,30091)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist963_i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17751_dupName_122_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17750)@134
    assign rightShiftStage1Idx1Rng8_uid17751_dupName_122_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17753_dupName_122_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17752)@134
    assign rightShiftStage1Idx1_uid17753_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17751_dupName_122_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17746_dupName_122_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17745)@134
    assign rightShiftStage0Idx1Rng4_uid17746_dupName_122_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q[33:4];

    // rightShiftStage0Idx1_uid17748_dupName_122_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17747)@134
    assign rightShiftStage0Idx1_uid17748_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17746_dupName_122_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x(MUX,17749)@134
    assign rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q or rightShiftStage0Idx1_uid17748_dupName_122_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_30_i_c_compmm_m1116_q;
            1'b1 : rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17748_dupName_122_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x(MUX,17754)@134
    assign rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17753_dupName_122_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17750_dupName_122_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17753_dupName_122_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1119_vt_select_21(BITSELECT,10313)@134
    assign i_unnamed_c_compmm_m1119_vt_select_21_b = rightShiftStage1_uid17755_dupName_122_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1119_vt_join(BITJOIN,10312)@134
    assign i_unnamed_c_compmm_m1119_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1119_vt_select_21_b};

    // i_unnamed_c_compmm_m1120_sel_x(BITSELECT,6012)@134
    assign i_unnamed_c_compmm_m1120_sel_x_b = i_unnamed_c_compmm_m1119_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1121_BitSelect_for_a(BITSELECT,28376)@134
    assign i_unnamed_c_compmm_m1121_BitSelect_for_a_b = i_unnamed_c_compmm_m1120_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1121_join(BITJOIN,28377)@134
    assign i_unnamed_c_compmm_m1121_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1121_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1121_vt_select_0(BITSELECT,10318)@134
    assign i_unnamed_c_compmm_m1121_vt_select_0_b = i_unnamed_c_compmm_m1121_join_q[0:0];

    // redist246_i_unnamed_c_compmm_m1121_vt_select_0_b_1(DELAY,29374)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist246_i_unnamed_c_compmm_m1121_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1121_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1121_vt_join(BITJOIN,10317)@135
    assign i_unnamed_c_compmm_m1121_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist246_i_unnamed_c_compmm_m1121_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_30_c_compmm_m1122(ADD,7210)@135
    assign i_add_i_i_i_i_i_i_30_c_compmm_m1122_a = {1'b0, i_unnamed_c_compmm_m1121_vt_join_q};
    assign i_add_i_i_i_i_i_i_30_c_compmm_m1122_b = {1'b0, redist963_i_conv_i_i_i_i_i_30_c_compmm_m1118_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_30_c_compmm_m1122_o = $unsigned(i_add_i_i_i_i_i_i_30_c_compmm_m1122_a) + $unsigned(i_add_i_i_i_i_i_i_30_c_compmm_m1122_b);
    assign i_add_i_i_i_i_i_i_30_c_compmm_m1122_q = i_add_i_i_i_i_i_i_30_c_compmm_m1122_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_30_c_compmm_m1122_sel_x(BITSELECT,2224)@135
    assign bgTrunc_i_add_i_i_i_i_i_i_30_c_compmm_m1122_sel_x_b = i_add_i_i_i_i_i_i_30_c_compmm_m1122_q[15:0];

    // i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_sel_x(BITSELECT,3884)@135
    assign i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_30_c_compmm_m1122_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_select_15(BITSELECT,8263)@135
    assign i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_select_15_b = i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_join(BITJOIN,8262)@135
    assign i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_select_15_b};

    // leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(MUX,26980)@135
    assign leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_join_q or leftShiftStage0Idx1_uid26979_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_31_c_compmm_m1142_vt_join_q;
            1'b1 : leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26979_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(MUX,26985)@135
    assign leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s or leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26984_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = leftShiftStage0_uid26981_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26984_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x(MUX,26990)@135
    assign leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s or leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26989_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = leftShiftStage1_uid26986_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26989_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28(BITSELECT,9994)@135
    assign i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28_b = leftShiftStage2_uid26991_i_shl_i_i_i_i_i_i_31_c_compmm_m0_shift_x_q[28:13];

    // redist329_i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28_b_1(DELAY,29457)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist329_i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_join(BITJOIN,9993)@136
    assign i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_join_q = {redist329_i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg193(REG,13488)@129 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg193_q <= $unsigned(redist790_sync_together4364_aunroll_x_in_i_valid_61_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_6482_c_compmm_m194(BLACKBOX,8800)@130
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6482_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_6482_c_compmm_m194 (
        .in_intel_reserved_ffwd_64_0(in_intel_reserved_ffwd_64_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg193_q),
        .out_dest_data_out_64_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_6482_c_compmm_m194_out_dest_data_out_64_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_offset(CONSTANT,30647)
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_offset_q = $unsigned(5'b01000);

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt(ADD,30648)
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_a = {1'b0, redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_q};
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_b = {1'b0, redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_o <= $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_a) + $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_b);
        end
    end
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_q = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_o[5:0];

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt(ADD,31968)
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_a = {1'b0, redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_q};
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_o <= $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_a) + $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_b);
        end
    end
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_q = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_o[5:0];

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_inputreg0(DELAY,31963)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_inputreg0_q <= $unsigned(in_c1_eni5_63_tpl);
        end
    end

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem(DUALMEM,31965)
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_ia = $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_inputreg0_q);
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_aa = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_q;
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_ab = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_aa),
        .data_a(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_ab),
        .q_b(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_q = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_iq[15:0];

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_outputreg0(DELAY,31964)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_outputreg0_q <= $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_mem_q);
        end
    end

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_inputreg0(DELAY,30643)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_inputreg0_q <= $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_split_0_outputreg0_q);
        end
    end

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr(COUNTER,30646)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_i <= $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_q = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_i[4:0];

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem(DUALMEM,30645)
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_ia = $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_inputreg0_q);
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_aa = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_wraddr_q;
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_ab = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_aa),
        .data_a(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_ab),
        .q_b(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_q = redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_iq[15:0];

    // redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_outputreg0(DELAY,30644)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_outputreg0_q <= $unsigned(redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_mem_q);
        end
    end

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt(ADD,30654)
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_a = {1'b0, redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_q};
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_b = {1'b0, redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_o <= $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_a) + $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_b);
        end
    end
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_q = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_o[5:0];

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt(ADD,31974)
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_a = {1'b0, redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_q};
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_o <= $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_a) + $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_b);
        end
    end
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_q = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_o[5:0];

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_inputreg0(DELAY,31969)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_inputreg0_q <= $unsigned(in_c1_eni5_64_tpl);
        end
    end

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem(DUALMEM,31971)
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_ia = $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_inputreg0_q);
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_aa = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_q;
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_ab = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_aa),
        .data_a(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_ab),
        .q_b(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_q = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_iq[15:0];

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_outputreg0(DELAY,31970)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_outputreg0_q <= $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_mem_q);
        end
    end

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_inputreg0(DELAY,30649)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_inputreg0_q <= $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_split_0_outputreg0_q);
        end
    end

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr(COUNTER,30652)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_i <= $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_q = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_i[4:0];

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem(DUALMEM,30651)
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_ia = $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_inputreg0_q);
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_aa = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_wraddr_q;
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_ab = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_aa),
        .data_a(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_ab),
        .q_b(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_q = redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_iq[15:0];

    // redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_outputreg0(DELAY,30650)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_outputreg0_q <= $unsigned(redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_mem_q);
        end
    end

    // valid_fanout_reg194(REG,13489)@129 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg194_q <= $unsigned(redist790_sync_together4364_aunroll_x_in_i_valid_61_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_6481_c_compmm_m195(BLACKBOX,8796)@130
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6481_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_6481_c_compmm_m195 (
        .in_intel_reserved_ffwd_63_0(in_intel_reserved_ffwd_63_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg194_q),
        .out_dest_data_out_63_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_6481_c_compmm_m195_out_dest_data_out_63_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28902)@130 + 5
    // out q@136
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_6481_c_compmm_m195_out_dest_data_out_63_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_6482_c_compmm_m194_out_dest_data_out_64_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144(ADD,8998)@136
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod437_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_b = $unsigned({{5{i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_31_c_compmm_m1143_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_o[33:0];

    // rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x(MUX,17793)@136
    assign rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q or rightShiftStage0Idx1_uid17792_dupName_125_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q;
            1'b1 : rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17792_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x(MUX,17798)@136
    assign rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17797_dupName_125_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17794_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17797_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x(MUX,17803)@136
    assign rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17802_dupName_125_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17799_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17802_dupName_125_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1145_vt_select_20(BITSELECT,10332)@136
    assign i_unnamed_c_compmm_m1145_vt_select_20_b = rightShiftStage2_uid17804_dupName_125_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1145_vt_join(BITJOIN,10331)@136
    assign i_unnamed_c_compmm_m1145_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1145_vt_select_20_b};

    // i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x(BITSELECT,3756)@136
    assign i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x_b = i_unnamed_c_compmm_m1145_vt_join_q[15:0];

    // redist962_i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x_b_1(DELAY,30090)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist962_i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17813_dupName_126_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17812)@136
    assign rightShiftStage1Idx1Rng8_uid17813_dupName_126_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17815_dupName_126_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17814)@136
    assign rightShiftStage1Idx1_uid17815_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17813_dupName_126_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17808_dupName_126_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17807)@136
    assign rightShiftStage0Idx1Rng4_uid17808_dupName_126_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q[33:4];

    // rightShiftStage0Idx1_uid17810_dupName_126_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17809)@136
    assign rightShiftStage0Idx1_uid17810_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17808_dupName_126_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x(MUX,17811)@136
    assign rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q or rightShiftStage0Idx1_uid17810_dupName_126_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_31_i_c_compmm_m1144_q;
            1'b1 : rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17810_dupName_126_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x(MUX,17816)@136
    assign rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17815_dupName_126_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17812_dupName_126_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17815_dupName_126_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1147_vt_select_21(BITSELECT,10335)@136
    assign i_unnamed_c_compmm_m1147_vt_select_21_b = rightShiftStage1_uid17817_dupName_126_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1147_vt_join(BITJOIN,10334)@136
    assign i_unnamed_c_compmm_m1147_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1147_vt_select_21_b};

    // i_unnamed_c_compmm_m1148_sel_x(BITSELECT,6014)@136
    assign i_unnamed_c_compmm_m1148_sel_x_b = i_unnamed_c_compmm_m1147_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1149_BitSelect_for_a(BITSELECT,28380)@136
    assign i_unnamed_c_compmm_m1149_BitSelect_for_a_b = i_unnamed_c_compmm_m1148_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1149_join(BITJOIN,28381)@136
    assign i_unnamed_c_compmm_m1149_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1149_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1149_vt_select_0(BITSELECT,10340)@136
    assign i_unnamed_c_compmm_m1149_vt_select_0_b = i_unnamed_c_compmm_m1149_join_q[0:0];

    // redist244_i_unnamed_c_compmm_m1149_vt_select_0_b_1(DELAY,29372)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist244_i_unnamed_c_compmm_m1149_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1149_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1149_vt_join(BITJOIN,10339)@137
    assign i_unnamed_c_compmm_m1149_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist244_i_unnamed_c_compmm_m1149_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_31_c_compmm_m1150(ADD,7211)@137
    assign i_add_i_i_i_i_i_i_31_c_compmm_m1150_a = {1'b0, i_unnamed_c_compmm_m1149_vt_join_q};
    assign i_add_i_i_i_i_i_i_31_c_compmm_m1150_b = {1'b0, redist962_i_conv_i_i_i_i_i_31_c_compmm_m1146_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_31_c_compmm_m1150_o = $unsigned(i_add_i_i_i_i_i_i_31_c_compmm_m1150_a) + $unsigned(i_add_i_i_i_i_i_i_31_c_compmm_m1150_b);
    assign i_add_i_i_i_i_i_i_31_c_compmm_m1150_q = i_add_i_i_i_i_i_i_31_c_compmm_m1150_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_31_c_compmm_m1150_sel_x(BITSELECT,2225)@137
    assign bgTrunc_i_add_i_i_i_i_i_i_31_c_compmm_m1150_sel_x_b = i_add_i_i_i_i_i_i_31_c_compmm_m1150_q[15:0];

    // i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_sel_x(BITSELECT,3885)@137
    assign i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_31_c_compmm_m1150_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_select_15(BITSELECT,8267)@137
    assign i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_select_15_b = i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_join(BITJOIN,8266)@137
    assign i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_select_15_b};

    // leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(MUX,26998)@137
    assign leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_join_q or leftShiftStage0Idx1_uid26997_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_32_c_compmm_m1171_vt_join_q;
            1'b1 : leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26997_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(MUX,27003)@137
    assign leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s or leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27002_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = leftShiftStage0_uid26999_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27002_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x(MUX,27008)@137
    assign leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s or leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27007_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = leftShiftStage1_uid27004_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27007_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28(BITSELECT,9997)@137
    assign i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28_b = leftShiftStage2_uid27009_i_shl_i_i_i_i_i_i_32_c_compmm_m0_shift_x_q[28:13];

    // redist328_i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28_b_1(DELAY,29456)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist328_i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_join(BITJOIN,9996)@138
    assign i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_join_q = {redist328_i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg191(REG,13486)@131 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg191_q <= $unsigned(redist791_sync_together4364_aunroll_x_in_i_valid_63_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6584_c_compmm_m192(BLACKBOX,8609)@132
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6584_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6584_c_compmm_m192 (
        .in_intel_reserved_ffwd_66_0(in_intel_reserved_ffwd_66_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg191_q),
        .out_dest_data_out_66_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6584_c_compmm_m192_out_dest_data_out_66_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_offset(CONSTANT,30659)
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_offset_q = $unsigned(5'b00110);

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt(ADD,30660)
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_a = {1'b0, redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_q};
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_b = {1'b0, redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_o <= $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_a) + $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_b);
        end
    end
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_q = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_o[5:0];

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt(ADD,31980)
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_a = {1'b0, redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_q};
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_o <= $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_a) + $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_b);
        end
    end
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_q = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_o[5:0];

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_inputreg0(DELAY,31975)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_inputreg0_q <= $unsigned(in_c1_eni5_65_tpl);
        end
    end

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem(DUALMEM,31977)
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_ia = $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_inputreg0_q);
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_aa = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_q;
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_ab = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_aa),
        .data_a(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_ab),
        .q_b(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_q = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_iq[15:0];

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_outputreg0(DELAY,31976)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_outputreg0_q <= $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_mem_q);
        end
    end

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_inputreg0(DELAY,30655)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_inputreg0_q <= $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_split_0_outputreg0_q);
        end
    end

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr(COUNTER,30658)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_i <= $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_q = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_i[4:0];

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem(DUALMEM,30657)
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_ia = $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_inputreg0_q);
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_aa = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_wraddr_q;
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_ab = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_aa),
        .data_a(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_ab),
        .q_b(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_q = redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_iq[15:0];

    // redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_outputreg0(DELAY,30656)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_outputreg0_q <= $unsigned(redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_mem_q);
        end
    end

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt(ADD,30666)
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_a = {1'b0, redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_q};
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_b = {1'b0, redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_o <= $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_a) + $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_b);
        end
    end
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_q = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_o[5:0];

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt(ADD,31986)
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_a = {1'b0, redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_q};
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_o <= $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_a) + $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_b);
        end
    end
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_q = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_o[5:0];

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_inputreg0(DELAY,31981)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_inputreg0_q <= $unsigned(in_c1_eni5_66_tpl);
        end
    end

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem(DUALMEM,31983)
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_ia = $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_inputreg0_q);
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_aa = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_q;
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_ab = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_aa),
        .data_a(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_ab),
        .q_b(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_q = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_iq[15:0];

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_outputreg0(DELAY,31982)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_outputreg0_q <= $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_mem_q);
        end
    end

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_inputreg0(DELAY,30661)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_inputreg0_q <= $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_split_0_outputreg0_q);
        end
    end

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr(COUNTER,30664)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_i <= $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_q = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_i[4:0];

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem(DUALMEM,30663)
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_ia = $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_inputreg0_q);
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_aa = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_wraddr_q;
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_ab = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_aa),
        .data_a(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_ab),
        .q_b(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_q = redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_iq[15:0];

    // redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_outputreg0(DELAY,30662)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_outputreg0_q <= $unsigned(redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_mem_q);
        end
    end

    // valid_fanout_reg192(REG,13487)@131 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg192_q <= $unsigned(redist791_sync_together4364_aunroll_x_in_i_valid_63_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6583_c_compmm_m193(BLACKBOX,8565)@132
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6583_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6583_c_compmm_m193 (
        .in_intel_reserved_ffwd_65_0(in_intel_reserved_ffwd_65_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg192_q),
        .out_dest_data_out_65_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6583_c_compmm_m193_out_dest_data_out_65_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28903)@132 + 5
    // out q@138
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6583_c_compmm_m193_out_dest_data_out_65_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6584_c_compmm_m192_out_dest_data_out_66_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173(ADD,8999)@138
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod442_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_b = $unsigned({{5{i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_32_c_compmm_m1172_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_o[33:0];

    // rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x(MUX,17855)@138
    assign rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q or rightShiftStage0Idx1_uid17854_dupName_129_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q;
            1'b1 : rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17854_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x(MUX,17860)@138
    assign rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17859_dupName_129_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17856_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17859_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x(MUX,17865)@138
    assign rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17864_dupName_129_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17861_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17864_dupName_129_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1174_vt_select_20(BITSELECT,10354)@138
    assign i_unnamed_c_compmm_m1174_vt_select_20_b = rightShiftStage2_uid17866_dupName_129_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1174_vt_join(BITJOIN,10353)@138
    assign i_unnamed_c_compmm_m1174_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1174_vt_select_20_b};

    // i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x(BITSELECT,3757)@138
    assign i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x_b = i_unnamed_c_compmm_m1174_vt_join_q[15:0];

    // redist961_i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x_b_1(DELAY,30089)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist961_i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17875_dupName_130_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17874)@138
    assign rightShiftStage1Idx1Rng8_uid17875_dupName_130_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17877_dupName_130_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17876)@138
    assign rightShiftStage1Idx1_uid17877_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17875_dupName_130_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17870_dupName_130_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17869)@138
    assign rightShiftStage0Idx1Rng4_uid17870_dupName_130_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q[33:4];

    // rightShiftStage0Idx1_uid17872_dupName_130_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17871)@138
    assign rightShiftStage0Idx1_uid17872_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17870_dupName_130_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x(MUX,17873)@138
    assign rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q or rightShiftStage0Idx1_uid17872_dupName_130_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_32_i_c_compmm_m1173_q;
            1'b1 : rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17872_dupName_130_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x(MUX,17878)@138
    assign rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17877_dupName_130_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17874_dupName_130_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17877_dupName_130_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1176_vt_select_21(BITSELECT,10357)@138
    assign i_unnamed_c_compmm_m1176_vt_select_21_b = rightShiftStage1_uid17879_dupName_130_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1176_vt_join(BITJOIN,10356)@138
    assign i_unnamed_c_compmm_m1176_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1176_vt_select_21_b};

    // i_unnamed_c_compmm_m1177_sel_x(BITSELECT,6016)@138
    assign i_unnamed_c_compmm_m1177_sel_x_b = i_unnamed_c_compmm_m1176_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1178_BitSelect_for_a(BITSELECT,28384)@138
    assign i_unnamed_c_compmm_m1178_BitSelect_for_a_b = i_unnamed_c_compmm_m1177_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1178_join(BITJOIN,28385)@138
    assign i_unnamed_c_compmm_m1178_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1178_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1178_vt_select_0(BITSELECT,10362)@138
    assign i_unnamed_c_compmm_m1178_vt_select_0_b = i_unnamed_c_compmm_m1178_join_q[0:0];

    // redist242_i_unnamed_c_compmm_m1178_vt_select_0_b_1(DELAY,29370)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist242_i_unnamed_c_compmm_m1178_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1178_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1178_vt_join(BITJOIN,10361)@139
    assign i_unnamed_c_compmm_m1178_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist242_i_unnamed_c_compmm_m1178_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_32_c_compmm_m1179(ADD,7212)@139
    assign i_add_i_i_i_i_i_i_32_c_compmm_m1179_a = {1'b0, i_unnamed_c_compmm_m1178_vt_join_q};
    assign i_add_i_i_i_i_i_i_32_c_compmm_m1179_b = {1'b0, redist961_i_conv_i_i_i_i_i_32_c_compmm_m1175_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_32_c_compmm_m1179_o = $unsigned(i_add_i_i_i_i_i_i_32_c_compmm_m1179_a) + $unsigned(i_add_i_i_i_i_i_i_32_c_compmm_m1179_b);
    assign i_add_i_i_i_i_i_i_32_c_compmm_m1179_q = i_add_i_i_i_i_i_i_32_c_compmm_m1179_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_32_c_compmm_m1179_sel_x(BITSELECT,2226)@139
    assign bgTrunc_i_add_i_i_i_i_i_i_32_c_compmm_m1179_sel_x_b = i_add_i_i_i_i_i_i_32_c_compmm_m1179_q[15:0];

    // i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_sel_x(BITSELECT,3886)@139
    assign i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_32_c_compmm_m1179_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_select_15(BITSELECT,8271)@139
    assign i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_select_15_b = i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_join(BITJOIN,8270)@139
    assign i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_select_15_b};

    // leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(MUX,27016)@139
    assign leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_join_q or leftShiftStage0Idx1_uid27015_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_33_c_compmm_m1199_vt_join_q;
            1'b1 : leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27015_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(MUX,27021)@139
    assign leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s or leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27020_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = leftShiftStage0_uid27017_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27020_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x(MUX,27026)@139
    assign leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s or leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27025_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = leftShiftStage1_uid27022_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27025_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28(BITSELECT,10000)@139
    assign i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28_b = leftShiftStage2_uid27027_i_shl_i_i_i_i_i_i_33_c_compmm_m0_shift_x_q[28:13];

    // redist327_i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28_b_1(DELAY,29455)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist327_i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_join(BITJOIN,9999)@140
    assign i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_join_q = {redist327_i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg189(REG,13484)@133 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg189_q <= $unsigned(redist792_sync_together4364_aunroll_x_in_i_valid_65_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6586_c_compmm_m190(BLACKBOX,8697)@134
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6586_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6586_c_compmm_m190 (
        .in_intel_reserved_ffwd_68_0(in_intel_reserved_ffwd_68_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg189_q),
        .out_dest_data_out_68_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6586_c_compmm_m190_out_dest_data_out_68_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt(ADD,30672)
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_a = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_q};
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_o <= $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_a) + $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_b);
        end
    end
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_q = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_o[5:0];

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_inputreg0(DELAY,31987)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_inputreg0_q <= $unsigned(in_c1_eni5_67_tpl);
        end
    end

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem(DUALMEM,31989)
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_ia = $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_inputreg0_q);
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_aa = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_q;
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_ab = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_aa),
        .data_a(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_ab),
        .q_b(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_q = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_iq[15:0];

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_outputreg0(DELAY,31988)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_outputreg0_q <= $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_mem_q);
        end
    end

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_inputreg0(DELAY,30667)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_inputreg0_q <= $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_split_0_outputreg0_q);
        end
    end

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr(COUNTER,30670)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_i <= $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_q = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_i[4:0];

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem(DUALMEM,30669)
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_ia = $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_inputreg0_q);
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_aa = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_wraddr_q;
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_ab = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_aa),
        .data_a(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_ab),
        .q_b(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_q = redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_iq[15:0];

    // redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_outputreg0(DELAY,30668)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_outputreg0_q <= $unsigned(redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_mem_q);
        end
    end

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt(ADD,30678)
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_a = {1'b0, redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_q};
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_o <= $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_a) + $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_b);
        end
    end
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_q = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_o[5:0];

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_inputreg0(DELAY,31993)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_inputreg0_q <= $unsigned(in_c1_eni5_68_tpl);
        end
    end

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem(DUALMEM,31995)
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_ia = $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_inputreg0_q);
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_aa = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_q;
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_ab = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_aa),
        .data_a(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_ab),
        .q_b(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_q = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_iq[15:0];

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_outputreg0(DELAY,31994)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_outputreg0_q <= $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_mem_q);
        end
    end

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_inputreg0(DELAY,30673)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_inputreg0_q <= $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_split_0_outputreg0_q);
        end
    end

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr(COUNTER,30676)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_i <= $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_q = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_i[4:0];

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem(DUALMEM,30675)
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_ia = $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_inputreg0_q);
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_aa = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_wraddr_q;
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_ab = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_aa),
        .data_a(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_ab),
        .q_b(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_q = redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_iq[15:0];

    // redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_outputreg0(DELAY,30674)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_outputreg0_q <= $unsigned(redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_mem_q);
        end
    end

    // valid_fanout_reg190(REG,13485)@133 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg190_q <= $unsigned(redist792_sync_together4364_aunroll_x_in_i_valid_65_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6585_c_compmm_m191(BLACKBOX,8653)@134
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6585_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6585_c_compmm_m191 (
        .in_intel_reserved_ffwd_67_0(in_intel_reserved_ffwd_67_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg190_q),
        .out_dest_data_out_67_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6585_c_compmm_m191_out_dest_data_out_67_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28904)@134 + 5
    // out q@140
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6585_c_compmm_m191_out_dest_data_out_67_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6586_c_compmm_m190_out_dest_data_out_68_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201(ADD,9000)@140
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod447_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_b = $unsigned({{5{i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_33_c_compmm_m1200_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_o[33:0];

    // rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x(MUX,17917)@140
    assign rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q or rightShiftStage0Idx1_uid17916_dupName_133_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q;
            1'b1 : rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17916_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x(MUX,17922)@140
    assign rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17921_dupName_133_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17918_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17921_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x(MUX,17927)@140
    assign rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17926_dupName_133_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17923_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17926_dupName_133_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1202_vt_select_20(BITSELECT,10376)@140
    assign i_unnamed_c_compmm_m1202_vt_select_20_b = rightShiftStage2_uid17928_dupName_133_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1202_vt_join(BITJOIN,10375)@140
    assign i_unnamed_c_compmm_m1202_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1202_vt_select_20_b};

    // i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x(BITSELECT,3758)@140
    assign i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x_b = i_unnamed_c_compmm_m1202_vt_join_q[15:0];

    // redist960_i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x_b_1(DELAY,30088)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist960_i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17937_dupName_134_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17936)@140
    assign rightShiftStage1Idx1Rng8_uid17937_dupName_134_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17939_dupName_134_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17938)@140
    assign rightShiftStage1Idx1_uid17939_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17937_dupName_134_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17932_dupName_134_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17931)@140
    assign rightShiftStage0Idx1Rng4_uid17932_dupName_134_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q[33:4];

    // rightShiftStage0Idx1_uid17934_dupName_134_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17933)@140
    assign rightShiftStage0Idx1_uid17934_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17932_dupName_134_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x(MUX,17935)@140
    assign rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q or rightShiftStage0Idx1_uid17934_dupName_134_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_33_i_c_compmm_m1201_q;
            1'b1 : rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17934_dupName_134_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x(MUX,17940)@140
    assign rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17939_dupName_134_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17936_dupName_134_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17939_dupName_134_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1204_vt_select_21(BITSELECT,10379)@140
    assign i_unnamed_c_compmm_m1204_vt_select_21_b = rightShiftStage1_uid17941_dupName_134_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1204_vt_join(BITJOIN,10378)@140
    assign i_unnamed_c_compmm_m1204_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1204_vt_select_21_b};

    // i_unnamed_c_compmm_m1205_sel_x(BITSELECT,6018)@140
    assign i_unnamed_c_compmm_m1205_sel_x_b = i_unnamed_c_compmm_m1204_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1206_BitSelect_for_a(BITSELECT,28388)@140
    assign i_unnamed_c_compmm_m1206_BitSelect_for_a_b = i_unnamed_c_compmm_m1205_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1206_join(BITJOIN,28389)@140
    assign i_unnamed_c_compmm_m1206_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1206_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1206_vt_select_0(BITSELECT,10384)@140
    assign i_unnamed_c_compmm_m1206_vt_select_0_b = i_unnamed_c_compmm_m1206_join_q[0:0];

    // redist240_i_unnamed_c_compmm_m1206_vt_select_0_b_1(DELAY,29368)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist240_i_unnamed_c_compmm_m1206_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1206_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1206_vt_join(BITJOIN,10383)@141
    assign i_unnamed_c_compmm_m1206_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist240_i_unnamed_c_compmm_m1206_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_33_c_compmm_m1207(ADD,7213)@141
    assign i_add_i_i_i_i_i_i_33_c_compmm_m1207_a = {1'b0, i_unnamed_c_compmm_m1206_vt_join_q};
    assign i_add_i_i_i_i_i_i_33_c_compmm_m1207_b = {1'b0, redist960_i_conv_i_i_i_i_i_33_c_compmm_m1203_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_33_c_compmm_m1207_o = $unsigned(i_add_i_i_i_i_i_i_33_c_compmm_m1207_a) + $unsigned(i_add_i_i_i_i_i_i_33_c_compmm_m1207_b);
    assign i_add_i_i_i_i_i_i_33_c_compmm_m1207_q = i_add_i_i_i_i_i_i_33_c_compmm_m1207_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_33_c_compmm_m1207_sel_x(BITSELECT,2227)@141
    assign bgTrunc_i_add_i_i_i_i_i_i_33_c_compmm_m1207_sel_x_b = i_add_i_i_i_i_i_i_33_c_compmm_m1207_q[15:0];

    // i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_sel_x(BITSELECT,3887)@141
    assign i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_33_c_compmm_m1207_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_select_15(BITSELECT,8275)@141
    assign i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_select_15_b = i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_join(BITJOIN,8274)@141
    assign i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_select_15_b};

    // leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(MUX,27034)@141
    assign leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_join_q or leftShiftStage0Idx1_uid27033_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_34_c_compmm_m1227_vt_join_q;
            1'b1 : leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27033_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(MUX,27039)@141
    assign leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s or leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27038_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = leftShiftStage0_uid27035_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27038_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x(MUX,27044)@141
    assign leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s or leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27043_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = leftShiftStage1_uid27040_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27043_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28(BITSELECT,10003)@141
    assign i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28_b = leftShiftStage2_uid27045_i_shl_i_i_i_i_i_i_34_c_compmm_m0_shift_x_q[28:13];

    // redist326_i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28_b_1(DELAY,29454)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist326_i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_join(BITJOIN,10002)@142
    assign i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_join_q = {redist326_i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg187(REG,13482)@135 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg187_q <= $unsigned(redist793_sync_together4364_aunroll_x_in_i_valid_67_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6588_c_compmm_m188(BLACKBOX,8785)@136
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6588_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6588_c_compmm_m188 (
        .in_intel_reserved_ffwd_70_0(in_intel_reserved_ffwd_70_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg187_q),
        .out_dest_data_out_70_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6588_c_compmm_m188_out_dest_data_out_70_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt(ADD,32004)
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_a = {1'b0, redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_q};
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_o <= $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_a) + $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_b);
        end
    end
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_q = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_o[5:0];

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_inputreg0(DELAY,31999)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_inputreg0_q <= $unsigned(in_c1_eni5_69_tpl);
        end
    end

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem(DUALMEM,32001)
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_ia = $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_inputreg0_q);
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_aa = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_q;
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_ab = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_aa),
        .data_a(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_ab),
        .q_b(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_q = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_iq[15:0];

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_outputreg0(DELAY,32000)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_outputreg0_q <= $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_mem_q);
        end
    end

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_inputreg0(DELAY,32005)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_inputreg0_q <= $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_outputreg0_q);
        end
    end

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr(COUNTER,32002)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_i <= $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_q = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_i[4:0];

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem(DUALMEM,32007)
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_ia = $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_inputreg0_q);
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_aa = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_wraddr_q;
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_ab = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_aa),
        .data_a(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_ab),
        .q_b(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_q = redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_iq[15:0];

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_outputreg0(DELAY,32006)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_outputreg0_q <= $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_mem_q);
        end
    end

    // redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68(DELAY,29699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_delay_0 <= $unsigned(redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_split_1_outputreg0_q);
            redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_q <= redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_delay_0;
        end
    end

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt(ADD,32016)
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_a = {1'b0, redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_q};
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_o <= $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_a) + $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_b);
        end
    end
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_q = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_o[5:0];

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_inputreg0(DELAY,32011)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_inputreg0_q <= $unsigned(in_c1_eni5_70_tpl);
        end
    end

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem(DUALMEM,32013)
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_ia = $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_inputreg0_q);
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_aa = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_q;
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_ab = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_aa),
        .data_a(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_ab),
        .q_b(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_q = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_iq[15:0];

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_outputreg0(DELAY,32012)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_outputreg0_q <= $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_mem_q);
        end
    end

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_inputreg0(DELAY,32017)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_inputreg0_q <= $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_outputreg0_q);
        end
    end

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr(COUNTER,32014)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_i <= $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_q = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_i[4:0];

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem(DUALMEM,32019)
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_ia = $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_inputreg0_q);
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_aa = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_wraddr_q;
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_ab = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_aa),
        .data_a(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_ab),
        .q_b(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_q = redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_iq[15:0];

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_outputreg0(DELAY,32018)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_outputreg0_q <= $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_mem_q);
        end
    end

    // redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68(DELAY,29700)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_delay_0 <= $unsigned(redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_split_1_outputreg0_q);
            redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_q <= redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_delay_0;
        end
    end

    // valid_fanout_reg188(REG,13483)@135 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg188_q <= $unsigned(redist793_sync_together4364_aunroll_x_in_i_valid_67_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6587_c_compmm_m189(BLACKBOX,8741)@136
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6587_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6587_c_compmm_m189 (
        .in_intel_reserved_ffwd_69_0(in_intel_reserved_ffwd_69_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg188_q),
        .out_dest_data_out_69_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6587_c_compmm_m189_out_dest_data_out_69_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28905)@136 + 5
    // out q@142
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6587_c_compmm_m189_out_dest_data_out_69_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6588_c_compmm_m188_out_dest_data_out_70_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229(ADD,9001)@142
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod452_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_b = $unsigned({{5{i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_34_c_compmm_m1228_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_o[33:0];

    // rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x(MUX,17979)@142
    assign rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q or rightShiftStage0Idx1_uid17978_dupName_137_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q;
            1'b1 : rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17978_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x(MUX,17984)@142
    assign rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17983_dupName_137_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17980_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17983_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x(MUX,17989)@142
    assign rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17988_dupName_137_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17985_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17988_dupName_137_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1230_vt_select_20(BITSELECT,10398)@142
    assign i_unnamed_c_compmm_m1230_vt_select_20_b = rightShiftStage2_uid17990_dupName_137_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1230_vt_join(BITJOIN,10397)@142
    assign i_unnamed_c_compmm_m1230_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1230_vt_select_20_b};

    // i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x(BITSELECT,3759)@142
    assign i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x_b = i_unnamed_c_compmm_m1230_vt_join_q[15:0];

    // redist959_i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x_b_1(DELAY,30087)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist959_i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17999_dupName_138_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17998)@142
    assign rightShiftStage1Idx1Rng8_uid17999_dupName_138_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18001_dupName_138_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18000)@142
    assign rightShiftStage1Idx1_uid18001_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17999_dupName_138_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17994_dupName_138_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17993)@142
    assign rightShiftStage0Idx1Rng4_uid17994_dupName_138_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q[33:4];

    // rightShiftStage0Idx1_uid17996_dupName_138_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17995)@142
    assign rightShiftStage0Idx1_uid17996_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17994_dupName_138_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x(MUX,17997)@142
    assign rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q or rightShiftStage0Idx1_uid17996_dupName_138_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_34_i_c_compmm_m1229_q;
            1'b1 : rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17996_dupName_138_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x(MUX,18002)@142
    assign rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18001_dupName_138_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17998_dupName_138_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18001_dupName_138_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1232_vt_select_21(BITSELECT,10401)@142
    assign i_unnamed_c_compmm_m1232_vt_select_21_b = rightShiftStage1_uid18003_dupName_138_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1232_vt_join(BITJOIN,10400)@142
    assign i_unnamed_c_compmm_m1232_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1232_vt_select_21_b};

    // i_unnamed_c_compmm_m1233_sel_x(BITSELECT,6020)@142
    assign i_unnamed_c_compmm_m1233_sel_x_b = i_unnamed_c_compmm_m1232_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1234_BitSelect_for_a(BITSELECT,28392)@142
    assign i_unnamed_c_compmm_m1234_BitSelect_for_a_b = i_unnamed_c_compmm_m1233_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1234_join(BITJOIN,28393)@142
    assign i_unnamed_c_compmm_m1234_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1234_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1234_vt_select_0(BITSELECT,10406)@142
    assign i_unnamed_c_compmm_m1234_vt_select_0_b = i_unnamed_c_compmm_m1234_join_q[0:0];

    // redist238_i_unnamed_c_compmm_m1234_vt_select_0_b_1(DELAY,29366)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist238_i_unnamed_c_compmm_m1234_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1234_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1234_vt_join(BITJOIN,10405)@143
    assign i_unnamed_c_compmm_m1234_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist238_i_unnamed_c_compmm_m1234_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_34_c_compmm_m1235(ADD,7214)@143
    assign i_add_i_i_i_i_i_i_34_c_compmm_m1235_a = {1'b0, i_unnamed_c_compmm_m1234_vt_join_q};
    assign i_add_i_i_i_i_i_i_34_c_compmm_m1235_b = {1'b0, redist959_i_conv_i_i_i_i_i_34_c_compmm_m1231_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_34_c_compmm_m1235_o = $unsigned(i_add_i_i_i_i_i_i_34_c_compmm_m1235_a) + $unsigned(i_add_i_i_i_i_i_i_34_c_compmm_m1235_b);
    assign i_add_i_i_i_i_i_i_34_c_compmm_m1235_q = i_add_i_i_i_i_i_i_34_c_compmm_m1235_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_34_c_compmm_m1235_sel_x(BITSELECT,2228)@143
    assign bgTrunc_i_add_i_i_i_i_i_i_34_c_compmm_m1235_sel_x_b = i_add_i_i_i_i_i_i_34_c_compmm_m1235_q[15:0];

    // i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_sel_x(BITSELECT,3888)@143
    assign i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_34_c_compmm_m1235_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_select_15(BITSELECT,8279)@143
    assign i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_select_15_b = i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_join(BITJOIN,8278)@143
    assign i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_select_15_b};

    // leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(MUX,27052)@143
    assign leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_join_q or leftShiftStage0Idx1_uid27051_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_35_c_compmm_m1255_vt_join_q;
            1'b1 : leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27051_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(MUX,27057)@143
    assign leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s or leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27056_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = leftShiftStage0_uid27053_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27056_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x(MUX,27062)@143
    assign leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s or leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27061_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = leftShiftStage1_uid27058_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27061_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28(BITSELECT,10006)@143
    assign i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28_b = leftShiftStage2_uid27063_i_shl_i_i_i_i_i_i_35_c_compmm_m0_shift_x_q[28:13];

    // redist325_i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28_b_1(DELAY,29453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist325_i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_join(BITJOIN,10005)@144
    assign i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_join_q = {redist325_i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg185(REG,13480)@137 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg185_q <= $unsigned(redist794_sync_together4364_aunroll_x_in_i_valid_69_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6590_c_compmm_m186(BLACKBOX,8809)@138
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6590_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6590_c_compmm_m186 (
        .in_intel_reserved_ffwd_72_0(in_intel_reserved_ffwd_72_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg185_q),
        .out_dest_data_out_72_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6590_c_compmm_m186_out_dest_data_out_72_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt(ADD,32028)
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_a = {1'b0, redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_q};
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_o <= $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_a) + $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_b);
        end
    end
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_q = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_o[5:0];

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_inputreg0(DELAY,32023)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_inputreg0_q <= $unsigned(in_c1_eni5_71_tpl);
        end
    end

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem(DUALMEM,32025)
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_ia = $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_inputreg0_q);
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_aa = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_q;
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_ab = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_aa),
        .data_a(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_ab),
        .q_b(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_q = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_iq[15:0];

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_outputreg0(DELAY,32024)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_outputreg0_q <= $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_mem_q);
        end
    end

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_inputreg0(DELAY,32029)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_inputreg0_q <= $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_outputreg0_q);
        end
    end

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr(COUNTER,32026)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_i <= $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_q = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_i[4:0];

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem(DUALMEM,32031)
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_ia = $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_inputreg0_q);
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_aa = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_wraddr_q;
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_ab = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_aa),
        .data_a(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_ab),
        .q_b(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_q = redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_iq[15:0];

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_outputreg0(DELAY,32030)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_outputreg0_q <= $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_mem_q);
        end
    end

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_inputreg0(DELAY,30679)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_inputreg0_q <= $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_split_1_outputreg0_q);
        end
    end

    // redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70(DELAY,29701)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_delay_0 <= $unsigned(redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_inputreg0_q);
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_delay_1 <= redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_delay_0;
            redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_q <= redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_delay_1;
        end
    end

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt(ADD,32040)
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_a = {1'b0, redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_q};
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_o <= $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_a) + $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_b);
        end
    end
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_q = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_o[5:0];

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_inputreg0(DELAY,32035)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_inputreg0_q <= $unsigned(in_c1_eni5_72_tpl);
        end
    end

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem(DUALMEM,32037)
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_ia = $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_inputreg0_q);
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_aa = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_q;
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_ab = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_aa),
        .data_a(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_ab),
        .q_b(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_q = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_iq[15:0];

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_outputreg0(DELAY,32036)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_outputreg0_q <= $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_mem_q);
        end
    end

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_inputreg0(DELAY,32041)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_inputreg0_q <= $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_outputreg0_q);
        end
    end

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr(COUNTER,32038)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_i <= $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_q = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_i[4:0];

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem(DUALMEM,32043)
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_ia = $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_inputreg0_q);
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_aa = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_wraddr_q;
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_ab = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_aa),
        .data_a(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_ab),
        .q_b(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_q = redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_iq[15:0];

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_outputreg0(DELAY,32042)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_outputreg0_q <= $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_mem_q);
        end
    end

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_inputreg0(DELAY,30680)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_inputreg0_q <= $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_split_1_outputreg0_q);
        end
    end

    // redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70(DELAY,29702)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_delay_0 <= $unsigned(redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_inputreg0_q);
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_delay_1 <= redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_delay_0;
            redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_q <= redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_delay_1;
        end
    end

    // valid_fanout_reg186(REG,13481)@137 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg186_q <= $unsigned(redist794_sync_together4364_aunroll_x_in_i_valid_69_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6589_c_compmm_m187(BLACKBOX,8805)@138
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6589_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6589_c_compmm_m187 (
        .in_intel_reserved_ffwd_71_0(in_intel_reserved_ffwd_71_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg186_q),
        .out_dest_data_out_71_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6589_c_compmm_m187_out_dest_data_out_71_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28906)@138 + 5
    // out q@144
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6589_c_compmm_m187_out_dest_data_out_71_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6590_c_compmm_m186_out_dest_data_out_72_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257(ADD,9002)@144
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod457_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_b = $unsigned({{5{i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_35_c_compmm_m1256_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_o[33:0];

    // rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x(MUX,18041)@144
    assign rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q or rightShiftStage0Idx1_uid18040_dupName_141_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q;
            1'b1 : rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18040_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x(MUX,18046)@144
    assign rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18045_dupName_141_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18042_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18045_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x(MUX,18051)@144
    assign rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18050_dupName_141_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18047_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18050_dupName_141_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1258_vt_select_20(BITSELECT,10420)@144
    assign i_unnamed_c_compmm_m1258_vt_select_20_b = rightShiftStage2_uid18052_dupName_141_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1258_vt_join(BITJOIN,10419)@144
    assign i_unnamed_c_compmm_m1258_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1258_vt_select_20_b};

    // i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x(BITSELECT,3760)@144
    assign i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x_b = i_unnamed_c_compmm_m1258_vt_join_q[15:0];

    // redist958_i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x_b_1(DELAY,30086)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist958_i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18061_dupName_142_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18060)@144
    assign rightShiftStage1Idx1Rng8_uid18061_dupName_142_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18063_dupName_142_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18062)@144
    assign rightShiftStage1Idx1_uid18063_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18061_dupName_142_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18056_dupName_142_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18055)@144
    assign rightShiftStage0Idx1Rng4_uid18056_dupName_142_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q[33:4];

    // rightShiftStage0Idx1_uid18058_dupName_142_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18057)@144
    assign rightShiftStage0Idx1_uid18058_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18056_dupName_142_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x(MUX,18059)@144
    assign rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q or rightShiftStage0Idx1_uid18058_dupName_142_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_35_i_c_compmm_m1257_q;
            1'b1 : rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18058_dupName_142_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x(MUX,18064)@144
    assign rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18063_dupName_142_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18060_dupName_142_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18063_dupName_142_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1260_vt_select_21(BITSELECT,10423)@144
    assign i_unnamed_c_compmm_m1260_vt_select_21_b = rightShiftStage1_uid18065_dupName_142_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1260_vt_join(BITJOIN,10422)@144
    assign i_unnamed_c_compmm_m1260_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1260_vt_select_21_b};

    // i_unnamed_c_compmm_m1261_sel_x(BITSELECT,6022)@144
    assign i_unnamed_c_compmm_m1261_sel_x_b = i_unnamed_c_compmm_m1260_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1262_BitSelect_for_a(BITSELECT,28396)@144
    assign i_unnamed_c_compmm_m1262_BitSelect_for_a_b = i_unnamed_c_compmm_m1261_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1262_join(BITJOIN,28397)@144
    assign i_unnamed_c_compmm_m1262_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1262_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1262_vt_select_0(BITSELECT,10428)@144
    assign i_unnamed_c_compmm_m1262_vt_select_0_b = i_unnamed_c_compmm_m1262_join_q[0:0];

    // redist236_i_unnamed_c_compmm_m1262_vt_select_0_b_1(DELAY,29364)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist236_i_unnamed_c_compmm_m1262_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1262_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1262_vt_join(BITJOIN,10427)@145
    assign i_unnamed_c_compmm_m1262_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist236_i_unnamed_c_compmm_m1262_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_35_c_compmm_m1263(ADD,7215)@145
    assign i_add_i_i_i_i_i_i_35_c_compmm_m1263_a = {1'b0, i_unnamed_c_compmm_m1262_vt_join_q};
    assign i_add_i_i_i_i_i_i_35_c_compmm_m1263_b = {1'b0, redist958_i_conv_i_i_i_i_i_35_c_compmm_m1259_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_35_c_compmm_m1263_o = $unsigned(i_add_i_i_i_i_i_i_35_c_compmm_m1263_a) + $unsigned(i_add_i_i_i_i_i_i_35_c_compmm_m1263_b);
    assign i_add_i_i_i_i_i_i_35_c_compmm_m1263_q = i_add_i_i_i_i_i_i_35_c_compmm_m1263_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_35_c_compmm_m1263_sel_x(BITSELECT,2229)@145
    assign bgTrunc_i_add_i_i_i_i_i_i_35_c_compmm_m1263_sel_x_b = i_add_i_i_i_i_i_i_35_c_compmm_m1263_q[15:0];

    // i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_sel_x(BITSELECT,3889)@145
    assign i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_35_c_compmm_m1263_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_select_15(BITSELECT,8283)@145
    assign i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_select_15_b = i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_join(BITJOIN,8282)@145
    assign i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_select_15_b};

    // leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(MUX,27070)@145
    assign leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_join_q or leftShiftStage0Idx1_uid27069_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_36_c_compmm_m1283_vt_join_q;
            1'b1 : leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27069_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(MUX,27075)@145
    assign leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s or leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27074_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = leftShiftStage0_uid27071_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27074_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x(MUX,27080)@145
    assign leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s or leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27079_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = leftShiftStage1_uid27076_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27079_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28(BITSELECT,10009)@145
    assign i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28_b = leftShiftStage2_uid27081_i_shl_i_i_i_i_i_i_36_c_compmm_m0_shift_x_q[28:13];

    // redist324_i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28_b_1(DELAY,29452)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist324_i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_join(BITJOIN,10008)@146
    assign i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_join_q = {redist324_i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg183(REG,13478)@139 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg183_q <= $unsigned(redist795_sync_together4364_aunroll_x_in_i_valid_71_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6592_c_compmm_m184(BLACKBOX,8817)@140
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6592_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6592_c_compmm_m184 (
        .in_intel_reserved_ffwd_74_0(in_intel_reserved_ffwd_74_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg183_q),
        .out_dest_data_out_74_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6592_c_compmm_m184_out_dest_data_out_74_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt(ADD,30686)
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_a = {1'b0, redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_q};
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_b = {1'b0, redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_o <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_a) + $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_b);
        end
    end
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_q = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_o[2:0];

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt(ADD,32052)
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_a = {1'b0, redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_q};
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_o <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_a) + $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_b);
        end
    end
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_q = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_o[5:0];

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_inputreg0(DELAY,32047)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_inputreg0_q <= $unsigned(in_c1_eni5_73_tpl);
        end
    end

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem(DUALMEM,32049)
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_ia = $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_inputreg0_q);
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_aa = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_q;
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_ab = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_aa),
        .data_a(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_ab),
        .q_b(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_q = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_iq[15:0];

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_outputreg0(DELAY,32048)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_outputreg0_q <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_mem_q);
        end
    end

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_inputreg0(DELAY,32053)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_inputreg0_q <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_outputreg0_q);
        end
    end

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr(COUNTER,32050)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_i <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_q = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_i[4:0];

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem(DUALMEM,32055)
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_ia = $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_inputreg0_q);
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_aa = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_wraddr_q;
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_ab = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_aa),
        .data_a(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_ab),
        .q_b(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_q = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_iq[15:0];

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_outputreg0(DELAY,32054)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_outputreg0_q <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_mem_q);
        end
    end

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_inputreg0(DELAY,30681)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_inputreg0_q <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_split_1_outputreg0_q);
        end
    end

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr(COUNTER,30684)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_i <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_q = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_i[1:0];

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem(DUALMEM,30683)
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_ia = $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_inputreg0_q);
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_aa = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_wraddr_q;
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_ab = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_aa),
        .data_a(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_ab),
        .q_b(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_q = redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_iq[15:0];

    // redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_outputreg0(DELAY,30682)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_outputreg0_q <= $unsigned(redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_mem_q);
        end
    end

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt(ADD,30692)
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_a = {1'b0, redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_q};
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_b = {1'b0, redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_o <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_a) + $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_b);
        end
    end
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_q = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_o[2:0];

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt(ADD,32064)
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_a = {1'b0, redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_q};
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_o <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_a) + $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_b);
        end
    end
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_q = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_o[5:0];

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_inputreg0(DELAY,32059)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_inputreg0_q <= $unsigned(in_c1_eni5_74_tpl);
        end
    end

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem(DUALMEM,32061)
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_ia = $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_inputreg0_q);
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_aa = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_q;
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_ab = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_aa),
        .data_a(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_ab),
        .q_b(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_q = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_iq[15:0];

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_outputreg0(DELAY,32060)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_outputreg0_q <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_mem_q);
        end
    end

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_inputreg0(DELAY,32065)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_inputreg0_q <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_outputreg0_q);
        end
    end

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr(COUNTER,32062)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_i <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_q = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_i[4:0];

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem(DUALMEM,32067)
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_ia = $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_inputreg0_q);
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_aa = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_wraddr_q;
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_ab = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_aa),
        .data_a(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_ab),
        .q_b(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_q = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_iq[15:0];

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_outputreg0(DELAY,32066)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_outputreg0_q <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_mem_q);
        end
    end

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_inputreg0(DELAY,30687)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_inputreg0_q <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_split_1_outputreg0_q);
        end
    end

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr(COUNTER,30690)
    // low=0, high=3, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_i <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_i) + $unsigned(2'd1);
        end
    end
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_q = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_i[1:0];

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem(DUALMEM,30689)
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_ia = $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_inputreg0_q);
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_aa = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_wraddr_q;
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_ab = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_rdcnt_q[1:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(2),
        .numwords_a(4),
        .width_b(16),
        .widthad_b(2),
        .numwords_b(4),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_aa),
        .data_a(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_ab),
        .q_b(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_q = redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_iq[15:0];

    // redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_outputreg0(DELAY,30688)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_outputreg0_q <= $unsigned(redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_mem_q);
        end
    end

    // valid_fanout_reg184(REG,13479)@139 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg184_q <= $unsigned(redist795_sync_together4364_aunroll_x_in_i_valid_71_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6591_c_compmm_m185(BLACKBOX,8813)@140
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6591_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6591_c_compmm_m185 (
        .in_intel_reserved_ffwd_73_0(in_intel_reserved_ffwd_73_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg184_q),
        .out_dest_data_out_73_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6591_c_compmm_m185_out_dest_data_out_73_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28907)@140 + 5
    // out q@146
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6591_c_compmm_m185_out_dest_data_out_73_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6592_c_compmm_m184_out_dest_data_out_74_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285(ADD,9003)@146
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod462_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_b = $unsigned({{5{i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_36_c_compmm_m1284_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_o[33:0];

    // rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x(MUX,18103)@146
    assign rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q or rightShiftStage0Idx1_uid18102_dupName_145_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q;
            1'b1 : rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18102_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x(MUX,18108)@146
    assign rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18107_dupName_145_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18104_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18107_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x(MUX,18113)@146
    assign rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18112_dupName_145_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18109_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18112_dupName_145_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1286_vt_select_20(BITSELECT,10442)@146
    assign i_unnamed_c_compmm_m1286_vt_select_20_b = rightShiftStage2_uid18114_dupName_145_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1286_vt_join(BITJOIN,10441)@146
    assign i_unnamed_c_compmm_m1286_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1286_vt_select_20_b};

    // i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x(BITSELECT,3761)@146
    assign i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x_b = i_unnamed_c_compmm_m1286_vt_join_q[15:0];

    // redist957_i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x_b_1(DELAY,30085)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist957_i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18123_dupName_146_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18122)@146
    assign rightShiftStage1Idx1Rng8_uid18123_dupName_146_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18125_dupName_146_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18124)@146
    assign rightShiftStage1Idx1_uid18125_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18123_dupName_146_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18118_dupName_146_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18117)@146
    assign rightShiftStage0Idx1Rng4_uid18118_dupName_146_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q[33:4];

    // rightShiftStage0Idx1_uid18120_dupName_146_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18119)@146
    assign rightShiftStage0Idx1_uid18120_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18118_dupName_146_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x(MUX,18121)@146
    assign rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q or rightShiftStage0Idx1_uid18120_dupName_146_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_36_i_c_compmm_m1285_q;
            1'b1 : rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18120_dupName_146_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x(MUX,18126)@146
    assign rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18125_dupName_146_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18122_dupName_146_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18125_dupName_146_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1288_vt_select_21(BITSELECT,10445)@146
    assign i_unnamed_c_compmm_m1288_vt_select_21_b = rightShiftStage1_uid18127_dupName_146_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1288_vt_join(BITJOIN,10444)@146
    assign i_unnamed_c_compmm_m1288_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1288_vt_select_21_b};

    // i_unnamed_c_compmm_m1289_sel_x(BITSELECT,6024)@146
    assign i_unnamed_c_compmm_m1289_sel_x_b = i_unnamed_c_compmm_m1288_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1290_BitSelect_for_a(BITSELECT,28400)@146
    assign i_unnamed_c_compmm_m1290_BitSelect_for_a_b = i_unnamed_c_compmm_m1289_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1290_join(BITJOIN,28401)@146
    assign i_unnamed_c_compmm_m1290_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1290_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1290_vt_select_0(BITSELECT,10450)@146
    assign i_unnamed_c_compmm_m1290_vt_select_0_b = i_unnamed_c_compmm_m1290_join_q[0:0];

    // redist234_i_unnamed_c_compmm_m1290_vt_select_0_b_1(DELAY,29362)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist234_i_unnamed_c_compmm_m1290_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1290_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1290_vt_join(BITJOIN,10449)@147
    assign i_unnamed_c_compmm_m1290_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist234_i_unnamed_c_compmm_m1290_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_36_c_compmm_m1291(ADD,7216)@147
    assign i_add_i_i_i_i_i_i_36_c_compmm_m1291_a = {1'b0, i_unnamed_c_compmm_m1290_vt_join_q};
    assign i_add_i_i_i_i_i_i_36_c_compmm_m1291_b = {1'b0, redist957_i_conv_i_i_i_i_i_36_c_compmm_m1287_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_36_c_compmm_m1291_o = $unsigned(i_add_i_i_i_i_i_i_36_c_compmm_m1291_a) + $unsigned(i_add_i_i_i_i_i_i_36_c_compmm_m1291_b);
    assign i_add_i_i_i_i_i_i_36_c_compmm_m1291_q = i_add_i_i_i_i_i_i_36_c_compmm_m1291_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_36_c_compmm_m1291_sel_x(BITSELECT,2230)@147
    assign bgTrunc_i_add_i_i_i_i_i_i_36_c_compmm_m1291_sel_x_b = i_add_i_i_i_i_i_i_36_c_compmm_m1291_q[15:0];

    // i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_sel_x(BITSELECT,3890)@147
    assign i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_36_c_compmm_m1291_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_select_15(BITSELECT,8287)@147
    assign i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_select_15_b = i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_join(BITJOIN,8286)@147
    assign i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_select_15_b};

    // leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(MUX,27088)@147
    assign leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_join_q or leftShiftStage0Idx1_uid27087_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_37_c_compmm_m1311_vt_join_q;
            1'b1 : leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27087_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(MUX,27093)@147
    assign leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s or leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27092_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = leftShiftStage0_uid27089_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27092_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x(MUX,27098)@147
    assign leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s or leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27097_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = leftShiftStage1_uid27094_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27097_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28(BITSELECT,10012)@147
    assign i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28_b = leftShiftStage2_uid27099_i_shl_i_i_i_i_i_i_37_c_compmm_m0_shift_x_q[28:13];

    // redist323_i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28_b_1(DELAY,29451)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist323_i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_join(BITJOIN,10011)@148
    assign i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_join_q = {redist323_i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg181(REG,13476)@141 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg181_q <= $unsigned(redist796_sync_together4364_aunroll_x_in_i_valid_73_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6594_c_compmm_m182(BLACKBOX,8573)@142
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6594_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6594_c_compmm_m182 (
        .in_intel_reserved_ffwd_76_0(in_intel_reserved_ffwd_76_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg181_q),
        .out_dest_data_out_76_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6594_c_compmm_m182_out_dest_data_out_76_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt(ADD,30698)
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_a = {1'b0, redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_q};
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_b = {1'b0, redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_o <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_a) + $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_b);
        end
    end
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_q = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_o[3:0];

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt(ADD,32076)
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_a = {1'b0, redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_q};
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_o <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_a) + $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_b);
        end
    end
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_q = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_o[5:0];

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_inputreg0(DELAY,32071)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_inputreg0_q <= $unsigned(in_c1_eni5_75_tpl);
        end
    end

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem(DUALMEM,32073)
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_ia = $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_inputreg0_q);
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_aa = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_q;
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_ab = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_aa),
        .data_a(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_ab),
        .q_b(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_q = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_iq[15:0];

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_outputreg0(DELAY,32072)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_outputreg0_q <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_mem_q);
        end
    end

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_inputreg0(DELAY,32077)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_inputreg0_q <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_outputreg0_q);
        end
    end

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr(COUNTER,32074)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_i <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_q = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_i[4:0];

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem(DUALMEM,32079)
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_ia = $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_inputreg0_q);
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_aa = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_wraddr_q;
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_ab = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_aa),
        .data_a(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_ab),
        .q_b(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_q = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_iq[15:0];

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_outputreg0(DELAY,32078)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_outputreg0_q <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_mem_q);
        end
    end

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_inputreg0(DELAY,30693)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_inputreg0_q <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_split_1_outputreg0_q);
        end
    end

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr(COUNTER,30696)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_i <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_q = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_i[2:0];

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem(DUALMEM,30695)
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_ia = $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_inputreg0_q);
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_aa = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_wraddr_q;
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_ab = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_aa),
        .data_a(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_ab),
        .q_b(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_q = redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_iq[15:0];

    // redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_outputreg0(DELAY,30694)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_outputreg0_q <= $unsigned(redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_mem_q);
        end
    end

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt(ADD,30704)
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_a = {1'b0, redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_q};
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_b = {1'b0, redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_o <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_a) + $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_b);
        end
    end
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_q = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_o[3:0];

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt(ADD,32088)
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_a = {1'b0, redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_q};
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_o <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_a) + $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_b);
        end
    end
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_q = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_o[5:0];

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_inputreg0(DELAY,32083)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_inputreg0_q <= $unsigned(in_c1_eni5_76_tpl);
        end
    end

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem(DUALMEM,32085)
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_ia = $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_inputreg0_q);
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_aa = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_q;
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_ab = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_aa),
        .data_a(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_ab),
        .q_b(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_q = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_iq[15:0];

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_outputreg0(DELAY,32084)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_outputreg0_q <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_mem_q);
        end
    end

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_inputreg0(DELAY,32089)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_inputreg0_q <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_outputreg0_q);
        end
    end

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr(COUNTER,32086)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_i <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_q = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_i[4:0];

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem(DUALMEM,32091)
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_ia = $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_inputreg0_q);
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_aa = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_wraddr_q;
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_ab = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_aa),
        .data_a(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_ab),
        .q_b(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_q = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_iq[15:0];

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_outputreg0(DELAY,32090)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_outputreg0_q <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_mem_q);
        end
    end

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_inputreg0(DELAY,30699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_inputreg0_q <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_split_1_outputreg0_q);
        end
    end

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr(COUNTER,30702)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_i <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_q = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_i[2:0];

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem(DUALMEM,30701)
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_ia = $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_inputreg0_q);
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_aa = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_wraddr_q;
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_ab = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_aa),
        .data_a(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_ab),
        .q_b(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_q = redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_iq[15:0];

    // redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_outputreg0(DELAY,30700)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_outputreg0_q <= $unsigned(redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_mem_q);
        end
    end

    // valid_fanout_reg182(REG,13477)@141 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg182_q <= $unsigned(redist796_sync_together4364_aunroll_x_in_i_valid_73_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6593_c_compmm_m183(BLACKBOX,8569)@142
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6593_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6593_c_compmm_m183 (
        .in_intel_reserved_ffwd_75_0(in_intel_reserved_ffwd_75_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg182_q),
        .out_dest_data_out_75_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6593_c_compmm_m183_out_dest_data_out_75_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28908)@142 + 5
    // out q@148
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6593_c_compmm_m183_out_dest_data_out_75_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6594_c_compmm_m182_out_dest_data_out_76_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313(ADD,9004)@148
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod467_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_b = $unsigned({{5{i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_37_c_compmm_m1312_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_o[33:0];

    // rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x(MUX,18165)@148
    assign rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q or rightShiftStage0Idx1_uid18164_dupName_149_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q;
            1'b1 : rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18164_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x(MUX,18170)@148
    assign rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18169_dupName_149_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18166_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18169_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x(MUX,18175)@148
    assign rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18174_dupName_149_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18171_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18174_dupName_149_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1314_vt_select_20(BITSELECT,10464)@148
    assign i_unnamed_c_compmm_m1314_vt_select_20_b = rightShiftStage2_uid18176_dupName_149_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1314_vt_join(BITJOIN,10463)@148
    assign i_unnamed_c_compmm_m1314_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1314_vt_select_20_b};

    // i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x(BITSELECT,3762)@148
    assign i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x_b = i_unnamed_c_compmm_m1314_vt_join_q[15:0];

    // redist956_i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x_b_1(DELAY,30084)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist956_i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18185_dupName_150_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18184)@148
    assign rightShiftStage1Idx1Rng8_uid18185_dupName_150_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18187_dupName_150_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18186)@148
    assign rightShiftStage1Idx1_uid18187_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18185_dupName_150_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18180_dupName_150_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18179)@148
    assign rightShiftStage0Idx1Rng4_uid18180_dupName_150_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q[33:4];

    // rightShiftStage0Idx1_uid18182_dupName_150_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18181)@148
    assign rightShiftStage0Idx1_uid18182_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18180_dupName_150_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x(MUX,18183)@148
    assign rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q or rightShiftStage0Idx1_uid18182_dupName_150_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_37_i_c_compmm_m1313_q;
            1'b1 : rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18182_dupName_150_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x(MUX,18188)@148
    assign rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18187_dupName_150_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18184_dupName_150_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18187_dupName_150_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1316_vt_select_21(BITSELECT,10467)@148
    assign i_unnamed_c_compmm_m1316_vt_select_21_b = rightShiftStage1_uid18189_dupName_150_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1316_vt_join(BITJOIN,10466)@148
    assign i_unnamed_c_compmm_m1316_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1316_vt_select_21_b};

    // i_unnamed_c_compmm_m1317_sel_x(BITSELECT,6026)@148
    assign i_unnamed_c_compmm_m1317_sel_x_b = i_unnamed_c_compmm_m1316_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1318_BitSelect_for_a(BITSELECT,28404)@148
    assign i_unnamed_c_compmm_m1318_BitSelect_for_a_b = i_unnamed_c_compmm_m1317_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1318_join(BITJOIN,28405)@148
    assign i_unnamed_c_compmm_m1318_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1318_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1318_vt_select_0(BITSELECT,10472)@148
    assign i_unnamed_c_compmm_m1318_vt_select_0_b = i_unnamed_c_compmm_m1318_join_q[0:0];

    // redist232_i_unnamed_c_compmm_m1318_vt_select_0_b_1(DELAY,29360)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist232_i_unnamed_c_compmm_m1318_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1318_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1318_vt_join(BITJOIN,10471)@149
    assign i_unnamed_c_compmm_m1318_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist232_i_unnamed_c_compmm_m1318_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_37_c_compmm_m1319(ADD,7217)@149
    assign i_add_i_i_i_i_i_i_37_c_compmm_m1319_a = {1'b0, i_unnamed_c_compmm_m1318_vt_join_q};
    assign i_add_i_i_i_i_i_i_37_c_compmm_m1319_b = {1'b0, redist956_i_conv_i_i_i_i_i_37_c_compmm_m1315_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_37_c_compmm_m1319_o = $unsigned(i_add_i_i_i_i_i_i_37_c_compmm_m1319_a) + $unsigned(i_add_i_i_i_i_i_i_37_c_compmm_m1319_b);
    assign i_add_i_i_i_i_i_i_37_c_compmm_m1319_q = i_add_i_i_i_i_i_i_37_c_compmm_m1319_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_37_c_compmm_m1319_sel_x(BITSELECT,2231)@149
    assign bgTrunc_i_add_i_i_i_i_i_i_37_c_compmm_m1319_sel_x_b = i_add_i_i_i_i_i_i_37_c_compmm_m1319_q[15:0];

    // i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_sel_x(BITSELECT,3891)@149
    assign i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_37_c_compmm_m1319_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_select_15(BITSELECT,8291)@149
    assign i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_select_15_b = i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_join(BITJOIN,8290)@149
    assign i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_select_15_b};

    // leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(MUX,27106)@149
    assign leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_join_q or leftShiftStage0Idx1_uid27105_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_38_c_compmm_m1339_vt_join_q;
            1'b1 : leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27105_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(MUX,27111)@149
    assign leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s or leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27110_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = leftShiftStage0_uid27107_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27110_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x(MUX,27116)@149
    assign leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s or leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27115_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = leftShiftStage1_uid27112_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27115_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28(BITSELECT,10015)@149
    assign i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28_b = leftShiftStage2_uid27117_i_shl_i_i_i_i_i_i_38_c_compmm_m0_shift_x_q[28:13];

    // redist322_i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28_b_1(DELAY,29450)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist322_i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_join(BITJOIN,10014)@150
    assign i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_join_q = {redist322_i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg179(REG,13474)@143 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg179_q <= $unsigned(redist797_sync_together4364_aunroll_x_in_i_valid_75_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6596_c_compmm_m180(BLACKBOX,8581)@144
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6596_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6596_c_compmm_m180 (
        .in_intel_reserved_ffwd_78_0(in_intel_reserved_ffwd_78_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg179_q),
        .out_dest_data_out_78_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6596_c_compmm_m180_out_dest_data_out_78_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt(ADD,30710)
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_a = {1'b0, redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_q};
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_b = {1'b0, redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_o <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_a) + $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_b);
        end
    end
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_q = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_o[3:0];

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt(ADD,32100)
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_a = {1'b0, redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_q};
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_o <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_a) + $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_b);
        end
    end
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_q = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_o[5:0];

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_inputreg0(DELAY,32095)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_inputreg0_q <= $unsigned(in_c1_eni5_77_tpl);
        end
    end

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem(DUALMEM,32097)
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_ia = $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_inputreg0_q);
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_aa = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_q;
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_ab = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_aa),
        .data_a(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_ab),
        .q_b(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_q = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_iq[15:0];

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_outputreg0(DELAY,32096)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_outputreg0_q <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_mem_q);
        end
    end

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_inputreg0(DELAY,32101)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_inputreg0_q <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_outputreg0_q);
        end
    end

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr(COUNTER,32098)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_i <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_q = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_i[4:0];

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem(DUALMEM,32103)
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_ia = $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_inputreg0_q);
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_aa = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_wraddr_q;
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_ab = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_aa),
        .data_a(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_ab),
        .q_b(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_q = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_iq[15:0];

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_outputreg0(DELAY,32102)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_outputreg0_q <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_mem_q);
        end
    end

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_inputreg0(DELAY,30705)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_inputreg0_q <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_split_1_outputreg0_q);
        end
    end

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr(COUNTER,30708)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_i <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_q = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_i[2:0];

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem(DUALMEM,30707)
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_ia = $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_inputreg0_q);
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_aa = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_wraddr_q;
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_ab = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_aa),
        .data_a(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_ab),
        .q_b(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_q = redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_iq[15:0];

    // redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_outputreg0(DELAY,30706)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_outputreg0_q <= $unsigned(redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_mem_q);
        end
    end

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt(ADD,30716)
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_a = {1'b0, redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_q};
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_b = {1'b0, redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_o <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_a) + $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_b);
        end
    end
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_q = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_o[3:0];

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt(ADD,32112)
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_a = {1'b0, redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_q};
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_o <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_a) + $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_b);
        end
    end
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_q = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_o[5:0];

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_inputreg0(DELAY,32107)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_inputreg0_q <= $unsigned(in_c1_eni5_78_tpl);
        end
    end

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem(DUALMEM,32109)
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_ia = $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_inputreg0_q);
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_aa = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_q;
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_ab = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_aa),
        .data_a(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_ab),
        .q_b(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_q = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_iq[15:0];

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_outputreg0(DELAY,32108)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_outputreg0_q <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_mem_q);
        end
    end

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_inputreg0(DELAY,32113)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_inputreg0_q <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_outputreg0_q);
        end
    end

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr(COUNTER,32110)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_i <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_q = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_i[4:0];

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem(DUALMEM,32115)
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_ia = $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_inputreg0_q);
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_aa = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_wraddr_q;
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_ab = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_aa),
        .data_a(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_ab),
        .q_b(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_q = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_iq[15:0];

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_outputreg0(DELAY,32114)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_outputreg0_q <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_mem_q);
        end
    end

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_inputreg0(DELAY,30711)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_inputreg0_q <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_split_1_outputreg0_q);
        end
    end

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr(COUNTER,30714)
    // low=0, high=7, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_i <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_i) + $unsigned(3'd1);
        end
    end
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_q = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_i[2:0];

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem(DUALMEM,30713)
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_ia = $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_inputreg0_q);
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_aa = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_wraddr_q;
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_ab = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_rdcnt_q[2:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(3),
        .numwords_a(8),
        .width_b(16),
        .widthad_b(3),
        .numwords_b(8),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_aa),
        .data_a(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_ab),
        .q_b(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_q = redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_iq[15:0];

    // redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_outputreg0(DELAY,30712)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_outputreg0_q <= $unsigned(redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_mem_q);
        end
    end

    // valid_fanout_reg180(REG,13475)@143 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg180_q <= $unsigned(redist797_sync_together4364_aunroll_x_in_i_valid_75_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6595_c_compmm_m181(BLACKBOX,8577)@144
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6595_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6595_c_compmm_m181 (
        .in_intel_reserved_ffwd_77_0(in_intel_reserved_ffwd_77_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg180_q),
        .out_dest_data_out_77_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6595_c_compmm_m181_out_dest_data_out_77_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28909)@144 + 5
    // out q@150
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6595_c_compmm_m181_out_dest_data_out_77_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6596_c_compmm_m180_out_dest_data_out_78_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341(ADD,9005)@150
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod472_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_b = $unsigned({{5{i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_38_c_compmm_m1340_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_o[33:0];

    // rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x(MUX,18227)@150
    assign rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q or rightShiftStage0Idx1_uid18226_dupName_153_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q;
            1'b1 : rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18226_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x(MUX,18232)@150
    assign rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18231_dupName_153_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18228_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18231_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x(MUX,18237)@150
    assign rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18236_dupName_153_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18233_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18236_dupName_153_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1342_vt_select_20(BITSELECT,10486)@150
    assign i_unnamed_c_compmm_m1342_vt_select_20_b = rightShiftStage2_uid18238_dupName_153_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1342_vt_join(BITJOIN,10485)@150
    assign i_unnamed_c_compmm_m1342_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1342_vt_select_20_b};

    // i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x(BITSELECT,3763)@150
    assign i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x_b = i_unnamed_c_compmm_m1342_vt_join_q[15:0];

    // redist955_i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x_b_1(DELAY,30083)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist955_i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18247_dupName_154_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18246)@150
    assign rightShiftStage1Idx1Rng8_uid18247_dupName_154_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18249_dupName_154_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18248)@150
    assign rightShiftStage1Idx1_uid18249_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18247_dupName_154_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18242_dupName_154_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18241)@150
    assign rightShiftStage0Idx1Rng4_uid18242_dupName_154_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q[33:4];

    // rightShiftStage0Idx1_uid18244_dupName_154_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18243)@150
    assign rightShiftStage0Idx1_uid18244_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18242_dupName_154_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x(MUX,18245)@150
    assign rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q or rightShiftStage0Idx1_uid18244_dupName_154_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_38_i_c_compmm_m1341_q;
            1'b1 : rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18244_dupName_154_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x(MUX,18250)@150
    assign rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18249_dupName_154_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18246_dupName_154_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18249_dupName_154_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1344_vt_select_21(BITSELECT,10489)@150
    assign i_unnamed_c_compmm_m1344_vt_select_21_b = rightShiftStage1_uid18251_dupName_154_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1344_vt_join(BITJOIN,10488)@150
    assign i_unnamed_c_compmm_m1344_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1344_vt_select_21_b};

    // i_unnamed_c_compmm_m1345_sel_x(BITSELECT,6028)@150
    assign i_unnamed_c_compmm_m1345_sel_x_b = i_unnamed_c_compmm_m1344_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1346_BitSelect_for_a(BITSELECT,28408)@150
    assign i_unnamed_c_compmm_m1346_BitSelect_for_a_b = i_unnamed_c_compmm_m1345_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1346_join(BITJOIN,28409)@150
    assign i_unnamed_c_compmm_m1346_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1346_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1346_vt_select_0(BITSELECT,10494)@150
    assign i_unnamed_c_compmm_m1346_vt_select_0_b = i_unnamed_c_compmm_m1346_join_q[0:0];

    // redist230_i_unnamed_c_compmm_m1346_vt_select_0_b_1(DELAY,29358)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist230_i_unnamed_c_compmm_m1346_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1346_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1346_vt_join(BITJOIN,10493)@151
    assign i_unnamed_c_compmm_m1346_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist230_i_unnamed_c_compmm_m1346_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_38_c_compmm_m1347(ADD,7218)@151
    assign i_add_i_i_i_i_i_i_38_c_compmm_m1347_a = {1'b0, i_unnamed_c_compmm_m1346_vt_join_q};
    assign i_add_i_i_i_i_i_i_38_c_compmm_m1347_b = {1'b0, redist955_i_conv_i_i_i_i_i_38_c_compmm_m1343_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_38_c_compmm_m1347_o = $unsigned(i_add_i_i_i_i_i_i_38_c_compmm_m1347_a) + $unsigned(i_add_i_i_i_i_i_i_38_c_compmm_m1347_b);
    assign i_add_i_i_i_i_i_i_38_c_compmm_m1347_q = i_add_i_i_i_i_i_i_38_c_compmm_m1347_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_38_c_compmm_m1347_sel_x(BITSELECT,2232)@151
    assign bgTrunc_i_add_i_i_i_i_i_i_38_c_compmm_m1347_sel_x_b = i_add_i_i_i_i_i_i_38_c_compmm_m1347_q[15:0];

    // i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_sel_x(BITSELECT,3892)@151
    assign i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_38_c_compmm_m1347_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_select_15(BITSELECT,8295)@151
    assign i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_select_15_b = i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_join(BITJOIN,8294)@151
    assign i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_select_15_b};

    // leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(MUX,27124)@151
    assign leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_join_q or leftShiftStage0Idx1_uid27123_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_39_c_compmm_m1367_vt_join_q;
            1'b1 : leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27123_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(MUX,27129)@151
    assign leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s or leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27128_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = leftShiftStage0_uid27125_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27128_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x(MUX,27134)@151
    assign leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s or leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27133_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = leftShiftStage1_uid27130_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27133_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28(BITSELECT,10018)@151
    assign i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28_b = leftShiftStage2_uid27135_i_shl_i_i_i_i_i_i_39_c_compmm_m0_shift_x_q[28:13];

    // redist321_i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28_b_1(DELAY,29449)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist321_i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_join(BITJOIN,10017)@152
    assign i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_join_q = {redist321_i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg177(REG,13472)@145 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg177_q <= $unsigned(redist798_sync_together4364_aunroll_x_in_i_valid_77_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6598_c_compmm_m178(BLACKBOX,8589)@146
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6598_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6598_c_compmm_m178 (
        .in_intel_reserved_ffwd_80_0(in_intel_reserved_ffwd_80_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg177_q),
        .out_dest_data_out_80_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6598_c_compmm_m178_out_dest_data_out_80_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt(ADD,30722)
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_a = {1'b0, redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_q};
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_b = {1'b0, redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_o <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_a) + $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_b);
        end
    end
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_q = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_o[4:0];

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt(ADD,32124)
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_a = {1'b0, redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_q};
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_o <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_a) + $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_b);
        end
    end
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_q = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_o[5:0];

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_inputreg0(DELAY,32119)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_inputreg0_q <= $unsigned(in_c1_eni5_79_tpl);
        end
    end

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem(DUALMEM,32121)
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_ia = $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_inputreg0_q);
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_aa = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_q;
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_ab = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_aa),
        .data_a(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_ab),
        .q_b(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_q = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_iq[15:0];

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_outputreg0(DELAY,32120)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_outputreg0_q <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_mem_q);
        end
    end

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_inputreg0(DELAY,32125)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_inputreg0_q <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_outputreg0_q);
        end
    end

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr(COUNTER,32122)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_i <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_q = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_i[4:0];

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem(DUALMEM,32127)
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_ia = $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_inputreg0_q);
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_aa = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_wraddr_q;
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_ab = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_aa),
        .data_a(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_ab),
        .q_b(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_q = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_iq[15:0];

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_outputreg0(DELAY,32126)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_outputreg0_q <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_mem_q);
        end
    end

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_inputreg0(DELAY,30717)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_inputreg0_q <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_split_1_outputreg0_q);
        end
    end

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr(COUNTER,30720)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_i <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_q = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_i[3:0];

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem(DUALMEM,30719)
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_ia = $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_inputreg0_q);
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_aa = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_wraddr_q;
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_ab = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_aa),
        .data_a(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_ab),
        .q_b(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_q = redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_iq[15:0];

    // redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_outputreg0(DELAY,30718)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_outputreg0_q <= $unsigned(redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_mem_q);
        end
    end

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt(ADD,30728)
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_a = {1'b0, redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_q};
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_b = {1'b0, redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_o <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_a) + $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_b);
        end
    end
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_q = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_o[4:0];

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt(ADD,32136)
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_a = {1'b0, redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_q};
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_o <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_a) + $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_b);
        end
    end
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_q = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_o[5:0];

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_inputreg0(DELAY,32131)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_inputreg0_q <= $unsigned(in_c1_eni5_80_tpl);
        end
    end

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem(DUALMEM,32133)
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_ia = $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_inputreg0_q);
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_aa = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_q;
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_ab = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_aa),
        .data_a(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_ab),
        .q_b(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_q = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_iq[15:0];

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_outputreg0(DELAY,32132)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_outputreg0_q <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_mem_q);
        end
    end

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_inputreg0(DELAY,32137)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_inputreg0_q <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_outputreg0_q);
        end
    end

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr(COUNTER,32134)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_i <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_q = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_i[4:0];

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem(DUALMEM,32139)
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_ia = $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_inputreg0_q);
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_aa = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_wraddr_q;
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_ab = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_aa),
        .data_a(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_ab),
        .q_b(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_q = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_iq[15:0];

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_outputreg0(DELAY,32138)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_outputreg0_q <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_mem_q);
        end
    end

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_inputreg0(DELAY,30723)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_inputreg0_q <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_split_1_outputreg0_q);
        end
    end

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr(COUNTER,30726)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_i <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_q = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_i[3:0];

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem(DUALMEM,30725)
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_ia = $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_inputreg0_q);
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_aa = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_wraddr_q;
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_ab = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_aa),
        .data_a(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_ab),
        .q_b(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_q = redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_iq[15:0];

    // redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_outputreg0(DELAY,30724)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_outputreg0_q <= $unsigned(redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_mem_q);
        end
    end

    // valid_fanout_reg178(REG,13473)@145 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg178_q <= $unsigned(redist798_sync_together4364_aunroll_x_in_i_valid_77_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6597_c_compmm_m179(BLACKBOX,8585)@146
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6597_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6597_c_compmm_m179 (
        .in_intel_reserved_ffwd_79_0(in_intel_reserved_ffwd_79_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg178_q),
        .out_dest_data_out_79_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6597_c_compmm_m179_out_dest_data_out_79_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28910)@146 + 5
    // out q@152
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6597_c_compmm_m179_out_dest_data_out_79_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6598_c_compmm_m178_out_dest_data_out_80_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369(ADD,9006)@152
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod477_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_b = $unsigned({{5{i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_39_c_compmm_m1368_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_o[33:0];

    // rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x(MUX,18289)@152
    assign rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q or rightShiftStage0Idx1_uid18288_dupName_157_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q;
            1'b1 : rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18288_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x(MUX,18294)@152
    assign rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18293_dupName_157_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18290_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18293_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x(MUX,18299)@152
    assign rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18298_dupName_157_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18295_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18298_dupName_157_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1370_vt_select_20(BITSELECT,10508)@152
    assign i_unnamed_c_compmm_m1370_vt_select_20_b = rightShiftStage2_uid18300_dupName_157_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1370_vt_join(BITJOIN,10507)@152
    assign i_unnamed_c_compmm_m1370_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1370_vt_select_20_b};

    // i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x(BITSELECT,3764)@152
    assign i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x_b = i_unnamed_c_compmm_m1370_vt_join_q[15:0];

    // redist954_i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x_b_1(DELAY,30082)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist954_i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18309_dupName_158_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18308)@152
    assign rightShiftStage1Idx1Rng8_uid18309_dupName_158_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18311_dupName_158_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18310)@152
    assign rightShiftStage1Idx1_uid18311_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18309_dupName_158_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18304_dupName_158_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18303)@152
    assign rightShiftStage0Idx1Rng4_uid18304_dupName_158_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q[33:4];

    // rightShiftStage0Idx1_uid18306_dupName_158_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18305)@152
    assign rightShiftStage0Idx1_uid18306_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18304_dupName_158_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x(MUX,18307)@152
    assign rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q or rightShiftStage0Idx1_uid18306_dupName_158_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_39_i_c_compmm_m1369_q;
            1'b1 : rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18306_dupName_158_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x(MUX,18312)@152
    assign rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18311_dupName_158_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18308_dupName_158_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18311_dupName_158_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1372_vt_select_21(BITSELECT,10511)@152
    assign i_unnamed_c_compmm_m1372_vt_select_21_b = rightShiftStage1_uid18313_dupName_158_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1372_vt_join(BITJOIN,10510)@152
    assign i_unnamed_c_compmm_m1372_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1372_vt_select_21_b};

    // i_unnamed_c_compmm_m1373_sel_x(BITSELECT,6030)@152
    assign i_unnamed_c_compmm_m1373_sel_x_b = i_unnamed_c_compmm_m1372_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1374_BitSelect_for_a(BITSELECT,28412)@152
    assign i_unnamed_c_compmm_m1374_BitSelect_for_a_b = i_unnamed_c_compmm_m1373_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1374_join(BITJOIN,28413)@152
    assign i_unnamed_c_compmm_m1374_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1374_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1374_vt_select_0(BITSELECT,10516)@152
    assign i_unnamed_c_compmm_m1374_vt_select_0_b = i_unnamed_c_compmm_m1374_join_q[0:0];

    // redist228_i_unnamed_c_compmm_m1374_vt_select_0_b_1(DELAY,29356)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist228_i_unnamed_c_compmm_m1374_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1374_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1374_vt_join(BITJOIN,10515)@153
    assign i_unnamed_c_compmm_m1374_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist228_i_unnamed_c_compmm_m1374_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_39_c_compmm_m1375(ADD,7219)@153
    assign i_add_i_i_i_i_i_i_39_c_compmm_m1375_a = {1'b0, i_unnamed_c_compmm_m1374_vt_join_q};
    assign i_add_i_i_i_i_i_i_39_c_compmm_m1375_b = {1'b0, redist954_i_conv_i_i_i_i_i_39_c_compmm_m1371_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_39_c_compmm_m1375_o = $unsigned(i_add_i_i_i_i_i_i_39_c_compmm_m1375_a) + $unsigned(i_add_i_i_i_i_i_i_39_c_compmm_m1375_b);
    assign i_add_i_i_i_i_i_i_39_c_compmm_m1375_q = i_add_i_i_i_i_i_i_39_c_compmm_m1375_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_39_c_compmm_m1375_sel_x(BITSELECT,2233)@153
    assign bgTrunc_i_add_i_i_i_i_i_i_39_c_compmm_m1375_sel_x_b = i_add_i_i_i_i_i_i_39_c_compmm_m1375_q[15:0];

    // i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_sel_x(BITSELECT,3894)@153
    assign i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_39_c_compmm_m1375_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_select_15(BITSELECT,8303)@153
    assign i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_select_15_b = i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_join(BITJOIN,8302)@153
    assign i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_select_15_b};

    // leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(MUX,27160)@153
    assign leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_join_q or leftShiftStage0Idx1_uid27159_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_40_c_compmm_m1395_vt_join_q;
            1'b1 : leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27159_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(MUX,27165)@153
    assign leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s or leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27164_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = leftShiftStage0_uid27161_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27164_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x(MUX,27170)@153
    assign leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s or leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27169_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = leftShiftStage1_uid27166_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27169_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28(BITSELECT,10024)@153
    assign i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28_b = leftShiftStage2_uid27171_i_shl_i_i_i_i_i_i_40_c_compmm_m0_shift_x_q[28:13];

    // redist319_i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28_b_1(DELAY,29447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist319_i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_join(BITJOIN,10023)@154
    assign i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_join_q = {redist319_i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg175(REG,13470)@147 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg175_q <= $unsigned(redist799_sync_together4364_aunroll_x_in_i_valid_79_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_65100_c_compmm_m176(BLACKBOX,8597)@148
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65100_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_65100_c_compmm_m176 (
        .in_intel_reserved_ffwd_82_0(in_intel_reserved_ffwd_82_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg175_q),
        .out_dest_data_out_82_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_65100_c_compmm_m176_out_dest_data_out_82_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt(ADD,30734)
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_a = {1'b0, redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_q};
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_b = {1'b0, redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_o <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_a) + $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_b);
        end
    end
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_q = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_o[4:0];

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt(ADD,32148)
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_a = {1'b0, redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_q};
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_o <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_a) + $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_b);
        end
    end
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_q = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_o[5:0];

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_inputreg0(DELAY,32143)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_inputreg0_q <= $unsigned(in_c1_eni5_81_tpl);
        end
    end

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem(DUALMEM,32145)
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_ia = $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_inputreg0_q);
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_aa = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_q;
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_ab = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_aa),
        .data_a(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_ab),
        .q_b(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_q = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_iq[15:0];

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_outputreg0(DELAY,32144)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_outputreg0_q <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_mem_q);
        end
    end

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_inputreg0(DELAY,32149)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_inputreg0_q <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_outputreg0_q);
        end
    end

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr(COUNTER,32146)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_i <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_q = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_i[4:0];

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem(DUALMEM,32151)
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_ia = $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_inputreg0_q);
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_aa = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_wraddr_q;
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_ab = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_aa),
        .data_a(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_ab),
        .q_b(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_q = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_iq[15:0];

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_outputreg0(DELAY,32150)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_outputreg0_q <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_mem_q);
        end
    end

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_inputreg0(DELAY,30729)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_inputreg0_q <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_split_1_outputreg0_q);
        end
    end

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr(COUNTER,30732)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_i <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_q = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_i[3:0];

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem(DUALMEM,30731)
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_ia = $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_inputreg0_q);
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_aa = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_wraddr_q;
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_ab = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_aa),
        .data_a(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_ab),
        .q_b(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_q = redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_iq[15:0];

    // redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_outputreg0(DELAY,30730)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_outputreg0_q <= $unsigned(redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_mem_q);
        end
    end

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt(ADD,30740)
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_a = {1'b0, redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_q};
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_b = {1'b0, redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_o <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_a) + $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_b);
        end
    end
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_q = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_o[4:0];

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt(ADD,32160)
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_a = {1'b0, redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_q};
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_b = {1'b0, redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_o <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_a) + $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_b);
        end
    end
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_q = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_o[5:0];

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_inputreg0(DELAY,32155)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_inputreg0_q <= $unsigned(in_c1_eni5_82_tpl);
        end
    end

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem(DUALMEM,32157)
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_ia = $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_inputreg0_q);
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_aa = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_q;
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_ab = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_aa),
        .data_a(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_ab),
        .q_b(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_q = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_iq[15:0];

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_outputreg0(DELAY,32156)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_outputreg0_q <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_mem_q);
        end
    end

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_inputreg0(DELAY,32161)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_inputreg0_q <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_outputreg0_q);
        end
    end

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr(COUNTER,32158)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_i <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_q = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_i[4:0];

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem(DUALMEM,32163)
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_ia = $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_inputreg0_q);
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_aa = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_wraddr_q;
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_ab = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_aa),
        .data_a(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_ab),
        .q_b(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_q = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_iq[15:0];

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_outputreg0(DELAY,32162)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_outputreg0_q <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_mem_q);
        end
    end

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_inputreg0(DELAY,30735)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_inputreg0_q <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_split_1_outputreg0_q);
        end
    end

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr(COUNTER,30738)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_i <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_q = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_i[3:0];

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem(DUALMEM,30737)
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_ia = $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_inputreg0_q);
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_aa = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_wraddr_q;
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_ab = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_aa),
        .data_a(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_ab),
        .q_b(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_q = redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_iq[15:0];

    // redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_outputreg0(DELAY,30736)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_outputreg0_q <= $unsigned(redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_mem_q);
        end
    end

    // valid_fanout_reg176(REG,13471)@147 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg176_q <= $unsigned(redist799_sync_together4364_aunroll_x_in_i_valid_79_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6599_c_compmm_m177(BLACKBOX,8593)@148
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000que_6599_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6599_c_compmm_m177 (
        .in_intel_reserved_ffwd_81_0(in_intel_reserved_ffwd_81_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg176_q),
        .out_dest_data_out_81_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6599_c_compmm_m177_out_dest_data_out_81_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28911)@148 + 5
    // out q@154
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6599_c_compmm_m177_out_dest_data_out_81_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_65100_c_compmm_m176_out_dest_data_out_82_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397(ADD,9008)@154
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod482_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_b = $unsigned({{5{i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_40_c_compmm_m1396_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_o[33:0];

    // rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x(MUX,18351)@154
    assign rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q or rightShiftStage0Idx1_uid18350_dupName_161_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q;
            1'b1 : rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18350_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x(MUX,18356)@154
    assign rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18355_dupName_161_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18352_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18355_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x(MUX,18361)@154
    assign rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18360_dupName_161_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18357_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18360_dupName_161_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1398_vt_select_20(BITSELECT,10530)@154
    assign i_unnamed_c_compmm_m1398_vt_select_20_b = rightShiftStage2_uid18362_dupName_161_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1398_vt_join(BITJOIN,10529)@154
    assign i_unnamed_c_compmm_m1398_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1398_vt_select_20_b};

    // i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x(BITSELECT,3766)@154
    assign i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x_b = i_unnamed_c_compmm_m1398_vt_join_q[15:0];

    // redist952_i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x_b_1(DELAY,30080)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist952_i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18371_dupName_162_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18370)@154
    assign rightShiftStage1Idx1Rng8_uid18371_dupName_162_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18373_dupName_162_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18372)@154
    assign rightShiftStage1Idx1_uid18373_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18371_dupName_162_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18366_dupName_162_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18365)@154
    assign rightShiftStage0Idx1Rng4_uid18366_dupName_162_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q[33:4];

    // rightShiftStage0Idx1_uid18368_dupName_162_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18367)@154
    assign rightShiftStage0Idx1_uid18368_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18366_dupName_162_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x(MUX,18369)@154
    assign rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q or rightShiftStage0Idx1_uid18368_dupName_162_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_40_i_c_compmm_m1397_q;
            1'b1 : rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18368_dupName_162_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x(MUX,18374)@154
    assign rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18373_dupName_162_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18370_dupName_162_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18373_dupName_162_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1400_vt_select_21(BITSELECT,10533)@154
    assign i_unnamed_c_compmm_m1400_vt_select_21_b = rightShiftStage1_uid18375_dupName_162_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1400_vt_join(BITJOIN,10532)@154
    assign i_unnamed_c_compmm_m1400_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1400_vt_select_21_b};

    // i_unnamed_c_compmm_m1401_sel_x(BITSELECT,6032)@154
    assign i_unnamed_c_compmm_m1401_sel_x_b = i_unnamed_c_compmm_m1400_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1402_BitSelect_for_a(BITSELECT,28416)@154
    assign i_unnamed_c_compmm_m1402_BitSelect_for_a_b = i_unnamed_c_compmm_m1401_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1402_join(BITJOIN,28417)@154
    assign i_unnamed_c_compmm_m1402_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1402_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1402_vt_select_0(BITSELECT,10538)@154
    assign i_unnamed_c_compmm_m1402_vt_select_0_b = i_unnamed_c_compmm_m1402_join_q[0:0];

    // redist226_i_unnamed_c_compmm_m1402_vt_select_0_b_1(DELAY,29354)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist226_i_unnamed_c_compmm_m1402_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1402_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1402_vt_join(BITJOIN,10537)@155
    assign i_unnamed_c_compmm_m1402_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist226_i_unnamed_c_compmm_m1402_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_40_c_compmm_m1403(ADD,7221)@155
    assign i_add_i_i_i_i_i_i_40_c_compmm_m1403_a = {1'b0, i_unnamed_c_compmm_m1402_vt_join_q};
    assign i_add_i_i_i_i_i_i_40_c_compmm_m1403_b = {1'b0, redist952_i_conv_i_i_i_i_i_40_c_compmm_m1399_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_40_c_compmm_m1403_o = $unsigned(i_add_i_i_i_i_i_i_40_c_compmm_m1403_a) + $unsigned(i_add_i_i_i_i_i_i_40_c_compmm_m1403_b);
    assign i_add_i_i_i_i_i_i_40_c_compmm_m1403_q = i_add_i_i_i_i_i_i_40_c_compmm_m1403_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_40_c_compmm_m1403_sel_x(BITSELECT,2235)@155
    assign bgTrunc_i_add_i_i_i_i_i_i_40_c_compmm_m1403_sel_x_b = i_add_i_i_i_i_i_i_40_c_compmm_m1403_q[15:0];

    // i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_sel_x(BITSELECT,3895)@155
    assign i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_40_c_compmm_m1403_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_select_15(BITSELECT,8307)@155
    assign i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_select_15_b = i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_join(BITJOIN,8306)@155
    assign i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_select_15_b};

    // leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(MUX,27178)@155
    assign leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_join_q or leftShiftStage0Idx1_uid27177_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_41_c_compmm_m1423_vt_join_q;
            1'b1 : leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27177_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(MUX,27183)@155
    assign leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s or leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27182_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = leftShiftStage0_uid27179_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27182_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x(MUX,27188)@155
    assign leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s or leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27187_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = leftShiftStage1_uid27184_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27187_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28(BITSELECT,10027)@155
    assign i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28_b = leftShiftStage2_uid27189_i_shl_i_i_i_i_i_i_41_c_compmm_m0_shift_x_q[28:13];

    // redist318_i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28_b_1(DELAY,29446)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist318_i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_join(BITJOIN,10026)@156
    assign i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_join_q = {redist318_i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg173(REG,13468)@149 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg173_q <= $unsigned(redist800_sync_together4364_aunroll_x_in_i_valid_81_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_65102_c_compmm_m174(BLACKBOX,8605)@150
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65102_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_65102_c_compmm_m174 (
        .in_intel_reserved_ffwd_84_0(in_intel_reserved_ffwd_84_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg173_q),
        .out_dest_data_out_84_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_65102_c_compmm_m174_out_dest_data_out_84_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt(ADD,30748)
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_a = {1'b0, redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_q};
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_b = {1'b0, redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_o <= $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_a) + $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_b);
        end
    end
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_q = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_o[4:0];

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_offset(CONSTANT,32169)
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_offset_q = $unsigned(5'b00010);

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt(ADD,32170)
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_a = {1'b0, redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_q};
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_b = {1'b0, redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_o <= $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_a) + $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_b);
        end
    end
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_q = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_o[5:0];

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_inputreg0(DELAY,30741)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_inputreg0_q <= $unsigned(in_c1_eni5_83_tpl);
        end
    end

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem(DUALMEM,32167)
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_ia = $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_inputreg0_q);
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_aa = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_q;
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_ab = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_aa),
        .data_a(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_ab),
        .q_b(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_q = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_iq[15:0];

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr(COUNTER,32168)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_i <= $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_q = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_i[4:0];

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem(DUALMEM,32171)
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_ia = $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_mem_q);
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_aa = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_wraddr_q;
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_ab = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_aa),
        .data_a(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_ab),
        .q_b(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_q = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_iq[15:0];

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr(COUNTER,30746)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_i <= $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_q = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_i[3:0];

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem(DUALMEM,30745)
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_ia = $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_1_mem_q);
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_aa = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_wraddr_q;
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_ab = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_aa),
        .data_a(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_ab),
        .q_b(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_q = redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_iq[15:0];

    // redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_outputreg0(DELAY,30742)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_outputreg0_q <= $unsigned(redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_mem_q);
        end
    end

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt(ADD,30756)
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_a = {1'b0, redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_q};
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_b = {1'b0, redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_o <= $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_a) + $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_b);
        end
    end
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_q = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_o[4:0];

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt(ADD,32178)
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_a = {1'b0, redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_q};
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_b = {1'b0, redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_split_0_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_o <= $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_a) + $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_b);
        end
    end
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_q = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_o[5:0];

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_inputreg0(DELAY,30749)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_inputreg0_q <= $unsigned(in_c1_eni5_84_tpl);
        end
    end

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem(DUALMEM,32175)
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_ia = $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_inputreg0_q);
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_aa = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_q;
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_ab = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_aa),
        .data_a(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_ab),
        .q_b(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_q = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_iq[15:0];

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr(COUNTER,32176)
    // low=0, high=31, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_i <= $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_i) + $unsigned(5'd1);
        end
    end
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_q = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_i[4:0];

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem(DUALMEM,32179)
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_ia = $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_mem_q);
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_aa = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_wraddr_q;
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_ab = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_0_rdcnt_q[4:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(5),
        .numwords_a(32),
        .width_b(16),
        .widthad_b(5),
        .numwords_b(32),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_aa),
        .data_a(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_ab),
        .q_b(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_q = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_iq[15:0];

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr(COUNTER,30754)
    // low=0, high=15, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_i <= $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_i) + $unsigned(4'd1);
        end
    end
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_q = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_i[3:0];

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem(DUALMEM,30753)
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_ia = $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_split_1_mem_q);
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_aa = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_wraddr_q;
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_ab = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_rdcnt_q[3:0];
    altera_syncram #(
        .ram_block_type("MLAB"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(4),
        .numwords_a(16),
        .width_b(16),
        .widthad_b(4),
        .numwords_b(16),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_aa),
        .data_a(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_ab),
        .q_b(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_q = redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_iq[15:0];

    // redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_outputreg0(DELAY,30750)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_outputreg0_q <= $unsigned(redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_mem_q);
        end
    end

    // valid_fanout_reg174(REG,13469)@149 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg174_q <= $unsigned(redist800_sync_together4364_aunroll_x_in_i_valid_81_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_65101_c_compmm_m175(BLACKBOX,8601)@150
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65101_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_65101_c_compmm_m175 (
        .in_intel_reserved_ffwd_83_0(in_intel_reserved_ffwd_83_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg174_q),
        .out_dest_data_out_83_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_65101_c_compmm_m175_out_dest_data_out_83_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28912)@150 + 5
    // out q@156
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_65101_c_compmm_m175_out_dest_data_out_83_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_65102_c_compmm_m174_out_dest_data_out_84_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425(ADD,9009)@156
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod487_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_b = $unsigned({{5{i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_41_c_compmm_m1424_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_o[33:0];

    // rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x(MUX,18413)@156
    assign rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q or rightShiftStage0Idx1_uid18412_dupName_165_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q;
            1'b1 : rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18412_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x(MUX,18418)@156
    assign rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18417_dupName_165_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18414_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18417_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x(MUX,18423)@156
    assign rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18422_dupName_165_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18419_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18422_dupName_165_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1426_vt_select_20(BITSELECT,10552)@156
    assign i_unnamed_c_compmm_m1426_vt_select_20_b = rightShiftStage2_uid18424_dupName_165_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1426_vt_join(BITJOIN,10551)@156
    assign i_unnamed_c_compmm_m1426_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1426_vt_select_20_b};

    // i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x(BITSELECT,3767)@156
    assign i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x_b = i_unnamed_c_compmm_m1426_vt_join_q[15:0];

    // redist951_i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x_b_1(DELAY,30079)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist951_i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18433_dupName_166_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18432)@156
    assign rightShiftStage1Idx1Rng8_uid18433_dupName_166_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18435_dupName_166_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18434)@156
    assign rightShiftStage1Idx1_uid18435_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18433_dupName_166_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18428_dupName_166_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18427)@156
    assign rightShiftStage0Idx1Rng4_uid18428_dupName_166_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q[33:4];

    // rightShiftStage0Idx1_uid18430_dupName_166_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18429)@156
    assign rightShiftStage0Idx1_uid18430_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18428_dupName_166_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x(MUX,18431)@156
    assign rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q or rightShiftStage0Idx1_uid18430_dupName_166_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_41_i_c_compmm_m1425_q;
            1'b1 : rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18430_dupName_166_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x(MUX,18436)@156
    assign rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18435_dupName_166_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18432_dupName_166_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18435_dupName_166_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1428_vt_select_21(BITSELECT,10555)@156
    assign i_unnamed_c_compmm_m1428_vt_select_21_b = rightShiftStage1_uid18437_dupName_166_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1428_vt_join(BITJOIN,10554)@156
    assign i_unnamed_c_compmm_m1428_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1428_vt_select_21_b};

    // i_unnamed_c_compmm_m1429_sel_x(BITSELECT,6034)@156
    assign i_unnamed_c_compmm_m1429_sel_x_b = i_unnamed_c_compmm_m1428_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1430_BitSelect_for_a(BITSELECT,28420)@156
    assign i_unnamed_c_compmm_m1430_BitSelect_for_a_b = i_unnamed_c_compmm_m1429_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1430_join(BITJOIN,28421)@156
    assign i_unnamed_c_compmm_m1430_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1430_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1430_vt_select_0(BITSELECT,10560)@156
    assign i_unnamed_c_compmm_m1430_vt_select_0_b = i_unnamed_c_compmm_m1430_join_q[0:0];

    // redist224_i_unnamed_c_compmm_m1430_vt_select_0_b_1(DELAY,29352)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist224_i_unnamed_c_compmm_m1430_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1430_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1430_vt_join(BITJOIN,10559)@157
    assign i_unnamed_c_compmm_m1430_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist224_i_unnamed_c_compmm_m1430_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_41_c_compmm_m1431(ADD,7222)@157
    assign i_add_i_i_i_i_i_i_41_c_compmm_m1431_a = {1'b0, i_unnamed_c_compmm_m1430_vt_join_q};
    assign i_add_i_i_i_i_i_i_41_c_compmm_m1431_b = {1'b0, redist951_i_conv_i_i_i_i_i_41_c_compmm_m1427_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_41_c_compmm_m1431_o = $unsigned(i_add_i_i_i_i_i_i_41_c_compmm_m1431_a) + $unsigned(i_add_i_i_i_i_i_i_41_c_compmm_m1431_b);
    assign i_add_i_i_i_i_i_i_41_c_compmm_m1431_q = i_add_i_i_i_i_i_i_41_c_compmm_m1431_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_41_c_compmm_m1431_sel_x(BITSELECT,2236)@157
    assign bgTrunc_i_add_i_i_i_i_i_i_41_c_compmm_m1431_sel_x_b = i_add_i_i_i_i_i_i_41_c_compmm_m1431_q[15:0];

    // i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_sel_x(BITSELECT,3896)@157
    assign i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_41_c_compmm_m1431_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_select_15(BITSELECT,8311)@157
    assign i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_select_15_b = i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_join(BITJOIN,8310)@157
    assign i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_select_15_b};

    // leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(MUX,27196)@157
    assign leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_join_q or leftShiftStage0Idx1_uid27195_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_42_c_compmm_m1451_vt_join_q;
            1'b1 : leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27195_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(MUX,27201)@157
    assign leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s or leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27200_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = leftShiftStage0_uid27197_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27200_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x(MUX,27206)@157
    assign leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s or leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27205_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = leftShiftStage1_uid27202_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27205_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28(BITSELECT,10030)@157
    assign i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28_b = leftShiftStage2_uid27207_i_shl_i_i_i_i_i_i_42_c_compmm_m0_shift_x_q[28:13];

    // redist317_i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28_b_1(DELAY,29445)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist317_i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_join(BITJOIN,10029)@158
    assign i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_join_q = {redist317_i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg171(REG,13466)@151 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg171_q <= $unsigned(redist801_sync_together4364_aunroll_x_in_i_valid_83_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_65104_c_compmm_m172(BLACKBOX,8617)@152
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65104_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_65104_c_compmm_m172 (
        .in_intel_reserved_ffwd_86_0(in_intel_reserved_ffwd_86_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg171_q),
        .out_dest_data_out_86_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_65104_c_compmm_m172_out_dest_data_out_86_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_offset(CONSTANT,30761)
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_offset_q = $unsigned(7'b0110001);

    // redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt(ADD,30762)
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_a = {1'b0, redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_q};
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_b = {1'b0, redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_o <= $unsigned(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_a) + $unsigned(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_b);
        end
    end
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_q = redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_o[7:0];

    // redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_inputreg0(DELAY,30757)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_inputreg0_q <= $unsigned(in_c1_eni5_85_tpl);
        end
    end

    // redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr(COUNTER,30760)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_i <= $unsigned(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_q = redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_i[6:0];

    // redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem(DUALMEM,30759)
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_ia = $unsigned(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_inputreg0_q);
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_aa = redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_wraddr_q;
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_ab = redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_aa),
        .data_a(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_ab),
        .q_b(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_q = redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_iq[15:0];

    // redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_outputreg0(DELAY,30758)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_outputreg0_q <= $unsigned(redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_mem_q);
        end
    end

    // redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt(ADD,30768)
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_a = {1'b0, redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_q};
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_b = {1'b0, redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_o <= $unsigned(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_a) + $unsigned(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_b);
        end
    end
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_q = redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_o[7:0];

    // redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_inputreg0(DELAY,30763)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_inputreg0_q <= $unsigned(in_c1_eni5_86_tpl);
        end
    end

    // redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr(COUNTER,30766)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_i <= $unsigned(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_q = redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_i[6:0];

    // redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem(DUALMEM,30765)
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_ia = $unsigned(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_inputreg0_q);
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_aa = redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_wraddr_q;
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_ab = redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_aa),
        .data_a(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_ab),
        .q_b(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_q = redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_iq[15:0];

    // redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_outputreg0(DELAY,30764)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_outputreg0_q <= $unsigned(redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_mem_q);
        end
    end

    // valid_fanout_reg172(REG,13467)@151 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg172_q <= $unsigned(redist801_sync_together4364_aunroll_x_in_i_valid_83_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_65103_c_compmm_m173(BLACKBOX,8613)@152
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65103_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_65103_c_compmm_m173 (
        .in_intel_reserved_ffwd_85_0(in_intel_reserved_ffwd_85_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg172_q),
        .out_dest_data_out_85_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_65103_c_compmm_m173_out_dest_data_out_85_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28913)@152 + 5
    // out q@158
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_65103_c_compmm_m173_out_dest_data_out_85_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_65104_c_compmm_m172_out_dest_data_out_86_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453(ADD,9010)@158
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod492_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_b = $unsigned({{5{i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_42_c_compmm_m1452_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_o[33:0];

    // rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x(MUX,18475)@158
    assign rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q or rightShiftStage0Idx1_uid18474_dupName_169_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q;
            1'b1 : rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18474_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x(MUX,18480)@158
    assign rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18479_dupName_169_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18476_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18479_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x(MUX,18485)@158
    assign rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18484_dupName_169_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18481_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18484_dupName_169_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1454_vt_select_20(BITSELECT,10574)@158
    assign i_unnamed_c_compmm_m1454_vt_select_20_b = rightShiftStage2_uid18486_dupName_169_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1454_vt_join(BITJOIN,10573)@158
    assign i_unnamed_c_compmm_m1454_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1454_vt_select_20_b};

    // i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x(BITSELECT,3768)@158
    assign i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x_b = i_unnamed_c_compmm_m1454_vt_join_q[15:0];

    // redist950_i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x_b_1(DELAY,30078)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist950_i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18495_dupName_170_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18494)@158
    assign rightShiftStage1Idx1Rng8_uid18495_dupName_170_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18497_dupName_170_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18496)@158
    assign rightShiftStage1Idx1_uid18497_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18495_dupName_170_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18490_dupName_170_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18489)@158
    assign rightShiftStage0Idx1Rng4_uid18490_dupName_170_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q[33:4];

    // rightShiftStage0Idx1_uid18492_dupName_170_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18491)@158
    assign rightShiftStage0Idx1_uid18492_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18490_dupName_170_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x(MUX,18493)@158
    assign rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q or rightShiftStage0Idx1_uid18492_dupName_170_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_42_i_c_compmm_m1453_q;
            1'b1 : rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18492_dupName_170_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x(MUX,18498)@158
    assign rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18497_dupName_170_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18494_dupName_170_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18497_dupName_170_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1456_vt_select_21(BITSELECT,10577)@158
    assign i_unnamed_c_compmm_m1456_vt_select_21_b = rightShiftStage1_uid18499_dupName_170_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1456_vt_join(BITJOIN,10576)@158
    assign i_unnamed_c_compmm_m1456_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1456_vt_select_21_b};

    // i_unnamed_c_compmm_m1457_sel_x(BITSELECT,6036)@158
    assign i_unnamed_c_compmm_m1457_sel_x_b = i_unnamed_c_compmm_m1456_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1458_BitSelect_for_a(BITSELECT,28424)@158
    assign i_unnamed_c_compmm_m1458_BitSelect_for_a_b = i_unnamed_c_compmm_m1457_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1458_join(BITJOIN,28425)@158
    assign i_unnamed_c_compmm_m1458_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1458_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1458_vt_select_0(BITSELECT,10582)@158
    assign i_unnamed_c_compmm_m1458_vt_select_0_b = i_unnamed_c_compmm_m1458_join_q[0:0];

    // redist222_i_unnamed_c_compmm_m1458_vt_select_0_b_1(DELAY,29350)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist222_i_unnamed_c_compmm_m1458_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1458_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1458_vt_join(BITJOIN,10581)@159
    assign i_unnamed_c_compmm_m1458_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist222_i_unnamed_c_compmm_m1458_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_42_c_compmm_m1459(ADD,7223)@159
    assign i_add_i_i_i_i_i_i_42_c_compmm_m1459_a = {1'b0, i_unnamed_c_compmm_m1458_vt_join_q};
    assign i_add_i_i_i_i_i_i_42_c_compmm_m1459_b = {1'b0, redist950_i_conv_i_i_i_i_i_42_c_compmm_m1455_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_42_c_compmm_m1459_o = $unsigned(i_add_i_i_i_i_i_i_42_c_compmm_m1459_a) + $unsigned(i_add_i_i_i_i_i_i_42_c_compmm_m1459_b);
    assign i_add_i_i_i_i_i_i_42_c_compmm_m1459_q = i_add_i_i_i_i_i_i_42_c_compmm_m1459_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_42_c_compmm_m1459_sel_x(BITSELECT,2237)@159
    assign bgTrunc_i_add_i_i_i_i_i_i_42_c_compmm_m1459_sel_x_b = i_add_i_i_i_i_i_i_42_c_compmm_m1459_q[15:0];

    // i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_sel_x(BITSELECT,3897)@159
    assign i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_42_c_compmm_m1459_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_select_15(BITSELECT,8315)@159
    assign i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_select_15_b = i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_join(BITJOIN,8314)@159
    assign i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_select_15_b};

    // leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(MUX,27214)@159
    assign leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_join_q or leftShiftStage0Idx1_uid27213_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_43_c_compmm_m1479_vt_join_q;
            1'b1 : leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27213_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(MUX,27219)@159
    assign leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s or leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27218_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = leftShiftStage0_uid27215_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27218_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x(MUX,27224)@159
    assign leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s or leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27223_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = leftShiftStage1_uid27220_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27223_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28(BITSELECT,10033)@159
    assign i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28_b = leftShiftStage2_uid27225_i_shl_i_i_i_i_i_i_43_c_compmm_m0_shift_x_q[28:13];

    // redist316_i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28_b_1(DELAY,29444)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist316_i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_join(BITJOIN,10032)@160
    assign i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_join_q = {redist316_i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg169(REG,13464)@153 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg169_q <= $unsigned(redist802_sync_together4364_aunroll_x_in_i_valid_85_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_65106_c_compmm_m170(BLACKBOX,8625)@154
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65106_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_65106_c_compmm_m170 (
        .in_intel_reserved_ffwd_88_0(in_intel_reserved_ffwd_88_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg169_q),
        .out_dest_data_out_88_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_65106_c_compmm_m170_out_dest_data_out_88_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_offset(CONSTANT,30773)
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_offset_q = $unsigned(7'b0101111);

    // redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt(ADD,30774)
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_a = {1'b0, redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_q};
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_b = {1'b0, redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_o <= $unsigned(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_a) + $unsigned(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_b);
        end
    end
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_q = redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_o[7:0];

    // redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_inputreg0(DELAY,30769)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_inputreg0_q <= $unsigned(in_c1_eni5_87_tpl);
        end
    end

    // redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr(COUNTER,30772)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_i <= $unsigned(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_q = redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_i[6:0];

    // redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem(DUALMEM,30771)
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_ia = $unsigned(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_inputreg0_q);
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_aa = redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_wraddr_q;
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_ab = redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_aa),
        .data_a(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_ab),
        .q_b(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_q = redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_iq[15:0];

    // redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_outputreg0(DELAY,30770)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_outputreg0_q <= $unsigned(redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_mem_q);
        end
    end

    // redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt(ADD,30780)
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_a = {1'b0, redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_q};
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_b = {1'b0, redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_o <= $unsigned(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_a) + $unsigned(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_b);
        end
    end
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_q = redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_o[7:0];

    // redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_inputreg0(DELAY,30775)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_inputreg0_q <= $unsigned(in_c1_eni5_88_tpl);
        end
    end

    // redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr(COUNTER,30778)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_i <= $unsigned(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_q = redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_i[6:0];

    // redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem(DUALMEM,30777)
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_ia = $unsigned(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_inputreg0_q);
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_aa = redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_wraddr_q;
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_ab = redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_aa),
        .data_a(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_ab),
        .q_b(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_q = redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_iq[15:0];

    // redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_outputreg0(DELAY,30776)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_outputreg0_q <= $unsigned(redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_mem_q);
        end
    end

    // valid_fanout_reg170(REG,13465)@153 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg170_q <= $unsigned(redist802_sync_together4364_aunroll_x_in_i_valid_85_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_65105_c_compmm_m171(BLACKBOX,8621)@154
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65105_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_65105_c_compmm_m171 (
        .in_intel_reserved_ffwd_87_0(in_intel_reserved_ffwd_87_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg170_q),
        .out_dest_data_out_87_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_65105_c_compmm_m171_out_dest_data_out_87_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28914)@154 + 5
    // out q@160
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_65105_c_compmm_m171_out_dest_data_out_87_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_65106_c_compmm_m170_out_dest_data_out_88_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481(ADD,9011)@160
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod497_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_b = $unsigned({{5{i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_43_c_compmm_m1480_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_o[33:0];

    // rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x(MUX,18537)@160
    assign rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q or rightShiftStage0Idx1_uid18536_dupName_173_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q;
            1'b1 : rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18536_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x(MUX,18542)@160
    assign rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18541_dupName_173_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18538_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18541_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x(MUX,18547)@160
    assign rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18546_dupName_173_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18543_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18546_dupName_173_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1482_vt_select_20(BITSELECT,10596)@160
    assign i_unnamed_c_compmm_m1482_vt_select_20_b = rightShiftStage2_uid18548_dupName_173_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1482_vt_join(BITJOIN,10595)@160
    assign i_unnamed_c_compmm_m1482_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1482_vt_select_20_b};

    // i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x(BITSELECT,3769)@160
    assign i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x_b = i_unnamed_c_compmm_m1482_vt_join_q[15:0];

    // redist949_i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x_b_1(DELAY,30077)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist949_i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18557_dupName_174_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18556)@160
    assign rightShiftStage1Idx1Rng8_uid18557_dupName_174_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18559_dupName_174_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18558)@160
    assign rightShiftStage1Idx1_uid18559_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18557_dupName_174_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18552_dupName_174_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18551)@160
    assign rightShiftStage0Idx1Rng4_uid18552_dupName_174_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q[33:4];

    // rightShiftStage0Idx1_uid18554_dupName_174_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18553)@160
    assign rightShiftStage0Idx1_uid18554_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18552_dupName_174_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x(MUX,18555)@160
    assign rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q or rightShiftStage0Idx1_uid18554_dupName_174_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_43_i_c_compmm_m1481_q;
            1'b1 : rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18554_dupName_174_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x(MUX,18560)@160
    assign rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18559_dupName_174_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18556_dupName_174_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18559_dupName_174_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1484_vt_select_21(BITSELECT,10599)@160
    assign i_unnamed_c_compmm_m1484_vt_select_21_b = rightShiftStage1_uid18561_dupName_174_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1484_vt_join(BITJOIN,10598)@160
    assign i_unnamed_c_compmm_m1484_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1484_vt_select_21_b};

    // i_unnamed_c_compmm_m1485_sel_x(BITSELECT,6038)@160
    assign i_unnamed_c_compmm_m1485_sel_x_b = i_unnamed_c_compmm_m1484_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1486_BitSelect_for_a(BITSELECT,28428)@160
    assign i_unnamed_c_compmm_m1486_BitSelect_for_a_b = i_unnamed_c_compmm_m1485_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1486_join(BITJOIN,28429)@160
    assign i_unnamed_c_compmm_m1486_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1486_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1486_vt_select_0(BITSELECT,10604)@160
    assign i_unnamed_c_compmm_m1486_vt_select_0_b = i_unnamed_c_compmm_m1486_join_q[0:0];

    // redist220_i_unnamed_c_compmm_m1486_vt_select_0_b_1(DELAY,29348)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist220_i_unnamed_c_compmm_m1486_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1486_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1486_vt_join(BITJOIN,10603)@161
    assign i_unnamed_c_compmm_m1486_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist220_i_unnamed_c_compmm_m1486_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_43_c_compmm_m1487(ADD,7224)@161
    assign i_add_i_i_i_i_i_i_43_c_compmm_m1487_a = {1'b0, i_unnamed_c_compmm_m1486_vt_join_q};
    assign i_add_i_i_i_i_i_i_43_c_compmm_m1487_b = {1'b0, redist949_i_conv_i_i_i_i_i_43_c_compmm_m1483_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_43_c_compmm_m1487_o = $unsigned(i_add_i_i_i_i_i_i_43_c_compmm_m1487_a) + $unsigned(i_add_i_i_i_i_i_i_43_c_compmm_m1487_b);
    assign i_add_i_i_i_i_i_i_43_c_compmm_m1487_q = i_add_i_i_i_i_i_i_43_c_compmm_m1487_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_43_c_compmm_m1487_sel_x(BITSELECT,2238)@161
    assign bgTrunc_i_add_i_i_i_i_i_i_43_c_compmm_m1487_sel_x_b = i_add_i_i_i_i_i_i_43_c_compmm_m1487_q[15:0];

    // i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_sel_x(BITSELECT,3898)@161
    assign i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_43_c_compmm_m1487_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_select_15(BITSELECT,8319)@161
    assign i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_select_15_b = i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_join(BITJOIN,8318)@161
    assign i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_select_15_b};

    // leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(MUX,27232)@161
    assign leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_join_q or leftShiftStage0Idx1_uid27231_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_44_c_compmm_m1507_vt_join_q;
            1'b1 : leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27231_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(MUX,27237)@161
    assign leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s or leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27236_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = leftShiftStage0_uid27233_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27236_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x(MUX,27242)@161
    assign leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s or leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27241_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = leftShiftStage1_uid27238_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27241_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28(BITSELECT,10036)@161
    assign i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28_b = leftShiftStage2_uid27243_i_shl_i_i_i_i_i_i_44_c_compmm_m0_shift_x_q[28:13];

    // redist315_i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28_b_1(DELAY,29443)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist315_i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_join(BITJOIN,10035)@162
    assign i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_join_q = {redist315_i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg167(REG,13462)@155 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg167_q <= $unsigned(redist803_sync_together4364_aunroll_x_in_i_valid_87_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_65108_c_compmm_m168(BLACKBOX,8633)@156
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65108_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_65108_c_compmm_m168 (
        .in_intel_reserved_ffwd_90_0(in_intel_reserved_ffwd_90_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg167_q),
        .out_dest_data_out_90_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_65108_c_compmm_m168_out_dest_data_out_90_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_offset(CONSTANT,30785)
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_offset_q = $unsigned(7'b0101101);

    // redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt(ADD,30786)
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_a = {1'b0, redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_q};
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_b = {1'b0, redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_o <= $unsigned(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_a) + $unsigned(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_b);
        end
    end
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_q = redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_o[7:0];

    // redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_inputreg0(DELAY,30781)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_inputreg0_q <= $unsigned(in_c1_eni5_89_tpl);
        end
    end

    // redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr(COUNTER,30784)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_i <= $unsigned(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_q = redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_i[6:0];

    // redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem(DUALMEM,30783)
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_ia = $unsigned(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_inputreg0_q);
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_aa = redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_wraddr_q;
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_ab = redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_aa),
        .data_a(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_ab),
        .q_b(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_q = redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_iq[15:0];

    // redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_outputreg0(DELAY,30782)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_outputreg0_q <= $unsigned(redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_mem_q);
        end
    end

    // redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt(ADD,30792)
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_a = {1'b0, redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_q};
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_b = {1'b0, redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_o <= $unsigned(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_a) + $unsigned(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_b);
        end
    end
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_q = redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_o[7:0];

    // redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_inputreg0(DELAY,30787)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_inputreg0_q <= $unsigned(in_c1_eni5_90_tpl);
        end
    end

    // redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr(COUNTER,30790)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_i <= $unsigned(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_q = redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_i[6:0];

    // redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem(DUALMEM,30789)
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_ia = $unsigned(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_inputreg0_q);
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_aa = redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_wraddr_q;
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_ab = redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_aa),
        .data_a(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_ab),
        .q_b(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_q = redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_iq[15:0];

    // redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_outputreg0(DELAY,30788)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_outputreg0_q <= $unsigned(redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_mem_q);
        end
    end

    // valid_fanout_reg168(REG,13463)@155 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg168_q <= $unsigned(redist803_sync_together4364_aunroll_x_in_i_valid_87_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_65107_c_compmm_m169(BLACKBOX,8629)@156
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65107_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_65107_c_compmm_m169 (
        .in_intel_reserved_ffwd_89_0(in_intel_reserved_ffwd_89_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg168_q),
        .out_dest_data_out_89_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_65107_c_compmm_m169_out_dest_data_out_89_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28915)@156 + 5
    // out q@162
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_65107_c_compmm_m169_out_dest_data_out_89_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_65108_c_compmm_m168_out_dest_data_out_90_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509(ADD,9012)@162
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod502_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_b = $unsigned({{5{i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_44_c_compmm_m1508_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_o[33:0];

    // rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x(MUX,18599)@162
    assign rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q or rightShiftStage0Idx1_uid18598_dupName_177_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q;
            1'b1 : rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18598_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x(MUX,18604)@162
    assign rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18603_dupName_177_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18600_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18603_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x(MUX,18609)@162
    assign rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18608_dupName_177_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18605_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18608_dupName_177_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1510_vt_select_20(BITSELECT,10618)@162
    assign i_unnamed_c_compmm_m1510_vt_select_20_b = rightShiftStage2_uid18610_dupName_177_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1510_vt_join(BITJOIN,10617)@162
    assign i_unnamed_c_compmm_m1510_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1510_vt_select_20_b};

    // i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x(BITSELECT,3770)@162
    assign i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x_b = i_unnamed_c_compmm_m1510_vt_join_q[15:0];

    // redist948_i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x_b_1(DELAY,30076)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist948_i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18619_dupName_178_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18618)@162
    assign rightShiftStage1Idx1Rng8_uid18619_dupName_178_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18621_dupName_178_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18620)@162
    assign rightShiftStage1Idx1_uid18621_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18619_dupName_178_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18614_dupName_178_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18613)@162
    assign rightShiftStage0Idx1Rng4_uid18614_dupName_178_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q[33:4];

    // rightShiftStage0Idx1_uid18616_dupName_178_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18615)@162
    assign rightShiftStage0Idx1_uid18616_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18614_dupName_178_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x(MUX,18617)@162
    assign rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q or rightShiftStage0Idx1_uid18616_dupName_178_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_44_i_c_compmm_m1509_q;
            1'b1 : rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18616_dupName_178_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x(MUX,18622)@162
    assign rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18621_dupName_178_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18618_dupName_178_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18621_dupName_178_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1512_vt_select_21(BITSELECT,10621)@162
    assign i_unnamed_c_compmm_m1512_vt_select_21_b = rightShiftStage1_uid18623_dupName_178_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1512_vt_join(BITJOIN,10620)@162
    assign i_unnamed_c_compmm_m1512_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1512_vt_select_21_b};

    // i_unnamed_c_compmm_m1513_sel_x(BITSELECT,6040)@162
    assign i_unnamed_c_compmm_m1513_sel_x_b = i_unnamed_c_compmm_m1512_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1514_BitSelect_for_a(BITSELECT,28432)@162
    assign i_unnamed_c_compmm_m1514_BitSelect_for_a_b = i_unnamed_c_compmm_m1513_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1514_join(BITJOIN,28433)@162
    assign i_unnamed_c_compmm_m1514_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1514_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1514_vt_select_0(BITSELECT,10626)@162
    assign i_unnamed_c_compmm_m1514_vt_select_0_b = i_unnamed_c_compmm_m1514_join_q[0:0];

    // redist218_i_unnamed_c_compmm_m1514_vt_select_0_b_1(DELAY,29346)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist218_i_unnamed_c_compmm_m1514_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1514_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1514_vt_join(BITJOIN,10625)@163
    assign i_unnamed_c_compmm_m1514_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist218_i_unnamed_c_compmm_m1514_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_44_c_compmm_m1515(ADD,7225)@163
    assign i_add_i_i_i_i_i_i_44_c_compmm_m1515_a = {1'b0, i_unnamed_c_compmm_m1514_vt_join_q};
    assign i_add_i_i_i_i_i_i_44_c_compmm_m1515_b = {1'b0, redist948_i_conv_i_i_i_i_i_44_c_compmm_m1511_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_44_c_compmm_m1515_o = $unsigned(i_add_i_i_i_i_i_i_44_c_compmm_m1515_a) + $unsigned(i_add_i_i_i_i_i_i_44_c_compmm_m1515_b);
    assign i_add_i_i_i_i_i_i_44_c_compmm_m1515_q = i_add_i_i_i_i_i_i_44_c_compmm_m1515_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_44_c_compmm_m1515_sel_x(BITSELECT,2239)@163
    assign bgTrunc_i_add_i_i_i_i_i_i_44_c_compmm_m1515_sel_x_b = i_add_i_i_i_i_i_i_44_c_compmm_m1515_q[15:0];

    // i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_sel_x(BITSELECT,3899)@163
    assign i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_44_c_compmm_m1515_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_select_15(BITSELECT,8323)@163
    assign i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_select_15_b = i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_join(BITJOIN,8322)@163
    assign i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_select_15_b};

    // leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(MUX,27250)@163
    assign leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_join_q or leftShiftStage0Idx1_uid27249_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_45_c_compmm_m1535_vt_join_q;
            1'b1 : leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27249_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(MUX,27255)@163
    assign leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s or leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27254_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = leftShiftStage0_uid27251_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27254_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x(MUX,27260)@163
    assign leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s or leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27259_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = leftShiftStage1_uid27256_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27259_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28(BITSELECT,10039)@163
    assign i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28_b = leftShiftStage2_uid27261_i_shl_i_i_i_i_i_i_45_c_compmm_m0_shift_x_q[28:13];

    // redist314_i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28_b_1(DELAY,29442)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist314_i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_join(BITJOIN,10038)@164
    assign i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_join_q = {redist314_i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg165(REG,13460)@157 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg165_q <= $unsigned(redist804_sync_together4364_aunroll_x_in_i_valid_89_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_65110_c_compmm_m166(BLACKBOX,8641)@158
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65110_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_65110_c_compmm_m166 (
        .in_intel_reserved_ffwd_92_0(in_intel_reserved_ffwd_92_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg165_q),
        .out_dest_data_out_92_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_65110_c_compmm_m166_out_dest_data_out_92_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_offset(CONSTANT,30797)
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_offset_q = $unsigned(7'b0101011);

    // redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt(ADD,30798)
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_a = {1'b0, redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_q};
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_b = {1'b0, redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_o <= $unsigned(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_a) + $unsigned(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_b);
        end
    end
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_q = redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_o[7:0];

    // redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_inputreg0(DELAY,30793)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_inputreg0_q <= $unsigned(in_c1_eni5_91_tpl);
        end
    end

    // redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr(COUNTER,30796)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_i <= $unsigned(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_q = redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_i[6:0];

    // redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem(DUALMEM,30795)
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_ia = $unsigned(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_inputreg0_q);
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_aa = redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_wraddr_q;
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_ab = redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_aa),
        .data_a(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_ab),
        .q_b(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_q = redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_iq[15:0];

    // redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_outputreg0(DELAY,30794)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_outputreg0_q <= $unsigned(redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_mem_q);
        end
    end

    // redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt(ADD,30804)
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_a = {1'b0, redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_q};
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_b = {1'b0, redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_o <= $unsigned(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_a) + $unsigned(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_b);
        end
    end
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_q = redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_o[7:0];

    // redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_inputreg0(DELAY,30799)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_inputreg0_q <= $unsigned(in_c1_eni5_92_tpl);
        end
    end

    // redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr(COUNTER,30802)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_i <= $unsigned(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_q = redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_i[6:0];

    // redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem(DUALMEM,30801)
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_ia = $unsigned(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_inputreg0_q);
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_aa = redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_wraddr_q;
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_ab = redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_aa),
        .data_a(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_ab),
        .q_b(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_q = redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_iq[15:0];

    // redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_outputreg0(DELAY,30800)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_outputreg0_q <= $unsigned(redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_mem_q);
        end
    end

    // valid_fanout_reg166(REG,13461)@157 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg166_q <= $unsigned(redist804_sync_together4364_aunroll_x_in_i_valid_89_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_65109_c_compmm_m167(BLACKBOX,8637)@158
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65109_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_65109_c_compmm_m167 (
        .in_intel_reserved_ffwd_91_0(in_intel_reserved_ffwd_91_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg166_q),
        .out_dest_data_out_91_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_65109_c_compmm_m167_out_dest_data_out_91_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28916)@158 + 5
    // out q@164
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_65109_c_compmm_m167_out_dest_data_out_91_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_65110_c_compmm_m166_out_dest_data_out_92_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537(ADD,9013)@164
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod507_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_b = $unsigned({{5{i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_45_c_compmm_m1536_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_o[33:0];

    // rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x(MUX,18661)@164
    assign rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q or rightShiftStage0Idx1_uid18660_dupName_181_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q;
            1'b1 : rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18660_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x(MUX,18666)@164
    assign rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18665_dupName_181_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18662_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18665_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x(MUX,18671)@164
    assign rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18670_dupName_181_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18667_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18670_dupName_181_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1538_vt_select_20(BITSELECT,10640)@164
    assign i_unnamed_c_compmm_m1538_vt_select_20_b = rightShiftStage2_uid18672_dupName_181_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1538_vt_join(BITJOIN,10639)@164
    assign i_unnamed_c_compmm_m1538_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1538_vt_select_20_b};

    // i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x(BITSELECT,3771)@164
    assign i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x_b = i_unnamed_c_compmm_m1538_vt_join_q[15:0];

    // redist947_i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x_b_1(DELAY,30075)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist947_i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18681_dupName_182_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18680)@164
    assign rightShiftStage1Idx1Rng8_uid18681_dupName_182_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18683_dupName_182_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18682)@164
    assign rightShiftStage1Idx1_uid18683_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18681_dupName_182_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18676_dupName_182_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18675)@164
    assign rightShiftStage0Idx1Rng4_uid18676_dupName_182_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q[33:4];

    // rightShiftStage0Idx1_uid18678_dupName_182_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18677)@164
    assign rightShiftStage0Idx1_uid18678_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18676_dupName_182_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x(MUX,18679)@164
    assign rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q or rightShiftStage0Idx1_uid18678_dupName_182_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_45_i_c_compmm_m1537_q;
            1'b1 : rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18678_dupName_182_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x(MUX,18684)@164
    assign rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18683_dupName_182_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18680_dupName_182_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18683_dupName_182_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1540_vt_select_21(BITSELECT,10643)@164
    assign i_unnamed_c_compmm_m1540_vt_select_21_b = rightShiftStage1_uid18685_dupName_182_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1540_vt_join(BITJOIN,10642)@164
    assign i_unnamed_c_compmm_m1540_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1540_vt_select_21_b};

    // i_unnamed_c_compmm_m1541_sel_x(BITSELECT,6042)@164
    assign i_unnamed_c_compmm_m1541_sel_x_b = i_unnamed_c_compmm_m1540_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1542_BitSelect_for_a(BITSELECT,28436)@164
    assign i_unnamed_c_compmm_m1542_BitSelect_for_a_b = i_unnamed_c_compmm_m1541_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1542_join(BITJOIN,28437)@164
    assign i_unnamed_c_compmm_m1542_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1542_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1542_vt_select_0(BITSELECT,10648)@164
    assign i_unnamed_c_compmm_m1542_vt_select_0_b = i_unnamed_c_compmm_m1542_join_q[0:0];

    // redist216_i_unnamed_c_compmm_m1542_vt_select_0_b_1(DELAY,29344)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist216_i_unnamed_c_compmm_m1542_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1542_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1542_vt_join(BITJOIN,10647)@165
    assign i_unnamed_c_compmm_m1542_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist216_i_unnamed_c_compmm_m1542_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_45_c_compmm_m1543(ADD,7226)@165
    assign i_add_i_i_i_i_i_i_45_c_compmm_m1543_a = {1'b0, i_unnamed_c_compmm_m1542_vt_join_q};
    assign i_add_i_i_i_i_i_i_45_c_compmm_m1543_b = {1'b0, redist947_i_conv_i_i_i_i_i_45_c_compmm_m1539_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_45_c_compmm_m1543_o = $unsigned(i_add_i_i_i_i_i_i_45_c_compmm_m1543_a) + $unsigned(i_add_i_i_i_i_i_i_45_c_compmm_m1543_b);
    assign i_add_i_i_i_i_i_i_45_c_compmm_m1543_q = i_add_i_i_i_i_i_i_45_c_compmm_m1543_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_45_c_compmm_m1543_sel_x(BITSELECT,2240)@165
    assign bgTrunc_i_add_i_i_i_i_i_i_45_c_compmm_m1543_sel_x_b = i_add_i_i_i_i_i_i_45_c_compmm_m1543_q[15:0];

    // i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_sel_x(BITSELECT,3900)@165
    assign i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_45_c_compmm_m1543_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_select_15(BITSELECT,8327)@165
    assign i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_select_15_b = i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_join(BITJOIN,8326)@165
    assign i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_select_15_b};

    // leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(MUX,27268)@165
    assign leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_join_q or leftShiftStage0Idx1_uid27267_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_46_c_compmm_m1563_vt_join_q;
            1'b1 : leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27267_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(MUX,27273)@165
    assign leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s or leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27272_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = leftShiftStage0_uid27269_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27272_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x(MUX,27278)@165
    assign leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s or leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27277_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = leftShiftStage1_uid27274_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27277_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28(BITSELECT,10042)@165
    assign i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28_b = leftShiftStage2_uid27279_i_shl_i_i_i_i_i_i_46_c_compmm_m0_shift_x_q[28:13];

    // redist313_i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28_b_1(DELAY,29441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist313_i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_join(BITJOIN,10041)@166
    assign i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_join_q = {redist313_i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg163(REG,13458)@159 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg163_q <= $unsigned(redist805_sync_together4364_aunroll_x_in_i_valid_91_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_65112_c_compmm_m164(BLACKBOX,8649)@160
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65112_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_65112_c_compmm_m164 (
        .in_intel_reserved_ffwd_94_0(in_intel_reserved_ffwd_94_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg163_q),
        .out_dest_data_out_94_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_65112_c_compmm_m164_out_dest_data_out_94_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_offset(CONSTANT,30809)
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_offset_q = $unsigned(7'b0101001);

    // redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt(ADD,30810)
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_a = {1'b0, redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_q};
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_b = {1'b0, redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_o <= $unsigned(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_a) + $unsigned(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_b);
        end
    end
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_q = redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_o[7:0];

    // redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_inputreg0(DELAY,30805)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_inputreg0_q <= $unsigned(in_c1_eni5_93_tpl);
        end
    end

    // redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr(COUNTER,30808)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_i <= $unsigned(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_q = redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_i[6:0];

    // redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem(DUALMEM,30807)
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_ia = $unsigned(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_inputreg0_q);
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_aa = redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_wraddr_q;
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_ab = redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_aa),
        .data_a(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_ab),
        .q_b(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_q = redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_iq[15:0];

    // redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_outputreg0(DELAY,30806)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_outputreg0_q <= $unsigned(redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_mem_q);
        end
    end

    // redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt(ADD,30816)
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_a = {1'b0, redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_q};
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_b = {1'b0, redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_o <= $unsigned(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_a) + $unsigned(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_b);
        end
    end
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_q = redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_o[7:0];

    // redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_inputreg0(DELAY,30811)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_inputreg0_q <= $unsigned(in_c1_eni5_94_tpl);
        end
    end

    // redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr(COUNTER,30814)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_i <= $unsigned(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_q = redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_i[6:0];

    // redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem(DUALMEM,30813)
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_ia = $unsigned(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_inputreg0_q);
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_aa = redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_wraddr_q;
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_ab = redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_aa),
        .data_a(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_ab),
        .q_b(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_q = redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_iq[15:0];

    // redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_outputreg0(DELAY,30812)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_outputreg0_q <= $unsigned(redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_mem_q);
        end
    end

    // valid_fanout_reg164(REG,13459)@159 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg164_q <= $unsigned(redist805_sync_together4364_aunroll_x_in_i_valid_91_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_65111_c_compmm_m165(BLACKBOX,8645)@160
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65111_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_65111_c_compmm_m165 (
        .in_intel_reserved_ffwd_93_0(in_intel_reserved_ffwd_93_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg164_q),
        .out_dest_data_out_93_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_65111_c_compmm_m165_out_dest_data_out_93_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28917)@160 + 5
    // out q@166
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_65111_c_compmm_m165_out_dest_data_out_93_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_65112_c_compmm_m164_out_dest_data_out_94_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565(ADD,9014)@166
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod512_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_b = $unsigned({{5{i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_46_c_compmm_m1564_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_o[33:0];

    // rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x(MUX,18723)@166
    assign rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q or rightShiftStage0Idx1_uid18722_dupName_185_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q;
            1'b1 : rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18722_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x(MUX,18728)@166
    assign rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18727_dupName_185_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18724_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18727_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x(MUX,18733)@166
    assign rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18732_dupName_185_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18729_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18732_dupName_185_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1566_vt_select_20(BITSELECT,10662)@166
    assign i_unnamed_c_compmm_m1566_vt_select_20_b = rightShiftStage2_uid18734_dupName_185_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1566_vt_join(BITJOIN,10661)@166
    assign i_unnamed_c_compmm_m1566_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1566_vt_select_20_b};

    // i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x(BITSELECT,3772)@166
    assign i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x_b = i_unnamed_c_compmm_m1566_vt_join_q[15:0];

    // redist946_i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x_b_1(DELAY,30074)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist946_i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18743_dupName_186_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18742)@166
    assign rightShiftStage1Idx1Rng8_uid18743_dupName_186_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18745_dupName_186_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18744)@166
    assign rightShiftStage1Idx1_uid18745_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18743_dupName_186_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18738_dupName_186_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18737)@166
    assign rightShiftStage0Idx1Rng4_uid18738_dupName_186_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q[33:4];

    // rightShiftStage0Idx1_uid18740_dupName_186_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18739)@166
    assign rightShiftStage0Idx1_uid18740_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18738_dupName_186_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x(MUX,18741)@166
    assign rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q or rightShiftStage0Idx1_uid18740_dupName_186_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_46_i_c_compmm_m1565_q;
            1'b1 : rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18740_dupName_186_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x(MUX,18746)@166
    assign rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18745_dupName_186_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18742_dupName_186_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18745_dupName_186_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1568_vt_select_21(BITSELECT,10665)@166
    assign i_unnamed_c_compmm_m1568_vt_select_21_b = rightShiftStage1_uid18747_dupName_186_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1568_vt_join(BITJOIN,10664)@166
    assign i_unnamed_c_compmm_m1568_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1568_vt_select_21_b};

    // i_unnamed_c_compmm_m1569_sel_x(BITSELECT,6044)@166
    assign i_unnamed_c_compmm_m1569_sel_x_b = i_unnamed_c_compmm_m1568_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1570_BitSelect_for_a(BITSELECT,28440)@166
    assign i_unnamed_c_compmm_m1570_BitSelect_for_a_b = i_unnamed_c_compmm_m1569_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1570_join(BITJOIN,28441)@166
    assign i_unnamed_c_compmm_m1570_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1570_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1570_vt_select_0(BITSELECT,10670)@166
    assign i_unnamed_c_compmm_m1570_vt_select_0_b = i_unnamed_c_compmm_m1570_join_q[0:0];

    // redist214_i_unnamed_c_compmm_m1570_vt_select_0_b_1(DELAY,29342)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist214_i_unnamed_c_compmm_m1570_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1570_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1570_vt_join(BITJOIN,10669)@167
    assign i_unnamed_c_compmm_m1570_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist214_i_unnamed_c_compmm_m1570_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_46_c_compmm_m1571(ADD,7227)@167
    assign i_add_i_i_i_i_i_i_46_c_compmm_m1571_a = {1'b0, i_unnamed_c_compmm_m1570_vt_join_q};
    assign i_add_i_i_i_i_i_i_46_c_compmm_m1571_b = {1'b0, redist946_i_conv_i_i_i_i_i_46_c_compmm_m1567_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_46_c_compmm_m1571_o = $unsigned(i_add_i_i_i_i_i_i_46_c_compmm_m1571_a) + $unsigned(i_add_i_i_i_i_i_i_46_c_compmm_m1571_b);
    assign i_add_i_i_i_i_i_i_46_c_compmm_m1571_q = i_add_i_i_i_i_i_i_46_c_compmm_m1571_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_46_c_compmm_m1571_sel_x(BITSELECT,2241)@167
    assign bgTrunc_i_add_i_i_i_i_i_i_46_c_compmm_m1571_sel_x_b = i_add_i_i_i_i_i_i_46_c_compmm_m1571_q[15:0];

    // i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_sel_x(BITSELECT,3901)@167
    assign i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_46_c_compmm_m1571_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_select_15(BITSELECT,8331)@167
    assign i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_select_15_b = i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_join(BITJOIN,8330)@167
    assign i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_select_15_b};

    // leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(MUX,27286)@167
    assign leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_join_q or leftShiftStage0Idx1_uid27285_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_47_c_compmm_m1591_vt_join_q;
            1'b1 : leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27285_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(MUX,27291)@167
    assign leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s or leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27290_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = leftShiftStage0_uid27287_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27290_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x(MUX,27296)@167
    assign leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s or leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27295_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = leftShiftStage1_uid27292_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27295_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28(BITSELECT,10045)@167
    assign i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28_b = leftShiftStage2_uid27297_i_shl_i_i_i_i_i_i_47_c_compmm_m0_shift_x_q[28:13];

    // redist312_i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28_b_1(DELAY,29440)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist312_i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_join(BITJOIN,10044)@168
    assign i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_join_q = {redist312_i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg161(REG,13456)@161 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg161_q <= $unsigned(redist806_sync_together4364_aunroll_x_in_i_valid_93_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_65114_c_compmm_m162(BLACKBOX,8661)@162
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65114_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_65114_c_compmm_m162 (
        .in_intel_reserved_ffwd_96_0(in_intel_reserved_ffwd_96_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg161_q),
        .out_dest_data_out_96_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_65114_c_compmm_m162_out_dest_data_out_96_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_offset(CONSTANT,30821)
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_offset_q = $unsigned(7'b0100111);

    // redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt(ADD,30822)
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_a = {1'b0, redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_q};
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_b = {1'b0, redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_o <= $unsigned(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_a) + $unsigned(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_b);
        end
    end
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_q = redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_o[7:0];

    // redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_inputreg0(DELAY,30817)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_inputreg0_q <= $unsigned(in_c1_eni5_95_tpl);
        end
    end

    // redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr(COUNTER,30820)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_i <= $unsigned(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_q = redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_i[6:0];

    // redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem(DUALMEM,30819)
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_ia = $unsigned(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_inputreg0_q);
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_aa = redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_wraddr_q;
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_ab = redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_aa),
        .data_a(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_ab),
        .q_b(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_q = redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_iq[15:0];

    // redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_outputreg0(DELAY,30818)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_outputreg0_q <= $unsigned(redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_mem_q);
        end
    end

    // redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt(ADD,30828)
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_a = {1'b0, redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_q};
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_b = {1'b0, redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_o <= $unsigned(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_a) + $unsigned(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_b);
        end
    end
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_q = redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_o[7:0];

    // redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_inputreg0(DELAY,30823)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_inputreg0_q <= $unsigned(in_c1_eni5_96_tpl);
        end
    end

    // redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr(COUNTER,30826)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_i <= $unsigned(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_q = redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_i[6:0];

    // redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem(DUALMEM,30825)
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_ia = $unsigned(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_inputreg0_q);
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_aa = redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_wraddr_q;
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_ab = redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_aa),
        .data_a(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_ab),
        .q_b(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_q = redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_iq[15:0];

    // redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_outputreg0(DELAY,30824)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_outputreg0_q <= $unsigned(redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_mem_q);
        end
    end

    // valid_fanout_reg162(REG,13457)@161 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg162_q <= $unsigned(redist806_sync_together4364_aunroll_x_in_i_valid_93_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_65113_c_compmm_m163(BLACKBOX,8657)@162
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65113_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_65113_c_compmm_m163 (
        .in_intel_reserved_ffwd_95_0(in_intel_reserved_ffwd_95_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg162_q),
        .out_dest_data_out_95_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_65113_c_compmm_m163_out_dest_data_out_95_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28918)@162 + 5
    // out q@168
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_65113_c_compmm_m163_out_dest_data_out_95_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_65114_c_compmm_m162_out_dest_data_out_96_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593(ADD,9015)@168
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod517_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_b = $unsigned({{5{i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_47_c_compmm_m1592_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_o[33:0];

    // rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x(MUX,18785)@168
    assign rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q or rightShiftStage0Idx1_uid18784_dupName_189_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q;
            1'b1 : rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18784_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x(MUX,18790)@168
    assign rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18789_dupName_189_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18786_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18789_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x(MUX,18795)@168
    assign rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18794_dupName_189_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18791_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18794_dupName_189_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1594_vt_select_20(BITSELECT,10684)@168
    assign i_unnamed_c_compmm_m1594_vt_select_20_b = rightShiftStage2_uid18796_dupName_189_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1594_vt_join(BITJOIN,10683)@168
    assign i_unnamed_c_compmm_m1594_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1594_vt_select_20_b};

    // i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x(BITSELECT,3773)@168
    assign i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x_b = i_unnamed_c_compmm_m1594_vt_join_q[15:0];

    // redist945_i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x_b_1(DELAY,30073)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist945_i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18805_dupName_190_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18804)@168
    assign rightShiftStage1Idx1Rng8_uid18805_dupName_190_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18807_dupName_190_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18806)@168
    assign rightShiftStage1Idx1_uid18807_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18805_dupName_190_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18800_dupName_190_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18799)@168
    assign rightShiftStage0Idx1Rng4_uid18800_dupName_190_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q[33:4];

    // rightShiftStage0Idx1_uid18802_dupName_190_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18801)@168
    assign rightShiftStage0Idx1_uid18802_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18800_dupName_190_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x(MUX,18803)@168
    assign rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q or rightShiftStage0Idx1_uid18802_dupName_190_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_47_i_c_compmm_m1593_q;
            1'b1 : rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18802_dupName_190_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x(MUX,18808)@168
    assign rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18807_dupName_190_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18804_dupName_190_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18807_dupName_190_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1596_vt_select_21(BITSELECT,10687)@168
    assign i_unnamed_c_compmm_m1596_vt_select_21_b = rightShiftStage1_uid18809_dupName_190_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1596_vt_join(BITJOIN,10686)@168
    assign i_unnamed_c_compmm_m1596_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1596_vt_select_21_b};

    // i_unnamed_c_compmm_m1597_sel_x(BITSELECT,6046)@168
    assign i_unnamed_c_compmm_m1597_sel_x_b = i_unnamed_c_compmm_m1596_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1598_BitSelect_for_a(BITSELECT,28444)@168
    assign i_unnamed_c_compmm_m1598_BitSelect_for_a_b = i_unnamed_c_compmm_m1597_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1598_join(BITJOIN,28445)@168
    assign i_unnamed_c_compmm_m1598_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1598_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1598_vt_select_0(BITSELECT,10692)@168
    assign i_unnamed_c_compmm_m1598_vt_select_0_b = i_unnamed_c_compmm_m1598_join_q[0:0];

    // redist212_i_unnamed_c_compmm_m1598_vt_select_0_b_1(DELAY,29340)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist212_i_unnamed_c_compmm_m1598_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1598_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1598_vt_join(BITJOIN,10691)@169
    assign i_unnamed_c_compmm_m1598_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist212_i_unnamed_c_compmm_m1598_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_47_c_compmm_m1599(ADD,7228)@169
    assign i_add_i_i_i_i_i_i_47_c_compmm_m1599_a = {1'b0, i_unnamed_c_compmm_m1598_vt_join_q};
    assign i_add_i_i_i_i_i_i_47_c_compmm_m1599_b = {1'b0, redist945_i_conv_i_i_i_i_i_47_c_compmm_m1595_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_47_c_compmm_m1599_o = $unsigned(i_add_i_i_i_i_i_i_47_c_compmm_m1599_a) + $unsigned(i_add_i_i_i_i_i_i_47_c_compmm_m1599_b);
    assign i_add_i_i_i_i_i_i_47_c_compmm_m1599_q = i_add_i_i_i_i_i_i_47_c_compmm_m1599_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_47_c_compmm_m1599_sel_x(BITSELECT,2242)@169
    assign bgTrunc_i_add_i_i_i_i_i_i_47_c_compmm_m1599_sel_x_b = i_add_i_i_i_i_i_i_47_c_compmm_m1599_q[15:0];

    // i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_sel_x(BITSELECT,3902)@169
    assign i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_47_c_compmm_m1599_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_select_15(BITSELECT,8335)@169
    assign i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_select_15_b = i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_join(BITJOIN,8334)@169
    assign i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_select_15_b};

    // leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(MUX,27304)@169
    assign leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_join_q or leftShiftStage0Idx1_uid27303_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_48_c_compmm_m1619_vt_join_q;
            1'b1 : leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27303_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(MUX,27309)@169
    assign leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s or leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27308_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = leftShiftStage0_uid27305_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27308_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x(MUX,27314)@169
    assign leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s or leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27313_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = leftShiftStage1_uid27310_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27313_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28(BITSELECT,10048)@169
    assign i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28_b = leftShiftStage2_uid27315_i_shl_i_i_i_i_i_i_48_c_compmm_m0_shift_x_q[28:13];

    // redist311_i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28_b_1(DELAY,29439)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist311_i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_join(BITJOIN,10047)@170
    assign i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_join_q = {redist311_i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg159(REG,13454)@163 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg159_q <= $unsigned(redist807_sync_together4364_aunroll_x_in_i_valid_95_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_65116_c_compmm_m160(BLACKBOX,8669)@164
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65116_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_65116_c_compmm_m160 (
        .in_intel_reserved_ffwd_98_0(in_intel_reserved_ffwd_98_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg159_q),
        .out_dest_data_out_98_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_65116_c_compmm_m160_out_dest_data_out_98_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_offset(CONSTANT,30833)
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_offset_q = $unsigned(7'b0100101);

    // redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt(ADD,30834)
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_a = {1'b0, redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_q};
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_b = {1'b0, redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_o <= $unsigned(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_a) + $unsigned(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_b);
        end
    end
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_q = redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_o[7:0];

    // redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_inputreg0(DELAY,30829)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_inputreg0_q <= $unsigned(in_c1_eni5_97_tpl);
        end
    end

    // redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr(COUNTER,30832)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_i <= $unsigned(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_q = redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_i[6:0];

    // redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem(DUALMEM,30831)
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_ia = $unsigned(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_inputreg0_q);
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_aa = redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_wraddr_q;
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_ab = redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_aa),
        .data_a(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_ab),
        .q_b(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_q = redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_iq[15:0];

    // redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_outputreg0(DELAY,30830)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_outputreg0_q <= $unsigned(redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_mem_q);
        end
    end

    // redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt(ADD,30840)
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_a = {1'b0, redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_q};
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_b = {1'b0, redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_o <= $unsigned(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_a) + $unsigned(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_b);
        end
    end
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_q = redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_o[7:0];

    // redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_inputreg0(DELAY,30835)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_inputreg0_q <= $unsigned(in_c1_eni5_98_tpl);
        end
    end

    // redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr(COUNTER,30838)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_i <= $unsigned(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_q = redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_i[6:0];

    // redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem(DUALMEM,30837)
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_ia = $unsigned(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_inputreg0_q);
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_aa = redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_wraddr_q;
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_ab = redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_aa),
        .data_a(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_ab),
        .q_b(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_q = redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_iq[15:0];

    // redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_outputreg0(DELAY,30836)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_outputreg0_q <= $unsigned(redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_mem_q);
        end
    end

    // valid_fanout_reg160(REG,13455)@163 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg160_q <= $unsigned(redist807_sync_together4364_aunroll_x_in_i_valid_95_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_65115_c_compmm_m161(BLACKBOX,8665)@164
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65115_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_65115_c_compmm_m161 (
        .in_intel_reserved_ffwd_97_0(in_intel_reserved_ffwd_97_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg160_q),
        .out_dest_data_out_97_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_65115_c_compmm_m161_out_dest_data_out_97_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28919)@164 + 5
    // out q@170
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_65115_c_compmm_m161_out_dest_data_out_97_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_65116_c_compmm_m160_out_dest_data_out_98_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621(ADD,9016)@170
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod522_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_b = $unsigned({{5{i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_48_c_compmm_m1620_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_o[33:0];

    // rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x(MUX,18847)@170
    assign rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q or rightShiftStage0Idx1_uid18846_dupName_193_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q;
            1'b1 : rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18846_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x(MUX,18852)@170
    assign rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18851_dupName_193_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18848_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18851_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x(MUX,18857)@170
    assign rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18856_dupName_193_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18853_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18856_dupName_193_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1622_vt_select_20(BITSELECT,10706)@170
    assign i_unnamed_c_compmm_m1622_vt_select_20_b = rightShiftStage2_uid18858_dupName_193_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1622_vt_join(BITJOIN,10705)@170
    assign i_unnamed_c_compmm_m1622_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1622_vt_select_20_b};

    // i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x(BITSELECT,3774)@170
    assign i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x_b = i_unnamed_c_compmm_m1622_vt_join_q[15:0];

    // redist944_i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x_b_1(DELAY,30072)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist944_i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18867_dupName_194_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18866)@170
    assign rightShiftStage1Idx1Rng8_uid18867_dupName_194_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18869_dupName_194_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18868)@170
    assign rightShiftStage1Idx1_uid18869_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18867_dupName_194_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18862_dupName_194_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18861)@170
    assign rightShiftStage0Idx1Rng4_uid18862_dupName_194_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q[33:4];

    // rightShiftStage0Idx1_uid18864_dupName_194_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18863)@170
    assign rightShiftStage0Idx1_uid18864_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18862_dupName_194_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x(MUX,18865)@170
    assign rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q or rightShiftStage0Idx1_uid18864_dupName_194_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_48_i_c_compmm_m1621_q;
            1'b1 : rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18864_dupName_194_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x(MUX,18870)@170
    assign rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18869_dupName_194_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18866_dupName_194_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18869_dupName_194_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1624_vt_select_21(BITSELECT,10709)@170
    assign i_unnamed_c_compmm_m1624_vt_select_21_b = rightShiftStage1_uid18871_dupName_194_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1624_vt_join(BITJOIN,10708)@170
    assign i_unnamed_c_compmm_m1624_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1624_vt_select_21_b};

    // i_unnamed_c_compmm_m1625_sel_x(BITSELECT,6048)@170
    assign i_unnamed_c_compmm_m1625_sel_x_b = i_unnamed_c_compmm_m1624_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1626_BitSelect_for_a(BITSELECT,28448)@170
    assign i_unnamed_c_compmm_m1626_BitSelect_for_a_b = i_unnamed_c_compmm_m1625_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1626_join(BITJOIN,28449)@170
    assign i_unnamed_c_compmm_m1626_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1626_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1626_vt_select_0(BITSELECT,10714)@170
    assign i_unnamed_c_compmm_m1626_vt_select_0_b = i_unnamed_c_compmm_m1626_join_q[0:0];

    // redist210_i_unnamed_c_compmm_m1626_vt_select_0_b_1(DELAY,29338)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist210_i_unnamed_c_compmm_m1626_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1626_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1626_vt_join(BITJOIN,10713)@171
    assign i_unnamed_c_compmm_m1626_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist210_i_unnamed_c_compmm_m1626_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_48_c_compmm_m1627(ADD,7229)@171
    assign i_add_i_i_i_i_i_i_48_c_compmm_m1627_a = {1'b0, i_unnamed_c_compmm_m1626_vt_join_q};
    assign i_add_i_i_i_i_i_i_48_c_compmm_m1627_b = {1'b0, redist944_i_conv_i_i_i_i_i_48_c_compmm_m1623_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_48_c_compmm_m1627_o = $unsigned(i_add_i_i_i_i_i_i_48_c_compmm_m1627_a) + $unsigned(i_add_i_i_i_i_i_i_48_c_compmm_m1627_b);
    assign i_add_i_i_i_i_i_i_48_c_compmm_m1627_q = i_add_i_i_i_i_i_i_48_c_compmm_m1627_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_48_c_compmm_m1627_sel_x(BITSELECT,2243)@171
    assign bgTrunc_i_add_i_i_i_i_i_i_48_c_compmm_m1627_sel_x_b = i_add_i_i_i_i_i_i_48_c_compmm_m1627_q[15:0];

    // i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_sel_x(BITSELECT,3903)@171
    assign i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_48_c_compmm_m1627_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_select_15(BITSELECT,8339)@171
    assign i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_select_15_b = i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_join(BITJOIN,8338)@171
    assign i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_select_15_b};

    // leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(MUX,27322)@171
    assign leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_join_q or leftShiftStage0Idx1_uid27321_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_49_c_compmm_m1647_vt_join_q;
            1'b1 : leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27321_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(MUX,27327)@171
    assign leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s or leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27326_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = leftShiftStage0_uid27323_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27326_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x(MUX,27332)@171
    assign leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s or leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27331_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = leftShiftStage1_uid27328_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27331_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28(BITSELECT,10051)@171
    assign i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28_b = leftShiftStage2_uid27333_i_shl_i_i_i_i_i_i_49_c_compmm_m0_shift_x_q[28:13];

    // redist310_i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28_b_1(DELAY,29438)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist310_i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_join(BITJOIN,10050)@172
    assign i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_join_q = {redist310_i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg157(REG,13452)@165 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg157_q <= $unsigned(redist808_sync_together4364_aunroll_x_in_i_valid_97_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_65118_c_compmm_m158(BLACKBOX,8677)@166
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65118_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_65118_c_compmm_m158 (
        .in_intel_reserved_ffwd_100_0(in_intel_reserved_ffwd_100_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg157_q),
        .out_dest_data_out_100_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_65118_c_compmm_m158_out_dest_data_out_100_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_offset(CONSTANT,30845)
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_offset_q = $unsigned(7'b0100011);

    // redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt(ADD,30846)
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_a = {1'b0, redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_q};
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_b = {1'b0, redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_o <= $unsigned(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_a) + $unsigned(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_b);
        end
    end
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_q = redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_o[7:0];

    // redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_inputreg0(DELAY,30841)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_inputreg0_q <= $unsigned(in_c1_eni5_99_tpl);
        end
    end

    // redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr(COUNTER,30844)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_i <= $unsigned(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_q = redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_i[6:0];

    // redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem(DUALMEM,30843)
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_ia = $unsigned(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_inputreg0_q);
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_aa = redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_wraddr_q;
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_ab = redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_aa),
        .data_a(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_ab),
        .q_b(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_q = redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_iq[15:0];

    // redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_outputreg0(DELAY,30842)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_outputreg0_q <= $unsigned(redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_mem_q);
        end
    end

    // redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt(ADD,30852)
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_a = {1'b0, redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_q};
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_b = {1'b0, redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_o <= $unsigned(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_a) + $unsigned(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_b);
        end
    end
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_q = redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_o[7:0];

    // redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_inputreg0(DELAY,30847)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_inputreg0_q <= $unsigned(in_c1_eni5_100_tpl);
        end
    end

    // redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr(COUNTER,30850)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_i <= $unsigned(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_q = redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_i[6:0];

    // redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem(DUALMEM,30849)
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_ia = $unsigned(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_inputreg0_q);
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_aa = redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_wraddr_q;
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_ab = redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_aa),
        .data_a(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_ab),
        .q_b(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_q = redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_iq[15:0];

    // redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_outputreg0(DELAY,30848)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_outputreg0_q <= $unsigned(redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_mem_q);
        end
    end

    // valid_fanout_reg158(REG,13453)@165 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg158_q <= $unsigned(redist808_sync_together4364_aunroll_x_in_i_valid_97_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_65117_c_compmm_m159(BLACKBOX,8673)@166
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65117_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_65117_c_compmm_m159 (
        .in_intel_reserved_ffwd_99_0(in_intel_reserved_ffwd_99_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg158_q),
        .out_dest_data_out_99_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_65117_c_compmm_m159_out_dest_data_out_99_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28920)@166 + 5
    // out q@172
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_65117_c_compmm_m159_out_dest_data_out_99_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_65118_c_compmm_m158_out_dest_data_out_100_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649(ADD,9017)@172
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod527_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_b = $unsigned({{5{i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_49_c_compmm_m1648_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_o[33:0];

    // rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x(MUX,18909)@172
    assign rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q or rightShiftStage0Idx1_uid18908_dupName_197_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q;
            1'b1 : rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18908_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x(MUX,18914)@172
    assign rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18913_dupName_197_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18910_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18913_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x(MUX,18919)@172
    assign rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18918_dupName_197_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18915_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18918_dupName_197_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1650_vt_select_20(BITSELECT,10728)@172
    assign i_unnamed_c_compmm_m1650_vt_select_20_b = rightShiftStage2_uid18920_dupName_197_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1650_vt_join(BITJOIN,10727)@172
    assign i_unnamed_c_compmm_m1650_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1650_vt_select_20_b};

    // i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x(BITSELECT,3775)@172
    assign i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x_b = i_unnamed_c_compmm_m1650_vt_join_q[15:0];

    // redist943_i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x_b_1(DELAY,30071)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist943_i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18929_dupName_198_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18928)@172
    assign rightShiftStage1Idx1Rng8_uid18929_dupName_198_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18931_dupName_198_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18930)@172
    assign rightShiftStage1Idx1_uid18931_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18929_dupName_198_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18924_dupName_198_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18923)@172
    assign rightShiftStage0Idx1Rng4_uid18924_dupName_198_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q[33:4];

    // rightShiftStage0Idx1_uid18926_dupName_198_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18925)@172
    assign rightShiftStage0Idx1_uid18926_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18924_dupName_198_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x(MUX,18927)@172
    assign rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q or rightShiftStage0Idx1_uid18926_dupName_198_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_49_i_c_compmm_m1649_q;
            1'b1 : rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18926_dupName_198_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x(MUX,18932)@172
    assign rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18931_dupName_198_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18928_dupName_198_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18931_dupName_198_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1652_vt_select_21(BITSELECT,10731)@172
    assign i_unnamed_c_compmm_m1652_vt_select_21_b = rightShiftStage1_uid18933_dupName_198_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1652_vt_join(BITJOIN,10730)@172
    assign i_unnamed_c_compmm_m1652_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1652_vt_select_21_b};

    // i_unnamed_c_compmm_m1653_sel_x(BITSELECT,6050)@172
    assign i_unnamed_c_compmm_m1653_sel_x_b = i_unnamed_c_compmm_m1652_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1654_BitSelect_for_a(BITSELECT,28452)@172
    assign i_unnamed_c_compmm_m1654_BitSelect_for_a_b = i_unnamed_c_compmm_m1653_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1654_join(BITJOIN,28453)@172
    assign i_unnamed_c_compmm_m1654_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1654_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1654_vt_select_0(BITSELECT,10736)@172
    assign i_unnamed_c_compmm_m1654_vt_select_0_b = i_unnamed_c_compmm_m1654_join_q[0:0];

    // redist208_i_unnamed_c_compmm_m1654_vt_select_0_b_1(DELAY,29336)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist208_i_unnamed_c_compmm_m1654_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1654_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1654_vt_join(BITJOIN,10735)@173
    assign i_unnamed_c_compmm_m1654_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist208_i_unnamed_c_compmm_m1654_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_49_c_compmm_m1655(ADD,7230)@173
    assign i_add_i_i_i_i_i_i_49_c_compmm_m1655_a = {1'b0, i_unnamed_c_compmm_m1654_vt_join_q};
    assign i_add_i_i_i_i_i_i_49_c_compmm_m1655_b = {1'b0, redist943_i_conv_i_i_i_i_i_49_c_compmm_m1651_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_49_c_compmm_m1655_o = $unsigned(i_add_i_i_i_i_i_i_49_c_compmm_m1655_a) + $unsigned(i_add_i_i_i_i_i_i_49_c_compmm_m1655_b);
    assign i_add_i_i_i_i_i_i_49_c_compmm_m1655_q = i_add_i_i_i_i_i_i_49_c_compmm_m1655_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_49_c_compmm_m1655_sel_x(BITSELECT,2244)@173
    assign bgTrunc_i_add_i_i_i_i_i_i_49_c_compmm_m1655_sel_x_b = i_add_i_i_i_i_i_i_49_c_compmm_m1655_q[15:0];

    // i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_sel_x(BITSELECT,3905)@173
    assign i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_49_c_compmm_m1655_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_select_15(BITSELECT,8347)@173
    assign i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_select_15_b = i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_join(BITJOIN,8346)@173
    assign i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_select_15_b};

    // leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(MUX,27358)@173
    assign leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_join_q or leftShiftStage0Idx1_uid27357_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_50_c_compmm_m1675_vt_join_q;
            1'b1 : leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27357_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(MUX,27363)@173
    assign leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s or leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27362_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = leftShiftStage0_uid27359_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27362_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x(MUX,27368)@173
    assign leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s or leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27367_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = leftShiftStage1_uid27364_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27367_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28(BITSELECT,10057)@173
    assign i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28_b = leftShiftStage2_uid27369_i_shl_i_i_i_i_i_i_50_c_compmm_m0_shift_x_q[28:13];

    // redist308_i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28_b_1(DELAY,29436)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist308_i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_join(BITJOIN,10056)@174
    assign i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_join_q = {redist308_i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg155(REG,13450)@167 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg155_q <= $unsigned(redist809_sync_together4364_aunroll_x_in_i_valid_99_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_65120_c_compmm_m156(BLACKBOX,8685)@168
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65120_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_65120_c_compmm_m156 (
        .in_intel_reserved_ffwd_102_0(in_intel_reserved_ffwd_102_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg155_q),
        .out_dest_data_out_102_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_65120_c_compmm_m156_out_dest_data_out_102_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_offset(CONSTANT,30857)
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_offset_q = $unsigned(7'b0100001);

    // redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt(ADD,30858)
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_a = {1'b0, redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_q};
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_b = {1'b0, redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_o <= $unsigned(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_a) + $unsigned(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_b);
        end
    end
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_q = redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_o[7:0];

    // redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_inputreg0(DELAY,30853)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_inputreg0_q <= $unsigned(in_c1_eni5_101_tpl);
        end
    end

    // redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr(COUNTER,30856)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_i <= $unsigned(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_q = redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_i[6:0];

    // redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem(DUALMEM,30855)
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_ia = $unsigned(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_inputreg0_q);
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_aa = redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_wraddr_q;
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_ab = redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_aa),
        .data_a(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_ab),
        .q_b(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_q = redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_iq[15:0];

    // redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_outputreg0(DELAY,30854)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_outputreg0_q <= $unsigned(redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_mem_q);
        end
    end

    // redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt(ADD,30864)
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_a = {1'b0, redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_q};
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_b = {1'b0, redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_o <= $unsigned(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_a) + $unsigned(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_b);
        end
    end
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_q = redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_o[7:0];

    // redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_inputreg0(DELAY,30859)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_inputreg0_q <= $unsigned(in_c1_eni5_102_tpl);
        end
    end

    // redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr(COUNTER,30862)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_i <= $unsigned(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_q = redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_i[6:0];

    // redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem(DUALMEM,30861)
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_ia = $unsigned(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_inputreg0_q);
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_aa = redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_wraddr_q;
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_ab = redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_aa),
        .data_a(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_ab),
        .q_b(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_q = redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_iq[15:0];

    // redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_outputreg0(DELAY,30860)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_outputreg0_q <= $unsigned(redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_mem_q);
        end
    end

    // valid_fanout_reg156(REG,13451)@167 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg156_q <= $unsigned(redist809_sync_together4364_aunroll_x_in_i_valid_99_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_65119_c_compmm_m157(BLACKBOX,8681)@168
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65119_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_65119_c_compmm_m157 (
        .in_intel_reserved_ffwd_101_0(in_intel_reserved_ffwd_101_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg156_q),
        .out_dest_data_out_101_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_65119_c_compmm_m157_out_dest_data_out_101_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28921)@168 + 5
    // out q@174
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_65119_c_compmm_m157_out_dest_data_out_101_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_65120_c_compmm_m156_out_dest_data_out_102_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677(ADD,9019)@174
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod532_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_b = $unsigned({{5{i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_50_c_compmm_m1676_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_o[33:0];

    // rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x(MUX,18971)@174
    assign rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q or rightShiftStage0Idx1_uid18970_dupName_201_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q;
            1'b1 : rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18970_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x(MUX,18976)@174
    assign rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18975_dupName_201_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18972_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18975_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x(MUX,18981)@174
    assign rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18980_dupName_201_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18977_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18980_dupName_201_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1678_vt_select_20(BITSELECT,10750)@174
    assign i_unnamed_c_compmm_m1678_vt_select_20_b = rightShiftStage2_uid18982_dupName_201_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1678_vt_join(BITJOIN,10749)@174
    assign i_unnamed_c_compmm_m1678_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1678_vt_select_20_b};

    // i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x(BITSELECT,3777)@174
    assign i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x_b = i_unnamed_c_compmm_m1678_vt_join_q[15:0];

    // redist941_i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x_b_1(DELAY,30069)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist941_i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18991_dupName_202_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18990)@174
    assign rightShiftStage1Idx1Rng8_uid18991_dupName_202_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18993_dupName_202_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18992)@174
    assign rightShiftStage1Idx1_uid18993_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18991_dupName_202_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18986_dupName_202_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18985)@174
    assign rightShiftStage0Idx1Rng4_uid18986_dupName_202_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q[33:4];

    // rightShiftStage0Idx1_uid18988_dupName_202_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18987)@174
    assign rightShiftStage0Idx1_uid18988_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18986_dupName_202_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x(MUX,18989)@174
    assign rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q or rightShiftStage0Idx1_uid18988_dupName_202_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_50_i_c_compmm_m1677_q;
            1'b1 : rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18988_dupName_202_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x(MUX,18994)@174
    assign rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18993_dupName_202_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18990_dupName_202_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18993_dupName_202_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1680_vt_select_21(BITSELECT,10753)@174
    assign i_unnamed_c_compmm_m1680_vt_select_21_b = rightShiftStage1_uid18995_dupName_202_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1680_vt_join(BITJOIN,10752)@174
    assign i_unnamed_c_compmm_m1680_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1680_vt_select_21_b};

    // i_unnamed_c_compmm_m1681_sel_x(BITSELECT,6052)@174
    assign i_unnamed_c_compmm_m1681_sel_x_b = i_unnamed_c_compmm_m1680_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1682_BitSelect_for_a(BITSELECT,28456)@174
    assign i_unnamed_c_compmm_m1682_BitSelect_for_a_b = i_unnamed_c_compmm_m1681_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1682_join(BITJOIN,28457)@174
    assign i_unnamed_c_compmm_m1682_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1682_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1682_vt_select_0(BITSELECT,10758)@174
    assign i_unnamed_c_compmm_m1682_vt_select_0_b = i_unnamed_c_compmm_m1682_join_q[0:0];

    // redist206_i_unnamed_c_compmm_m1682_vt_select_0_b_1(DELAY,29334)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist206_i_unnamed_c_compmm_m1682_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1682_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1682_vt_join(BITJOIN,10757)@175
    assign i_unnamed_c_compmm_m1682_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist206_i_unnamed_c_compmm_m1682_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_50_c_compmm_m1683(ADD,7232)@175
    assign i_add_i_i_i_i_i_i_50_c_compmm_m1683_a = {1'b0, i_unnamed_c_compmm_m1682_vt_join_q};
    assign i_add_i_i_i_i_i_i_50_c_compmm_m1683_b = {1'b0, redist941_i_conv_i_i_i_i_i_50_c_compmm_m1679_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_50_c_compmm_m1683_o = $unsigned(i_add_i_i_i_i_i_i_50_c_compmm_m1683_a) + $unsigned(i_add_i_i_i_i_i_i_50_c_compmm_m1683_b);
    assign i_add_i_i_i_i_i_i_50_c_compmm_m1683_q = i_add_i_i_i_i_i_i_50_c_compmm_m1683_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_50_c_compmm_m1683_sel_x(BITSELECT,2246)@175
    assign bgTrunc_i_add_i_i_i_i_i_i_50_c_compmm_m1683_sel_x_b = i_add_i_i_i_i_i_i_50_c_compmm_m1683_q[15:0];

    // i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_sel_x(BITSELECT,3906)@175
    assign i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_50_c_compmm_m1683_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_select_15(BITSELECT,8351)@175
    assign i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_select_15_b = i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_join(BITJOIN,8350)@175
    assign i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_select_15_b};

    // leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(MUX,27376)@175
    assign leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_join_q or leftShiftStage0Idx1_uid27375_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_51_c_compmm_m1703_vt_join_q;
            1'b1 : leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27375_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(MUX,27381)@175
    assign leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s or leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27380_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = leftShiftStage0_uid27377_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27380_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x(MUX,27386)@175
    assign leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s or leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27385_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = leftShiftStage1_uid27382_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27385_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28(BITSELECT,10060)@175
    assign i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28_b = leftShiftStage2_uid27387_i_shl_i_i_i_i_i_i_51_c_compmm_m0_shift_x_q[28:13];

    // redist307_i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28_b_1(DELAY,29435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist307_i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_join(BITJOIN,10059)@176
    assign i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_join_q = {redist307_i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg153(REG,13448)@169 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg153_q <= $unsigned(redist810_sync_together4364_aunroll_x_in_i_valid_101_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_65122_c_compmm_m154(BLACKBOX,8693)@170
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65122_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_65122_c_compmm_m154 (
        .in_intel_reserved_ffwd_104_0(in_intel_reserved_ffwd_104_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg153_q),
        .out_dest_data_out_104_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_65122_c_compmm_m154_out_dest_data_out_104_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_offset(CONSTANT,30869)
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_offset_q = $unsigned(7'b0011111);

    // redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt(ADD,30870)
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_a = {1'b0, redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_q};
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_b = {1'b0, redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_o <= $unsigned(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_a) + $unsigned(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_b);
        end
    end
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_q = redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_o[7:0];

    // redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_inputreg0(DELAY,30865)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_inputreg0_q <= $unsigned(in_c1_eni5_103_tpl);
        end
    end

    // redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr(COUNTER,30868)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_i <= $unsigned(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_q = redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_i[6:0];

    // redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem(DUALMEM,30867)
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_ia = $unsigned(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_inputreg0_q);
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_aa = redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_wraddr_q;
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_ab = redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_aa),
        .data_a(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_ab),
        .q_b(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_q = redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_iq[15:0];

    // redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_outputreg0(DELAY,30866)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_outputreg0_q <= $unsigned(redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_mem_q);
        end
    end

    // redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt(ADD,30876)
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_a = {1'b0, redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_q};
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_b = {1'b0, redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_o <= $unsigned(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_a) + $unsigned(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_b);
        end
    end
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_q = redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_o[7:0];

    // redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_inputreg0(DELAY,30871)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_inputreg0_q <= $unsigned(in_c1_eni5_104_tpl);
        end
    end

    // redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr(COUNTER,30874)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_i <= $unsigned(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_q = redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_i[6:0];

    // redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem(DUALMEM,30873)
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_ia = $unsigned(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_inputreg0_q);
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_aa = redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_wraddr_q;
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_ab = redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_aa),
        .data_a(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_ab),
        .q_b(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_q = redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_iq[15:0];

    // redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_outputreg0(DELAY,30872)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_outputreg0_q <= $unsigned(redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_mem_q);
        end
    end

    // valid_fanout_reg154(REG,13449)@169 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg154_q <= $unsigned(redist810_sync_together4364_aunroll_x_in_i_valid_101_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_65121_c_compmm_m155(BLACKBOX,8689)@170
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65121_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_65121_c_compmm_m155 (
        .in_intel_reserved_ffwd_103_0(in_intel_reserved_ffwd_103_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg154_q),
        .out_dest_data_out_103_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_65121_c_compmm_m155_out_dest_data_out_103_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28922)@170 + 5
    // out q@176
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_65121_c_compmm_m155_out_dest_data_out_103_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_65122_c_compmm_m154_out_dest_data_out_104_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705(ADD,9020)@176
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod537_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_b = $unsigned({{5{i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_51_c_compmm_m1704_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_o[33:0];

    // rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x(MUX,19033)@176
    assign rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q or rightShiftStage0Idx1_uid19032_dupName_205_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q;
            1'b1 : rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19032_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x(MUX,19038)@176
    assign rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19037_dupName_205_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19034_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19037_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x(MUX,19043)@176
    assign rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19042_dupName_205_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19039_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19042_dupName_205_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1706_vt_select_20(BITSELECT,10772)@176
    assign i_unnamed_c_compmm_m1706_vt_select_20_b = rightShiftStage2_uid19044_dupName_205_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1706_vt_join(BITJOIN,10771)@176
    assign i_unnamed_c_compmm_m1706_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1706_vt_select_20_b};

    // i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x(BITSELECT,3778)@176
    assign i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x_b = i_unnamed_c_compmm_m1706_vt_join_q[15:0];

    // redist940_i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x_b_1(DELAY,30068)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist940_i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19053_dupName_206_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19052)@176
    assign rightShiftStage1Idx1Rng8_uid19053_dupName_206_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19055_dupName_206_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19054)@176
    assign rightShiftStage1Idx1_uid19055_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19053_dupName_206_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19048_dupName_206_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19047)@176
    assign rightShiftStage0Idx1Rng4_uid19048_dupName_206_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q[33:4];

    // rightShiftStage0Idx1_uid19050_dupName_206_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19049)@176
    assign rightShiftStage0Idx1_uid19050_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19048_dupName_206_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x(MUX,19051)@176
    assign rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q or rightShiftStage0Idx1_uid19050_dupName_206_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_51_i_c_compmm_m1705_q;
            1'b1 : rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19050_dupName_206_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x(MUX,19056)@176
    assign rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19055_dupName_206_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19052_dupName_206_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19055_dupName_206_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1708_vt_select_21(BITSELECT,10775)@176
    assign i_unnamed_c_compmm_m1708_vt_select_21_b = rightShiftStage1_uid19057_dupName_206_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1708_vt_join(BITJOIN,10774)@176
    assign i_unnamed_c_compmm_m1708_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1708_vt_select_21_b};

    // i_unnamed_c_compmm_m1709_sel_x(BITSELECT,6054)@176
    assign i_unnamed_c_compmm_m1709_sel_x_b = i_unnamed_c_compmm_m1708_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1710_BitSelect_for_a(BITSELECT,28460)@176
    assign i_unnamed_c_compmm_m1710_BitSelect_for_a_b = i_unnamed_c_compmm_m1709_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1710_join(BITJOIN,28461)@176
    assign i_unnamed_c_compmm_m1710_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1710_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1710_vt_select_0(BITSELECT,10780)@176
    assign i_unnamed_c_compmm_m1710_vt_select_0_b = i_unnamed_c_compmm_m1710_join_q[0:0];

    // redist204_i_unnamed_c_compmm_m1710_vt_select_0_b_1(DELAY,29332)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist204_i_unnamed_c_compmm_m1710_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1710_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1710_vt_join(BITJOIN,10779)@177
    assign i_unnamed_c_compmm_m1710_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist204_i_unnamed_c_compmm_m1710_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_51_c_compmm_m1711(ADD,7233)@177
    assign i_add_i_i_i_i_i_i_51_c_compmm_m1711_a = {1'b0, i_unnamed_c_compmm_m1710_vt_join_q};
    assign i_add_i_i_i_i_i_i_51_c_compmm_m1711_b = {1'b0, redist940_i_conv_i_i_i_i_i_51_c_compmm_m1707_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_51_c_compmm_m1711_o = $unsigned(i_add_i_i_i_i_i_i_51_c_compmm_m1711_a) + $unsigned(i_add_i_i_i_i_i_i_51_c_compmm_m1711_b);
    assign i_add_i_i_i_i_i_i_51_c_compmm_m1711_q = i_add_i_i_i_i_i_i_51_c_compmm_m1711_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_51_c_compmm_m1711_sel_x(BITSELECT,2247)@177
    assign bgTrunc_i_add_i_i_i_i_i_i_51_c_compmm_m1711_sel_x_b = i_add_i_i_i_i_i_i_51_c_compmm_m1711_q[15:0];

    // i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_sel_x(BITSELECT,3907)@177
    assign i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_51_c_compmm_m1711_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_select_15(BITSELECT,8355)@177
    assign i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_select_15_b = i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_join(BITJOIN,8354)@177
    assign i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_select_15_b};

    // leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(MUX,27394)@177
    assign leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_join_q or leftShiftStage0Idx1_uid27393_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_52_c_compmm_m1731_vt_join_q;
            1'b1 : leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27393_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(MUX,27399)@177
    assign leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s or leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27398_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = leftShiftStage0_uid27395_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27398_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x(MUX,27404)@177
    assign leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s or leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27403_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = leftShiftStage1_uid27400_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27403_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28(BITSELECT,10063)@177
    assign i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28_b = leftShiftStage2_uid27405_i_shl_i_i_i_i_i_i_52_c_compmm_m0_shift_x_q[28:13];

    // redist306_i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28_b_1(DELAY,29434)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist306_i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_join(BITJOIN,10062)@178
    assign i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_join_q = {redist306_i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg151(REG,13446)@171 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg151_q <= $unsigned(redist811_sync_together4364_aunroll_x_in_i_valid_103_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_65124_c_compmm_m152(BLACKBOX,8705)@172
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65124_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_65124_c_compmm_m152 (
        .in_intel_reserved_ffwd_106_0(in_intel_reserved_ffwd_106_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg151_q),
        .out_dest_data_out_106_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_65124_c_compmm_m152_out_dest_data_out_106_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_offset(CONSTANT,30881)
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_offset_q = $unsigned(7'b0011101);

    // redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt(ADD,30882)
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_a = {1'b0, redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_q};
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_b = {1'b0, redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_o <= $unsigned(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_a) + $unsigned(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_b);
        end
    end
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_q = redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_o[7:0];

    // redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_inputreg0(DELAY,30877)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_inputreg0_q <= $unsigned(in_c1_eni5_105_tpl);
        end
    end

    // redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr(COUNTER,30880)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_i <= $unsigned(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_q = redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_i[6:0];

    // redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem(DUALMEM,30879)
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_ia = $unsigned(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_inputreg0_q);
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_aa = redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_wraddr_q;
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_ab = redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_aa),
        .data_a(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_ab),
        .q_b(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_q = redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_iq[15:0];

    // redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_outputreg0(DELAY,30878)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_outputreg0_q <= $unsigned(redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_mem_q);
        end
    end

    // redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt(ADD,30888)
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_a = {1'b0, redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_q};
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_b = {1'b0, redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_o <= $unsigned(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_a) + $unsigned(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_b);
        end
    end
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_q = redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_o[7:0];

    // redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_inputreg0(DELAY,30883)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_inputreg0_q <= $unsigned(in_c1_eni5_106_tpl);
        end
    end

    // redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr(COUNTER,30886)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_i <= $unsigned(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_q = redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_i[6:0];

    // redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem(DUALMEM,30885)
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_ia = $unsigned(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_inputreg0_q);
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_aa = redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_wraddr_q;
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_ab = redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_aa),
        .data_a(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_ab),
        .q_b(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_q = redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_iq[15:0];

    // redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_outputreg0(DELAY,30884)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_outputreg0_q <= $unsigned(redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_mem_q);
        end
    end

    // valid_fanout_reg152(REG,13447)@171 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg152_q <= $unsigned(redist811_sync_together4364_aunroll_x_in_i_valid_103_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_65123_c_compmm_m153(BLACKBOX,8701)@172
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65123_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_65123_c_compmm_m153 (
        .in_intel_reserved_ffwd_105_0(in_intel_reserved_ffwd_105_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg152_q),
        .out_dest_data_out_105_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_65123_c_compmm_m153_out_dest_data_out_105_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28923)@172 + 5
    // out q@178
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_65123_c_compmm_m153_out_dest_data_out_105_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_65124_c_compmm_m152_out_dest_data_out_106_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733(ADD,9021)@178
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod542_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_b = $unsigned({{5{i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_52_c_compmm_m1732_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_o[33:0];

    // rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x(MUX,19095)@178
    assign rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q or rightShiftStage0Idx1_uid19094_dupName_209_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q;
            1'b1 : rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19094_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x(MUX,19100)@178
    assign rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19099_dupName_209_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19096_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19099_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x(MUX,19105)@178
    assign rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19104_dupName_209_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19101_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19104_dupName_209_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1734_vt_select_20(BITSELECT,10794)@178
    assign i_unnamed_c_compmm_m1734_vt_select_20_b = rightShiftStage2_uid19106_dupName_209_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1734_vt_join(BITJOIN,10793)@178
    assign i_unnamed_c_compmm_m1734_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1734_vt_select_20_b};

    // i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x(BITSELECT,3779)@178
    assign i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x_b = i_unnamed_c_compmm_m1734_vt_join_q[15:0];

    // redist939_i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x_b_1(DELAY,30067)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist939_i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19115_dupName_210_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19114)@178
    assign rightShiftStage1Idx1Rng8_uid19115_dupName_210_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19117_dupName_210_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19116)@178
    assign rightShiftStage1Idx1_uid19117_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19115_dupName_210_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19110_dupName_210_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19109)@178
    assign rightShiftStage0Idx1Rng4_uid19110_dupName_210_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q[33:4];

    // rightShiftStage0Idx1_uid19112_dupName_210_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19111)@178
    assign rightShiftStage0Idx1_uid19112_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19110_dupName_210_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x(MUX,19113)@178
    assign rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q or rightShiftStage0Idx1_uid19112_dupName_210_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_52_i_c_compmm_m1733_q;
            1'b1 : rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19112_dupName_210_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x(MUX,19118)@178
    assign rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19117_dupName_210_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19114_dupName_210_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19117_dupName_210_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1736_vt_select_21(BITSELECT,10797)@178
    assign i_unnamed_c_compmm_m1736_vt_select_21_b = rightShiftStage1_uid19119_dupName_210_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1736_vt_join(BITJOIN,10796)@178
    assign i_unnamed_c_compmm_m1736_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1736_vt_select_21_b};

    // i_unnamed_c_compmm_m1737_sel_x(BITSELECT,6056)@178
    assign i_unnamed_c_compmm_m1737_sel_x_b = i_unnamed_c_compmm_m1736_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1738_BitSelect_for_a(BITSELECT,28464)@178
    assign i_unnamed_c_compmm_m1738_BitSelect_for_a_b = i_unnamed_c_compmm_m1737_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1738_join(BITJOIN,28465)@178
    assign i_unnamed_c_compmm_m1738_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1738_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1738_vt_select_0(BITSELECT,10802)@178
    assign i_unnamed_c_compmm_m1738_vt_select_0_b = i_unnamed_c_compmm_m1738_join_q[0:0];

    // redist202_i_unnamed_c_compmm_m1738_vt_select_0_b_1(DELAY,29330)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist202_i_unnamed_c_compmm_m1738_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1738_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1738_vt_join(BITJOIN,10801)@179
    assign i_unnamed_c_compmm_m1738_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist202_i_unnamed_c_compmm_m1738_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_52_c_compmm_m1739(ADD,7234)@179
    assign i_add_i_i_i_i_i_i_52_c_compmm_m1739_a = {1'b0, i_unnamed_c_compmm_m1738_vt_join_q};
    assign i_add_i_i_i_i_i_i_52_c_compmm_m1739_b = {1'b0, redist939_i_conv_i_i_i_i_i_52_c_compmm_m1735_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_52_c_compmm_m1739_o = $unsigned(i_add_i_i_i_i_i_i_52_c_compmm_m1739_a) + $unsigned(i_add_i_i_i_i_i_i_52_c_compmm_m1739_b);
    assign i_add_i_i_i_i_i_i_52_c_compmm_m1739_q = i_add_i_i_i_i_i_i_52_c_compmm_m1739_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_52_c_compmm_m1739_sel_x(BITSELECT,2248)@179
    assign bgTrunc_i_add_i_i_i_i_i_i_52_c_compmm_m1739_sel_x_b = i_add_i_i_i_i_i_i_52_c_compmm_m1739_q[15:0];

    // i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_sel_x(BITSELECT,3908)@179
    assign i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_52_c_compmm_m1739_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_select_15(BITSELECT,8359)@179
    assign i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_select_15_b = i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_join(BITJOIN,8358)@179
    assign i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_select_15_b};

    // leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(MUX,27412)@179
    assign leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_join_q or leftShiftStage0Idx1_uid27411_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_53_c_compmm_m1759_vt_join_q;
            1'b1 : leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27411_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(MUX,27417)@179
    assign leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s or leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27416_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = leftShiftStage0_uid27413_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27416_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x(MUX,27422)@179
    assign leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s or leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27421_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = leftShiftStage1_uid27418_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27421_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28(BITSELECT,10066)@179
    assign i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28_b = leftShiftStage2_uid27423_i_shl_i_i_i_i_i_i_53_c_compmm_m0_shift_x_q[28:13];

    // redist305_i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28_b_1(DELAY,29433)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist305_i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_join(BITJOIN,10065)@180
    assign i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_join_q = {redist305_i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg149(REG,13444)@173 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg149_q <= $unsigned(redist812_sync_together4364_aunroll_x_in_i_valid_105_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_65126_c_compmm_m150(BLACKBOX,8713)@174
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65126_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_65126_c_compmm_m150 (
        .in_intel_reserved_ffwd_108_0(in_intel_reserved_ffwd_108_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg149_q),
        .out_dest_data_out_108_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_65126_c_compmm_m150_out_dest_data_out_108_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_offset(CONSTANT,30893)
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_offset_q = $unsigned(7'b0011011);

    // redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt(ADD,30894)
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_a = {1'b0, redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_q};
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_b = {1'b0, redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_o <= $unsigned(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_a) + $unsigned(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_b);
        end
    end
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_q = redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_o[7:0];

    // redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_inputreg0(DELAY,30889)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_inputreg0_q <= $unsigned(in_c1_eni5_107_tpl);
        end
    end

    // redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr(COUNTER,30892)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_i <= $unsigned(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_q = redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_i[6:0];

    // redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem(DUALMEM,30891)
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_ia = $unsigned(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_inputreg0_q);
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_aa = redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_wraddr_q;
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_ab = redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_aa),
        .data_a(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_ab),
        .q_b(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_q = redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_iq[15:0];

    // redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_outputreg0(DELAY,30890)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_outputreg0_q <= $unsigned(redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_mem_q);
        end
    end

    // redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt(ADD,30900)
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_a = {1'b0, redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_q};
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_b = {1'b0, redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_o <= $unsigned(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_a) + $unsigned(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_b);
        end
    end
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_q = redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_o[7:0];

    // redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_inputreg0(DELAY,30895)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_inputreg0_q <= $unsigned(in_c1_eni5_108_tpl);
        end
    end

    // redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr(COUNTER,30898)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_i <= $unsigned(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_q = redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_i[6:0];

    // redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem(DUALMEM,30897)
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_ia = $unsigned(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_inputreg0_q);
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_aa = redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_wraddr_q;
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_ab = redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_aa),
        .data_a(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_ab),
        .q_b(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_q = redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_iq[15:0];

    // redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_outputreg0(DELAY,30896)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_outputreg0_q <= $unsigned(redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_mem_q);
        end
    end

    // valid_fanout_reg150(REG,13445)@173 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg150_q <= $unsigned(redist812_sync_together4364_aunroll_x_in_i_valid_105_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_65125_c_compmm_m151(BLACKBOX,8709)@174
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65125_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_65125_c_compmm_m151 (
        .in_intel_reserved_ffwd_107_0(in_intel_reserved_ffwd_107_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg150_q),
        .out_dest_data_out_107_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_65125_c_compmm_m151_out_dest_data_out_107_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28924)@174 + 5
    // out q@180
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_65125_c_compmm_m151_out_dest_data_out_107_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_65126_c_compmm_m150_out_dest_data_out_108_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761(ADD,9022)@180
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod547_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_b = $unsigned({{5{i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_53_c_compmm_m1760_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_o[33:0];

    // rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x(MUX,19157)@180
    assign rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q or rightShiftStage0Idx1_uid19156_dupName_213_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q;
            1'b1 : rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19156_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x(MUX,19162)@180
    assign rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19161_dupName_213_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19158_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19161_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x(MUX,19167)@180
    assign rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19166_dupName_213_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19163_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19166_dupName_213_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1762_vt_select_20(BITSELECT,10816)@180
    assign i_unnamed_c_compmm_m1762_vt_select_20_b = rightShiftStage2_uid19168_dupName_213_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1762_vt_join(BITJOIN,10815)@180
    assign i_unnamed_c_compmm_m1762_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1762_vt_select_20_b};

    // i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x(BITSELECT,3780)@180
    assign i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x_b = i_unnamed_c_compmm_m1762_vt_join_q[15:0];

    // redist938_i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x_b_1(DELAY,30066)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist938_i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19177_dupName_214_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19176)@180
    assign rightShiftStage1Idx1Rng8_uid19177_dupName_214_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19179_dupName_214_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19178)@180
    assign rightShiftStage1Idx1_uid19179_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19177_dupName_214_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19172_dupName_214_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19171)@180
    assign rightShiftStage0Idx1Rng4_uid19172_dupName_214_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q[33:4];

    // rightShiftStage0Idx1_uid19174_dupName_214_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19173)@180
    assign rightShiftStage0Idx1_uid19174_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19172_dupName_214_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x(MUX,19175)@180
    assign rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q or rightShiftStage0Idx1_uid19174_dupName_214_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_53_i_c_compmm_m1761_q;
            1'b1 : rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19174_dupName_214_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x(MUX,19180)@180
    assign rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19179_dupName_214_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19176_dupName_214_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19179_dupName_214_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1764_vt_select_21(BITSELECT,10819)@180
    assign i_unnamed_c_compmm_m1764_vt_select_21_b = rightShiftStage1_uid19181_dupName_214_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1764_vt_join(BITJOIN,10818)@180
    assign i_unnamed_c_compmm_m1764_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1764_vt_select_21_b};

    // i_unnamed_c_compmm_m1765_sel_x(BITSELECT,6058)@180
    assign i_unnamed_c_compmm_m1765_sel_x_b = i_unnamed_c_compmm_m1764_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1766_BitSelect_for_a(BITSELECT,28468)@180
    assign i_unnamed_c_compmm_m1766_BitSelect_for_a_b = i_unnamed_c_compmm_m1765_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1766_join(BITJOIN,28469)@180
    assign i_unnamed_c_compmm_m1766_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1766_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1766_vt_select_0(BITSELECT,10824)@180
    assign i_unnamed_c_compmm_m1766_vt_select_0_b = i_unnamed_c_compmm_m1766_join_q[0:0];

    // redist200_i_unnamed_c_compmm_m1766_vt_select_0_b_1(DELAY,29328)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist200_i_unnamed_c_compmm_m1766_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1766_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1766_vt_join(BITJOIN,10823)@181
    assign i_unnamed_c_compmm_m1766_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist200_i_unnamed_c_compmm_m1766_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_53_c_compmm_m1767(ADD,7235)@181
    assign i_add_i_i_i_i_i_i_53_c_compmm_m1767_a = {1'b0, i_unnamed_c_compmm_m1766_vt_join_q};
    assign i_add_i_i_i_i_i_i_53_c_compmm_m1767_b = {1'b0, redist938_i_conv_i_i_i_i_i_53_c_compmm_m1763_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_53_c_compmm_m1767_o = $unsigned(i_add_i_i_i_i_i_i_53_c_compmm_m1767_a) + $unsigned(i_add_i_i_i_i_i_i_53_c_compmm_m1767_b);
    assign i_add_i_i_i_i_i_i_53_c_compmm_m1767_q = i_add_i_i_i_i_i_i_53_c_compmm_m1767_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_53_c_compmm_m1767_sel_x(BITSELECT,2249)@181
    assign bgTrunc_i_add_i_i_i_i_i_i_53_c_compmm_m1767_sel_x_b = i_add_i_i_i_i_i_i_53_c_compmm_m1767_q[15:0];

    // i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_sel_x(BITSELECT,3909)@181
    assign i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_53_c_compmm_m1767_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_select_15(BITSELECT,8363)@181
    assign i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_select_15_b = i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_join(BITJOIN,8362)@181
    assign i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_select_15_b};

    // leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(MUX,27430)@181
    assign leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_join_q or leftShiftStage0Idx1_uid27429_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_54_c_compmm_m1787_vt_join_q;
            1'b1 : leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27429_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(MUX,27435)@181
    assign leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s or leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27434_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = leftShiftStage0_uid27431_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27434_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x(MUX,27440)@181
    assign leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s or leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27439_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = leftShiftStage1_uid27436_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27439_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28(BITSELECT,10069)@181
    assign i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28_b = leftShiftStage2_uid27441_i_shl_i_i_i_i_i_i_54_c_compmm_m0_shift_x_q[28:13];

    // redist304_i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28_b_1(DELAY,29432)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist304_i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_join(BITJOIN,10068)@182
    assign i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_join_q = {redist304_i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg147(REG,13442)@175 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg147_q <= $unsigned(redist813_sync_together4364_aunroll_x_in_i_valid_107_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_65128_c_compmm_m148(BLACKBOX,8721)@176
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65128_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_65128_c_compmm_m148 (
        .in_intel_reserved_ffwd_110_0(in_intel_reserved_ffwd_110_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg147_q),
        .out_dest_data_out_110_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_65128_c_compmm_m148_out_dest_data_out_110_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_offset(CONSTANT,30905)
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_offset_q = $unsigned(7'b0011001);

    // redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt(ADD,30906)
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_a = {1'b0, redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_q};
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_b = {1'b0, redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_o <= $unsigned(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_a) + $unsigned(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_b);
        end
    end
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_q = redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_o[7:0];

    // redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_inputreg0(DELAY,30901)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_inputreg0_q <= $unsigned(in_c1_eni5_109_tpl);
        end
    end

    // redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr(COUNTER,30904)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_i <= $unsigned(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_q = redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_i[6:0];

    // redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem(DUALMEM,30903)
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_ia = $unsigned(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_inputreg0_q);
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_aa = redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_wraddr_q;
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_ab = redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_aa),
        .data_a(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_ab),
        .q_b(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_q = redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_iq[15:0];

    // redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_outputreg0(DELAY,30902)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_outputreg0_q <= $unsigned(redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_mem_q);
        end
    end

    // redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt(ADD,30912)
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_a = {1'b0, redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_q};
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_b = {1'b0, redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_o <= $unsigned(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_a) + $unsigned(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_b);
        end
    end
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_q = redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_o[7:0];

    // redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_inputreg0(DELAY,30907)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_inputreg0_q <= $unsigned(in_c1_eni5_110_tpl);
        end
    end

    // redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr(COUNTER,30910)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_i <= $unsigned(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_q = redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_i[6:0];

    // redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem(DUALMEM,30909)
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_ia = $unsigned(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_inputreg0_q);
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_aa = redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_wraddr_q;
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_ab = redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_aa),
        .data_a(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_ab),
        .q_b(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_q = redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_iq[15:0];

    // redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_outputreg0(DELAY,30908)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_outputreg0_q <= $unsigned(redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_mem_q);
        end
    end

    // valid_fanout_reg148(REG,13443)@175 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg148_q <= $unsigned(redist813_sync_together4364_aunroll_x_in_i_valid_107_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_65127_c_compmm_m149(BLACKBOX,8717)@176
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65127_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_65127_c_compmm_m149 (
        .in_intel_reserved_ffwd_109_0(in_intel_reserved_ffwd_109_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg148_q),
        .out_dest_data_out_109_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_65127_c_compmm_m149_out_dest_data_out_109_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28925)@176 + 5
    // out q@182
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_65127_c_compmm_m149_out_dest_data_out_109_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_65128_c_compmm_m148_out_dest_data_out_110_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789(ADD,9023)@182
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod552_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_b = $unsigned({{5{i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_54_c_compmm_m1788_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_o[33:0];

    // rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x(MUX,19219)@182
    assign rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q or rightShiftStage0Idx1_uid19218_dupName_217_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q;
            1'b1 : rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19218_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x(MUX,19224)@182
    assign rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19223_dupName_217_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19220_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19223_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x(MUX,19229)@182
    assign rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19228_dupName_217_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19225_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19228_dupName_217_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1790_vt_select_20(BITSELECT,10838)@182
    assign i_unnamed_c_compmm_m1790_vt_select_20_b = rightShiftStage2_uid19230_dupName_217_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1790_vt_join(BITJOIN,10837)@182
    assign i_unnamed_c_compmm_m1790_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1790_vt_select_20_b};

    // i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x(BITSELECT,3781)@182
    assign i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x_b = i_unnamed_c_compmm_m1790_vt_join_q[15:0];

    // redist937_i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x_b_1(DELAY,30065)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist937_i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19239_dupName_218_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19238)@182
    assign rightShiftStage1Idx1Rng8_uid19239_dupName_218_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19241_dupName_218_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19240)@182
    assign rightShiftStage1Idx1_uid19241_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19239_dupName_218_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19234_dupName_218_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19233)@182
    assign rightShiftStage0Idx1Rng4_uid19234_dupName_218_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q[33:4];

    // rightShiftStage0Idx1_uid19236_dupName_218_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19235)@182
    assign rightShiftStage0Idx1_uid19236_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19234_dupName_218_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x(MUX,19237)@182
    assign rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q or rightShiftStage0Idx1_uid19236_dupName_218_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_54_i_c_compmm_m1789_q;
            1'b1 : rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19236_dupName_218_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x(MUX,19242)@182
    assign rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19241_dupName_218_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19238_dupName_218_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19241_dupName_218_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1792_vt_select_21(BITSELECT,10841)@182
    assign i_unnamed_c_compmm_m1792_vt_select_21_b = rightShiftStage1_uid19243_dupName_218_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1792_vt_join(BITJOIN,10840)@182
    assign i_unnamed_c_compmm_m1792_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1792_vt_select_21_b};

    // i_unnamed_c_compmm_m1793_sel_x(BITSELECT,6060)@182
    assign i_unnamed_c_compmm_m1793_sel_x_b = i_unnamed_c_compmm_m1792_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1794_BitSelect_for_a(BITSELECT,28472)@182
    assign i_unnamed_c_compmm_m1794_BitSelect_for_a_b = i_unnamed_c_compmm_m1793_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1794_join(BITJOIN,28473)@182
    assign i_unnamed_c_compmm_m1794_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1794_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1794_vt_select_0(BITSELECT,10846)@182
    assign i_unnamed_c_compmm_m1794_vt_select_0_b = i_unnamed_c_compmm_m1794_join_q[0:0];

    // redist198_i_unnamed_c_compmm_m1794_vt_select_0_b_1(DELAY,29326)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist198_i_unnamed_c_compmm_m1794_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1794_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1794_vt_join(BITJOIN,10845)@183
    assign i_unnamed_c_compmm_m1794_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist198_i_unnamed_c_compmm_m1794_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_54_c_compmm_m1795(ADD,7236)@183
    assign i_add_i_i_i_i_i_i_54_c_compmm_m1795_a = {1'b0, i_unnamed_c_compmm_m1794_vt_join_q};
    assign i_add_i_i_i_i_i_i_54_c_compmm_m1795_b = {1'b0, redist937_i_conv_i_i_i_i_i_54_c_compmm_m1791_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_54_c_compmm_m1795_o = $unsigned(i_add_i_i_i_i_i_i_54_c_compmm_m1795_a) + $unsigned(i_add_i_i_i_i_i_i_54_c_compmm_m1795_b);
    assign i_add_i_i_i_i_i_i_54_c_compmm_m1795_q = i_add_i_i_i_i_i_i_54_c_compmm_m1795_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_54_c_compmm_m1795_sel_x(BITSELECT,2250)@183
    assign bgTrunc_i_add_i_i_i_i_i_i_54_c_compmm_m1795_sel_x_b = i_add_i_i_i_i_i_i_54_c_compmm_m1795_q[15:0];

    // i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_sel_x(BITSELECT,3910)@183
    assign i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_54_c_compmm_m1795_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_select_15(BITSELECT,8367)@183
    assign i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_select_15_b = i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_join(BITJOIN,8366)@183
    assign i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_select_15_b};

    // leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(MUX,27448)@183
    assign leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_join_q or leftShiftStage0Idx1_uid27447_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_55_c_compmm_m1815_vt_join_q;
            1'b1 : leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27447_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(MUX,27453)@183
    assign leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s or leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27452_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = leftShiftStage0_uid27449_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27452_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x(MUX,27458)@183
    assign leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s or leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27457_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = leftShiftStage1_uid27454_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27457_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28(BITSELECT,10072)@183
    assign i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28_b = leftShiftStage2_uid27459_i_shl_i_i_i_i_i_i_55_c_compmm_m0_shift_x_q[28:13];

    // redist303_i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28_b_1(DELAY,29431)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist303_i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_join(BITJOIN,10071)@184
    assign i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_join_q = {redist303_i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg145(REG,13440)@177 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg145_q <= $unsigned(redist814_sync_together4364_aunroll_x_in_i_valid_109_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_65130_c_compmm_m146(BLACKBOX,8729)@178
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65130_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_65130_c_compmm_m146 (
        .in_intel_reserved_ffwd_112_0(in_intel_reserved_ffwd_112_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg145_q),
        .out_dest_data_out_112_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_65130_c_compmm_m146_out_dest_data_out_112_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_offset(CONSTANT,30917)
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_offset_q = $unsigned(7'b0010111);

    // redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt(ADD,30918)
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_a = {1'b0, redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_q};
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_b = {1'b0, redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_o <= $unsigned(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_a) + $unsigned(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_b);
        end
    end
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_q = redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_o[7:0];

    // redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_inputreg0(DELAY,30913)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_inputreg0_q <= $unsigned(in_c1_eni5_111_tpl);
        end
    end

    // redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr(COUNTER,30916)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_i <= $unsigned(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_q = redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_i[6:0];

    // redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem(DUALMEM,30915)
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_ia = $unsigned(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_inputreg0_q);
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_aa = redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_wraddr_q;
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_ab = redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_aa),
        .data_a(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_ab),
        .q_b(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_q = redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_iq[15:0];

    // redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_outputreg0(DELAY,30914)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_outputreg0_q <= $unsigned(redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_mem_q);
        end
    end

    // redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt(ADD,30924)
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_a = {1'b0, redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_q};
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_b = {1'b0, redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_o <= $unsigned(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_a) + $unsigned(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_b);
        end
    end
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_q = redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_o[7:0];

    // redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_inputreg0(DELAY,30919)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_inputreg0_q <= $unsigned(in_c1_eni5_112_tpl);
        end
    end

    // redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr(COUNTER,30922)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_i <= $unsigned(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_q = redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_i[6:0];

    // redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem(DUALMEM,30921)
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_ia = $unsigned(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_inputreg0_q);
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_aa = redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_wraddr_q;
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_ab = redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_aa),
        .data_a(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_ab),
        .q_b(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_q = redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_iq[15:0];

    // redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_outputreg0(DELAY,30920)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_outputreg0_q <= $unsigned(redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_mem_q);
        end
    end

    // valid_fanout_reg146(REG,13441)@177 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg146_q <= $unsigned(redist814_sync_together4364_aunroll_x_in_i_valid_109_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_65129_c_compmm_m147(BLACKBOX,8725)@178
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65129_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_65129_c_compmm_m147 (
        .in_intel_reserved_ffwd_111_0(in_intel_reserved_ffwd_111_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg146_q),
        .out_dest_data_out_111_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_65129_c_compmm_m147_out_dest_data_out_111_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28926)@178 + 5
    // out q@184
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_65129_c_compmm_m147_out_dest_data_out_111_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_65130_c_compmm_m146_out_dest_data_out_112_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817(ADD,9024)@184
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod557_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_b = $unsigned({{5{i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_55_c_compmm_m1816_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_o[33:0];

    // rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x(MUX,19281)@184
    assign rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q or rightShiftStage0Idx1_uid19280_dupName_221_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q;
            1'b1 : rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19280_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x(MUX,19286)@184
    assign rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19285_dupName_221_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19282_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19285_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x(MUX,19291)@184
    assign rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19290_dupName_221_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19287_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19290_dupName_221_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1818_vt_select_20(BITSELECT,10860)@184
    assign i_unnamed_c_compmm_m1818_vt_select_20_b = rightShiftStage2_uid19292_dupName_221_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1818_vt_join(BITJOIN,10859)@184
    assign i_unnamed_c_compmm_m1818_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1818_vt_select_20_b};

    // i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x(BITSELECT,3782)@184
    assign i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x_b = i_unnamed_c_compmm_m1818_vt_join_q[15:0];

    // redist936_i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x_b_1(DELAY,30064)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist936_i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19301_dupName_222_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19300)@184
    assign rightShiftStage1Idx1Rng8_uid19301_dupName_222_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19303_dupName_222_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19302)@184
    assign rightShiftStage1Idx1_uid19303_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19301_dupName_222_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19296_dupName_222_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19295)@184
    assign rightShiftStage0Idx1Rng4_uid19296_dupName_222_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q[33:4];

    // rightShiftStage0Idx1_uid19298_dupName_222_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19297)@184
    assign rightShiftStage0Idx1_uid19298_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19296_dupName_222_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x(MUX,19299)@184
    assign rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q or rightShiftStage0Idx1_uid19298_dupName_222_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_55_i_c_compmm_m1817_q;
            1'b1 : rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19298_dupName_222_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x(MUX,19304)@184
    assign rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19303_dupName_222_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19300_dupName_222_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19303_dupName_222_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1820_vt_select_21(BITSELECT,10863)@184
    assign i_unnamed_c_compmm_m1820_vt_select_21_b = rightShiftStage1_uid19305_dupName_222_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1820_vt_join(BITJOIN,10862)@184
    assign i_unnamed_c_compmm_m1820_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1820_vt_select_21_b};

    // i_unnamed_c_compmm_m1821_sel_x(BITSELECT,6062)@184
    assign i_unnamed_c_compmm_m1821_sel_x_b = i_unnamed_c_compmm_m1820_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1822_BitSelect_for_a(BITSELECT,28476)@184
    assign i_unnamed_c_compmm_m1822_BitSelect_for_a_b = i_unnamed_c_compmm_m1821_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1822_join(BITJOIN,28477)@184
    assign i_unnamed_c_compmm_m1822_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1822_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1822_vt_select_0(BITSELECT,10868)@184
    assign i_unnamed_c_compmm_m1822_vt_select_0_b = i_unnamed_c_compmm_m1822_join_q[0:0];

    // redist196_i_unnamed_c_compmm_m1822_vt_select_0_b_1(DELAY,29324)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist196_i_unnamed_c_compmm_m1822_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1822_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1822_vt_join(BITJOIN,10867)@185
    assign i_unnamed_c_compmm_m1822_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist196_i_unnamed_c_compmm_m1822_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_55_c_compmm_m1823(ADD,7237)@185
    assign i_add_i_i_i_i_i_i_55_c_compmm_m1823_a = {1'b0, i_unnamed_c_compmm_m1822_vt_join_q};
    assign i_add_i_i_i_i_i_i_55_c_compmm_m1823_b = {1'b0, redist936_i_conv_i_i_i_i_i_55_c_compmm_m1819_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_55_c_compmm_m1823_o = $unsigned(i_add_i_i_i_i_i_i_55_c_compmm_m1823_a) + $unsigned(i_add_i_i_i_i_i_i_55_c_compmm_m1823_b);
    assign i_add_i_i_i_i_i_i_55_c_compmm_m1823_q = i_add_i_i_i_i_i_i_55_c_compmm_m1823_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_55_c_compmm_m1823_sel_x(BITSELECT,2251)@185
    assign bgTrunc_i_add_i_i_i_i_i_i_55_c_compmm_m1823_sel_x_b = i_add_i_i_i_i_i_i_55_c_compmm_m1823_q[15:0];

    // i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_sel_x(BITSELECT,3911)@185
    assign i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_55_c_compmm_m1823_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_select_15(BITSELECT,8371)@185
    assign i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_select_15_b = i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_join(BITJOIN,8370)@185
    assign i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_select_15_b};

    // leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(MUX,27466)@185
    assign leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_join_q or leftShiftStage0Idx1_uid27465_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_56_c_compmm_m1843_vt_join_q;
            1'b1 : leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27465_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(MUX,27471)@185
    assign leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s or leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27470_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = leftShiftStage0_uid27467_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27470_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x(MUX,27476)@185
    assign leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s or leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27475_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = leftShiftStage1_uid27472_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27475_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28(BITSELECT,10075)@185
    assign i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28_b = leftShiftStage2_uid27477_i_shl_i_i_i_i_i_i_56_c_compmm_m0_shift_x_q[28:13];

    // redist302_i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28_b_1(DELAY,29430)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist302_i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_join(BITJOIN,10074)@186
    assign i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_join_q = {redist302_i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg143(REG,13438)@179 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg143_q <= $unsigned(redist815_sync_together4364_aunroll_x_in_i_valid_111_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_65132_c_compmm_m144(BLACKBOX,8737)@180
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65132_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_65132_c_compmm_m144 (
        .in_intel_reserved_ffwd_114_0(in_intel_reserved_ffwd_114_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg143_q),
        .out_dest_data_out_114_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_65132_c_compmm_m144_out_dest_data_out_114_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_offset(CONSTANT,30929)
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_offset_q = $unsigned(7'b0010101);

    // redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt(ADD,30930)
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_a = {1'b0, redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_q};
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_b = {1'b0, redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_o <= $unsigned(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_a) + $unsigned(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_b);
        end
    end
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_q = redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_o[7:0];

    // redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_inputreg0(DELAY,30925)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_inputreg0_q <= $unsigned(in_c1_eni5_113_tpl);
        end
    end

    // redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr(COUNTER,30928)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_i <= $unsigned(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_q = redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_i[6:0];

    // redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem(DUALMEM,30927)
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_ia = $unsigned(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_inputreg0_q);
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_aa = redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_wraddr_q;
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_ab = redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_aa),
        .data_a(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_ab),
        .q_b(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_q = redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_iq[15:0];

    // redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_outputreg0(DELAY,30926)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_outputreg0_q <= $unsigned(redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_mem_q);
        end
    end

    // redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt(ADD,30936)
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_a = {1'b0, redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_q};
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_b = {1'b0, redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_o <= $unsigned(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_a) + $unsigned(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_b);
        end
    end
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_q = redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_o[7:0];

    // redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_inputreg0(DELAY,30931)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_inputreg0_q <= $unsigned(in_c1_eni5_114_tpl);
        end
    end

    // redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr(COUNTER,30934)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_i <= $unsigned(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_q = redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_i[6:0];

    // redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem(DUALMEM,30933)
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_ia = $unsigned(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_inputreg0_q);
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_aa = redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_wraddr_q;
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_ab = redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_aa),
        .data_a(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_ab),
        .q_b(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_q = redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_iq[15:0];

    // redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_outputreg0(DELAY,30932)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_outputreg0_q <= $unsigned(redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_mem_q);
        end
    end

    // valid_fanout_reg144(REG,13439)@179 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg144_q <= $unsigned(redist815_sync_together4364_aunroll_x_in_i_valid_111_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_65131_c_compmm_m145(BLACKBOX,8733)@180
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65131_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_65131_c_compmm_m145 (
        .in_intel_reserved_ffwd_113_0(in_intel_reserved_ffwd_113_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg144_q),
        .out_dest_data_out_113_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_65131_c_compmm_m145_out_dest_data_out_113_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28927)@180 + 5
    // out q@186
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_65131_c_compmm_m145_out_dest_data_out_113_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_65132_c_compmm_m144_out_dest_data_out_114_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845(ADD,9025)@186
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod562_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_b = $unsigned({{5{i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_56_c_compmm_m1844_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_o[33:0];

    // rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x(MUX,19343)@186
    assign rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q or rightShiftStage0Idx1_uid19342_dupName_225_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q;
            1'b1 : rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19342_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x(MUX,19348)@186
    assign rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19347_dupName_225_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19344_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19347_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x(MUX,19353)@186
    assign rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19352_dupName_225_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19349_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19352_dupName_225_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1846_vt_select_20(BITSELECT,10882)@186
    assign i_unnamed_c_compmm_m1846_vt_select_20_b = rightShiftStage2_uid19354_dupName_225_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1846_vt_join(BITJOIN,10881)@186
    assign i_unnamed_c_compmm_m1846_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1846_vt_select_20_b};

    // i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x(BITSELECT,3783)@186
    assign i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x_b = i_unnamed_c_compmm_m1846_vt_join_q[15:0];

    // redist935_i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x_b_1(DELAY,30063)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist935_i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19363_dupName_226_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19362)@186
    assign rightShiftStage1Idx1Rng8_uid19363_dupName_226_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19365_dupName_226_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19364)@186
    assign rightShiftStage1Idx1_uid19365_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19363_dupName_226_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19358_dupName_226_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19357)@186
    assign rightShiftStage0Idx1Rng4_uid19358_dupName_226_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q[33:4];

    // rightShiftStage0Idx1_uid19360_dupName_226_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19359)@186
    assign rightShiftStage0Idx1_uid19360_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19358_dupName_226_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x(MUX,19361)@186
    assign rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q or rightShiftStage0Idx1_uid19360_dupName_226_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_56_i_c_compmm_m1845_q;
            1'b1 : rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19360_dupName_226_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x(MUX,19366)@186
    assign rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19365_dupName_226_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19362_dupName_226_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19365_dupName_226_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1848_vt_select_21(BITSELECT,10885)@186
    assign i_unnamed_c_compmm_m1848_vt_select_21_b = rightShiftStage1_uid19367_dupName_226_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1848_vt_join(BITJOIN,10884)@186
    assign i_unnamed_c_compmm_m1848_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1848_vt_select_21_b};

    // i_unnamed_c_compmm_m1849_sel_x(BITSELECT,6064)@186
    assign i_unnamed_c_compmm_m1849_sel_x_b = i_unnamed_c_compmm_m1848_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1850_BitSelect_for_a(BITSELECT,28480)@186
    assign i_unnamed_c_compmm_m1850_BitSelect_for_a_b = i_unnamed_c_compmm_m1849_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1850_join(BITJOIN,28481)@186
    assign i_unnamed_c_compmm_m1850_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1850_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1850_vt_select_0(BITSELECT,10890)@186
    assign i_unnamed_c_compmm_m1850_vt_select_0_b = i_unnamed_c_compmm_m1850_join_q[0:0];

    // redist194_i_unnamed_c_compmm_m1850_vt_select_0_b_1(DELAY,29322)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist194_i_unnamed_c_compmm_m1850_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1850_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1850_vt_join(BITJOIN,10889)@187
    assign i_unnamed_c_compmm_m1850_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist194_i_unnamed_c_compmm_m1850_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_56_c_compmm_m1851(ADD,7238)@187
    assign i_add_i_i_i_i_i_i_56_c_compmm_m1851_a = {1'b0, i_unnamed_c_compmm_m1850_vt_join_q};
    assign i_add_i_i_i_i_i_i_56_c_compmm_m1851_b = {1'b0, redist935_i_conv_i_i_i_i_i_56_c_compmm_m1847_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_56_c_compmm_m1851_o = $unsigned(i_add_i_i_i_i_i_i_56_c_compmm_m1851_a) + $unsigned(i_add_i_i_i_i_i_i_56_c_compmm_m1851_b);
    assign i_add_i_i_i_i_i_i_56_c_compmm_m1851_q = i_add_i_i_i_i_i_i_56_c_compmm_m1851_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_56_c_compmm_m1851_sel_x(BITSELECT,2252)@187
    assign bgTrunc_i_add_i_i_i_i_i_i_56_c_compmm_m1851_sel_x_b = i_add_i_i_i_i_i_i_56_c_compmm_m1851_q[15:0];

    // i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_sel_x(BITSELECT,3912)@187
    assign i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_56_c_compmm_m1851_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_select_15(BITSELECT,8375)@187
    assign i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_select_15_b = i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_join(BITJOIN,8374)@187
    assign i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_select_15_b};

    // leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(MUX,27484)@187
    assign leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_join_q or leftShiftStage0Idx1_uid27483_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_57_c_compmm_m1871_vt_join_q;
            1'b1 : leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27483_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(MUX,27489)@187
    assign leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s or leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27488_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = leftShiftStage0_uid27485_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27488_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x(MUX,27494)@187
    assign leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s or leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27493_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = leftShiftStage1_uid27490_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27493_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28(BITSELECT,10078)@187
    assign i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28_b = leftShiftStage2_uid27495_i_shl_i_i_i_i_i_i_57_c_compmm_m0_shift_x_q[28:13];

    // redist301_i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28_b_1(DELAY,29429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist301_i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_join(BITJOIN,10077)@188
    assign i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_join_q = {redist301_i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg141(REG,13436)@181 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg141_q <= $unsigned(redist816_sync_together4364_aunroll_x_in_i_valid_113_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_65134_c_compmm_m142(BLACKBOX,8749)@182
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65134_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_65134_c_compmm_m142 (
        .in_intel_reserved_ffwd_116_0(in_intel_reserved_ffwd_116_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg141_q),
        .out_dest_data_out_116_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_65134_c_compmm_m142_out_dest_data_out_116_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_offset(CONSTANT,30941)
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_offset_q = $unsigned(7'b0010011);

    // redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt(ADD,30942)
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_a = {1'b0, redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_q};
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_b = {1'b0, redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_o <= $unsigned(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_a) + $unsigned(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_b);
        end
    end
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_q = redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_o[7:0];

    // redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_inputreg0(DELAY,30937)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_inputreg0_q <= $unsigned(in_c1_eni5_115_tpl);
        end
    end

    // redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr(COUNTER,30940)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_i <= $unsigned(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_q = redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_i[6:0];

    // redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem(DUALMEM,30939)
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_ia = $unsigned(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_inputreg0_q);
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_aa = redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_wraddr_q;
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_ab = redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_aa),
        .data_a(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_ab),
        .q_b(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_q = redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_iq[15:0];

    // redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_outputreg0(DELAY,30938)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_outputreg0_q <= $unsigned(redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_mem_q);
        end
    end

    // redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt(ADD,30948)
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_a = {1'b0, redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_q};
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_b = {1'b0, redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_o <= $unsigned(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_a) + $unsigned(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_b);
        end
    end
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_q = redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_o[7:0];

    // redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_inputreg0(DELAY,30943)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_inputreg0_q <= $unsigned(in_c1_eni5_116_tpl);
        end
    end

    // redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr(COUNTER,30946)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_i <= $unsigned(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_q = redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_i[6:0];

    // redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem(DUALMEM,30945)
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_ia = $unsigned(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_inputreg0_q);
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_aa = redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_wraddr_q;
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_ab = redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_aa),
        .data_a(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_ab),
        .q_b(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_q = redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_iq[15:0];

    // redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_outputreg0(DELAY,30944)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_outputreg0_q <= $unsigned(redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_mem_q);
        end
    end

    // valid_fanout_reg142(REG,13437)@181 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg142_q <= $unsigned(redist816_sync_together4364_aunroll_x_in_i_valid_113_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_65133_c_compmm_m143(BLACKBOX,8745)@182
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65133_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_65133_c_compmm_m143 (
        .in_intel_reserved_ffwd_115_0(in_intel_reserved_ffwd_115_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg142_q),
        .out_dest_data_out_115_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_65133_c_compmm_m143_out_dest_data_out_115_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28928)@182 + 5
    // out q@188
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_65133_c_compmm_m143_out_dest_data_out_115_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_65134_c_compmm_m142_out_dest_data_out_116_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873(ADD,9026)@188
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod567_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_b = $unsigned({{5{i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_57_c_compmm_m1872_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_o[33:0];

    // rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x(MUX,19405)@188
    assign rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q or rightShiftStage0Idx1_uid19404_dupName_229_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q;
            1'b1 : rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19404_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x(MUX,19410)@188
    assign rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19409_dupName_229_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19406_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19409_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x(MUX,19415)@188
    assign rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19414_dupName_229_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19411_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19414_dupName_229_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1874_vt_select_20(BITSELECT,10904)@188
    assign i_unnamed_c_compmm_m1874_vt_select_20_b = rightShiftStage2_uid19416_dupName_229_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1874_vt_join(BITJOIN,10903)@188
    assign i_unnamed_c_compmm_m1874_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1874_vt_select_20_b};

    // i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x(BITSELECT,3784)@188
    assign i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x_b = i_unnamed_c_compmm_m1874_vt_join_q[15:0];

    // redist934_i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x_b_1(DELAY,30062)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist934_i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19425_dupName_230_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19424)@188
    assign rightShiftStage1Idx1Rng8_uid19425_dupName_230_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19427_dupName_230_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19426)@188
    assign rightShiftStage1Idx1_uid19427_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19425_dupName_230_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19420_dupName_230_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19419)@188
    assign rightShiftStage0Idx1Rng4_uid19420_dupName_230_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q[33:4];

    // rightShiftStage0Idx1_uid19422_dupName_230_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19421)@188
    assign rightShiftStage0Idx1_uid19422_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19420_dupName_230_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x(MUX,19423)@188
    assign rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q or rightShiftStage0Idx1_uid19422_dupName_230_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_57_i_c_compmm_m1873_q;
            1'b1 : rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19422_dupName_230_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x(MUX,19428)@188
    assign rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19427_dupName_230_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19424_dupName_230_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19427_dupName_230_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1876_vt_select_21(BITSELECT,10907)@188
    assign i_unnamed_c_compmm_m1876_vt_select_21_b = rightShiftStage1_uid19429_dupName_230_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1876_vt_join(BITJOIN,10906)@188
    assign i_unnamed_c_compmm_m1876_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1876_vt_select_21_b};

    // i_unnamed_c_compmm_m1877_sel_x(BITSELECT,6066)@188
    assign i_unnamed_c_compmm_m1877_sel_x_b = i_unnamed_c_compmm_m1876_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1878_BitSelect_for_a(BITSELECT,28484)@188
    assign i_unnamed_c_compmm_m1878_BitSelect_for_a_b = i_unnamed_c_compmm_m1877_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1878_join(BITJOIN,28485)@188
    assign i_unnamed_c_compmm_m1878_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1878_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1878_vt_select_0(BITSELECT,10912)@188
    assign i_unnamed_c_compmm_m1878_vt_select_0_b = i_unnamed_c_compmm_m1878_join_q[0:0];

    // redist192_i_unnamed_c_compmm_m1878_vt_select_0_b_1(DELAY,29320)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist192_i_unnamed_c_compmm_m1878_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1878_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1878_vt_join(BITJOIN,10911)@189
    assign i_unnamed_c_compmm_m1878_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist192_i_unnamed_c_compmm_m1878_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_57_c_compmm_m1879(ADD,7239)@189
    assign i_add_i_i_i_i_i_i_57_c_compmm_m1879_a = {1'b0, i_unnamed_c_compmm_m1878_vt_join_q};
    assign i_add_i_i_i_i_i_i_57_c_compmm_m1879_b = {1'b0, redist934_i_conv_i_i_i_i_i_57_c_compmm_m1875_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_57_c_compmm_m1879_o = $unsigned(i_add_i_i_i_i_i_i_57_c_compmm_m1879_a) + $unsigned(i_add_i_i_i_i_i_i_57_c_compmm_m1879_b);
    assign i_add_i_i_i_i_i_i_57_c_compmm_m1879_q = i_add_i_i_i_i_i_i_57_c_compmm_m1879_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_57_c_compmm_m1879_sel_x(BITSELECT,2253)@189
    assign bgTrunc_i_add_i_i_i_i_i_i_57_c_compmm_m1879_sel_x_b = i_add_i_i_i_i_i_i_57_c_compmm_m1879_q[15:0];

    // i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_sel_x(BITSELECT,3913)@189
    assign i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_57_c_compmm_m1879_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_select_15(BITSELECT,8379)@189
    assign i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_select_15_b = i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_join(BITJOIN,8378)@189
    assign i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_select_15_b};

    // leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(MUX,27502)@189
    assign leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_join_q or leftShiftStage0Idx1_uid27501_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_58_c_compmm_m1899_vt_join_q;
            1'b1 : leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27501_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(MUX,27507)@189
    assign leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s or leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27506_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = leftShiftStage0_uid27503_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27506_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x(MUX,27512)@189
    assign leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s or leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27511_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = leftShiftStage1_uid27508_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27511_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28(BITSELECT,10081)@189
    assign i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28_b = leftShiftStage2_uid27513_i_shl_i_i_i_i_i_i_58_c_compmm_m0_shift_x_q[28:13];

    // redist300_i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28_b_1(DELAY,29428)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist300_i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_join(BITJOIN,10080)@190
    assign i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_join_q = {redist300_i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg139(REG,13434)@183 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg139_q <= $unsigned(redist817_sync_together4364_aunroll_x_in_i_valid_115_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_65136_c_compmm_m140(BLACKBOX,8757)@184
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65136_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_65136_c_compmm_m140 (
        .in_intel_reserved_ffwd_118_0(in_intel_reserved_ffwd_118_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg139_q),
        .out_dest_data_out_118_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_65136_c_compmm_m140_out_dest_data_out_118_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_offset(CONSTANT,30953)
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_offset_q = $unsigned(7'b0010001);

    // redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt(ADD,30954)
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_a = {1'b0, redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_q};
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_b = {1'b0, redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_o <= $unsigned(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_a) + $unsigned(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_b);
        end
    end
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_q = redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_o[7:0];

    // redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_inputreg0(DELAY,30949)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_inputreg0_q <= $unsigned(in_c1_eni5_117_tpl);
        end
    end

    // redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr(COUNTER,30952)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_i <= $unsigned(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_q = redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_i[6:0];

    // redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem(DUALMEM,30951)
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_ia = $unsigned(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_inputreg0_q);
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_aa = redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_wraddr_q;
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_ab = redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_aa),
        .data_a(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_ab),
        .q_b(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_q = redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_iq[15:0];

    // redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_outputreg0(DELAY,30950)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_outputreg0_q <= $unsigned(redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_mem_q);
        end
    end

    // redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt(ADD,30960)
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_a = {1'b0, redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_q};
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_b = {1'b0, redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_o <= $unsigned(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_a) + $unsigned(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_b);
        end
    end
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_q = redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_o[7:0];

    // redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_inputreg0(DELAY,30955)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_inputreg0_q <= $unsigned(in_c1_eni5_118_tpl);
        end
    end

    // redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr(COUNTER,30958)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_i <= $unsigned(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_q = redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_i[6:0];

    // redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem(DUALMEM,30957)
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_ia = $unsigned(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_inputreg0_q);
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_aa = redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_wraddr_q;
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_ab = redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_aa),
        .data_a(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_ab),
        .q_b(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_q = redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_iq[15:0];

    // redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_outputreg0(DELAY,30956)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_outputreg0_q <= $unsigned(redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_mem_q);
        end
    end

    // valid_fanout_reg140(REG,13435)@183 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg140_q <= $unsigned(redist817_sync_together4364_aunroll_x_in_i_valid_115_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_65135_c_compmm_m141(BLACKBOX,8753)@184
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65135_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_65135_c_compmm_m141 (
        .in_intel_reserved_ffwd_117_0(in_intel_reserved_ffwd_117_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg140_q),
        .out_dest_data_out_117_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_65135_c_compmm_m141_out_dest_data_out_117_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28929)@184 + 5
    // out q@190
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_65135_c_compmm_m141_out_dest_data_out_117_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_65136_c_compmm_m140_out_dest_data_out_118_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901(ADD,9027)@190
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod572_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_b = $unsigned({{5{i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_58_c_compmm_m1900_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_o[33:0];

    // rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x(MUX,19467)@190
    assign rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q or rightShiftStage0Idx1_uid19466_dupName_233_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q;
            1'b1 : rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19466_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x(MUX,19472)@190
    assign rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19471_dupName_233_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19468_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19471_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x(MUX,19477)@190
    assign rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19476_dupName_233_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19473_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19476_dupName_233_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1902_vt_select_20(BITSELECT,10926)@190
    assign i_unnamed_c_compmm_m1902_vt_select_20_b = rightShiftStage2_uid19478_dupName_233_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1902_vt_join(BITJOIN,10925)@190
    assign i_unnamed_c_compmm_m1902_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1902_vt_select_20_b};

    // i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x(BITSELECT,3785)@190
    assign i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x_b = i_unnamed_c_compmm_m1902_vt_join_q[15:0];

    // redist933_i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x_b_1(DELAY,30061)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist933_i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19487_dupName_234_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19486)@190
    assign rightShiftStage1Idx1Rng8_uid19487_dupName_234_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19489_dupName_234_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19488)@190
    assign rightShiftStage1Idx1_uid19489_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19487_dupName_234_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19482_dupName_234_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19481)@190
    assign rightShiftStage0Idx1Rng4_uid19482_dupName_234_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q[33:4];

    // rightShiftStage0Idx1_uid19484_dupName_234_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19483)@190
    assign rightShiftStage0Idx1_uid19484_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19482_dupName_234_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x(MUX,19485)@190
    assign rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q or rightShiftStage0Idx1_uid19484_dupName_234_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_58_i_c_compmm_m1901_q;
            1'b1 : rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19484_dupName_234_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x(MUX,19490)@190
    assign rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19489_dupName_234_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19486_dupName_234_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19489_dupName_234_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1904_vt_select_21(BITSELECT,10929)@190
    assign i_unnamed_c_compmm_m1904_vt_select_21_b = rightShiftStage1_uid19491_dupName_234_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1904_vt_join(BITJOIN,10928)@190
    assign i_unnamed_c_compmm_m1904_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1904_vt_select_21_b};

    // i_unnamed_c_compmm_m1905_sel_x(BITSELECT,6068)@190
    assign i_unnamed_c_compmm_m1905_sel_x_b = i_unnamed_c_compmm_m1904_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1906_BitSelect_for_a(BITSELECT,28488)@190
    assign i_unnamed_c_compmm_m1906_BitSelect_for_a_b = i_unnamed_c_compmm_m1905_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1906_join(BITJOIN,28489)@190
    assign i_unnamed_c_compmm_m1906_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1906_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1906_vt_select_0(BITSELECT,10934)@190
    assign i_unnamed_c_compmm_m1906_vt_select_0_b = i_unnamed_c_compmm_m1906_join_q[0:0];

    // redist190_i_unnamed_c_compmm_m1906_vt_select_0_b_1(DELAY,29318)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist190_i_unnamed_c_compmm_m1906_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1906_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1906_vt_join(BITJOIN,10933)@191
    assign i_unnamed_c_compmm_m1906_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist190_i_unnamed_c_compmm_m1906_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_58_c_compmm_m1907(ADD,7240)@191
    assign i_add_i_i_i_i_i_i_58_c_compmm_m1907_a = {1'b0, i_unnamed_c_compmm_m1906_vt_join_q};
    assign i_add_i_i_i_i_i_i_58_c_compmm_m1907_b = {1'b0, redist933_i_conv_i_i_i_i_i_58_c_compmm_m1903_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_58_c_compmm_m1907_o = $unsigned(i_add_i_i_i_i_i_i_58_c_compmm_m1907_a) + $unsigned(i_add_i_i_i_i_i_i_58_c_compmm_m1907_b);
    assign i_add_i_i_i_i_i_i_58_c_compmm_m1907_q = i_add_i_i_i_i_i_i_58_c_compmm_m1907_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_58_c_compmm_m1907_sel_x(BITSELECT,2254)@191
    assign bgTrunc_i_add_i_i_i_i_i_i_58_c_compmm_m1907_sel_x_b = i_add_i_i_i_i_i_i_58_c_compmm_m1907_q[15:0];

    // i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_sel_x(BITSELECT,3914)@191
    assign i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_58_c_compmm_m1907_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_select_15(BITSELECT,8383)@191
    assign i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_select_15_b = i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_join(BITJOIN,8382)@191
    assign i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_select_15_b};

    // leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(MUX,27520)@191
    assign leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_join_q or leftShiftStage0Idx1_uid27519_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_59_c_compmm_m1927_vt_join_q;
            1'b1 : leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27519_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(MUX,27525)@191
    assign leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s or leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27524_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = leftShiftStage0_uid27521_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27524_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x(MUX,27530)@191
    assign leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s or leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27529_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = leftShiftStage1_uid27526_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27529_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28(BITSELECT,10084)@191
    assign i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28_b = leftShiftStage2_uid27531_i_shl_i_i_i_i_i_i_59_c_compmm_m0_shift_x_q[28:13];

    // redist299_i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28_b_1(DELAY,29427)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist299_i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_join(BITJOIN,10083)@192
    assign i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_join_q = {redist299_i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg137(REG,13432)@185 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg137_q <= $unsigned(redist818_sync_together4364_aunroll_x_in_i_valid_117_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_65138_c_compmm_m138(BLACKBOX,8765)@186
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65138_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_65138_c_compmm_m138 (
        .in_intel_reserved_ffwd_120_0(in_intel_reserved_ffwd_120_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg137_q),
        .out_dest_data_out_120_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_65138_c_compmm_m138_out_dest_data_out_120_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_offset(CONSTANT,30965)
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_offset_q = $unsigned(7'b0001111);

    // redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt(ADD,30966)
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_a = {1'b0, redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_q};
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_b = {1'b0, redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_o <= $unsigned(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_a) + $unsigned(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_b);
        end
    end
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_q = redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_o[7:0];

    // redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_inputreg0(DELAY,30961)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_inputreg0_q <= $unsigned(in_c1_eni5_119_tpl);
        end
    end

    // redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr(COUNTER,30964)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_i <= $unsigned(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_q = redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_i[6:0];

    // redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem(DUALMEM,30963)
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_ia = $unsigned(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_inputreg0_q);
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_aa = redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_wraddr_q;
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_ab = redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_aa),
        .data_a(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_ab),
        .q_b(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_q = redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_iq[15:0];

    // redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_outputreg0(DELAY,30962)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_outputreg0_q <= $unsigned(redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_mem_q);
        end
    end

    // redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt(ADD,30972)
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_a = {1'b0, redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_q};
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_b = {1'b0, redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_o <= $unsigned(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_a) + $unsigned(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_b);
        end
    end
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_q = redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_o[7:0];

    // redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_inputreg0(DELAY,30967)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_inputreg0_q <= $unsigned(in_c1_eni5_120_tpl);
        end
    end

    // redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr(COUNTER,30970)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_i <= $unsigned(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_q = redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_i[6:0];

    // redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem(DUALMEM,30969)
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_ia = $unsigned(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_inputreg0_q);
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_aa = redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_wraddr_q;
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_ab = redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_aa),
        .data_a(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_ab),
        .q_b(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_q = redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_iq[15:0];

    // redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_outputreg0(DELAY,30968)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_outputreg0_q <= $unsigned(redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_mem_q);
        end
    end

    // valid_fanout_reg138(REG,13433)@185 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg138_q <= $unsigned(redist818_sync_together4364_aunroll_x_in_i_valid_117_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_65137_c_compmm_m139(BLACKBOX,8761)@186
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65137_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_65137_c_compmm_m139 (
        .in_intel_reserved_ffwd_119_0(in_intel_reserved_ffwd_119_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg138_q),
        .out_dest_data_out_119_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_65137_c_compmm_m139_out_dest_data_out_119_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28930)@186 + 5
    // out q@192
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_65137_c_compmm_m139_out_dest_data_out_119_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_65138_c_compmm_m138_out_dest_data_out_120_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929(ADD,9028)@192
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod577_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_b = $unsigned({{5{i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_59_c_compmm_m1928_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_o[33:0];

    // rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x(MUX,19529)@192
    assign rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q or rightShiftStage0Idx1_uid19528_dupName_237_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q;
            1'b1 : rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19528_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x(MUX,19534)@192
    assign rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19533_dupName_237_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19530_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19533_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x(MUX,19539)@192
    assign rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19538_dupName_237_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19535_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19538_dupName_237_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1930_vt_select_20(BITSELECT,10948)@192
    assign i_unnamed_c_compmm_m1930_vt_select_20_b = rightShiftStage2_uid19540_dupName_237_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1930_vt_join(BITJOIN,10947)@192
    assign i_unnamed_c_compmm_m1930_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1930_vt_select_20_b};

    // i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x(BITSELECT,3786)@192
    assign i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x_b = i_unnamed_c_compmm_m1930_vt_join_q[15:0];

    // redist932_i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x_b_1(DELAY,30060)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist932_i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19549_dupName_238_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19548)@192
    assign rightShiftStage1Idx1Rng8_uid19549_dupName_238_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19551_dupName_238_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19550)@192
    assign rightShiftStage1Idx1_uid19551_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19549_dupName_238_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19544_dupName_238_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19543)@192
    assign rightShiftStage0Idx1Rng4_uid19544_dupName_238_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q[33:4];

    // rightShiftStage0Idx1_uid19546_dupName_238_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19545)@192
    assign rightShiftStage0Idx1_uid19546_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19544_dupName_238_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x(MUX,19547)@192
    assign rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q or rightShiftStage0Idx1_uid19546_dupName_238_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_59_i_c_compmm_m1929_q;
            1'b1 : rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19546_dupName_238_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x(MUX,19552)@192
    assign rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19551_dupName_238_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19548_dupName_238_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19551_dupName_238_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1932_vt_select_21(BITSELECT,10951)@192
    assign i_unnamed_c_compmm_m1932_vt_select_21_b = rightShiftStage1_uid19553_dupName_238_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1932_vt_join(BITJOIN,10950)@192
    assign i_unnamed_c_compmm_m1932_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1932_vt_select_21_b};

    // i_unnamed_c_compmm_m1933_sel_x(BITSELECT,6070)@192
    assign i_unnamed_c_compmm_m1933_sel_x_b = i_unnamed_c_compmm_m1932_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1934_BitSelect_for_a(BITSELECT,28492)@192
    assign i_unnamed_c_compmm_m1934_BitSelect_for_a_b = i_unnamed_c_compmm_m1933_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1934_join(BITJOIN,28493)@192
    assign i_unnamed_c_compmm_m1934_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1934_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1934_vt_select_0(BITSELECT,10956)@192
    assign i_unnamed_c_compmm_m1934_vt_select_0_b = i_unnamed_c_compmm_m1934_join_q[0:0];

    // redist188_i_unnamed_c_compmm_m1934_vt_select_0_b_1(DELAY,29316)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist188_i_unnamed_c_compmm_m1934_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1934_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1934_vt_join(BITJOIN,10955)@193
    assign i_unnamed_c_compmm_m1934_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist188_i_unnamed_c_compmm_m1934_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_59_c_compmm_m1935(ADD,7241)@193
    assign i_add_i_i_i_i_i_i_59_c_compmm_m1935_a = {1'b0, i_unnamed_c_compmm_m1934_vt_join_q};
    assign i_add_i_i_i_i_i_i_59_c_compmm_m1935_b = {1'b0, redist932_i_conv_i_i_i_i_i_59_c_compmm_m1931_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_59_c_compmm_m1935_o = $unsigned(i_add_i_i_i_i_i_i_59_c_compmm_m1935_a) + $unsigned(i_add_i_i_i_i_i_i_59_c_compmm_m1935_b);
    assign i_add_i_i_i_i_i_i_59_c_compmm_m1935_q = i_add_i_i_i_i_i_i_59_c_compmm_m1935_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_59_c_compmm_m1935_sel_x(BITSELECT,2255)@193
    assign bgTrunc_i_add_i_i_i_i_i_i_59_c_compmm_m1935_sel_x_b = i_add_i_i_i_i_i_i_59_c_compmm_m1935_q[15:0];

    // i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_sel_x(BITSELECT,3916)@193
    assign i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_59_c_compmm_m1935_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_select_15(BITSELECT,8391)@193
    assign i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_select_15_b = i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_join(BITJOIN,8390)@193
    assign i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_select_15_b};

    // leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(MUX,27556)@193
    assign leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_join_q or leftShiftStage0Idx1_uid27555_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_60_c_compmm_m1955_vt_join_q;
            1'b1 : leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27555_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(MUX,27561)@193
    assign leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s or leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27560_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = leftShiftStage0_uid27557_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27560_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x(MUX,27566)@193
    assign leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s or leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27565_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = leftShiftStage1_uid27562_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27565_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28(BITSELECT,10090)@193
    assign i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28_b = leftShiftStage2_uid27567_i_shl_i_i_i_i_i_i_60_c_compmm_m0_shift_x_q[28:13];

    // redist297_i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28_b_1(DELAY,29425)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist297_i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_join(BITJOIN,10089)@194
    assign i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_join_q = {redist297_i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg135(REG,13430)@187 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg135_q <= $unsigned(redist819_sync_together4364_aunroll_x_in_i_valid_119_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_65140_c_compmm_m136(BLACKBOX,8773)@188
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65140_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_65140_c_compmm_m136 (
        .in_intel_reserved_ffwd_122_0(in_intel_reserved_ffwd_122_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg135_q),
        .out_dest_data_out_122_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_65140_c_compmm_m136_out_dest_data_out_122_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_offset(CONSTANT,30977)
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_offset_q = $unsigned(7'b0001101);

    // redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt(ADD,30978)
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_a = {1'b0, redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_q};
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_b = {1'b0, redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_o <= $unsigned(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_a) + $unsigned(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_b);
        end
    end
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_q = redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_o[7:0];

    // redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_inputreg0(DELAY,30973)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_inputreg0_q <= $unsigned(in_c1_eni5_121_tpl);
        end
    end

    // redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr(COUNTER,30976)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_i <= $unsigned(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_q = redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_i[6:0];

    // redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem(DUALMEM,30975)
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_ia = $unsigned(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_inputreg0_q);
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_aa = redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_wraddr_q;
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_ab = redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_aa),
        .data_a(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_ab),
        .q_b(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_q = redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_iq[15:0];

    // redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_outputreg0(DELAY,30974)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_outputreg0_q <= $unsigned(redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_mem_q);
        end
    end

    // redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt(ADD,30984)
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_a = {1'b0, redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_q};
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_b = {1'b0, redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_o <= $unsigned(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_a) + $unsigned(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_b);
        end
    end
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_q = redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_o[7:0];

    // redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_inputreg0(DELAY,30979)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_inputreg0_q <= $unsigned(in_c1_eni5_122_tpl);
        end
    end

    // redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr(COUNTER,30982)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_i <= $unsigned(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_q = redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_i[6:0];

    // redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem(DUALMEM,30981)
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_ia = $unsigned(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_inputreg0_q);
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_aa = redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_wraddr_q;
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_ab = redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_aa),
        .data_a(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_ab),
        .q_b(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_q = redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_iq[15:0];

    // redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_outputreg0(DELAY,30980)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_outputreg0_q <= $unsigned(redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_mem_q);
        end
    end

    // valid_fanout_reg136(REG,13431)@187 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg136_q <= $unsigned(redist819_sync_together4364_aunroll_x_in_i_valid_119_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_65139_c_compmm_m137(BLACKBOX,8769)@188
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65139_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_65139_c_compmm_m137 (
        .in_intel_reserved_ffwd_121_0(in_intel_reserved_ffwd_121_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg136_q),
        .out_dest_data_out_121_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_65139_c_compmm_m137_out_dest_data_out_121_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28931)@188 + 5
    // out q@194
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_65139_c_compmm_m137_out_dest_data_out_121_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_65140_c_compmm_m136_out_dest_data_out_122_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957(ADD,9030)@194
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod582_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_b = $unsigned({{5{i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_60_c_compmm_m1956_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_o[33:0];

    // rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x(MUX,19591)@194
    assign rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q or rightShiftStage0Idx1_uid19590_dupName_241_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q;
            1'b1 : rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19590_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x(MUX,19596)@194
    assign rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19595_dupName_241_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19592_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19595_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x(MUX,19601)@194
    assign rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19600_dupName_241_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19597_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19600_dupName_241_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1958_vt_select_20(BITSELECT,10970)@194
    assign i_unnamed_c_compmm_m1958_vt_select_20_b = rightShiftStage2_uid19602_dupName_241_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1958_vt_join(BITJOIN,10969)@194
    assign i_unnamed_c_compmm_m1958_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1958_vt_select_20_b};

    // i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x(BITSELECT,3788)@194
    assign i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x_b = i_unnamed_c_compmm_m1958_vt_join_q[15:0];

    // redist930_i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x_b_1(DELAY,30058)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist930_i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19611_dupName_242_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19610)@194
    assign rightShiftStage1Idx1Rng8_uid19611_dupName_242_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19613_dupName_242_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19612)@194
    assign rightShiftStage1Idx1_uid19613_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19611_dupName_242_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19606_dupName_242_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19605)@194
    assign rightShiftStage0Idx1Rng4_uid19606_dupName_242_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q[33:4];

    // rightShiftStage0Idx1_uid19608_dupName_242_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19607)@194
    assign rightShiftStage0Idx1_uid19608_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19606_dupName_242_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x(MUX,19609)@194
    assign rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q or rightShiftStage0Idx1_uid19608_dupName_242_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_60_i_c_compmm_m1957_q;
            1'b1 : rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19608_dupName_242_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x(MUX,19614)@194
    assign rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19613_dupName_242_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19610_dupName_242_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19613_dupName_242_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1960_vt_select_21(BITSELECT,10973)@194
    assign i_unnamed_c_compmm_m1960_vt_select_21_b = rightShiftStage1_uid19615_dupName_242_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1960_vt_join(BITJOIN,10972)@194
    assign i_unnamed_c_compmm_m1960_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1960_vt_select_21_b};

    // i_unnamed_c_compmm_m1961_sel_x(BITSELECT,6072)@194
    assign i_unnamed_c_compmm_m1961_sel_x_b = i_unnamed_c_compmm_m1960_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1962_BitSelect_for_a(BITSELECT,28496)@194
    assign i_unnamed_c_compmm_m1962_BitSelect_for_a_b = i_unnamed_c_compmm_m1961_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1962_join(BITJOIN,28497)@194
    assign i_unnamed_c_compmm_m1962_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1962_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1962_vt_select_0(BITSELECT,10978)@194
    assign i_unnamed_c_compmm_m1962_vt_select_0_b = i_unnamed_c_compmm_m1962_join_q[0:0];

    // redist186_i_unnamed_c_compmm_m1962_vt_select_0_b_1(DELAY,29314)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist186_i_unnamed_c_compmm_m1962_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1962_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1962_vt_join(BITJOIN,10977)@195
    assign i_unnamed_c_compmm_m1962_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist186_i_unnamed_c_compmm_m1962_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_60_c_compmm_m1963(ADD,7243)@195
    assign i_add_i_i_i_i_i_i_60_c_compmm_m1963_a = {1'b0, i_unnamed_c_compmm_m1962_vt_join_q};
    assign i_add_i_i_i_i_i_i_60_c_compmm_m1963_b = {1'b0, redist930_i_conv_i_i_i_i_i_60_c_compmm_m1959_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_60_c_compmm_m1963_o = $unsigned(i_add_i_i_i_i_i_i_60_c_compmm_m1963_a) + $unsigned(i_add_i_i_i_i_i_i_60_c_compmm_m1963_b);
    assign i_add_i_i_i_i_i_i_60_c_compmm_m1963_q = i_add_i_i_i_i_i_i_60_c_compmm_m1963_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_60_c_compmm_m1963_sel_x(BITSELECT,2257)@195
    assign bgTrunc_i_add_i_i_i_i_i_i_60_c_compmm_m1963_sel_x_b = i_add_i_i_i_i_i_i_60_c_compmm_m1963_q[15:0];

    // i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_sel_x(BITSELECT,3917)@195
    assign i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_60_c_compmm_m1963_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_select_15(BITSELECT,8395)@195
    assign i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_select_15_b = i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_join(BITJOIN,8394)@195
    assign i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_select_15_b};

    // leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(MUX,27574)@195
    assign leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_join_q or leftShiftStage0Idx1_uid27573_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_61_c_compmm_m1983_vt_join_q;
            1'b1 : leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27573_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(MUX,27579)@195
    assign leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s or leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27578_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = leftShiftStage0_uid27575_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27578_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x(MUX,27584)@195
    assign leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s or leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27583_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = leftShiftStage1_uid27580_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27583_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28(BITSELECT,10093)@195
    assign i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28_b = leftShiftStage2_uid27585_i_shl_i_i_i_i_i_i_61_c_compmm_m0_shift_x_q[28:13];

    // redist296_i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28_b_1(DELAY,29424)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist296_i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_join(BITJOIN,10092)@196
    assign i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_join_q = {redist296_i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg133(REG,13428)@189 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg133_q <= $unsigned(redist820_sync_together4364_aunroll_x_in_i_valid_121_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_65142_c_compmm_m134(BLACKBOX,8781)@190
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65142_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_65142_c_compmm_m134 (
        .in_intel_reserved_ffwd_124_0(in_intel_reserved_ffwd_124_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg133_q),
        .out_dest_data_out_124_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_65142_c_compmm_m134_out_dest_data_out_124_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_offset(CONSTANT,30989)
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_offset_q = $unsigned(7'b0001011);

    // redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt(ADD,30990)
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_a = {1'b0, redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_q};
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_b = {1'b0, redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_o <= $unsigned(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_a) + $unsigned(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_b);
        end
    end
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_q = redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_o[7:0];

    // redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_inputreg0(DELAY,30985)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_inputreg0_q <= $unsigned(in_c1_eni5_123_tpl);
        end
    end

    // redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr(COUNTER,30988)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_i <= $unsigned(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_q = redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_i[6:0];

    // redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem(DUALMEM,30987)
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_ia = $unsigned(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_inputreg0_q);
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_aa = redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_wraddr_q;
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_ab = redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_aa),
        .data_a(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_ab),
        .q_b(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_q = redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_iq[15:0];

    // redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_outputreg0(DELAY,30986)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_outputreg0_q <= $unsigned(redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_mem_q);
        end
    end

    // redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt(ADD,30996)
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_a = {1'b0, redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_q};
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_b = {1'b0, redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_o <= $unsigned(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_a) + $unsigned(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_b);
        end
    end
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_q = redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_o[7:0];

    // redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_inputreg0(DELAY,30991)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_inputreg0_q <= $unsigned(in_c1_eni5_124_tpl);
        end
    end

    // redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr(COUNTER,30994)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_i <= $unsigned(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_q = redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_i[6:0];

    // redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem(DUALMEM,30993)
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_ia = $unsigned(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_inputreg0_q);
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_aa = redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_wraddr_q;
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_ab = redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_aa),
        .data_a(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_ab),
        .q_b(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_q = redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_iq[15:0];

    // redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_outputreg0(DELAY,30992)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_outputreg0_q <= $unsigned(redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_mem_q);
        end
    end

    // valid_fanout_reg134(REG,13429)@189 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg134_q <= $unsigned(redist820_sync_together4364_aunroll_x_in_i_valid_121_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_65141_c_compmm_m135(BLACKBOX,8777)@190
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65141_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_65141_c_compmm_m135 (
        .in_intel_reserved_ffwd_123_0(in_intel_reserved_ffwd_123_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg134_q),
        .out_dest_data_out_123_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_65141_c_compmm_m135_out_dest_data_out_123_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28932)@190 + 5
    // out q@196
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_65141_c_compmm_m135_out_dest_data_out_123_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_65142_c_compmm_m134_out_dest_data_out_124_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985(ADD,9031)@196
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod587_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_b = $unsigned({{5{i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_61_c_compmm_m1984_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_o[33:0];

    // rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x(MUX,19653)@196
    assign rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q or rightShiftStage0Idx1_uid19652_dupName_245_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q;
            1'b1 : rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19652_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x(MUX,19658)@196
    assign rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19657_dupName_245_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19654_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19657_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x(MUX,19663)@196
    assign rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19662_dupName_245_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19659_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19662_dupName_245_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1986_vt_select_20(BITSELECT,10992)@196
    assign i_unnamed_c_compmm_m1986_vt_select_20_b = rightShiftStage2_uid19664_dupName_245_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1986_vt_join(BITJOIN,10991)@196
    assign i_unnamed_c_compmm_m1986_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1986_vt_select_20_b};

    // i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x(BITSELECT,3789)@196
    assign i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x_b = i_unnamed_c_compmm_m1986_vt_join_q[15:0];

    // redist929_i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x_b_1(DELAY,30057)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist929_i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19673_dupName_246_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19672)@196
    assign rightShiftStage1Idx1Rng8_uid19673_dupName_246_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19675_dupName_246_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19674)@196
    assign rightShiftStage1Idx1_uid19675_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19673_dupName_246_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19668_dupName_246_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19667)@196
    assign rightShiftStage0Idx1Rng4_uid19668_dupName_246_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q[33:4];

    // rightShiftStage0Idx1_uid19670_dupName_246_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19669)@196
    assign rightShiftStage0Idx1_uid19670_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19668_dupName_246_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x(MUX,19671)@196
    assign rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q or rightShiftStage0Idx1_uid19670_dupName_246_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_61_i_c_compmm_m1985_q;
            1'b1 : rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19670_dupName_246_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x(MUX,19676)@196
    assign rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19675_dupName_246_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19672_dupName_246_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19675_dupName_246_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1988_vt_select_21(BITSELECT,10995)@196
    assign i_unnamed_c_compmm_m1988_vt_select_21_b = rightShiftStage1_uid19677_dupName_246_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1988_vt_join(BITJOIN,10994)@196
    assign i_unnamed_c_compmm_m1988_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1988_vt_select_21_b};

    // i_unnamed_c_compmm_m1989_sel_x(BITSELECT,6074)@196
    assign i_unnamed_c_compmm_m1989_sel_x_b = i_unnamed_c_compmm_m1988_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1990_BitSelect_for_a(BITSELECT,28500)@196
    assign i_unnamed_c_compmm_m1990_BitSelect_for_a_b = i_unnamed_c_compmm_m1989_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1990_join(BITJOIN,28501)@196
    assign i_unnamed_c_compmm_m1990_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1990_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1990_vt_select_0(BITSELECT,11000)@196
    assign i_unnamed_c_compmm_m1990_vt_select_0_b = i_unnamed_c_compmm_m1990_join_q[0:0];

    // redist184_i_unnamed_c_compmm_m1990_vt_select_0_b_1(DELAY,29312)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist184_i_unnamed_c_compmm_m1990_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1990_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1990_vt_join(BITJOIN,10999)@197
    assign i_unnamed_c_compmm_m1990_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist184_i_unnamed_c_compmm_m1990_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_61_c_compmm_m1991(ADD,7244)@197
    assign i_add_i_i_i_i_i_i_61_c_compmm_m1991_a = {1'b0, i_unnamed_c_compmm_m1990_vt_join_q};
    assign i_add_i_i_i_i_i_i_61_c_compmm_m1991_b = {1'b0, redist929_i_conv_i_i_i_i_i_61_c_compmm_m1987_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_61_c_compmm_m1991_o = $unsigned(i_add_i_i_i_i_i_i_61_c_compmm_m1991_a) + $unsigned(i_add_i_i_i_i_i_i_61_c_compmm_m1991_b);
    assign i_add_i_i_i_i_i_i_61_c_compmm_m1991_q = i_add_i_i_i_i_i_i_61_c_compmm_m1991_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_61_c_compmm_m1991_sel_x(BITSELECT,2258)@197
    assign bgTrunc_i_add_i_i_i_i_i_i_61_c_compmm_m1991_sel_x_b = i_add_i_i_i_i_i_i_61_c_compmm_m1991_q[15:0];

    // i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_sel_x(BITSELECT,3918)@197
    assign i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_61_c_compmm_m1991_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_select_15(BITSELECT,8399)@197
    assign i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_select_15_b = i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_join(BITJOIN,8398)@197
    assign i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_select_15_b};

    // leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(MUX,27592)@197
    assign leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_join_q or leftShiftStage0Idx1_uid27591_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_62_c_compmm_m2011_vt_join_q;
            1'b1 : leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27591_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(MUX,27597)@197
    assign leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s or leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27596_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = leftShiftStage0_uid27593_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27596_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x(MUX,27602)@197
    assign leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s or leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27601_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = leftShiftStage1_uid27598_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27601_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28(BITSELECT,10096)@197
    assign i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28_b = leftShiftStage2_uid27603_i_shl_i_i_i_i_i_i_62_c_compmm_m0_shift_x_q[28:13];

    // redist295_i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28_b_1(DELAY,29423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist295_i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_join(BITJOIN,10095)@198
    assign i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_join_q = {redist295_i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg131(REG,13426)@191 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg131_q <= $unsigned(redist821_sync_together4364_aunroll_x_in_i_valid_123_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_65144_c_compmm_m132(BLACKBOX,8793)@192
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65144_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_65144_c_compmm_m132 (
        .in_intel_reserved_ffwd_126_0(in_intel_reserved_ffwd_126_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg131_q),
        .out_dest_data_out_126_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_65144_c_compmm_m132_out_dest_data_out_126_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_offset(CONSTANT,31001)
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_offset_q = $unsigned(7'b0001001);

    // redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt(ADD,31002)
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_a = {1'b0, redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_q};
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_b = {1'b0, redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_o <= $unsigned(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_a) + $unsigned(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_b);
        end
    end
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_q = redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_o[7:0];

    // redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_inputreg0(DELAY,30997)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_inputreg0_q <= $unsigned(in_c1_eni5_125_tpl);
        end
    end

    // redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr(COUNTER,31000)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_i <= $unsigned(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_q = redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_i[6:0];

    // redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem(DUALMEM,30999)
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_ia = $unsigned(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_inputreg0_q);
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_aa = redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_wraddr_q;
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_ab = redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_aa),
        .data_a(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_ab),
        .q_b(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_q = redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_iq[15:0];

    // redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_outputreg0(DELAY,30998)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_outputreg0_q <= $unsigned(redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_mem_q);
        end
    end

    // redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt(ADD,31008)
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_a = {1'b0, redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_q};
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_b = {1'b0, redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_o <= $unsigned(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_a) + $unsigned(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_b);
        end
    end
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_q = redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_o[7:0];

    // redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_inputreg0(DELAY,31003)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_inputreg0_q <= $unsigned(in_c1_eni5_126_tpl);
        end
    end

    // redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr(COUNTER,31006)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_i <= $unsigned(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_q = redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_i[6:0];

    // redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem(DUALMEM,31005)
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_ia = $unsigned(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_inputreg0_q);
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_aa = redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_wraddr_q;
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_ab = redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_aa),
        .data_a(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_ab),
        .q_b(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_q = redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_iq[15:0];

    // redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_outputreg0(DELAY,31004)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_outputreg0_q <= $unsigned(redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_mem_q);
        end
    end

    // valid_fanout_reg132(REG,13427)@191 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg132_q <= $unsigned(redist821_sync_together4364_aunroll_x_in_i_valid_123_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_65143_c_compmm_m133(BLACKBOX,8789)@192
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65143_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_65143_c_compmm_m133 (
        .in_intel_reserved_ffwd_125_0(in_intel_reserved_ffwd_125_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg132_q),
        .out_dest_data_out_125_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_65143_c_compmm_m133_out_dest_data_out_125_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28933)@192 + 5
    // out q@198
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_65143_c_compmm_m133_out_dest_data_out_125_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_65144_c_compmm_m132_out_dest_data_out_126_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013(ADD,9032)@198
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod592_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_b = $unsigned({{5{i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_62_c_compmm_m2012_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_o[33:0];

    // rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x(MUX,19715)@198
    assign rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q or rightShiftStage0Idx1_uid19714_dupName_249_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q;
            1'b1 : rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19714_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x(MUX,19720)@198
    assign rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19719_dupName_249_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19716_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19719_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x(MUX,19725)@198
    assign rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19724_dupName_249_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19721_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19724_dupName_249_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2014_vt_select_20(BITSELECT,11014)@198
    assign i_unnamed_c_compmm_m2014_vt_select_20_b = rightShiftStage2_uid19726_dupName_249_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2014_vt_join(BITJOIN,11013)@198
    assign i_unnamed_c_compmm_m2014_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2014_vt_select_20_b};

    // i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x(BITSELECT,3790)@198
    assign i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x_b = i_unnamed_c_compmm_m2014_vt_join_q[15:0];

    // redist928_i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x_b_1(DELAY,30056)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist928_i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19735_dupName_250_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19734)@198
    assign rightShiftStage1Idx1Rng8_uid19735_dupName_250_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19737_dupName_250_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19736)@198
    assign rightShiftStage1Idx1_uid19737_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19735_dupName_250_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19730_dupName_250_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19729)@198
    assign rightShiftStage0Idx1Rng4_uid19730_dupName_250_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q[33:4];

    // rightShiftStage0Idx1_uid19732_dupName_250_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19731)@198
    assign rightShiftStage0Idx1_uid19732_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19730_dupName_250_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x(MUX,19733)@198
    assign rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q or rightShiftStage0Idx1_uid19732_dupName_250_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_62_i_c_compmm_m2013_q;
            1'b1 : rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19732_dupName_250_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x(MUX,19738)@198
    assign rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19737_dupName_250_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19734_dupName_250_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19737_dupName_250_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2016_vt_select_21(BITSELECT,11017)@198
    assign i_unnamed_c_compmm_m2016_vt_select_21_b = rightShiftStage1_uid19739_dupName_250_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2016_vt_join(BITJOIN,11016)@198
    assign i_unnamed_c_compmm_m2016_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2016_vt_select_21_b};

    // i_unnamed_c_compmm_m2017_sel_x(BITSELECT,6076)@198
    assign i_unnamed_c_compmm_m2017_sel_x_b = i_unnamed_c_compmm_m2016_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2018_BitSelect_for_a(BITSELECT,28504)@198
    assign i_unnamed_c_compmm_m2018_BitSelect_for_a_b = i_unnamed_c_compmm_m2017_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2018_join(BITJOIN,28505)@198
    assign i_unnamed_c_compmm_m2018_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2018_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2018_vt_select_0(BITSELECT,11022)@198
    assign i_unnamed_c_compmm_m2018_vt_select_0_b = i_unnamed_c_compmm_m2018_join_q[0:0];

    // redist182_i_unnamed_c_compmm_m2018_vt_select_0_b_1(DELAY,29310)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist182_i_unnamed_c_compmm_m2018_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2018_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2018_vt_join(BITJOIN,11021)@199
    assign i_unnamed_c_compmm_m2018_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist182_i_unnamed_c_compmm_m2018_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_62_c_compmm_m2019(ADD,7245)@199
    assign i_add_i_i_i_i_i_i_62_c_compmm_m2019_a = {1'b0, i_unnamed_c_compmm_m2018_vt_join_q};
    assign i_add_i_i_i_i_i_i_62_c_compmm_m2019_b = {1'b0, redist928_i_conv_i_i_i_i_i_62_c_compmm_m2015_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_62_c_compmm_m2019_o = $unsigned(i_add_i_i_i_i_i_i_62_c_compmm_m2019_a) + $unsigned(i_add_i_i_i_i_i_i_62_c_compmm_m2019_b);
    assign i_add_i_i_i_i_i_i_62_c_compmm_m2019_q = i_add_i_i_i_i_i_i_62_c_compmm_m2019_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_62_c_compmm_m2019_sel_x(BITSELECT,2259)@199
    assign bgTrunc_i_add_i_i_i_i_i_i_62_c_compmm_m2019_sel_x_b = i_add_i_i_i_i_i_i_62_c_compmm_m2019_q[15:0];

    // i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_sel_x(BITSELECT,3919)@199
    assign i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_62_c_compmm_m2019_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_select_15(BITSELECT,8403)@199
    assign i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_select_15_b = i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_join(BITJOIN,8402)@199
    assign i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_select_15_b};

    // leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(MUX,27610)@199
    assign leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_join_q or leftShiftStage0Idx1_uid27609_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_63_c_compmm_m2039_vt_join_q;
            1'b1 : leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27609_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(MUX,27615)@199
    assign leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s or leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27614_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = leftShiftStage0_uid27611_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27614_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x(MUX,27620)@199
    assign leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s or leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27619_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = leftShiftStage1_uid27616_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27619_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28(BITSELECT,10099)@199
    assign i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28_b = leftShiftStage2_uid27621_i_shl_i_i_i_i_i_i_63_c_compmm_m0_shift_x_q[28:13];

    // redist294_i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28_b_1(DELAY,29422)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist294_i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_join(BITJOIN,10098)@200
    assign i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_join_q = {redist294_i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg129(REG,13424)@193 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg129_q <= $unsigned(redist822_sync_together4364_aunroll_x_in_i_valid_125_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_65146_c_compmm_m130(BLACKBOX,8801)@194
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65146_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_65146_c_compmm_m130 (
        .in_intel_reserved_ffwd_128_0(in_intel_reserved_ffwd_128_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg129_q),
        .out_dest_data_out_128_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_65146_c_compmm_m130_out_dest_data_out_128_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_offset(CONSTANT,31013)
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_offset_q = $unsigned(7'b0000111);

    // redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt(ADD,31014)
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_a = {1'b0, redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_q};
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_b = {1'b0, redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_o <= $unsigned(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_a) + $unsigned(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_b);
        end
    end
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_q = redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_o[7:0];

    // redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_inputreg0(DELAY,31009)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_inputreg0_q <= $unsigned(in_c1_eni5_127_tpl);
        end
    end

    // redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr(COUNTER,31012)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_i <= $unsigned(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_q = redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_i[6:0];

    // redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem(DUALMEM,31011)
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_ia = $unsigned(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_inputreg0_q);
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_aa = redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_wraddr_q;
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_ab = redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_aa),
        .data_a(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_ab),
        .q_b(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_q = redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_iq[15:0];

    // redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_outputreg0(DELAY,31010)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_outputreg0_q <= $unsigned(redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_mem_q);
        end
    end

    // redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt(ADD,31020)
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_a = {1'b0, redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_q};
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_b = {1'b0, redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_o <= $unsigned(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_a) + $unsigned(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_b);
        end
    end
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_q = redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_o[7:0];

    // redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_inputreg0(DELAY,31015)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_inputreg0_q <= $unsigned(in_c1_eni5_128_tpl);
        end
    end

    // redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr(COUNTER,31018)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_i <= $unsigned(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_q = redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_i[6:0];

    // redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem(DUALMEM,31017)
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_ia = $unsigned(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_inputreg0_q);
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_aa = redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_wraddr_q;
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_ab = redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_aa),
        .data_a(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_ab),
        .q_b(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_q = redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_iq[15:0];

    // redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_outputreg0(DELAY,31016)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_outputreg0_q <= $unsigned(redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_mem_q);
        end
    end

    // valid_fanout_reg130(REG,13425)@193 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg130_q <= $unsigned(redist822_sync_together4364_aunroll_x_in_i_valid_125_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_65145_c_compmm_m131(BLACKBOX,8797)@194
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_65145_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_65145_c_compmm_m131 (
        .in_intel_reserved_ffwd_127_0(in_intel_reserved_ffwd_127_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg130_q),
        .out_dest_data_out_127_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_65145_c_compmm_m131_out_dest_data_out_127_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28934)@194 + 5
    // out q@200
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_65145_c_compmm_m131_out_dest_data_out_127_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_65146_c_compmm_m130_out_dest_data_out_128_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041(ADD,9033)@200
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod597_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_b = $unsigned({{5{i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_63_c_compmm_m2040_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_o[33:0];

    // rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x(MUX,19777)@200
    assign rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q or rightShiftStage0Idx1_uid19776_dupName_253_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q;
            1'b1 : rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19776_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x(MUX,19782)@200
    assign rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19781_dupName_253_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19778_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19781_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x(MUX,19787)@200
    assign rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19786_dupName_253_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19783_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19786_dupName_253_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2042_vt_select_20(BITSELECT,11036)@200
    assign i_unnamed_c_compmm_m2042_vt_select_20_b = rightShiftStage2_uid19788_dupName_253_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2042_vt_join(BITJOIN,11035)@200
    assign i_unnamed_c_compmm_m2042_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2042_vt_select_20_b};

    // i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x(BITSELECT,3791)@200
    assign i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x_b = i_unnamed_c_compmm_m2042_vt_join_q[15:0];

    // redist927_i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x_b_1(DELAY,30055)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist927_i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19797_dupName_254_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19796)@200
    assign rightShiftStage1Idx1Rng8_uid19797_dupName_254_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19799_dupName_254_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19798)@200
    assign rightShiftStage1Idx1_uid19799_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19797_dupName_254_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19792_dupName_254_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19791)@200
    assign rightShiftStage0Idx1Rng4_uid19792_dupName_254_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q[33:4];

    // rightShiftStage0Idx1_uid19794_dupName_254_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19793)@200
    assign rightShiftStage0Idx1_uid19794_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19792_dupName_254_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x(MUX,19795)@200
    assign rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q or rightShiftStage0Idx1_uid19794_dupName_254_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_63_i_c_compmm_m2041_q;
            1'b1 : rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19794_dupName_254_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x(MUX,19800)@200
    assign rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19799_dupName_254_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19796_dupName_254_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19799_dupName_254_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2044_vt_select_21(BITSELECT,11039)@200
    assign i_unnamed_c_compmm_m2044_vt_select_21_b = rightShiftStage1_uid19801_dupName_254_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2044_vt_join(BITJOIN,11038)@200
    assign i_unnamed_c_compmm_m2044_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2044_vt_select_21_b};

    // i_unnamed_c_compmm_m2045_sel_x(BITSELECT,6078)@200
    assign i_unnamed_c_compmm_m2045_sel_x_b = i_unnamed_c_compmm_m2044_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2046_BitSelect_for_a(BITSELECT,28508)@200
    assign i_unnamed_c_compmm_m2046_BitSelect_for_a_b = i_unnamed_c_compmm_m2045_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2046_join(BITJOIN,28509)@200
    assign i_unnamed_c_compmm_m2046_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2046_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2046_vt_select_0(BITSELECT,11044)@200
    assign i_unnamed_c_compmm_m2046_vt_select_0_b = i_unnamed_c_compmm_m2046_join_q[0:0];

    // redist180_i_unnamed_c_compmm_m2046_vt_select_0_b_1(DELAY,29308)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist180_i_unnamed_c_compmm_m2046_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2046_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2046_vt_join(BITJOIN,11043)@201
    assign i_unnamed_c_compmm_m2046_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist180_i_unnamed_c_compmm_m2046_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_63_c_compmm_m2047(ADD,7246)@201
    assign i_add_i_i_i_i_i_i_63_c_compmm_m2047_a = {1'b0, i_unnamed_c_compmm_m2046_vt_join_q};
    assign i_add_i_i_i_i_i_i_63_c_compmm_m2047_b = {1'b0, redist927_i_conv_i_i_i_i_i_63_c_compmm_m2043_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_63_c_compmm_m2047_o = $unsigned(i_add_i_i_i_i_i_i_63_c_compmm_m2047_a) + $unsigned(i_add_i_i_i_i_i_i_63_c_compmm_m2047_b);
    assign i_add_i_i_i_i_i_i_63_c_compmm_m2047_q = i_add_i_i_i_i_i_i_63_c_compmm_m2047_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_63_c_compmm_m2047_sel_x(BITSELECT,2260)@201
    assign bgTrunc_i_add_i_i_i_i_i_i_63_c_compmm_m2047_sel_x_b = i_add_i_i_i_i_i_i_63_c_compmm_m2047_q[15:0];

    // i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_sel_x(BITSELECT,3920)@201
    assign i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_63_c_compmm_m2047_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_select_15(BITSELECT,8407)@201
    assign i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_select_15_b = i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_join(BITJOIN,8406)@201
    assign i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_select_15_b};

    // leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(MUX,27628)@201
    assign leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_join_q or leftShiftStage0Idx1_uid27627_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_64_c_compmm_m2068_vt_join_q;
            1'b1 : leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27627_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(MUX,27633)@201
    assign leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s or leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27632_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = leftShiftStage0_uid27629_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27632_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x(MUX,27638)@201
    assign leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s or leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27637_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = leftShiftStage1_uid27634_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27637_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28(BITSELECT,10102)@201
    assign i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28_b = leftShiftStage2_uid27639_i_shl_i_i_i_i_i_i_64_c_compmm_m0_shift_x_q[28:13];

    // redist293_i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28_b_1(DELAY,29421)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist293_i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_join(BITJOIN,10101)@202
    assign i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_join_q = {redist293_i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg127(REG,13422)@195 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg127_q <= $unsigned(redist823_sync_together4364_aunroll_x_in_i_valid_127_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_66148_c_compmm_m128(BLACKBOX,8610)@196
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66148_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_66148_c_compmm_m128 (
        .in_intel_reserved_ffwd_130_0(in_intel_reserved_ffwd_130_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg127_q),
        .out_dest_data_out_130_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_66148_c_compmm_m128_out_dest_data_out_130_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_offset(CONSTANT,31025)
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_offset_q = $unsigned(7'b0000101);

    // redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt(ADD,31026)
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_a = {1'b0, redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_q};
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_b = {1'b0, redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_o <= $unsigned(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_a) + $unsigned(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_b);
        end
    end
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_q = redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_o[7:0];

    // redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_inputreg0(DELAY,31021)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_inputreg0_q <= $unsigned(in_c1_eni5_129_tpl);
        end
    end

    // redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr(COUNTER,31024)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_i <= $unsigned(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_q = redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_i[6:0];

    // redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem(DUALMEM,31023)
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_ia = $unsigned(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_inputreg0_q);
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_aa = redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_wraddr_q;
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_ab = redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_aa),
        .data_a(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_ab),
        .q_b(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_q = redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_iq[15:0];

    // redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_outputreg0(DELAY,31022)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_outputreg0_q <= $unsigned(redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_mem_q);
        end
    end

    // redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt(ADD,31032)
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_a = {1'b0, redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_q};
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_b = {1'b0, redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_o <= $unsigned(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_a) + $unsigned(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_b);
        end
    end
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_q = redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_o[7:0];

    // redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_inputreg0(DELAY,31027)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_inputreg0_q <= $unsigned(in_c1_eni5_130_tpl);
        end
    end

    // redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr(COUNTER,31030)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_i <= $unsigned(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_q = redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_i[6:0];

    // redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem(DUALMEM,31029)
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_ia = $unsigned(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_inputreg0_q);
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_aa = redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_wraddr_q;
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_ab = redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_aa),
        .data_a(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_ab),
        .q_b(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_q = redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_iq[15:0];

    // redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_outputreg0(DELAY,31028)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_outputreg0_q <= $unsigned(redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_mem_q);
        end
    end

    // valid_fanout_reg128(REG,13423)@195 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg128_q <= $unsigned(redist823_sync_together4364_aunroll_x_in_i_valid_127_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_66147_c_compmm_m129(BLACKBOX,8566)@196
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66147_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_66147_c_compmm_m129 (
        .in_intel_reserved_ffwd_129_0(in_intel_reserved_ffwd_129_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg128_q),
        .out_dest_data_out_129_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_66147_c_compmm_m129_out_dest_data_out_129_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28935)@196 + 5
    // out q@202
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_66147_c_compmm_m129_out_dest_data_out_129_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_66148_c_compmm_m128_out_dest_data_out_130_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070(ADD,9034)@202
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod602_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_b = $unsigned({{5{i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_64_c_compmm_m2069_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_o[33:0];

    // rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x(MUX,19839)@202
    assign rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q or rightShiftStage0Idx1_uid19838_dupName_257_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q;
            1'b1 : rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19838_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x(MUX,19844)@202
    assign rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19843_dupName_257_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19840_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19843_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x(MUX,19849)@202
    assign rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19848_dupName_257_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19845_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19848_dupName_257_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2071_vt_select_20(BITSELECT,11058)@202
    assign i_unnamed_c_compmm_m2071_vt_select_20_b = rightShiftStage2_uid19850_dupName_257_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2071_vt_join(BITJOIN,11057)@202
    assign i_unnamed_c_compmm_m2071_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2071_vt_select_20_b};

    // i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x(BITSELECT,3792)@202
    assign i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x_b = i_unnamed_c_compmm_m2071_vt_join_q[15:0];

    // redist926_i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x_b_1(DELAY,30054)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist926_i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19859_dupName_258_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19858)@202
    assign rightShiftStage1Idx1Rng8_uid19859_dupName_258_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19861_dupName_258_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19860)@202
    assign rightShiftStage1Idx1_uid19861_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19859_dupName_258_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19854_dupName_258_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19853)@202
    assign rightShiftStage0Idx1Rng4_uid19854_dupName_258_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q[33:4];

    // rightShiftStage0Idx1_uid19856_dupName_258_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19855)@202
    assign rightShiftStage0Idx1_uid19856_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19854_dupName_258_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x(MUX,19857)@202
    assign rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q or rightShiftStage0Idx1_uid19856_dupName_258_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_64_i_c_compmm_m2070_q;
            1'b1 : rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19856_dupName_258_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x(MUX,19862)@202
    assign rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19861_dupName_258_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19858_dupName_258_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19861_dupName_258_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2073_vt_select_21(BITSELECT,11061)@202
    assign i_unnamed_c_compmm_m2073_vt_select_21_b = rightShiftStage1_uid19863_dupName_258_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2073_vt_join(BITJOIN,11060)@202
    assign i_unnamed_c_compmm_m2073_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2073_vt_select_21_b};

    // i_unnamed_c_compmm_m2074_sel_x(BITSELECT,6080)@202
    assign i_unnamed_c_compmm_m2074_sel_x_b = i_unnamed_c_compmm_m2073_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2075_BitSelect_for_a(BITSELECT,28512)@202
    assign i_unnamed_c_compmm_m2075_BitSelect_for_a_b = i_unnamed_c_compmm_m2074_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2075_join(BITJOIN,28513)@202
    assign i_unnamed_c_compmm_m2075_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2075_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2075_vt_select_0(BITSELECT,11066)@202
    assign i_unnamed_c_compmm_m2075_vt_select_0_b = i_unnamed_c_compmm_m2075_join_q[0:0];

    // redist178_i_unnamed_c_compmm_m2075_vt_select_0_b_1(DELAY,29306)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist178_i_unnamed_c_compmm_m2075_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2075_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2075_vt_join(BITJOIN,11065)@203
    assign i_unnamed_c_compmm_m2075_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist178_i_unnamed_c_compmm_m2075_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_64_c_compmm_m2076(ADD,7247)@203
    assign i_add_i_i_i_i_i_i_64_c_compmm_m2076_a = {1'b0, i_unnamed_c_compmm_m2075_vt_join_q};
    assign i_add_i_i_i_i_i_i_64_c_compmm_m2076_b = {1'b0, redist926_i_conv_i_i_i_i_i_64_c_compmm_m2072_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_64_c_compmm_m2076_o = $unsigned(i_add_i_i_i_i_i_i_64_c_compmm_m2076_a) + $unsigned(i_add_i_i_i_i_i_i_64_c_compmm_m2076_b);
    assign i_add_i_i_i_i_i_i_64_c_compmm_m2076_q = i_add_i_i_i_i_i_i_64_c_compmm_m2076_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_64_c_compmm_m2076_sel_x(BITSELECT,2261)@203
    assign bgTrunc_i_add_i_i_i_i_i_i_64_c_compmm_m2076_sel_x_b = i_add_i_i_i_i_i_i_64_c_compmm_m2076_q[15:0];

    // i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_sel_x(BITSELECT,3921)@203
    assign i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_64_c_compmm_m2076_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_select_15(BITSELECT,8411)@203
    assign i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_select_15_b = i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_join(BITJOIN,8410)@203
    assign i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_select_15_b};

    // leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(MUX,27646)@203
    assign leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_join_q or leftShiftStage0Idx1_uid27645_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_65_c_compmm_m2096_vt_join_q;
            1'b1 : leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27645_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(MUX,27651)@203
    assign leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s or leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27650_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = leftShiftStage0_uid27647_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27650_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x(MUX,27656)@203
    assign leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s or leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27655_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = leftShiftStage1_uid27652_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27655_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28(BITSELECT,10105)@203
    assign i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28_b = leftShiftStage2_uid27657_i_shl_i_i_i_i_i_i_65_c_compmm_m0_shift_x_q[28:13];

    // redist292_i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28_b_1(DELAY,29420)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist292_i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_join(BITJOIN,10104)@204
    assign i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_join_q = {redist292_i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg125(REG,13420)@197 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg125_q <= $unsigned(redist824_sync_together4364_aunroll_x_in_i_valid_129_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_66150_c_compmm_m126(BLACKBOX,8698)@198
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66150_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_66150_c_compmm_m126 (
        .in_intel_reserved_ffwd_132_0(in_intel_reserved_ffwd_132_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg125_q),
        .out_dest_data_out_132_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_66150_c_compmm_m126_out_dest_data_out_132_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_offset(CONSTANT,31037)
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_offset_q = $unsigned(7'b0000011);

    // redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt(ADD,31038)
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_a = {1'b0, redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_q};
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_b = {1'b0, redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_o <= $unsigned(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_a) + $unsigned(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_b);
        end
    end
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_q = redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_o[7:0];

    // redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_inputreg0(DELAY,31033)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_inputreg0_q <= $unsigned(in_c1_eni5_131_tpl);
        end
    end

    // redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr(COUNTER,31036)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_i <= $unsigned(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_q = redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_i[6:0];

    // redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem(DUALMEM,31035)
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_ia = $unsigned(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_inputreg0_q);
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_aa = redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_wraddr_q;
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_ab = redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_aa),
        .data_a(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_ab),
        .q_b(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_q = redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_iq[15:0];

    // redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_outputreg0(DELAY,31034)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_outputreg0_q <= $unsigned(redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_mem_q);
        end
    end

    // redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt(ADD,31044)
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_a = {1'b0, redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_q};
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_b = {1'b0, redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_o <= $unsigned(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_a) + $unsigned(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_b);
        end
    end
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_q = redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_o[7:0];

    // redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_inputreg0(DELAY,31039)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_inputreg0_q <= $unsigned(in_c1_eni5_132_tpl);
        end
    end

    // redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr(COUNTER,31042)
    // low=0, high=127, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_i <= $unsigned(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_i) + $unsigned(7'd1);
        end
    end
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_q = redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_i[6:0];

    // redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem(DUALMEM,31041)
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_ia = $unsigned(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_inputreg0_q);
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_aa = redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_wraddr_q;
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_ab = redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_rdcnt_q[6:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(7),
        .numwords_a(128),
        .width_b(16),
        .widthad_b(7),
        .numwords_b(128),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_aa),
        .data_a(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_ab),
        .q_b(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_q = redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_iq[15:0];

    // redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_outputreg0(DELAY,31040)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_outputreg0_q <= $unsigned(redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_mem_q);
        end
    end

    // valid_fanout_reg126(REG,13421)@197 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg126_q <= $unsigned(redist824_sync_together4364_aunroll_x_in_i_valid_129_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_66149_c_compmm_m127(BLACKBOX,8654)@198
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66149_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_66149_c_compmm_m127 (
        .in_intel_reserved_ffwd_131_0(in_intel_reserved_ffwd_131_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg126_q),
        .out_dest_data_out_131_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_66149_c_compmm_m127_out_dest_data_out_131_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28936)@198 + 5
    // out q@204
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_66149_c_compmm_m127_out_dest_data_out_131_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_66150_c_compmm_m126_out_dest_data_out_132_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098(ADD,9035)@204
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod607_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_b = $unsigned({{5{i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_65_c_compmm_m2097_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_o[33:0];

    // rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x(MUX,19901)@204
    assign rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q or rightShiftStage0Idx1_uid19900_dupName_261_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q;
            1'b1 : rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19900_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x(MUX,19906)@204
    assign rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19905_dupName_261_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19902_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19905_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x(MUX,19911)@204
    assign rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19910_dupName_261_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19907_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19910_dupName_261_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2099_vt_select_20(BITSELECT,11080)@204
    assign i_unnamed_c_compmm_m2099_vt_select_20_b = rightShiftStage2_uid19912_dupName_261_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2099_vt_join(BITJOIN,11079)@204
    assign i_unnamed_c_compmm_m2099_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2099_vt_select_20_b};

    // i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x(BITSELECT,3793)@204
    assign i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x_b = i_unnamed_c_compmm_m2099_vt_join_q[15:0];

    // redist925_i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x_b_1(DELAY,30053)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist925_i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19921_dupName_262_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19920)@204
    assign rightShiftStage1Idx1Rng8_uid19921_dupName_262_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19923_dupName_262_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19922)@204
    assign rightShiftStage1Idx1_uid19923_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19921_dupName_262_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19916_dupName_262_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19915)@204
    assign rightShiftStage0Idx1Rng4_uid19916_dupName_262_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q[33:4];

    // rightShiftStage0Idx1_uid19918_dupName_262_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19917)@204
    assign rightShiftStage0Idx1_uid19918_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19916_dupName_262_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x(MUX,19919)@204
    assign rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q or rightShiftStage0Idx1_uid19918_dupName_262_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_65_i_c_compmm_m2098_q;
            1'b1 : rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19918_dupName_262_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x(MUX,19924)@204
    assign rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19923_dupName_262_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19920_dupName_262_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19923_dupName_262_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2101_vt_select_21(BITSELECT,11083)@204
    assign i_unnamed_c_compmm_m2101_vt_select_21_b = rightShiftStage1_uid19925_dupName_262_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2101_vt_join(BITJOIN,11082)@204
    assign i_unnamed_c_compmm_m2101_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2101_vt_select_21_b};

    // i_unnamed_c_compmm_m2102_sel_x(BITSELECT,6082)@204
    assign i_unnamed_c_compmm_m2102_sel_x_b = i_unnamed_c_compmm_m2101_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2103_BitSelect_for_a(BITSELECT,28516)@204
    assign i_unnamed_c_compmm_m2103_BitSelect_for_a_b = i_unnamed_c_compmm_m2102_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2103_join(BITJOIN,28517)@204
    assign i_unnamed_c_compmm_m2103_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2103_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2103_vt_select_0(BITSELECT,11088)@204
    assign i_unnamed_c_compmm_m2103_vt_select_0_b = i_unnamed_c_compmm_m2103_join_q[0:0];

    // redist176_i_unnamed_c_compmm_m2103_vt_select_0_b_1(DELAY,29304)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist176_i_unnamed_c_compmm_m2103_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2103_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2103_vt_join(BITJOIN,11087)@205
    assign i_unnamed_c_compmm_m2103_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist176_i_unnamed_c_compmm_m2103_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_65_c_compmm_m2104(ADD,7248)@205
    assign i_add_i_i_i_i_i_i_65_c_compmm_m2104_a = {1'b0, i_unnamed_c_compmm_m2103_vt_join_q};
    assign i_add_i_i_i_i_i_i_65_c_compmm_m2104_b = {1'b0, redist925_i_conv_i_i_i_i_i_65_c_compmm_m2100_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_65_c_compmm_m2104_o = $unsigned(i_add_i_i_i_i_i_i_65_c_compmm_m2104_a) + $unsigned(i_add_i_i_i_i_i_i_65_c_compmm_m2104_b);
    assign i_add_i_i_i_i_i_i_65_c_compmm_m2104_q = i_add_i_i_i_i_i_i_65_c_compmm_m2104_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_65_c_compmm_m2104_sel_x(BITSELECT,2262)@205
    assign bgTrunc_i_add_i_i_i_i_i_i_65_c_compmm_m2104_sel_x_b = i_add_i_i_i_i_i_i_65_c_compmm_m2104_q[15:0];

    // i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_sel_x(BITSELECT,3922)@205
    assign i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_65_c_compmm_m2104_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_select_15(BITSELECT,8415)@205
    assign i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_select_15_b = i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_join(BITJOIN,8414)@205
    assign i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_select_15_b};

    // leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(MUX,27664)@205
    assign leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_join_q or leftShiftStage0Idx1_uid27663_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_66_c_compmm_m2124_vt_join_q;
            1'b1 : leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27663_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(MUX,27669)@205
    assign leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s or leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27668_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = leftShiftStage0_uid27665_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27668_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x(MUX,27674)@205
    assign leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s or leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27673_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = leftShiftStage1_uid27670_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27673_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28(BITSELECT,10108)@205
    assign i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28_b = leftShiftStage2_uid27675_i_shl_i_i_i_i_i_i_66_c_compmm_m0_shift_x_q[28:13];

    // redist291_i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28_b_1(DELAY,29419)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist291_i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_join(BITJOIN,10107)@206
    assign i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_join_q = {redist291_i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg123(REG,13418)@199 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg123_q <= $unsigned(redist825_sync_together4364_aunroll_x_in_i_valid_131_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_66152_c_compmm_m124(BLACKBOX,8786)@200
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66152_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_66152_c_compmm_m124 (
        .in_intel_reserved_ffwd_134_0(in_intel_reserved_ffwd_134_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg123_q),
        .out_dest_data_out_134_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_66152_c_compmm_m124_out_dest_data_out_134_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_offset(CONSTANT,31049)
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_offset_q = $unsigned(8'b10000001);

    // redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt(ADD,31050)
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_a = {1'b0, redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_q};
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_b = {1'b0, redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_o <= $unsigned(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_a) + $unsigned(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_b);
        end
    end
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_q = redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_o[8:0];

    // redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_inputreg0(DELAY,31045)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_inputreg0_q <= $unsigned(in_c1_eni5_133_tpl);
        end
    end

    // redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr(COUNTER,31048)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_i <= $unsigned(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_q = redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_i[7:0];

    // redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem(DUALMEM,31047)
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_ia = $unsigned(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_inputreg0_q);
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_aa = redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_wraddr_q;
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_ab = redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_aa),
        .data_a(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_ab),
        .q_b(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_q = redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_iq[15:0];

    // redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_outputreg0(DELAY,31046)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_outputreg0_q <= $unsigned(redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_mem_q);
        end
    end

    // redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt(ADD,31056)
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_a = {1'b0, redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_q};
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_b = {1'b0, redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_o <= $unsigned(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_a) + $unsigned(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_b);
        end
    end
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_q = redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_o[8:0];

    // redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_inputreg0(DELAY,31051)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_inputreg0_q <= $unsigned(in_c1_eni5_134_tpl);
        end
    end

    // redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr(COUNTER,31054)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_i <= $unsigned(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_q = redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_i[7:0];

    // redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem(DUALMEM,31053)
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_ia = $unsigned(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_inputreg0_q);
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_aa = redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_wraddr_q;
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_ab = redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_aa),
        .data_a(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_ab),
        .q_b(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_q = redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_iq[15:0];

    // redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_outputreg0(DELAY,31052)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_outputreg0_q <= $unsigned(redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_mem_q);
        end
    end

    // valid_fanout_reg124(REG,13419)@199 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg124_q <= $unsigned(redist825_sync_together4364_aunroll_x_in_i_valid_131_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_66151_c_compmm_m125(BLACKBOX,8742)@200
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66151_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_66151_c_compmm_m125 (
        .in_intel_reserved_ffwd_133_0(in_intel_reserved_ffwd_133_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg124_q),
        .out_dest_data_out_133_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_66151_c_compmm_m125_out_dest_data_out_133_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28937)@200 + 5
    // out q@206
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_66151_c_compmm_m125_out_dest_data_out_133_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_66152_c_compmm_m124_out_dest_data_out_134_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126(ADD,9036)@206
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod612_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_b = $unsigned({{5{i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_66_c_compmm_m2125_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_o[33:0];

    // rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x(MUX,19963)@206
    assign rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q or rightShiftStage0Idx1_uid19962_dupName_265_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q;
            1'b1 : rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19962_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x(MUX,19968)@206
    assign rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19967_dupName_265_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19964_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19967_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x(MUX,19973)@206
    assign rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19972_dupName_265_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19969_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19972_dupName_265_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2127_vt_select_20(BITSELECT,11102)@206
    assign i_unnamed_c_compmm_m2127_vt_select_20_b = rightShiftStage2_uid19974_dupName_265_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2127_vt_join(BITJOIN,11101)@206
    assign i_unnamed_c_compmm_m2127_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2127_vt_select_20_b};

    // i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x(BITSELECT,3794)@206
    assign i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x_b = i_unnamed_c_compmm_m2127_vt_join_q[15:0];

    // redist924_i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x_b_1(DELAY,30052)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist924_i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19983_dupName_266_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19982)@206
    assign rightShiftStage1Idx1Rng8_uid19983_dupName_266_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19985_dupName_266_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19984)@206
    assign rightShiftStage1Idx1_uid19985_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19983_dupName_266_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19978_dupName_266_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19977)@206
    assign rightShiftStage0Idx1Rng4_uid19978_dupName_266_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q[33:4];

    // rightShiftStage0Idx1_uid19980_dupName_266_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19979)@206
    assign rightShiftStage0Idx1_uid19980_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19978_dupName_266_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x(MUX,19981)@206
    assign rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q or rightShiftStage0Idx1_uid19980_dupName_266_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_66_i_c_compmm_m2126_q;
            1'b1 : rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19980_dupName_266_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x(MUX,19986)@206
    assign rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19985_dupName_266_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19982_dupName_266_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19985_dupName_266_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2129_vt_select_21(BITSELECT,11105)@206
    assign i_unnamed_c_compmm_m2129_vt_select_21_b = rightShiftStage1_uid19987_dupName_266_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2129_vt_join(BITJOIN,11104)@206
    assign i_unnamed_c_compmm_m2129_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2129_vt_select_21_b};

    // i_unnamed_c_compmm_m2130_sel_x(BITSELECT,6084)@206
    assign i_unnamed_c_compmm_m2130_sel_x_b = i_unnamed_c_compmm_m2129_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2131_BitSelect_for_a(BITSELECT,28520)@206
    assign i_unnamed_c_compmm_m2131_BitSelect_for_a_b = i_unnamed_c_compmm_m2130_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2131_join(BITJOIN,28521)@206
    assign i_unnamed_c_compmm_m2131_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2131_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2131_vt_select_0(BITSELECT,11110)@206
    assign i_unnamed_c_compmm_m2131_vt_select_0_b = i_unnamed_c_compmm_m2131_join_q[0:0];

    // redist174_i_unnamed_c_compmm_m2131_vt_select_0_b_1(DELAY,29302)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist174_i_unnamed_c_compmm_m2131_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2131_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2131_vt_join(BITJOIN,11109)@207
    assign i_unnamed_c_compmm_m2131_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist174_i_unnamed_c_compmm_m2131_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_66_c_compmm_m2132(ADD,7249)@207
    assign i_add_i_i_i_i_i_i_66_c_compmm_m2132_a = {1'b0, i_unnamed_c_compmm_m2131_vt_join_q};
    assign i_add_i_i_i_i_i_i_66_c_compmm_m2132_b = {1'b0, redist924_i_conv_i_i_i_i_i_66_c_compmm_m2128_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_66_c_compmm_m2132_o = $unsigned(i_add_i_i_i_i_i_i_66_c_compmm_m2132_a) + $unsigned(i_add_i_i_i_i_i_i_66_c_compmm_m2132_b);
    assign i_add_i_i_i_i_i_i_66_c_compmm_m2132_q = i_add_i_i_i_i_i_i_66_c_compmm_m2132_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_66_c_compmm_m2132_sel_x(BITSELECT,2263)@207
    assign bgTrunc_i_add_i_i_i_i_i_i_66_c_compmm_m2132_sel_x_b = i_add_i_i_i_i_i_i_66_c_compmm_m2132_q[15:0];

    // i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_sel_x(BITSELECT,3923)@207
    assign i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_66_c_compmm_m2132_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_select_15(BITSELECT,8419)@207
    assign i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_select_15_b = i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_join(BITJOIN,8418)@207
    assign i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_select_15_b};

    // leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(MUX,27682)@207
    assign leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_join_q or leftShiftStage0Idx1_uid27681_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_67_c_compmm_m2152_vt_join_q;
            1'b1 : leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27681_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(MUX,27687)@207
    assign leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s or leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27686_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = leftShiftStage0_uid27683_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27686_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x(MUX,27692)@207
    assign leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s or leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27691_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = leftShiftStage1_uid27688_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27691_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28(BITSELECT,10111)@207
    assign i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28_b = leftShiftStage2_uid27693_i_shl_i_i_i_i_i_i_67_c_compmm_m0_shift_x_q[28:13];

    // redist290_i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28_b_1(DELAY,29418)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist290_i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_join(BITJOIN,10110)@208
    assign i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_join_q = {redist290_i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg121(REG,13416)@201 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg121_q <= $unsigned(redist826_sync_together4364_aunroll_x_in_i_valid_133_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_66154_c_compmm_m122(BLACKBOX,8810)@202
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66154_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_66154_c_compmm_m122 (
        .in_intel_reserved_ffwd_136_0(in_intel_reserved_ffwd_136_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg121_q),
        .out_dest_data_out_136_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_66154_c_compmm_m122_out_dest_data_out_136_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_offset(CONSTANT,31061)
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_offset_q = $unsigned(8'b01111111);

    // redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt(ADD,31062)
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_a = {1'b0, redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_q};
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_b = {1'b0, redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_o <= $unsigned(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_a) + $unsigned(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_b);
        end
    end
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_q = redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_o[8:0];

    // redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_inputreg0(DELAY,31057)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_inputreg0_q <= $unsigned(in_c1_eni5_135_tpl);
        end
    end

    // redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr(COUNTER,31060)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_i <= $unsigned(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_q = redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_i[7:0];

    // redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem(DUALMEM,31059)
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_ia = $unsigned(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_inputreg0_q);
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_aa = redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_wraddr_q;
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_ab = redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_aa),
        .data_a(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_ab),
        .q_b(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_q = redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_iq[15:0];

    // redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_outputreg0(DELAY,31058)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_outputreg0_q <= $unsigned(redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_mem_q);
        end
    end

    // redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt(ADD,31068)
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_a = {1'b0, redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_q};
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_b = {1'b0, redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_o <= $unsigned(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_a) + $unsigned(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_b);
        end
    end
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_q = redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_o[8:0];

    // redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_inputreg0(DELAY,31063)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_inputreg0_q <= $unsigned(in_c1_eni5_136_tpl);
        end
    end

    // redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr(COUNTER,31066)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_i <= $unsigned(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_q = redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_i[7:0];

    // redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem(DUALMEM,31065)
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_ia = $unsigned(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_inputreg0_q);
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_aa = redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_wraddr_q;
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_ab = redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_aa),
        .data_a(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_ab),
        .q_b(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_q = redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_iq[15:0];

    // redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_outputreg0(DELAY,31064)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_outputreg0_q <= $unsigned(redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_mem_q);
        end
    end

    // valid_fanout_reg122(REG,13417)@201 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg122_q <= $unsigned(redist826_sync_together4364_aunroll_x_in_i_valid_133_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_66153_c_compmm_m123(BLACKBOX,8806)@202
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66153_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_66153_c_compmm_m123 (
        .in_intel_reserved_ffwd_135_0(in_intel_reserved_ffwd_135_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg122_q),
        .out_dest_data_out_135_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_66153_c_compmm_m123_out_dest_data_out_135_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28938)@202 + 5
    // out q@208
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_66153_c_compmm_m123_out_dest_data_out_135_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_66154_c_compmm_m122_out_dest_data_out_136_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154(ADD,9037)@208
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod617_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_b = $unsigned({{5{i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_67_c_compmm_m2153_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_o[33:0];

    // rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x(MUX,20025)@208
    assign rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q or rightShiftStage0Idx1_uid20024_dupName_269_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q;
            1'b1 : rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20024_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x(MUX,20030)@208
    assign rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20029_dupName_269_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20026_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20029_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x(MUX,20035)@208
    assign rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20034_dupName_269_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20031_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20034_dupName_269_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2155_vt_select_20(BITSELECT,11124)@208
    assign i_unnamed_c_compmm_m2155_vt_select_20_b = rightShiftStage2_uid20036_dupName_269_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2155_vt_join(BITJOIN,11123)@208
    assign i_unnamed_c_compmm_m2155_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2155_vt_select_20_b};

    // i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x(BITSELECT,3795)@208
    assign i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x_b = i_unnamed_c_compmm_m2155_vt_join_q[15:0];

    // redist923_i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x_b_1(DELAY,30051)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist923_i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20045_dupName_270_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20044)@208
    assign rightShiftStage1Idx1Rng8_uid20045_dupName_270_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20047_dupName_270_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20046)@208
    assign rightShiftStage1Idx1_uid20047_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20045_dupName_270_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20040_dupName_270_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20039)@208
    assign rightShiftStage0Idx1Rng4_uid20040_dupName_270_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q[33:4];

    // rightShiftStage0Idx1_uid20042_dupName_270_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20041)@208
    assign rightShiftStage0Idx1_uid20042_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20040_dupName_270_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x(MUX,20043)@208
    assign rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q or rightShiftStage0Idx1_uid20042_dupName_270_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_67_i_c_compmm_m2154_q;
            1'b1 : rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20042_dupName_270_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x(MUX,20048)@208
    assign rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20047_dupName_270_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20044_dupName_270_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20047_dupName_270_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2157_vt_select_21(BITSELECT,11127)@208
    assign i_unnamed_c_compmm_m2157_vt_select_21_b = rightShiftStage1_uid20049_dupName_270_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2157_vt_join(BITJOIN,11126)@208
    assign i_unnamed_c_compmm_m2157_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2157_vt_select_21_b};

    // i_unnamed_c_compmm_m2158_sel_x(BITSELECT,6086)@208
    assign i_unnamed_c_compmm_m2158_sel_x_b = i_unnamed_c_compmm_m2157_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2159_BitSelect_for_a(BITSELECT,28524)@208
    assign i_unnamed_c_compmm_m2159_BitSelect_for_a_b = i_unnamed_c_compmm_m2158_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2159_join(BITJOIN,28525)@208
    assign i_unnamed_c_compmm_m2159_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2159_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2159_vt_select_0(BITSELECT,11132)@208
    assign i_unnamed_c_compmm_m2159_vt_select_0_b = i_unnamed_c_compmm_m2159_join_q[0:0];

    // redist172_i_unnamed_c_compmm_m2159_vt_select_0_b_1(DELAY,29300)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist172_i_unnamed_c_compmm_m2159_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2159_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2159_vt_join(BITJOIN,11131)@209
    assign i_unnamed_c_compmm_m2159_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist172_i_unnamed_c_compmm_m2159_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_67_c_compmm_m2160(ADD,7250)@209
    assign i_add_i_i_i_i_i_i_67_c_compmm_m2160_a = {1'b0, i_unnamed_c_compmm_m2159_vt_join_q};
    assign i_add_i_i_i_i_i_i_67_c_compmm_m2160_b = {1'b0, redist923_i_conv_i_i_i_i_i_67_c_compmm_m2156_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_67_c_compmm_m2160_o = $unsigned(i_add_i_i_i_i_i_i_67_c_compmm_m2160_a) + $unsigned(i_add_i_i_i_i_i_i_67_c_compmm_m2160_b);
    assign i_add_i_i_i_i_i_i_67_c_compmm_m2160_q = i_add_i_i_i_i_i_i_67_c_compmm_m2160_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_67_c_compmm_m2160_sel_x(BITSELECT,2264)@209
    assign bgTrunc_i_add_i_i_i_i_i_i_67_c_compmm_m2160_sel_x_b = i_add_i_i_i_i_i_i_67_c_compmm_m2160_q[15:0];

    // i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_sel_x(BITSELECT,3924)@209
    assign i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_67_c_compmm_m2160_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_select_15(BITSELECT,8423)@209
    assign i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_select_15_b = i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_join(BITJOIN,8422)@209
    assign i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_select_15_b};

    // leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(MUX,27700)@209
    assign leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_join_q or leftShiftStage0Idx1_uid27699_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_68_c_compmm_m2180_vt_join_q;
            1'b1 : leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27699_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(MUX,27705)@209
    assign leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s or leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27704_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = leftShiftStage0_uid27701_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27704_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x(MUX,27710)@209
    assign leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s or leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27709_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = leftShiftStage1_uid27706_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27709_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28(BITSELECT,10114)@209
    assign i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28_b = leftShiftStage2_uid27711_i_shl_i_i_i_i_i_i_68_c_compmm_m0_shift_x_q[28:13];

    // redist289_i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28_b_1(DELAY,29417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist289_i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_join(BITJOIN,10113)@210
    assign i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_join_q = {redist289_i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg119(REG,13414)@203 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg119_q <= $unsigned(redist827_sync_together4364_aunroll_x_in_i_valid_135_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_66156_c_compmm_m120(BLACKBOX,8818)@204
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66156_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_66156_c_compmm_m120 (
        .in_intel_reserved_ffwd_138_0(in_intel_reserved_ffwd_138_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg119_q),
        .out_dest_data_out_138_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_66156_c_compmm_m120_out_dest_data_out_138_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_offset(CONSTANT,31073)
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_offset_q = $unsigned(8'b01111101);

    // redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt(ADD,31074)
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_a = {1'b0, redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_q};
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_b = {1'b0, redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_o <= $unsigned(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_a) + $unsigned(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_b);
        end
    end
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_q = redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_o[8:0];

    // redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_inputreg0(DELAY,31069)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_inputreg0_q <= $unsigned(in_c1_eni5_137_tpl);
        end
    end

    // redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr(COUNTER,31072)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_i <= $unsigned(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_q = redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_i[7:0];

    // redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem(DUALMEM,31071)
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_ia = $unsigned(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_inputreg0_q);
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_aa = redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_wraddr_q;
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_ab = redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_aa),
        .data_a(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_ab),
        .q_b(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_q = redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_iq[15:0];

    // redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_outputreg0(DELAY,31070)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_outputreg0_q <= $unsigned(redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_mem_q);
        end
    end

    // redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt(ADD,31080)
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_a = {1'b0, redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_q};
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_b = {1'b0, redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_o <= $unsigned(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_a) + $unsigned(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_b);
        end
    end
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_q = redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_o[8:0];

    // redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_inputreg0(DELAY,31075)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_inputreg0_q <= $unsigned(in_c1_eni5_138_tpl);
        end
    end

    // redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr(COUNTER,31078)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_i <= $unsigned(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_q = redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_i[7:0];

    // redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem(DUALMEM,31077)
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_ia = $unsigned(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_inputreg0_q);
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_aa = redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_wraddr_q;
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_ab = redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_aa),
        .data_a(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_ab),
        .q_b(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_q = redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_iq[15:0];

    // redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_outputreg0(DELAY,31076)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_outputreg0_q <= $unsigned(redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_mem_q);
        end
    end

    // valid_fanout_reg120(REG,13415)@203 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg120_q <= $unsigned(redist827_sync_together4364_aunroll_x_in_i_valid_135_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_66155_c_compmm_m121(BLACKBOX,8814)@204
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66155_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_66155_c_compmm_m121 (
        .in_intel_reserved_ffwd_137_0(in_intel_reserved_ffwd_137_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg120_q),
        .out_dest_data_out_137_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_66155_c_compmm_m121_out_dest_data_out_137_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28939)@204 + 5
    // out q@210
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_66155_c_compmm_m121_out_dest_data_out_137_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_66156_c_compmm_m120_out_dest_data_out_138_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182(ADD,9038)@210
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod622_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_b = $unsigned({{5{i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_68_c_compmm_m2181_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_o[33:0];

    // rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x(MUX,20087)@210
    assign rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q or rightShiftStage0Idx1_uid20086_dupName_273_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q;
            1'b1 : rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20086_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x(MUX,20092)@210
    assign rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20091_dupName_273_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20088_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20091_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x(MUX,20097)@210
    assign rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20096_dupName_273_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20093_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20096_dupName_273_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2183_vt_select_20(BITSELECT,11146)@210
    assign i_unnamed_c_compmm_m2183_vt_select_20_b = rightShiftStage2_uid20098_dupName_273_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2183_vt_join(BITJOIN,11145)@210
    assign i_unnamed_c_compmm_m2183_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2183_vt_select_20_b};

    // i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x(BITSELECT,3796)@210
    assign i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x_b = i_unnamed_c_compmm_m2183_vt_join_q[15:0];

    // redist922_i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x_b_1(DELAY,30050)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist922_i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20107_dupName_274_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20106)@210
    assign rightShiftStage1Idx1Rng8_uid20107_dupName_274_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20109_dupName_274_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20108)@210
    assign rightShiftStage1Idx1_uid20109_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20107_dupName_274_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20102_dupName_274_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20101)@210
    assign rightShiftStage0Idx1Rng4_uid20102_dupName_274_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q[33:4];

    // rightShiftStage0Idx1_uid20104_dupName_274_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20103)@210
    assign rightShiftStage0Idx1_uid20104_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20102_dupName_274_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x(MUX,20105)@210
    assign rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q or rightShiftStage0Idx1_uid20104_dupName_274_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_68_i_c_compmm_m2182_q;
            1'b1 : rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20104_dupName_274_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x(MUX,20110)@210
    assign rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20109_dupName_274_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20106_dupName_274_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20109_dupName_274_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2185_vt_select_21(BITSELECT,11149)@210
    assign i_unnamed_c_compmm_m2185_vt_select_21_b = rightShiftStage1_uid20111_dupName_274_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2185_vt_join(BITJOIN,11148)@210
    assign i_unnamed_c_compmm_m2185_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2185_vt_select_21_b};

    // i_unnamed_c_compmm_m2186_sel_x(BITSELECT,6088)@210
    assign i_unnamed_c_compmm_m2186_sel_x_b = i_unnamed_c_compmm_m2185_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2187_BitSelect_for_a(BITSELECT,28528)@210
    assign i_unnamed_c_compmm_m2187_BitSelect_for_a_b = i_unnamed_c_compmm_m2186_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2187_join(BITJOIN,28529)@210
    assign i_unnamed_c_compmm_m2187_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2187_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2187_vt_select_0(BITSELECT,11154)@210
    assign i_unnamed_c_compmm_m2187_vt_select_0_b = i_unnamed_c_compmm_m2187_join_q[0:0];

    // redist170_i_unnamed_c_compmm_m2187_vt_select_0_b_1(DELAY,29298)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist170_i_unnamed_c_compmm_m2187_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2187_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2187_vt_join(BITJOIN,11153)@211
    assign i_unnamed_c_compmm_m2187_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist170_i_unnamed_c_compmm_m2187_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_68_c_compmm_m2188(ADD,7251)@211
    assign i_add_i_i_i_i_i_i_68_c_compmm_m2188_a = {1'b0, i_unnamed_c_compmm_m2187_vt_join_q};
    assign i_add_i_i_i_i_i_i_68_c_compmm_m2188_b = {1'b0, redist922_i_conv_i_i_i_i_i_68_c_compmm_m2184_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_68_c_compmm_m2188_o = $unsigned(i_add_i_i_i_i_i_i_68_c_compmm_m2188_a) + $unsigned(i_add_i_i_i_i_i_i_68_c_compmm_m2188_b);
    assign i_add_i_i_i_i_i_i_68_c_compmm_m2188_q = i_add_i_i_i_i_i_i_68_c_compmm_m2188_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_68_c_compmm_m2188_sel_x(BITSELECT,2265)@211
    assign bgTrunc_i_add_i_i_i_i_i_i_68_c_compmm_m2188_sel_x_b = i_add_i_i_i_i_i_i_68_c_compmm_m2188_q[15:0];

    // i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_sel_x(BITSELECT,3925)@211
    assign i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_68_c_compmm_m2188_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_select_15(BITSELECT,8427)@211
    assign i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_select_15_b = i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_join(BITJOIN,8426)@211
    assign i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_select_15_b};

    // leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(MUX,27718)@211
    assign leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_join_q or leftShiftStage0Idx1_uid27717_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_69_c_compmm_m2208_vt_join_q;
            1'b1 : leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27717_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(MUX,27723)@211
    assign leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s or leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27722_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = leftShiftStage0_uid27719_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27722_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x(MUX,27728)@211
    assign leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s or leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27727_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = leftShiftStage1_uid27724_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27727_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28(BITSELECT,10117)@211
    assign i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28_b = leftShiftStage2_uid27729_i_shl_i_i_i_i_i_i_69_c_compmm_m0_shift_x_q[28:13];

    // redist288_i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28_b_1(DELAY,29416)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist288_i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_join(BITJOIN,10116)@212
    assign i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_join_q = {redist288_i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg117(REG,13412)@205 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg117_q <= $unsigned(redist828_sync_together4364_aunroll_x_in_i_valid_137_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_66158_c_compmm_m118(BLACKBOX,8574)@206
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66158_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_66158_c_compmm_m118 (
        .in_intel_reserved_ffwd_140_0(in_intel_reserved_ffwd_140_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg117_q),
        .out_dest_data_out_140_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_66158_c_compmm_m118_out_dest_data_out_140_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_offset(CONSTANT,31085)
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_offset_q = $unsigned(8'b01111011);

    // redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt(ADD,31086)
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_a = {1'b0, redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_q};
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_b = {1'b0, redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_o <= $unsigned(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_a) + $unsigned(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_b);
        end
    end
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_q = redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_o[8:0];

    // redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_inputreg0(DELAY,31081)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_inputreg0_q <= $unsigned(in_c1_eni5_139_tpl);
        end
    end

    // redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr(COUNTER,31084)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_i <= $unsigned(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_q = redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_i[7:0];

    // redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem(DUALMEM,31083)
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_ia = $unsigned(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_inputreg0_q);
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_aa = redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_wraddr_q;
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_ab = redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_aa),
        .data_a(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_ab),
        .q_b(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_q = redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_iq[15:0];

    // redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_outputreg0(DELAY,31082)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_outputreg0_q <= $unsigned(redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_mem_q);
        end
    end

    // redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt(ADD,31092)
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_a = {1'b0, redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_q};
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_b = {1'b0, redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_o <= $unsigned(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_a) + $unsigned(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_b);
        end
    end
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_q = redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_o[8:0];

    // redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_inputreg0(DELAY,31087)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_inputreg0_q <= $unsigned(in_c1_eni5_140_tpl);
        end
    end

    // redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr(COUNTER,31090)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_i <= $unsigned(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_q = redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_i[7:0];

    // redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem(DUALMEM,31089)
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_ia = $unsigned(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_inputreg0_q);
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_aa = redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_wraddr_q;
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_ab = redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_aa),
        .data_a(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_ab),
        .q_b(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_q = redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_iq[15:0];

    // redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_outputreg0(DELAY,31088)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_outputreg0_q <= $unsigned(redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_mem_q);
        end
    end

    // valid_fanout_reg118(REG,13413)@205 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg118_q <= $unsigned(redist828_sync_together4364_aunroll_x_in_i_valid_137_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_66157_c_compmm_m119(BLACKBOX,8570)@206
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66157_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_66157_c_compmm_m119 (
        .in_intel_reserved_ffwd_139_0(in_intel_reserved_ffwd_139_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg118_q),
        .out_dest_data_out_139_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_66157_c_compmm_m119_out_dest_data_out_139_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28940)@206 + 5
    // out q@212
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_66157_c_compmm_m119_out_dest_data_out_139_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_66158_c_compmm_m118_out_dest_data_out_140_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210(ADD,9039)@212
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod627_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_b = $unsigned({{5{i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_69_c_compmm_m2209_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_o[33:0];

    // rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x(MUX,20149)@212
    assign rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q or rightShiftStage0Idx1_uid20148_dupName_277_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q;
            1'b1 : rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20148_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x(MUX,20154)@212
    assign rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20153_dupName_277_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20150_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20153_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x(MUX,20159)@212
    assign rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20158_dupName_277_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20155_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20158_dupName_277_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2211_vt_select_20(BITSELECT,11168)@212
    assign i_unnamed_c_compmm_m2211_vt_select_20_b = rightShiftStage2_uid20160_dupName_277_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2211_vt_join(BITJOIN,11167)@212
    assign i_unnamed_c_compmm_m2211_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2211_vt_select_20_b};

    // i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x(BITSELECT,3797)@212
    assign i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x_b = i_unnamed_c_compmm_m2211_vt_join_q[15:0];

    // redist921_i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x_b_1(DELAY,30049)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist921_i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20169_dupName_278_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20168)@212
    assign rightShiftStage1Idx1Rng8_uid20169_dupName_278_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20171_dupName_278_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20170)@212
    assign rightShiftStage1Idx1_uid20171_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20169_dupName_278_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20164_dupName_278_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20163)@212
    assign rightShiftStage0Idx1Rng4_uid20164_dupName_278_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q[33:4];

    // rightShiftStage0Idx1_uid20166_dupName_278_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20165)@212
    assign rightShiftStage0Idx1_uid20166_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20164_dupName_278_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x(MUX,20167)@212
    assign rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q or rightShiftStage0Idx1_uid20166_dupName_278_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_69_i_c_compmm_m2210_q;
            1'b1 : rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20166_dupName_278_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x(MUX,20172)@212
    assign rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20171_dupName_278_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20168_dupName_278_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20171_dupName_278_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2213_vt_select_21(BITSELECT,11171)@212
    assign i_unnamed_c_compmm_m2213_vt_select_21_b = rightShiftStage1_uid20173_dupName_278_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2213_vt_join(BITJOIN,11170)@212
    assign i_unnamed_c_compmm_m2213_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2213_vt_select_21_b};

    // i_unnamed_c_compmm_m2214_sel_x(BITSELECT,6090)@212
    assign i_unnamed_c_compmm_m2214_sel_x_b = i_unnamed_c_compmm_m2213_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2215_BitSelect_for_a(BITSELECT,28532)@212
    assign i_unnamed_c_compmm_m2215_BitSelect_for_a_b = i_unnamed_c_compmm_m2214_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2215_join(BITJOIN,28533)@212
    assign i_unnamed_c_compmm_m2215_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2215_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2215_vt_select_0(BITSELECT,11176)@212
    assign i_unnamed_c_compmm_m2215_vt_select_0_b = i_unnamed_c_compmm_m2215_join_q[0:0];

    // redist168_i_unnamed_c_compmm_m2215_vt_select_0_b_1(DELAY,29296)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist168_i_unnamed_c_compmm_m2215_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2215_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2215_vt_join(BITJOIN,11175)@213
    assign i_unnamed_c_compmm_m2215_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist168_i_unnamed_c_compmm_m2215_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_69_c_compmm_m2216(ADD,7252)@213
    assign i_add_i_i_i_i_i_i_69_c_compmm_m2216_a = {1'b0, i_unnamed_c_compmm_m2215_vt_join_q};
    assign i_add_i_i_i_i_i_i_69_c_compmm_m2216_b = {1'b0, redist921_i_conv_i_i_i_i_i_69_c_compmm_m2212_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_69_c_compmm_m2216_o = $unsigned(i_add_i_i_i_i_i_i_69_c_compmm_m2216_a) + $unsigned(i_add_i_i_i_i_i_i_69_c_compmm_m2216_b);
    assign i_add_i_i_i_i_i_i_69_c_compmm_m2216_q = i_add_i_i_i_i_i_i_69_c_compmm_m2216_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_69_c_compmm_m2216_sel_x(BITSELECT,2266)@213
    assign bgTrunc_i_add_i_i_i_i_i_i_69_c_compmm_m2216_sel_x_b = i_add_i_i_i_i_i_i_69_c_compmm_m2216_q[15:0];

    // i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_sel_x(BITSELECT,3927)@213
    assign i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_69_c_compmm_m2216_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_select_15(BITSELECT,8435)@213
    assign i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_select_15_b = i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_join(BITJOIN,8434)@213
    assign i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_select_15_b};

    // leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(MUX,27754)@213
    assign leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_join_q or leftShiftStage0Idx1_uid27753_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_70_c_compmm_m2236_vt_join_q;
            1'b1 : leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27753_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(MUX,27759)@213
    assign leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s or leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27758_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = leftShiftStage0_uid27755_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27758_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x(MUX,27764)@213
    assign leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s or leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27763_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = leftShiftStage1_uid27760_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27763_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28(BITSELECT,10123)@213
    assign i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28_b = leftShiftStage2_uid27765_i_shl_i_i_i_i_i_i_70_c_compmm_m0_shift_x_q[28:13];

    // redist286_i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28_b_1(DELAY,29414)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist286_i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_join(BITJOIN,10122)@214
    assign i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_join_q = {redist286_i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg115(REG,13410)@207 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg115_q <= $unsigned(redist829_sync_together4364_aunroll_x_in_i_valid_139_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_66160_c_compmm_m116(BLACKBOX,8582)@208
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66160_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_66160_c_compmm_m116 (
        .in_intel_reserved_ffwd_142_0(in_intel_reserved_ffwd_142_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg115_q),
        .out_dest_data_out_142_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_66160_c_compmm_m116_out_dest_data_out_142_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_offset(CONSTANT,31097)
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_offset_q = $unsigned(8'b01111001);

    // redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt(ADD,31098)
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_a = {1'b0, redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_q};
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_b = {1'b0, redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_o <= $unsigned(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_a) + $unsigned(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_b);
        end
    end
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_q = redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_o[8:0];

    // redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_inputreg0(DELAY,31093)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_inputreg0_q <= $unsigned(in_c1_eni5_141_tpl);
        end
    end

    // redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr(COUNTER,31096)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_i <= $unsigned(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_q = redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_i[7:0];

    // redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem(DUALMEM,31095)
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_ia = $unsigned(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_inputreg0_q);
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_aa = redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_wraddr_q;
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_ab = redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_aa),
        .data_a(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_ab),
        .q_b(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_q = redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_iq[15:0];

    // redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_outputreg0(DELAY,31094)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_outputreg0_q <= $unsigned(redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_mem_q);
        end
    end

    // redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt(ADD,31104)
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_a = {1'b0, redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_q};
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_b = {1'b0, redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_o <= $unsigned(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_a) + $unsigned(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_b);
        end
    end
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_q = redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_o[8:0];

    // redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_inputreg0(DELAY,31099)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_inputreg0_q <= $unsigned(in_c1_eni5_142_tpl);
        end
    end

    // redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr(COUNTER,31102)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_i <= $unsigned(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_q = redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_i[7:0];

    // redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem(DUALMEM,31101)
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_ia = $unsigned(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_inputreg0_q);
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_aa = redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_wraddr_q;
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_ab = redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_aa),
        .data_a(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_ab),
        .q_b(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_q = redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_iq[15:0];

    // redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_outputreg0(DELAY,31100)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_outputreg0_q <= $unsigned(redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_mem_q);
        end
    end

    // valid_fanout_reg116(REG,13411)@207 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg116_q <= $unsigned(redist829_sync_together4364_aunroll_x_in_i_valid_139_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_66159_c_compmm_m117(BLACKBOX,8578)@208
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66159_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_66159_c_compmm_m117 (
        .in_intel_reserved_ffwd_141_0(in_intel_reserved_ffwd_141_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg116_q),
        .out_dest_data_out_141_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_66159_c_compmm_m117_out_dest_data_out_141_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28941)@208 + 5
    // out q@214
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_66159_c_compmm_m117_out_dest_data_out_141_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_66160_c_compmm_m116_out_dest_data_out_142_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238(ADD,9041)@214
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod632_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_b = $unsigned({{5{i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_70_c_compmm_m2237_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_o[33:0];

    // rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x(MUX,20211)@214
    assign rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q or rightShiftStage0Idx1_uid20210_dupName_281_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q;
            1'b1 : rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20210_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x(MUX,20216)@214
    assign rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20215_dupName_281_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20212_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20215_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x(MUX,20221)@214
    assign rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20220_dupName_281_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20217_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20220_dupName_281_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2239_vt_select_20(BITSELECT,11190)@214
    assign i_unnamed_c_compmm_m2239_vt_select_20_b = rightShiftStage2_uid20222_dupName_281_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2239_vt_join(BITJOIN,11189)@214
    assign i_unnamed_c_compmm_m2239_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2239_vt_select_20_b};

    // i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x(BITSELECT,3799)@214
    assign i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x_b = i_unnamed_c_compmm_m2239_vt_join_q[15:0];

    // redist919_i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x_b_1(DELAY,30047)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist919_i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20231_dupName_282_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20230)@214
    assign rightShiftStage1Idx1Rng8_uid20231_dupName_282_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20233_dupName_282_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20232)@214
    assign rightShiftStage1Idx1_uid20233_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20231_dupName_282_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20226_dupName_282_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20225)@214
    assign rightShiftStage0Idx1Rng4_uid20226_dupName_282_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q[33:4];

    // rightShiftStage0Idx1_uid20228_dupName_282_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20227)@214
    assign rightShiftStage0Idx1_uid20228_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20226_dupName_282_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x(MUX,20229)@214
    assign rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q or rightShiftStage0Idx1_uid20228_dupName_282_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_70_i_c_compmm_m2238_q;
            1'b1 : rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20228_dupName_282_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x(MUX,20234)@214
    assign rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20233_dupName_282_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20230_dupName_282_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20233_dupName_282_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2241_vt_select_21(BITSELECT,11193)@214
    assign i_unnamed_c_compmm_m2241_vt_select_21_b = rightShiftStage1_uid20235_dupName_282_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2241_vt_join(BITJOIN,11192)@214
    assign i_unnamed_c_compmm_m2241_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2241_vt_select_21_b};

    // i_unnamed_c_compmm_m2242_sel_x(BITSELECT,6092)@214
    assign i_unnamed_c_compmm_m2242_sel_x_b = i_unnamed_c_compmm_m2241_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2243_BitSelect_for_a(BITSELECT,28536)@214
    assign i_unnamed_c_compmm_m2243_BitSelect_for_a_b = i_unnamed_c_compmm_m2242_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2243_join(BITJOIN,28537)@214
    assign i_unnamed_c_compmm_m2243_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2243_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2243_vt_select_0(BITSELECT,11198)@214
    assign i_unnamed_c_compmm_m2243_vt_select_0_b = i_unnamed_c_compmm_m2243_join_q[0:0];

    // redist166_i_unnamed_c_compmm_m2243_vt_select_0_b_1(DELAY,29294)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist166_i_unnamed_c_compmm_m2243_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2243_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2243_vt_join(BITJOIN,11197)@215
    assign i_unnamed_c_compmm_m2243_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist166_i_unnamed_c_compmm_m2243_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_70_c_compmm_m2244(ADD,7254)@215
    assign i_add_i_i_i_i_i_i_70_c_compmm_m2244_a = {1'b0, i_unnamed_c_compmm_m2243_vt_join_q};
    assign i_add_i_i_i_i_i_i_70_c_compmm_m2244_b = {1'b0, redist919_i_conv_i_i_i_i_i_70_c_compmm_m2240_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_70_c_compmm_m2244_o = $unsigned(i_add_i_i_i_i_i_i_70_c_compmm_m2244_a) + $unsigned(i_add_i_i_i_i_i_i_70_c_compmm_m2244_b);
    assign i_add_i_i_i_i_i_i_70_c_compmm_m2244_q = i_add_i_i_i_i_i_i_70_c_compmm_m2244_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_70_c_compmm_m2244_sel_x(BITSELECT,2268)@215
    assign bgTrunc_i_add_i_i_i_i_i_i_70_c_compmm_m2244_sel_x_b = i_add_i_i_i_i_i_i_70_c_compmm_m2244_q[15:0];

    // i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_sel_x(BITSELECT,3928)@215
    assign i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_70_c_compmm_m2244_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_select_15(BITSELECT,8439)@215
    assign i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_select_15_b = i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_join(BITJOIN,8438)@215
    assign i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_select_15_b};

    // leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(MUX,27772)@215
    assign leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_join_q or leftShiftStage0Idx1_uid27771_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_71_c_compmm_m2264_vt_join_q;
            1'b1 : leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27771_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(MUX,27777)@215
    assign leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s or leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27776_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = leftShiftStage0_uid27773_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27776_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x(MUX,27782)@215
    assign leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s or leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27781_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = leftShiftStage1_uid27778_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27781_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28(BITSELECT,10126)@215
    assign i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28_b = leftShiftStage2_uid27783_i_shl_i_i_i_i_i_i_71_c_compmm_m0_shift_x_q[28:13];

    // redist285_i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28_b_1(DELAY,29413)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist285_i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_join(BITJOIN,10125)@216
    assign i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_join_q = {redist285_i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg113(REG,13408)@209 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg113_q <= $unsigned(redist830_sync_together4364_aunroll_x_in_i_valid_141_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_66162_c_compmm_m114(BLACKBOX,8590)@210
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66162_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_66162_c_compmm_m114 (
        .in_intel_reserved_ffwd_144_0(in_intel_reserved_ffwd_144_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg113_q),
        .out_dest_data_out_144_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_66162_c_compmm_m114_out_dest_data_out_144_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_offset(CONSTANT,31109)
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_offset_q = $unsigned(8'b01110111);

    // redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt(ADD,31110)
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_a = {1'b0, redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_q};
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_b = {1'b0, redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_o <= $unsigned(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_a) + $unsigned(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_b);
        end
    end
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_q = redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_o[8:0];

    // redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_inputreg0(DELAY,31105)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_inputreg0_q <= $unsigned(in_c1_eni5_143_tpl);
        end
    end

    // redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr(COUNTER,31108)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_i <= $unsigned(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_q = redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_i[7:0];

    // redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem(DUALMEM,31107)
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_ia = $unsigned(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_inputreg0_q);
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_aa = redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_wraddr_q;
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_ab = redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_aa),
        .data_a(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_ab),
        .q_b(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_q = redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_iq[15:0];

    // redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_outputreg0(DELAY,31106)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_outputreg0_q <= $unsigned(redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_mem_q);
        end
    end

    // redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt(ADD,31116)
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_a = {1'b0, redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_q};
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_b = {1'b0, redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_o <= $unsigned(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_a) + $unsigned(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_b);
        end
    end
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_q = redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_o[8:0];

    // redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_inputreg0(DELAY,31111)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_inputreg0_q <= $unsigned(in_c1_eni5_144_tpl);
        end
    end

    // redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr(COUNTER,31114)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_i <= $unsigned(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_q = redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_i[7:0];

    // redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem(DUALMEM,31113)
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_ia = $unsigned(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_inputreg0_q);
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_aa = redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_wraddr_q;
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_ab = redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_aa),
        .data_a(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_ab),
        .q_b(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_q = redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_iq[15:0];

    // redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_outputreg0(DELAY,31112)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_outputreg0_q <= $unsigned(redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_mem_q);
        end
    end

    // valid_fanout_reg114(REG,13409)@209 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg114_q <= $unsigned(redist830_sync_together4364_aunroll_x_in_i_valid_141_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_66161_c_compmm_m115(BLACKBOX,8586)@210
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66161_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_66161_c_compmm_m115 (
        .in_intel_reserved_ffwd_143_0(in_intel_reserved_ffwd_143_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg114_q),
        .out_dest_data_out_143_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_66161_c_compmm_m115_out_dest_data_out_143_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28942)@210 + 5
    // out q@216
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_66161_c_compmm_m115_out_dest_data_out_143_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_66162_c_compmm_m114_out_dest_data_out_144_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266(ADD,9042)@216
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod637_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_b = $unsigned({{5{i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_71_c_compmm_m2265_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_o[33:0];

    // rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x(MUX,20273)@216
    assign rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q or rightShiftStage0Idx1_uid20272_dupName_285_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q;
            1'b1 : rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20272_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x(MUX,20278)@216
    assign rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20277_dupName_285_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20274_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20277_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x(MUX,20283)@216
    assign rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20282_dupName_285_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20279_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20282_dupName_285_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2267_vt_select_20(BITSELECT,11212)@216
    assign i_unnamed_c_compmm_m2267_vt_select_20_b = rightShiftStage2_uid20284_dupName_285_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2267_vt_join(BITJOIN,11211)@216
    assign i_unnamed_c_compmm_m2267_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2267_vt_select_20_b};

    // i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x(BITSELECT,3800)@216
    assign i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x_b = i_unnamed_c_compmm_m2267_vt_join_q[15:0];

    // redist918_i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x_b_1(DELAY,30046)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist918_i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20293_dupName_286_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20292)@216
    assign rightShiftStage1Idx1Rng8_uid20293_dupName_286_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20295_dupName_286_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20294)@216
    assign rightShiftStage1Idx1_uid20295_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20293_dupName_286_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20288_dupName_286_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20287)@216
    assign rightShiftStage0Idx1Rng4_uid20288_dupName_286_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q[33:4];

    // rightShiftStage0Idx1_uid20290_dupName_286_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20289)@216
    assign rightShiftStage0Idx1_uid20290_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20288_dupName_286_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x(MUX,20291)@216
    assign rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q or rightShiftStage0Idx1_uid20290_dupName_286_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_71_i_c_compmm_m2266_q;
            1'b1 : rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20290_dupName_286_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x(MUX,20296)@216
    assign rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20295_dupName_286_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20292_dupName_286_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20295_dupName_286_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2269_vt_select_21(BITSELECT,11215)@216
    assign i_unnamed_c_compmm_m2269_vt_select_21_b = rightShiftStage1_uid20297_dupName_286_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2269_vt_join(BITJOIN,11214)@216
    assign i_unnamed_c_compmm_m2269_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2269_vt_select_21_b};

    // i_unnamed_c_compmm_m2270_sel_x(BITSELECT,6094)@216
    assign i_unnamed_c_compmm_m2270_sel_x_b = i_unnamed_c_compmm_m2269_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2271_BitSelect_for_a(BITSELECT,28540)@216
    assign i_unnamed_c_compmm_m2271_BitSelect_for_a_b = i_unnamed_c_compmm_m2270_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2271_join(BITJOIN,28541)@216
    assign i_unnamed_c_compmm_m2271_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2271_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2271_vt_select_0(BITSELECT,11220)@216
    assign i_unnamed_c_compmm_m2271_vt_select_0_b = i_unnamed_c_compmm_m2271_join_q[0:0];

    // redist164_i_unnamed_c_compmm_m2271_vt_select_0_b_1(DELAY,29292)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist164_i_unnamed_c_compmm_m2271_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2271_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2271_vt_join(BITJOIN,11219)@217
    assign i_unnamed_c_compmm_m2271_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist164_i_unnamed_c_compmm_m2271_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_71_c_compmm_m2272(ADD,7255)@217
    assign i_add_i_i_i_i_i_i_71_c_compmm_m2272_a = {1'b0, i_unnamed_c_compmm_m2271_vt_join_q};
    assign i_add_i_i_i_i_i_i_71_c_compmm_m2272_b = {1'b0, redist918_i_conv_i_i_i_i_i_71_c_compmm_m2268_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_71_c_compmm_m2272_o = $unsigned(i_add_i_i_i_i_i_i_71_c_compmm_m2272_a) + $unsigned(i_add_i_i_i_i_i_i_71_c_compmm_m2272_b);
    assign i_add_i_i_i_i_i_i_71_c_compmm_m2272_q = i_add_i_i_i_i_i_i_71_c_compmm_m2272_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_71_c_compmm_m2272_sel_x(BITSELECT,2269)@217
    assign bgTrunc_i_add_i_i_i_i_i_i_71_c_compmm_m2272_sel_x_b = i_add_i_i_i_i_i_i_71_c_compmm_m2272_q[15:0];

    // i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_sel_x(BITSELECT,3929)@217
    assign i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_71_c_compmm_m2272_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_select_15(BITSELECT,8443)@217
    assign i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_select_15_b = i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_join(BITJOIN,8442)@217
    assign i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_select_15_b};

    // leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(MUX,27790)@217
    assign leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_join_q or leftShiftStage0Idx1_uid27789_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_72_c_compmm_m2292_vt_join_q;
            1'b1 : leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27789_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(MUX,27795)@217
    assign leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s or leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27794_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = leftShiftStage0_uid27791_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27794_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x(MUX,27800)@217
    assign leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s or leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27799_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = leftShiftStage1_uid27796_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27799_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28(BITSELECT,10129)@217
    assign i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28_b = leftShiftStage2_uid27801_i_shl_i_i_i_i_i_i_72_c_compmm_m0_shift_x_q[28:13];

    // redist284_i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28_b_1(DELAY,29412)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist284_i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_join(BITJOIN,10128)@218
    assign i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_join_q = {redist284_i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg111(REG,13406)@211 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg111_q <= $unsigned(redist831_sync_together4364_aunroll_x_in_i_valid_143_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_66164_c_compmm_m112(BLACKBOX,8598)@212
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66164_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_66164_c_compmm_m112 (
        .in_intel_reserved_ffwd_146_0(in_intel_reserved_ffwd_146_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg111_q),
        .out_dest_data_out_146_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_66164_c_compmm_m112_out_dest_data_out_146_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_offset(CONSTANT,31121)
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_offset_q = $unsigned(8'b01110101);

    // redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt(ADD,31122)
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_a = {1'b0, redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_q};
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_b = {1'b0, redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_o <= $unsigned(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_a) + $unsigned(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_b);
        end
    end
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_q = redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_o[8:0];

    // redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_inputreg0(DELAY,31117)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_inputreg0_q <= $unsigned(in_c1_eni5_145_tpl);
        end
    end

    // redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr(COUNTER,31120)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_i <= $unsigned(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_q = redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_i[7:0];

    // redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem(DUALMEM,31119)
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_ia = $unsigned(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_inputreg0_q);
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_aa = redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_wraddr_q;
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_ab = redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_aa),
        .data_a(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_ab),
        .q_b(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_q = redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_iq[15:0];

    // redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_outputreg0(DELAY,31118)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_outputreg0_q <= $unsigned(redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_mem_q);
        end
    end

    // redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt(ADD,31128)
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_a = {1'b0, redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_q};
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_b = {1'b0, redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_o <= $unsigned(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_a) + $unsigned(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_b);
        end
    end
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_q = redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_o[8:0];

    // redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_inputreg0(DELAY,31123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_inputreg0_q <= $unsigned(in_c1_eni5_146_tpl);
        end
    end

    // redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr(COUNTER,31126)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_i <= $unsigned(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_q = redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_i[7:0];

    // redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem(DUALMEM,31125)
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_ia = $unsigned(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_inputreg0_q);
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_aa = redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_wraddr_q;
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_ab = redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_aa),
        .data_a(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_ab),
        .q_b(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_q = redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_iq[15:0];

    // redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_outputreg0(DELAY,31124)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_outputreg0_q <= $unsigned(redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_mem_q);
        end
    end

    // valid_fanout_reg112(REG,13407)@211 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg112_q <= $unsigned(redist831_sync_together4364_aunroll_x_in_i_valid_143_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_66163_c_compmm_m113(BLACKBOX,8594)@212
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66163_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_66163_c_compmm_m113 (
        .in_intel_reserved_ffwd_145_0(in_intel_reserved_ffwd_145_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg112_q),
        .out_dest_data_out_145_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_66163_c_compmm_m113_out_dest_data_out_145_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28943)@212 + 5
    // out q@218
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_66163_c_compmm_m113_out_dest_data_out_145_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_66164_c_compmm_m112_out_dest_data_out_146_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294(ADD,9043)@218
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod642_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_b = $unsigned({{5{i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_72_c_compmm_m2293_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_o[33:0];

    // rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x(MUX,20335)@218
    assign rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q or rightShiftStage0Idx1_uid20334_dupName_289_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q;
            1'b1 : rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20334_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x(MUX,20340)@218
    assign rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20339_dupName_289_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20336_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20339_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x(MUX,20345)@218
    assign rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20344_dupName_289_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20341_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20344_dupName_289_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2295_vt_select_20(BITSELECT,11234)@218
    assign i_unnamed_c_compmm_m2295_vt_select_20_b = rightShiftStage2_uid20346_dupName_289_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2295_vt_join(BITJOIN,11233)@218
    assign i_unnamed_c_compmm_m2295_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2295_vt_select_20_b};

    // i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x(BITSELECT,3801)@218
    assign i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x_b = i_unnamed_c_compmm_m2295_vt_join_q[15:0];

    // redist917_i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x_b_1(DELAY,30045)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist917_i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20355_dupName_290_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20354)@218
    assign rightShiftStage1Idx1Rng8_uid20355_dupName_290_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20357_dupName_290_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20356)@218
    assign rightShiftStage1Idx1_uid20357_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20355_dupName_290_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20350_dupName_290_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20349)@218
    assign rightShiftStage0Idx1Rng4_uid20350_dupName_290_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q[33:4];

    // rightShiftStage0Idx1_uid20352_dupName_290_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20351)@218
    assign rightShiftStage0Idx1_uid20352_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20350_dupName_290_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x(MUX,20353)@218
    assign rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q or rightShiftStage0Idx1_uid20352_dupName_290_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_72_i_c_compmm_m2294_q;
            1'b1 : rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20352_dupName_290_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x(MUX,20358)@218
    assign rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20357_dupName_290_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20354_dupName_290_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20357_dupName_290_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2297_vt_select_21(BITSELECT,11237)@218
    assign i_unnamed_c_compmm_m2297_vt_select_21_b = rightShiftStage1_uid20359_dupName_290_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2297_vt_join(BITJOIN,11236)@218
    assign i_unnamed_c_compmm_m2297_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2297_vt_select_21_b};

    // i_unnamed_c_compmm_m2298_sel_x(BITSELECT,6096)@218
    assign i_unnamed_c_compmm_m2298_sel_x_b = i_unnamed_c_compmm_m2297_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2299_BitSelect_for_a(BITSELECT,28544)@218
    assign i_unnamed_c_compmm_m2299_BitSelect_for_a_b = i_unnamed_c_compmm_m2298_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2299_join(BITJOIN,28545)@218
    assign i_unnamed_c_compmm_m2299_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2299_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2299_vt_select_0(BITSELECT,11242)@218
    assign i_unnamed_c_compmm_m2299_vt_select_0_b = i_unnamed_c_compmm_m2299_join_q[0:0];

    // redist162_i_unnamed_c_compmm_m2299_vt_select_0_b_1(DELAY,29290)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist162_i_unnamed_c_compmm_m2299_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2299_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2299_vt_join(BITJOIN,11241)@219
    assign i_unnamed_c_compmm_m2299_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist162_i_unnamed_c_compmm_m2299_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_72_c_compmm_m2300(ADD,7256)@219
    assign i_add_i_i_i_i_i_i_72_c_compmm_m2300_a = {1'b0, i_unnamed_c_compmm_m2299_vt_join_q};
    assign i_add_i_i_i_i_i_i_72_c_compmm_m2300_b = {1'b0, redist917_i_conv_i_i_i_i_i_72_c_compmm_m2296_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_72_c_compmm_m2300_o = $unsigned(i_add_i_i_i_i_i_i_72_c_compmm_m2300_a) + $unsigned(i_add_i_i_i_i_i_i_72_c_compmm_m2300_b);
    assign i_add_i_i_i_i_i_i_72_c_compmm_m2300_q = i_add_i_i_i_i_i_i_72_c_compmm_m2300_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_72_c_compmm_m2300_sel_x(BITSELECT,2270)@219
    assign bgTrunc_i_add_i_i_i_i_i_i_72_c_compmm_m2300_sel_x_b = i_add_i_i_i_i_i_i_72_c_compmm_m2300_q[15:0];

    // i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_sel_x(BITSELECT,3930)@219
    assign i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_72_c_compmm_m2300_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_select_15(BITSELECT,8447)@219
    assign i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_select_15_b = i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_join(BITJOIN,8446)@219
    assign i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_select_15_b};

    // leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(MUX,27808)@219
    assign leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_join_q or leftShiftStage0Idx1_uid27807_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_73_c_compmm_m2320_vt_join_q;
            1'b1 : leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27807_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(MUX,27813)@219
    assign leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s or leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27812_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = leftShiftStage0_uid27809_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27812_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x(MUX,27818)@219
    assign leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s or leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27817_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = leftShiftStage1_uid27814_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27817_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28(BITSELECT,10132)@219
    assign i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28_b = leftShiftStage2_uid27819_i_shl_i_i_i_i_i_i_73_c_compmm_m0_shift_x_q[28:13];

    // redist283_i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28_b_1(DELAY,29411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist283_i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_join(BITJOIN,10131)@220
    assign i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_join_q = {redist283_i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg109(REG,13404)@213 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg109_q <= $unsigned(redist832_sync_together4364_aunroll_x_in_i_valid_145_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_66166_c_compmm_m110(BLACKBOX,8606)@214
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66166_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_66166_c_compmm_m110 (
        .in_intel_reserved_ffwd_148_0(in_intel_reserved_ffwd_148_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg109_q),
        .out_dest_data_out_148_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_66166_c_compmm_m110_out_dest_data_out_148_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_offset(CONSTANT,31133)
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_offset_q = $unsigned(8'b01110011);

    // redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt(ADD,31134)
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_a = {1'b0, redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_q};
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_b = {1'b0, redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_o <= $unsigned(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_a) + $unsigned(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_b);
        end
    end
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_q = redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_o[8:0];

    // redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_inputreg0(DELAY,31129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_inputreg0_q <= $unsigned(in_c1_eni5_147_tpl);
        end
    end

    // redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr(COUNTER,31132)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_i <= $unsigned(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_q = redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_i[7:0];

    // redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem(DUALMEM,31131)
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_ia = $unsigned(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_inputreg0_q);
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_aa = redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_wraddr_q;
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_ab = redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_aa),
        .data_a(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_ab),
        .q_b(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_q = redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_iq[15:0];

    // redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_outputreg0(DELAY,31130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_outputreg0_q <= $unsigned(redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_mem_q);
        end
    end

    // redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt(ADD,31140)
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_a = {1'b0, redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_q};
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_b = {1'b0, redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_o <= $unsigned(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_a) + $unsigned(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_b);
        end
    end
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_q = redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_o[8:0];

    // redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_inputreg0(DELAY,31135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_inputreg0_q <= $unsigned(in_c1_eni5_148_tpl);
        end
    end

    // redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr(COUNTER,31138)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_i <= $unsigned(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_q = redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_i[7:0];

    // redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem(DUALMEM,31137)
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_ia = $unsigned(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_inputreg0_q);
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_aa = redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_wraddr_q;
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_ab = redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_aa),
        .data_a(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_ab),
        .q_b(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_q = redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_iq[15:0];

    // redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_outputreg0(DELAY,31136)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_outputreg0_q <= $unsigned(redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_mem_q);
        end
    end

    // valid_fanout_reg110(REG,13405)@213 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg110_q <= $unsigned(redist832_sync_together4364_aunroll_x_in_i_valid_145_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_66165_c_compmm_m111(BLACKBOX,8602)@214
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66165_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_66165_c_compmm_m111 (
        .in_intel_reserved_ffwd_147_0(in_intel_reserved_ffwd_147_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg110_q),
        .out_dest_data_out_147_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_66165_c_compmm_m111_out_dest_data_out_147_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28944)@214 + 5
    // out q@220
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_66165_c_compmm_m111_out_dest_data_out_147_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_66166_c_compmm_m110_out_dest_data_out_148_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322(ADD,9044)@220
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod647_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_b = $unsigned({{5{i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_73_c_compmm_m2321_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_o[33:0];

    // rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x(MUX,20397)@220
    assign rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q or rightShiftStage0Idx1_uid20396_dupName_293_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q;
            1'b1 : rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20396_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x(MUX,20402)@220
    assign rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20401_dupName_293_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20398_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20401_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x(MUX,20407)@220
    assign rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20406_dupName_293_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20403_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20406_dupName_293_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2323_vt_select_20(BITSELECT,11256)@220
    assign i_unnamed_c_compmm_m2323_vt_select_20_b = rightShiftStage2_uid20408_dupName_293_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2323_vt_join(BITJOIN,11255)@220
    assign i_unnamed_c_compmm_m2323_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2323_vt_select_20_b};

    // i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x(BITSELECT,3802)@220
    assign i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x_b = i_unnamed_c_compmm_m2323_vt_join_q[15:0];

    // redist916_i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x_b_1(DELAY,30044)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist916_i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20417_dupName_294_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20416)@220
    assign rightShiftStage1Idx1Rng8_uid20417_dupName_294_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20419_dupName_294_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20418)@220
    assign rightShiftStage1Idx1_uid20419_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20417_dupName_294_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20412_dupName_294_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20411)@220
    assign rightShiftStage0Idx1Rng4_uid20412_dupName_294_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q[33:4];

    // rightShiftStage0Idx1_uid20414_dupName_294_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20413)@220
    assign rightShiftStage0Idx1_uid20414_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20412_dupName_294_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x(MUX,20415)@220
    assign rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q or rightShiftStage0Idx1_uid20414_dupName_294_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_73_i_c_compmm_m2322_q;
            1'b1 : rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20414_dupName_294_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x(MUX,20420)@220
    assign rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20419_dupName_294_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20416_dupName_294_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20419_dupName_294_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2325_vt_select_21(BITSELECT,11259)@220
    assign i_unnamed_c_compmm_m2325_vt_select_21_b = rightShiftStage1_uid20421_dupName_294_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2325_vt_join(BITJOIN,11258)@220
    assign i_unnamed_c_compmm_m2325_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2325_vt_select_21_b};

    // i_unnamed_c_compmm_m2326_sel_x(BITSELECT,6098)@220
    assign i_unnamed_c_compmm_m2326_sel_x_b = i_unnamed_c_compmm_m2325_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2327_BitSelect_for_a(BITSELECT,28548)@220
    assign i_unnamed_c_compmm_m2327_BitSelect_for_a_b = i_unnamed_c_compmm_m2326_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2327_join(BITJOIN,28549)@220
    assign i_unnamed_c_compmm_m2327_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2327_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2327_vt_select_0(BITSELECT,11264)@220
    assign i_unnamed_c_compmm_m2327_vt_select_0_b = i_unnamed_c_compmm_m2327_join_q[0:0];

    // redist160_i_unnamed_c_compmm_m2327_vt_select_0_b_1(DELAY,29288)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist160_i_unnamed_c_compmm_m2327_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2327_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2327_vt_join(BITJOIN,11263)@221
    assign i_unnamed_c_compmm_m2327_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist160_i_unnamed_c_compmm_m2327_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_73_c_compmm_m2328(ADD,7257)@221
    assign i_add_i_i_i_i_i_i_73_c_compmm_m2328_a = {1'b0, i_unnamed_c_compmm_m2327_vt_join_q};
    assign i_add_i_i_i_i_i_i_73_c_compmm_m2328_b = {1'b0, redist916_i_conv_i_i_i_i_i_73_c_compmm_m2324_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_73_c_compmm_m2328_o = $unsigned(i_add_i_i_i_i_i_i_73_c_compmm_m2328_a) + $unsigned(i_add_i_i_i_i_i_i_73_c_compmm_m2328_b);
    assign i_add_i_i_i_i_i_i_73_c_compmm_m2328_q = i_add_i_i_i_i_i_i_73_c_compmm_m2328_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_73_c_compmm_m2328_sel_x(BITSELECT,2271)@221
    assign bgTrunc_i_add_i_i_i_i_i_i_73_c_compmm_m2328_sel_x_b = i_add_i_i_i_i_i_i_73_c_compmm_m2328_q[15:0];

    // i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_sel_x(BITSELECT,3931)@221
    assign i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_73_c_compmm_m2328_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_select_15(BITSELECT,8451)@221
    assign i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_select_15_b = i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_join(BITJOIN,8450)@221
    assign i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_select_15_b};

    // leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(MUX,27826)@221
    assign leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_join_q or leftShiftStage0Idx1_uid27825_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_74_c_compmm_m2348_vt_join_q;
            1'b1 : leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27825_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(MUX,27831)@221
    assign leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s or leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27830_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = leftShiftStage0_uid27827_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27830_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x(MUX,27836)@221
    assign leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s or leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27835_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = leftShiftStage1_uid27832_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27835_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28(BITSELECT,10135)@221
    assign i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28_b = leftShiftStage2_uid27837_i_shl_i_i_i_i_i_i_74_c_compmm_m0_shift_x_q[28:13];

    // redist282_i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28_b_1(DELAY,29410)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist282_i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_join(BITJOIN,10134)@222
    assign i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_join_q = {redist282_i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg107(REG,13402)@215 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg107_q <= $unsigned(redist833_sync_together4364_aunroll_x_in_i_valid_147_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_66168_c_compmm_m108(BLACKBOX,8618)@216
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66168_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_66168_c_compmm_m108 (
        .in_intel_reserved_ffwd_150_0(in_intel_reserved_ffwd_150_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg107_q),
        .out_dest_data_out_150_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_66168_c_compmm_m108_out_dest_data_out_150_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_offset(CONSTANT,31145)
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_offset_q = $unsigned(8'b01110001);

    // redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt(ADD,31146)
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_a = {1'b0, redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_q};
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_b = {1'b0, redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_o <= $unsigned(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_a) + $unsigned(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_b);
        end
    end
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_q = redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_o[8:0];

    // redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_inputreg0(DELAY,31141)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_inputreg0_q <= $unsigned(in_c1_eni5_149_tpl);
        end
    end

    // redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr(COUNTER,31144)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_i <= $unsigned(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_q = redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_i[7:0];

    // redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem(DUALMEM,31143)
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_ia = $unsigned(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_inputreg0_q);
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_aa = redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_wraddr_q;
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_ab = redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_aa),
        .data_a(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_ab),
        .q_b(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_q = redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_iq[15:0];

    // redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_outputreg0(DELAY,31142)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_outputreg0_q <= $unsigned(redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_mem_q);
        end
    end

    // redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt(ADD,31152)
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_a = {1'b0, redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_q};
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_b = {1'b0, redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_o <= $unsigned(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_a) + $unsigned(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_b);
        end
    end
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_q = redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_o[8:0];

    // redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_inputreg0(DELAY,31147)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_inputreg0_q <= $unsigned(in_c1_eni5_150_tpl);
        end
    end

    // redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr(COUNTER,31150)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_i <= $unsigned(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_q = redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_i[7:0];

    // redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem(DUALMEM,31149)
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_ia = $unsigned(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_inputreg0_q);
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_aa = redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_wraddr_q;
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_ab = redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_aa),
        .data_a(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_ab),
        .q_b(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_q = redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_iq[15:0];

    // redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_outputreg0(DELAY,31148)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_outputreg0_q <= $unsigned(redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_mem_q);
        end
    end

    // valid_fanout_reg108(REG,13403)@215 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg108_q <= $unsigned(redist833_sync_together4364_aunroll_x_in_i_valid_147_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_66167_c_compmm_m109(BLACKBOX,8614)@216
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66167_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_66167_c_compmm_m109 (
        .in_intel_reserved_ffwd_149_0(in_intel_reserved_ffwd_149_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg108_q),
        .out_dest_data_out_149_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_66167_c_compmm_m109_out_dest_data_out_149_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28945)@216 + 5
    // out q@222
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_66167_c_compmm_m109_out_dest_data_out_149_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_66168_c_compmm_m108_out_dest_data_out_150_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350(ADD,9045)@222
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod652_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_b = $unsigned({{5{i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_74_c_compmm_m2349_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_o[33:0];

    // rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x(MUX,20459)@222
    assign rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q or rightShiftStage0Idx1_uid20458_dupName_297_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q;
            1'b1 : rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20458_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x(MUX,20464)@222
    assign rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20463_dupName_297_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20460_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20463_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x(MUX,20469)@222
    assign rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20468_dupName_297_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20465_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20468_dupName_297_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2351_vt_select_20(BITSELECT,11278)@222
    assign i_unnamed_c_compmm_m2351_vt_select_20_b = rightShiftStage2_uid20470_dupName_297_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2351_vt_join(BITJOIN,11277)@222
    assign i_unnamed_c_compmm_m2351_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2351_vt_select_20_b};

    // i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x(BITSELECT,3803)@222
    assign i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x_b = i_unnamed_c_compmm_m2351_vt_join_q[15:0];

    // redist915_i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x_b_1(DELAY,30043)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist915_i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20479_dupName_298_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20478)@222
    assign rightShiftStage1Idx1Rng8_uid20479_dupName_298_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20481_dupName_298_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20480)@222
    assign rightShiftStage1Idx1_uid20481_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20479_dupName_298_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20474_dupName_298_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20473)@222
    assign rightShiftStage0Idx1Rng4_uid20474_dupName_298_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q[33:4];

    // rightShiftStage0Idx1_uid20476_dupName_298_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20475)@222
    assign rightShiftStage0Idx1_uid20476_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20474_dupName_298_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x(MUX,20477)@222
    assign rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q or rightShiftStage0Idx1_uid20476_dupName_298_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_74_i_c_compmm_m2350_q;
            1'b1 : rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20476_dupName_298_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x(MUX,20482)@222
    assign rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20481_dupName_298_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20478_dupName_298_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20481_dupName_298_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2353_vt_select_21(BITSELECT,11281)@222
    assign i_unnamed_c_compmm_m2353_vt_select_21_b = rightShiftStage1_uid20483_dupName_298_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2353_vt_join(BITJOIN,11280)@222
    assign i_unnamed_c_compmm_m2353_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2353_vt_select_21_b};

    // i_unnamed_c_compmm_m2354_sel_x(BITSELECT,6100)@222
    assign i_unnamed_c_compmm_m2354_sel_x_b = i_unnamed_c_compmm_m2353_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2355_BitSelect_for_a(BITSELECT,28552)@222
    assign i_unnamed_c_compmm_m2355_BitSelect_for_a_b = i_unnamed_c_compmm_m2354_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2355_join(BITJOIN,28553)@222
    assign i_unnamed_c_compmm_m2355_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2355_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2355_vt_select_0(BITSELECT,11286)@222
    assign i_unnamed_c_compmm_m2355_vt_select_0_b = i_unnamed_c_compmm_m2355_join_q[0:0];

    // redist158_i_unnamed_c_compmm_m2355_vt_select_0_b_1(DELAY,29286)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist158_i_unnamed_c_compmm_m2355_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2355_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2355_vt_join(BITJOIN,11285)@223
    assign i_unnamed_c_compmm_m2355_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist158_i_unnamed_c_compmm_m2355_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_74_c_compmm_m2356(ADD,7258)@223
    assign i_add_i_i_i_i_i_i_74_c_compmm_m2356_a = {1'b0, i_unnamed_c_compmm_m2355_vt_join_q};
    assign i_add_i_i_i_i_i_i_74_c_compmm_m2356_b = {1'b0, redist915_i_conv_i_i_i_i_i_74_c_compmm_m2352_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_74_c_compmm_m2356_o = $unsigned(i_add_i_i_i_i_i_i_74_c_compmm_m2356_a) + $unsigned(i_add_i_i_i_i_i_i_74_c_compmm_m2356_b);
    assign i_add_i_i_i_i_i_i_74_c_compmm_m2356_q = i_add_i_i_i_i_i_i_74_c_compmm_m2356_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_74_c_compmm_m2356_sel_x(BITSELECT,2272)@223
    assign bgTrunc_i_add_i_i_i_i_i_i_74_c_compmm_m2356_sel_x_b = i_add_i_i_i_i_i_i_74_c_compmm_m2356_q[15:0];

    // i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_sel_x(BITSELECT,3932)@223
    assign i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_74_c_compmm_m2356_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_select_15(BITSELECT,8455)@223
    assign i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_select_15_b = i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_join(BITJOIN,8454)@223
    assign i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_select_15_b};

    // leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(MUX,27844)@223
    assign leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_join_q or leftShiftStage0Idx1_uid27843_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_75_c_compmm_m2376_vt_join_q;
            1'b1 : leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27843_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(MUX,27849)@223
    assign leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s or leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27848_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = leftShiftStage0_uid27845_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27848_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x(MUX,27854)@223
    assign leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s or leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27853_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = leftShiftStage1_uid27850_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27853_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28(BITSELECT,10138)@223
    assign i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28_b = leftShiftStage2_uid27855_i_shl_i_i_i_i_i_i_75_c_compmm_m0_shift_x_q[28:13];

    // redist281_i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28_b_1(DELAY,29409)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist281_i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_join(BITJOIN,10137)@224
    assign i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_join_q = {redist281_i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg105(REG,13400)@217 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg105_q <= $unsigned(redist834_sync_together4364_aunroll_x_in_i_valid_149_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_66170_c_compmm_m106(BLACKBOX,8626)@218
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66170_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_66170_c_compmm_m106 (
        .in_intel_reserved_ffwd_152_0(in_intel_reserved_ffwd_152_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg105_q),
        .out_dest_data_out_152_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_66170_c_compmm_m106_out_dest_data_out_152_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_offset(CONSTANT,31157)
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_offset_q = $unsigned(8'b01101111);

    // redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt(ADD,31158)
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_a = {1'b0, redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_q};
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_b = {1'b0, redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_o <= $unsigned(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_a) + $unsigned(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_b);
        end
    end
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_q = redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_o[8:0];

    // redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_inputreg0(DELAY,31153)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_inputreg0_q <= $unsigned(in_c1_eni5_151_tpl);
        end
    end

    // redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr(COUNTER,31156)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_i <= $unsigned(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_q = redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_i[7:0];

    // redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem(DUALMEM,31155)
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_ia = $unsigned(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_inputreg0_q);
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_aa = redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_wraddr_q;
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_ab = redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_aa),
        .data_a(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_ab),
        .q_b(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_q = redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_iq[15:0];

    // redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_outputreg0(DELAY,31154)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_outputreg0_q <= $unsigned(redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_mem_q);
        end
    end

    // redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt(ADD,31164)
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_a = {1'b0, redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_q};
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_b = {1'b0, redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_o <= $unsigned(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_a) + $unsigned(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_b);
        end
    end
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_q = redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_o[8:0];

    // redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_inputreg0(DELAY,31159)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_inputreg0_q <= $unsigned(in_c1_eni5_152_tpl);
        end
    end

    // redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr(COUNTER,31162)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_i <= $unsigned(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_q = redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_i[7:0];

    // redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem(DUALMEM,31161)
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_ia = $unsigned(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_inputreg0_q);
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_aa = redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_wraddr_q;
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_ab = redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_aa),
        .data_a(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_ab),
        .q_b(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_q = redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_iq[15:0];

    // redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_outputreg0(DELAY,31160)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_outputreg0_q <= $unsigned(redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_mem_q);
        end
    end

    // valid_fanout_reg106(REG,13401)@217 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg106_q <= $unsigned(redist834_sync_together4364_aunroll_x_in_i_valid_149_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_66169_c_compmm_m107(BLACKBOX,8622)@218
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66169_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_66169_c_compmm_m107 (
        .in_intel_reserved_ffwd_151_0(in_intel_reserved_ffwd_151_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg106_q),
        .out_dest_data_out_151_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_66169_c_compmm_m107_out_dest_data_out_151_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28946)@218 + 5
    // out q@224
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_66169_c_compmm_m107_out_dest_data_out_151_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_66170_c_compmm_m106_out_dest_data_out_152_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378(ADD,9046)@224
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod657_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_b = $unsigned({{5{i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_75_c_compmm_m2377_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_o[33:0];

    // rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x(MUX,20521)@224
    assign rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q or rightShiftStage0Idx1_uid20520_dupName_301_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q;
            1'b1 : rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20520_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x(MUX,20526)@224
    assign rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20525_dupName_301_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20522_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20525_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x(MUX,20531)@224
    assign rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20530_dupName_301_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20527_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20530_dupName_301_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2379_vt_select_20(BITSELECT,11300)@224
    assign i_unnamed_c_compmm_m2379_vt_select_20_b = rightShiftStage2_uid20532_dupName_301_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2379_vt_join(BITJOIN,11299)@224
    assign i_unnamed_c_compmm_m2379_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2379_vt_select_20_b};

    // i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x(BITSELECT,3804)@224
    assign i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x_b = i_unnamed_c_compmm_m2379_vt_join_q[15:0];

    // redist914_i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x_b_1(DELAY,30042)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist914_i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20541_dupName_302_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20540)@224
    assign rightShiftStage1Idx1Rng8_uid20541_dupName_302_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20543_dupName_302_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20542)@224
    assign rightShiftStage1Idx1_uid20543_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20541_dupName_302_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20536_dupName_302_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20535)@224
    assign rightShiftStage0Idx1Rng4_uid20536_dupName_302_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q[33:4];

    // rightShiftStage0Idx1_uid20538_dupName_302_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20537)@224
    assign rightShiftStage0Idx1_uid20538_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20536_dupName_302_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x(MUX,20539)@224
    assign rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q or rightShiftStage0Idx1_uid20538_dupName_302_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_75_i_c_compmm_m2378_q;
            1'b1 : rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20538_dupName_302_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x(MUX,20544)@224
    assign rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20543_dupName_302_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20540_dupName_302_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20543_dupName_302_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2381_vt_select_21(BITSELECT,11303)@224
    assign i_unnamed_c_compmm_m2381_vt_select_21_b = rightShiftStage1_uid20545_dupName_302_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2381_vt_join(BITJOIN,11302)@224
    assign i_unnamed_c_compmm_m2381_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2381_vt_select_21_b};

    // i_unnamed_c_compmm_m2382_sel_x(BITSELECT,6102)@224
    assign i_unnamed_c_compmm_m2382_sel_x_b = i_unnamed_c_compmm_m2381_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2383_BitSelect_for_a(BITSELECT,28556)@224
    assign i_unnamed_c_compmm_m2383_BitSelect_for_a_b = i_unnamed_c_compmm_m2382_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2383_join(BITJOIN,28557)@224
    assign i_unnamed_c_compmm_m2383_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2383_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2383_vt_select_0(BITSELECT,11308)@224
    assign i_unnamed_c_compmm_m2383_vt_select_0_b = i_unnamed_c_compmm_m2383_join_q[0:0];

    // redist156_i_unnamed_c_compmm_m2383_vt_select_0_b_1(DELAY,29284)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist156_i_unnamed_c_compmm_m2383_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2383_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2383_vt_join(BITJOIN,11307)@225
    assign i_unnamed_c_compmm_m2383_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist156_i_unnamed_c_compmm_m2383_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_75_c_compmm_m2384(ADD,7259)@225
    assign i_add_i_i_i_i_i_i_75_c_compmm_m2384_a = {1'b0, i_unnamed_c_compmm_m2383_vt_join_q};
    assign i_add_i_i_i_i_i_i_75_c_compmm_m2384_b = {1'b0, redist914_i_conv_i_i_i_i_i_75_c_compmm_m2380_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_75_c_compmm_m2384_o = $unsigned(i_add_i_i_i_i_i_i_75_c_compmm_m2384_a) + $unsigned(i_add_i_i_i_i_i_i_75_c_compmm_m2384_b);
    assign i_add_i_i_i_i_i_i_75_c_compmm_m2384_q = i_add_i_i_i_i_i_i_75_c_compmm_m2384_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_75_c_compmm_m2384_sel_x(BITSELECT,2273)@225
    assign bgTrunc_i_add_i_i_i_i_i_i_75_c_compmm_m2384_sel_x_b = i_add_i_i_i_i_i_i_75_c_compmm_m2384_q[15:0];

    // i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_sel_x(BITSELECT,3933)@225
    assign i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_75_c_compmm_m2384_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_select_15(BITSELECT,8459)@225
    assign i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_select_15_b = i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_join(BITJOIN,8458)@225
    assign i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_select_15_b};

    // leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(MUX,27862)@225
    assign leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_join_q or leftShiftStage0Idx1_uid27861_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_76_c_compmm_m2404_vt_join_q;
            1'b1 : leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27861_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(MUX,27867)@225
    assign leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s or leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27866_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = leftShiftStage0_uid27863_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27866_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x(MUX,27872)@225
    assign leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s or leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27871_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = leftShiftStage1_uid27868_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27871_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28(BITSELECT,10141)@225
    assign i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28_b = leftShiftStage2_uid27873_i_shl_i_i_i_i_i_i_76_c_compmm_m0_shift_x_q[28:13];

    // redist280_i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28_b_1(DELAY,29408)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist280_i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_join(BITJOIN,10140)@226
    assign i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_join_q = {redist280_i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg103(REG,13398)@219 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg103_q <= $unsigned(redist835_sync_together4364_aunroll_x_in_i_valid_151_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_66172_c_compmm_m104(BLACKBOX,8634)@220
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66172_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_66172_c_compmm_m104 (
        .in_intel_reserved_ffwd_154_0(in_intel_reserved_ffwd_154_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg103_q),
        .out_dest_data_out_154_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_66172_c_compmm_m104_out_dest_data_out_154_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_offset(CONSTANT,31169)
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_offset_q = $unsigned(8'b01101101);

    // redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt(ADD,31170)
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_a = {1'b0, redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_q};
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_b = {1'b0, redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_o <= $unsigned(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_a) + $unsigned(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_b);
        end
    end
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_q = redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_o[8:0];

    // redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_inputreg0(DELAY,31165)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_inputreg0_q <= $unsigned(in_c1_eni5_153_tpl);
        end
    end

    // redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr(COUNTER,31168)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_i <= $unsigned(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_q = redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_i[7:0];

    // redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem(DUALMEM,31167)
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_ia = $unsigned(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_inputreg0_q);
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_aa = redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_wraddr_q;
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_ab = redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_aa),
        .data_a(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_ab),
        .q_b(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_q = redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_iq[15:0];

    // redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_outputreg0(DELAY,31166)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_outputreg0_q <= $unsigned(redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_mem_q);
        end
    end

    // redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt(ADD,31176)
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_a = {1'b0, redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_q};
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_b = {1'b0, redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_o <= $unsigned(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_a) + $unsigned(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_b);
        end
    end
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_q = redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_o[8:0];

    // redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_inputreg0(DELAY,31171)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_inputreg0_q <= $unsigned(in_c1_eni5_154_tpl);
        end
    end

    // redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr(COUNTER,31174)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_i <= $unsigned(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_q = redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_i[7:0];

    // redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem(DUALMEM,31173)
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_ia = $unsigned(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_inputreg0_q);
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_aa = redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_wraddr_q;
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_ab = redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_aa),
        .data_a(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_ab),
        .q_b(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_q = redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_iq[15:0];

    // redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_outputreg0(DELAY,31172)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_outputreg0_q <= $unsigned(redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_mem_q);
        end
    end

    // valid_fanout_reg104(REG,13399)@219 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg104_q <= $unsigned(redist835_sync_together4364_aunroll_x_in_i_valid_151_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_66171_c_compmm_m105(BLACKBOX,8630)@220
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66171_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_66171_c_compmm_m105 (
        .in_intel_reserved_ffwd_153_0(in_intel_reserved_ffwd_153_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg104_q),
        .out_dest_data_out_153_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_66171_c_compmm_m105_out_dest_data_out_153_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28947)@220 + 5
    // out q@226
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_66171_c_compmm_m105_out_dest_data_out_153_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_66172_c_compmm_m104_out_dest_data_out_154_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406(ADD,9047)@226
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod662_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_b = $unsigned({{5{i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_76_c_compmm_m2405_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_o[33:0];

    // rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x(MUX,20583)@226
    assign rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q or rightShiftStage0Idx1_uid20582_dupName_305_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q;
            1'b1 : rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20582_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x(MUX,20588)@226
    assign rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20587_dupName_305_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20584_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20587_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x(MUX,20593)@226
    assign rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20592_dupName_305_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20589_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20592_dupName_305_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2407_vt_select_20(BITSELECT,11322)@226
    assign i_unnamed_c_compmm_m2407_vt_select_20_b = rightShiftStage2_uid20594_dupName_305_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2407_vt_join(BITJOIN,11321)@226
    assign i_unnamed_c_compmm_m2407_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2407_vt_select_20_b};

    // i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x(BITSELECT,3805)@226
    assign i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x_b = i_unnamed_c_compmm_m2407_vt_join_q[15:0];

    // redist913_i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x_b_1(DELAY,30041)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist913_i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20603_dupName_306_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20602)@226
    assign rightShiftStage1Idx1Rng8_uid20603_dupName_306_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20605_dupName_306_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20604)@226
    assign rightShiftStage1Idx1_uid20605_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20603_dupName_306_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20598_dupName_306_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20597)@226
    assign rightShiftStage0Idx1Rng4_uid20598_dupName_306_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q[33:4];

    // rightShiftStage0Idx1_uid20600_dupName_306_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20599)@226
    assign rightShiftStage0Idx1_uid20600_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20598_dupName_306_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x(MUX,20601)@226
    assign rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q or rightShiftStage0Idx1_uid20600_dupName_306_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_76_i_c_compmm_m2406_q;
            1'b1 : rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20600_dupName_306_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x(MUX,20606)@226
    assign rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20605_dupName_306_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20602_dupName_306_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20605_dupName_306_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2409_vt_select_21(BITSELECT,11325)@226
    assign i_unnamed_c_compmm_m2409_vt_select_21_b = rightShiftStage1_uid20607_dupName_306_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2409_vt_join(BITJOIN,11324)@226
    assign i_unnamed_c_compmm_m2409_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2409_vt_select_21_b};

    // i_unnamed_c_compmm_m2410_sel_x(BITSELECT,6104)@226
    assign i_unnamed_c_compmm_m2410_sel_x_b = i_unnamed_c_compmm_m2409_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2411_BitSelect_for_a(BITSELECT,28560)@226
    assign i_unnamed_c_compmm_m2411_BitSelect_for_a_b = i_unnamed_c_compmm_m2410_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2411_join(BITJOIN,28561)@226
    assign i_unnamed_c_compmm_m2411_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2411_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2411_vt_select_0(BITSELECT,11330)@226
    assign i_unnamed_c_compmm_m2411_vt_select_0_b = i_unnamed_c_compmm_m2411_join_q[0:0];

    // redist154_i_unnamed_c_compmm_m2411_vt_select_0_b_1(DELAY,29282)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist154_i_unnamed_c_compmm_m2411_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2411_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2411_vt_join(BITJOIN,11329)@227
    assign i_unnamed_c_compmm_m2411_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist154_i_unnamed_c_compmm_m2411_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_76_c_compmm_m2412(ADD,7260)@227
    assign i_add_i_i_i_i_i_i_76_c_compmm_m2412_a = {1'b0, i_unnamed_c_compmm_m2411_vt_join_q};
    assign i_add_i_i_i_i_i_i_76_c_compmm_m2412_b = {1'b0, redist913_i_conv_i_i_i_i_i_76_c_compmm_m2408_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_76_c_compmm_m2412_o = $unsigned(i_add_i_i_i_i_i_i_76_c_compmm_m2412_a) + $unsigned(i_add_i_i_i_i_i_i_76_c_compmm_m2412_b);
    assign i_add_i_i_i_i_i_i_76_c_compmm_m2412_q = i_add_i_i_i_i_i_i_76_c_compmm_m2412_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_76_c_compmm_m2412_sel_x(BITSELECT,2274)@227
    assign bgTrunc_i_add_i_i_i_i_i_i_76_c_compmm_m2412_sel_x_b = i_add_i_i_i_i_i_i_76_c_compmm_m2412_q[15:0];

    // i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_sel_x(BITSELECT,3934)@227
    assign i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_76_c_compmm_m2412_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_select_15(BITSELECT,8463)@227
    assign i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_select_15_b = i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_join(BITJOIN,8462)@227
    assign i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_select_15_b};

    // leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(MUX,27880)@227
    assign leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_join_q or leftShiftStage0Idx1_uid27879_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_77_c_compmm_m2432_vt_join_q;
            1'b1 : leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27879_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(MUX,27885)@227
    assign leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s or leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27884_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = leftShiftStage0_uid27881_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27884_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x(MUX,27890)@227
    assign leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s or leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27889_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = leftShiftStage1_uid27886_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27889_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28(BITSELECT,10144)@227
    assign i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28_b = leftShiftStage2_uid27891_i_shl_i_i_i_i_i_i_77_c_compmm_m0_shift_x_q[28:13];

    // redist279_i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28_b_1(DELAY,29407)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist279_i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_join(BITJOIN,10143)@228
    assign i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_join_q = {redist279_i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg101(REG,13396)@221 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg101_q <= $unsigned(redist836_sync_together4364_aunroll_x_in_i_valid_153_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_66174_c_compmm_m102(BLACKBOX,8642)@222
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66174_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_66174_c_compmm_m102 (
        .in_intel_reserved_ffwd_156_0(in_intel_reserved_ffwd_156_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg101_q),
        .out_dest_data_out_156_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_66174_c_compmm_m102_out_dest_data_out_156_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_offset(CONSTANT,31181)
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_offset_q = $unsigned(8'b01101011);

    // redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt(ADD,31182)
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_a = {1'b0, redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_q};
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_b = {1'b0, redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_o <= $unsigned(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_a) + $unsigned(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_b);
        end
    end
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_q = redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_o[8:0];

    // redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_inputreg0(DELAY,31177)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_inputreg0_q <= $unsigned(in_c1_eni5_155_tpl);
        end
    end

    // redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr(COUNTER,31180)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_i <= $unsigned(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_q = redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_i[7:0];

    // redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem(DUALMEM,31179)
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_ia = $unsigned(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_inputreg0_q);
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_aa = redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_wraddr_q;
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_ab = redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_aa),
        .data_a(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_ab),
        .q_b(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_q = redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_iq[15:0];

    // redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_outputreg0(DELAY,31178)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_outputreg0_q <= $unsigned(redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_mem_q);
        end
    end

    // redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt(ADD,31188)
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_a = {1'b0, redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_q};
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_b = {1'b0, redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_o <= $unsigned(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_a) + $unsigned(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_b);
        end
    end
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_q = redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_o[8:0];

    // redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_inputreg0(DELAY,31183)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_inputreg0_q <= $unsigned(in_c1_eni5_156_tpl);
        end
    end

    // redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr(COUNTER,31186)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_i <= $unsigned(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_q = redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_i[7:0];

    // redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem(DUALMEM,31185)
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_ia = $unsigned(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_inputreg0_q);
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_aa = redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_wraddr_q;
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_ab = redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_aa),
        .data_a(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_ab),
        .q_b(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_q = redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_iq[15:0];

    // redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_outputreg0(DELAY,31184)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_outputreg0_q <= $unsigned(redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_mem_q);
        end
    end

    // valid_fanout_reg102(REG,13397)@221 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg102_q <= $unsigned(redist836_sync_together4364_aunroll_x_in_i_valid_153_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_66173_c_compmm_m103(BLACKBOX,8638)@222
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66173_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_66173_c_compmm_m103 (
        .in_intel_reserved_ffwd_155_0(in_intel_reserved_ffwd_155_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg102_q),
        .out_dest_data_out_155_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_66173_c_compmm_m103_out_dest_data_out_155_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28948)@222 + 5
    // out q@228
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_66173_c_compmm_m103_out_dest_data_out_155_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_66174_c_compmm_m102_out_dest_data_out_156_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434(ADD,9048)@228
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod667_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_b = $unsigned({{5{i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_77_c_compmm_m2433_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_o[33:0];

    // rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x(MUX,20645)@228
    assign rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q or rightShiftStage0Idx1_uid20644_dupName_309_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q;
            1'b1 : rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20644_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x(MUX,20650)@228
    assign rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20649_dupName_309_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20646_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20649_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x(MUX,20655)@228
    assign rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20654_dupName_309_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20651_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20654_dupName_309_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2435_vt_select_20(BITSELECT,11344)@228
    assign i_unnamed_c_compmm_m2435_vt_select_20_b = rightShiftStage2_uid20656_dupName_309_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2435_vt_join(BITJOIN,11343)@228
    assign i_unnamed_c_compmm_m2435_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2435_vt_select_20_b};

    // i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x(BITSELECT,3806)@228
    assign i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x_b = i_unnamed_c_compmm_m2435_vt_join_q[15:0];

    // redist912_i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x_b_1(DELAY,30040)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist912_i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20665_dupName_310_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20664)@228
    assign rightShiftStage1Idx1Rng8_uid20665_dupName_310_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20667_dupName_310_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20666)@228
    assign rightShiftStage1Idx1_uid20667_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20665_dupName_310_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20660_dupName_310_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20659)@228
    assign rightShiftStage0Idx1Rng4_uid20660_dupName_310_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q[33:4];

    // rightShiftStage0Idx1_uid20662_dupName_310_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20661)@228
    assign rightShiftStage0Idx1_uid20662_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20660_dupName_310_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x(MUX,20663)@228
    assign rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q or rightShiftStage0Idx1_uid20662_dupName_310_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_77_i_c_compmm_m2434_q;
            1'b1 : rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20662_dupName_310_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x(MUX,20668)@228
    assign rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20667_dupName_310_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20664_dupName_310_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20667_dupName_310_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2437_vt_select_21(BITSELECT,11347)@228
    assign i_unnamed_c_compmm_m2437_vt_select_21_b = rightShiftStage1_uid20669_dupName_310_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2437_vt_join(BITJOIN,11346)@228
    assign i_unnamed_c_compmm_m2437_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2437_vt_select_21_b};

    // i_unnamed_c_compmm_m2438_sel_x(BITSELECT,6106)@228
    assign i_unnamed_c_compmm_m2438_sel_x_b = i_unnamed_c_compmm_m2437_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2439_BitSelect_for_a(BITSELECT,28564)@228
    assign i_unnamed_c_compmm_m2439_BitSelect_for_a_b = i_unnamed_c_compmm_m2438_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2439_join(BITJOIN,28565)@228
    assign i_unnamed_c_compmm_m2439_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2439_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2439_vt_select_0(BITSELECT,11352)@228
    assign i_unnamed_c_compmm_m2439_vt_select_0_b = i_unnamed_c_compmm_m2439_join_q[0:0];

    // redist152_i_unnamed_c_compmm_m2439_vt_select_0_b_1(DELAY,29280)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist152_i_unnamed_c_compmm_m2439_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2439_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2439_vt_join(BITJOIN,11351)@229
    assign i_unnamed_c_compmm_m2439_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist152_i_unnamed_c_compmm_m2439_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_77_c_compmm_m2440(ADD,7261)@229
    assign i_add_i_i_i_i_i_i_77_c_compmm_m2440_a = {1'b0, i_unnamed_c_compmm_m2439_vt_join_q};
    assign i_add_i_i_i_i_i_i_77_c_compmm_m2440_b = {1'b0, redist912_i_conv_i_i_i_i_i_77_c_compmm_m2436_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_77_c_compmm_m2440_o = $unsigned(i_add_i_i_i_i_i_i_77_c_compmm_m2440_a) + $unsigned(i_add_i_i_i_i_i_i_77_c_compmm_m2440_b);
    assign i_add_i_i_i_i_i_i_77_c_compmm_m2440_q = i_add_i_i_i_i_i_i_77_c_compmm_m2440_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_77_c_compmm_m2440_sel_x(BITSELECT,2275)@229
    assign bgTrunc_i_add_i_i_i_i_i_i_77_c_compmm_m2440_sel_x_b = i_add_i_i_i_i_i_i_77_c_compmm_m2440_q[15:0];

    // i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_sel_x(BITSELECT,3935)@229
    assign i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_77_c_compmm_m2440_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_select_15(BITSELECT,8467)@229
    assign i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_select_15_b = i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_join(BITJOIN,8466)@229
    assign i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_select_15_b};

    // leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(MUX,27898)@229
    assign leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_join_q or leftShiftStage0Idx1_uid27897_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_78_c_compmm_m2460_vt_join_q;
            1'b1 : leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27897_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(MUX,27903)@229
    assign leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s or leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27902_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = leftShiftStage0_uid27899_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27902_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x(MUX,27908)@229
    assign leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s or leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27907_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = leftShiftStage1_uid27904_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27907_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28(BITSELECT,10147)@229
    assign i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28_b = leftShiftStage2_uid27909_i_shl_i_i_i_i_i_i_78_c_compmm_m0_shift_x_q[28:13];

    // redist278_i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28_b_1(DELAY,29406)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist278_i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_join(BITJOIN,10146)@230
    assign i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_join_q = {redist278_i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg99(REG,13394)@223 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg99_q <= $unsigned(redist837_sync_together4364_aunroll_x_in_i_valid_155_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_66176_c_compmm_m100(BLACKBOX,8650)@224
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66176_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_66176_c_compmm_m100 (
        .in_intel_reserved_ffwd_158_0(in_intel_reserved_ffwd_158_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg99_q),
        .out_dest_data_out_158_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_66176_c_compmm_m100_out_dest_data_out_158_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_offset(CONSTANT,31193)
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_offset_q = $unsigned(8'b01101001);

    // redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt(ADD,31194)
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_a = {1'b0, redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_q};
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_b = {1'b0, redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_o <= $unsigned(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_a) + $unsigned(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_b);
        end
    end
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_q = redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_o[8:0];

    // redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_inputreg0(DELAY,31189)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_inputreg0_q <= $unsigned(in_c1_eni5_157_tpl);
        end
    end

    // redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr(COUNTER,31192)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_i <= $unsigned(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_q = redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_i[7:0];

    // redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem(DUALMEM,31191)
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_ia = $unsigned(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_inputreg0_q);
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_aa = redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_wraddr_q;
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_ab = redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_aa),
        .data_a(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_ab),
        .q_b(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_q = redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_iq[15:0];

    // redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_outputreg0(DELAY,31190)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_outputreg0_q <= $unsigned(redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_mem_q);
        end
    end

    // redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt(ADD,31200)
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_a = {1'b0, redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_q};
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_b = {1'b0, redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_o <= $unsigned(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_a) + $unsigned(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_b);
        end
    end
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_q = redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_o[8:0];

    // redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_inputreg0(DELAY,31195)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_inputreg0_q <= $unsigned(in_c1_eni5_158_tpl);
        end
    end

    // redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr(COUNTER,31198)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_i <= $unsigned(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_q = redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_i[7:0];

    // redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem(DUALMEM,31197)
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_ia = $unsigned(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_inputreg0_q);
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_aa = redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_wraddr_q;
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_ab = redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_aa),
        .data_a(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_ab),
        .q_b(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_q = redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_iq[15:0];

    // redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_outputreg0(DELAY,31196)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_outputreg0_q <= $unsigned(redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_mem_q);
        end
    end

    // valid_fanout_reg100(REG,13395)@223 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg100_q <= $unsigned(redist837_sync_together4364_aunroll_x_in_i_valid_155_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_66175_c_compmm_m101(BLACKBOX,8646)@224
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66175_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_66175_c_compmm_m101 (
        .in_intel_reserved_ffwd_157_0(in_intel_reserved_ffwd_157_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg100_q),
        .out_dest_data_out_157_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_66175_c_compmm_m101_out_dest_data_out_157_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28949)@224 + 5
    // out q@230
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_66175_c_compmm_m101_out_dest_data_out_157_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_66176_c_compmm_m100_out_dest_data_out_158_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462(ADD,9049)@230
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod672_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_b = $unsigned({{5{i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_78_c_compmm_m2461_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_o[33:0];

    // rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x(MUX,20707)@230
    assign rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q or rightShiftStage0Idx1_uid20706_dupName_313_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q;
            1'b1 : rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20706_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x(MUX,20712)@230
    assign rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20711_dupName_313_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20708_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20711_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x(MUX,20717)@230
    assign rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20716_dupName_313_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20713_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20716_dupName_313_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2463_vt_select_20(BITSELECT,11366)@230
    assign i_unnamed_c_compmm_m2463_vt_select_20_b = rightShiftStage2_uid20718_dupName_313_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2463_vt_join(BITJOIN,11365)@230
    assign i_unnamed_c_compmm_m2463_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2463_vt_select_20_b};

    // i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x(BITSELECT,3807)@230
    assign i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x_b = i_unnamed_c_compmm_m2463_vt_join_q[15:0];

    // redist911_i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x_b_1(DELAY,30039)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist911_i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20727_dupName_314_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20726)@230
    assign rightShiftStage1Idx1Rng8_uid20727_dupName_314_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20729_dupName_314_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20728)@230
    assign rightShiftStage1Idx1_uid20729_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20727_dupName_314_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20722_dupName_314_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20721)@230
    assign rightShiftStage0Idx1Rng4_uid20722_dupName_314_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q[33:4];

    // rightShiftStage0Idx1_uid20724_dupName_314_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20723)@230
    assign rightShiftStage0Idx1_uid20724_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20722_dupName_314_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x(MUX,20725)@230
    assign rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q or rightShiftStage0Idx1_uid20724_dupName_314_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_78_i_c_compmm_m2462_q;
            1'b1 : rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20724_dupName_314_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x(MUX,20730)@230
    assign rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20729_dupName_314_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20726_dupName_314_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20729_dupName_314_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2465_vt_select_21(BITSELECT,11369)@230
    assign i_unnamed_c_compmm_m2465_vt_select_21_b = rightShiftStage1_uid20731_dupName_314_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2465_vt_join(BITJOIN,11368)@230
    assign i_unnamed_c_compmm_m2465_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2465_vt_select_21_b};

    // i_unnamed_c_compmm_m2466_sel_x(BITSELECT,6108)@230
    assign i_unnamed_c_compmm_m2466_sel_x_b = i_unnamed_c_compmm_m2465_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2467_BitSelect_for_a(BITSELECT,28568)@230
    assign i_unnamed_c_compmm_m2467_BitSelect_for_a_b = i_unnamed_c_compmm_m2466_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2467_join(BITJOIN,28569)@230
    assign i_unnamed_c_compmm_m2467_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2467_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2467_vt_select_0(BITSELECT,11374)@230
    assign i_unnamed_c_compmm_m2467_vt_select_0_b = i_unnamed_c_compmm_m2467_join_q[0:0];

    // redist150_i_unnamed_c_compmm_m2467_vt_select_0_b_1(DELAY,29278)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist150_i_unnamed_c_compmm_m2467_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2467_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2467_vt_join(BITJOIN,11373)@231
    assign i_unnamed_c_compmm_m2467_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist150_i_unnamed_c_compmm_m2467_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_78_c_compmm_m2468(ADD,7262)@231
    assign i_add_i_i_i_i_i_i_78_c_compmm_m2468_a = {1'b0, i_unnamed_c_compmm_m2467_vt_join_q};
    assign i_add_i_i_i_i_i_i_78_c_compmm_m2468_b = {1'b0, redist911_i_conv_i_i_i_i_i_78_c_compmm_m2464_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_78_c_compmm_m2468_o = $unsigned(i_add_i_i_i_i_i_i_78_c_compmm_m2468_a) + $unsigned(i_add_i_i_i_i_i_i_78_c_compmm_m2468_b);
    assign i_add_i_i_i_i_i_i_78_c_compmm_m2468_q = i_add_i_i_i_i_i_i_78_c_compmm_m2468_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_78_c_compmm_m2468_sel_x(BITSELECT,2276)@231
    assign bgTrunc_i_add_i_i_i_i_i_i_78_c_compmm_m2468_sel_x_b = i_add_i_i_i_i_i_i_78_c_compmm_m2468_q[15:0];

    // i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_sel_x(BITSELECT,3936)@231
    assign i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_78_c_compmm_m2468_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_select_15(BITSELECT,8471)@231
    assign i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_select_15_b = i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_join(BITJOIN,8470)@231
    assign i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_select_15_b};

    // leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(MUX,27916)@231
    assign leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_join_q or leftShiftStage0Idx1_uid27915_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_79_c_compmm_m2488_vt_join_q;
            1'b1 : leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27915_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(MUX,27921)@231
    assign leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s or leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27920_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = leftShiftStage0_uid27917_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27920_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x(MUX,27926)@231
    assign leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s or leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27925_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = leftShiftStage1_uid27922_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27925_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28(BITSELECT,10150)@231
    assign i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28_b = leftShiftStage2_uid27927_i_shl_i_i_i_i_i_i_79_c_compmm_m0_shift_x_q[28:13];

    // redist277_i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28_b_1(DELAY,29405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist277_i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_join(BITJOIN,10149)@232
    assign i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_join_q = {redist277_i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg97(REG,13392)@225 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg97_q <= $unsigned(redist838_sync_together4364_aunroll_x_in_i_valid_157_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_66178_c_compmm_m98(BLACKBOX,8662)@226
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66178_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_66178_c_compmm_m98 (
        .in_intel_reserved_ffwd_160_0(in_intel_reserved_ffwd_160_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg97_q),
        .out_dest_data_out_160_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_66178_c_compmm_m98_out_dest_data_out_160_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_offset(CONSTANT,31205)
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_offset_q = $unsigned(8'b01100111);

    // redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt(ADD,31206)
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_a = {1'b0, redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_q};
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_b = {1'b0, redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_o <= $unsigned(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_a) + $unsigned(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_b);
        end
    end
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_q = redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_o[8:0];

    // redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_inputreg0(DELAY,31201)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_inputreg0_q <= $unsigned(in_c1_eni5_159_tpl);
        end
    end

    // redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr(COUNTER,31204)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_i <= $unsigned(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_q = redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_i[7:0];

    // redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem(DUALMEM,31203)
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_ia = $unsigned(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_inputreg0_q);
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_aa = redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_wraddr_q;
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_ab = redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_aa),
        .data_a(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_ab),
        .q_b(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_q = redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_iq[15:0];

    // redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_outputreg0(DELAY,31202)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_outputreg0_q <= $unsigned(redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_mem_q);
        end
    end

    // redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt(ADD,31212)
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_a = {1'b0, redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_q};
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_b = {1'b0, redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_o <= $unsigned(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_a) + $unsigned(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_b);
        end
    end
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_q = redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_o[8:0];

    // redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_inputreg0(DELAY,31207)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_inputreg0_q <= $unsigned(in_c1_eni5_160_tpl);
        end
    end

    // redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr(COUNTER,31210)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_i <= $unsigned(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_q = redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_i[7:0];

    // redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem(DUALMEM,31209)
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_ia = $unsigned(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_inputreg0_q);
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_aa = redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_wraddr_q;
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_ab = redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_aa),
        .data_a(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_ab),
        .q_b(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_q = redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_iq[15:0];

    // redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_outputreg0(DELAY,31208)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_outputreg0_q <= $unsigned(redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_mem_q);
        end
    end

    // valid_fanout_reg98(REG,13393)@225 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg98_q <= $unsigned(redist838_sync_together4364_aunroll_x_in_i_valid_157_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_66177_c_compmm_m99(BLACKBOX,8658)@226
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66177_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_66177_c_compmm_m99 (
        .in_intel_reserved_ffwd_159_0(in_intel_reserved_ffwd_159_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg98_q),
        .out_dest_data_out_159_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_66177_c_compmm_m99_out_dest_data_out_159_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28950)@226 + 5
    // out q@232
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_66177_c_compmm_m99_out_dest_data_out_159_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_66178_c_compmm_m98_out_dest_data_out_160_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490(ADD,9050)@232
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod677_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_b = $unsigned({{5{i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_79_c_compmm_m2489_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_o[33:0];

    // rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x(MUX,20769)@232
    assign rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q or rightShiftStage0Idx1_uid20768_dupName_317_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q;
            1'b1 : rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20768_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x(MUX,20774)@232
    assign rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20773_dupName_317_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20770_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20773_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x(MUX,20779)@232
    assign rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20778_dupName_317_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20775_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20778_dupName_317_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2491_vt_select_20(BITSELECT,11388)@232
    assign i_unnamed_c_compmm_m2491_vt_select_20_b = rightShiftStage2_uid20780_dupName_317_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2491_vt_join(BITJOIN,11387)@232
    assign i_unnamed_c_compmm_m2491_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2491_vt_select_20_b};

    // i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x(BITSELECT,3808)@232
    assign i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x_b = i_unnamed_c_compmm_m2491_vt_join_q[15:0];

    // redist910_i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x_b_1(DELAY,30038)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist910_i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20789_dupName_318_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20788)@232
    assign rightShiftStage1Idx1Rng8_uid20789_dupName_318_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20791_dupName_318_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20790)@232
    assign rightShiftStage1Idx1_uid20791_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20789_dupName_318_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20784_dupName_318_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20783)@232
    assign rightShiftStage0Idx1Rng4_uid20784_dupName_318_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q[33:4];

    // rightShiftStage0Idx1_uid20786_dupName_318_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20785)@232
    assign rightShiftStage0Idx1_uid20786_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20784_dupName_318_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x(MUX,20787)@232
    assign rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q or rightShiftStage0Idx1_uid20786_dupName_318_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_79_i_c_compmm_m2490_q;
            1'b1 : rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20786_dupName_318_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x(MUX,20792)@232
    assign rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20791_dupName_318_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20788_dupName_318_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20791_dupName_318_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2493_vt_select_21(BITSELECT,11391)@232
    assign i_unnamed_c_compmm_m2493_vt_select_21_b = rightShiftStage1_uid20793_dupName_318_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2493_vt_join(BITJOIN,11390)@232
    assign i_unnamed_c_compmm_m2493_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2493_vt_select_21_b};

    // i_unnamed_c_compmm_m2494_sel_x(BITSELECT,6110)@232
    assign i_unnamed_c_compmm_m2494_sel_x_b = i_unnamed_c_compmm_m2493_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2495_BitSelect_for_a(BITSELECT,28572)@232
    assign i_unnamed_c_compmm_m2495_BitSelect_for_a_b = i_unnamed_c_compmm_m2494_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2495_join(BITJOIN,28573)@232
    assign i_unnamed_c_compmm_m2495_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2495_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2495_vt_select_0(BITSELECT,11396)@232
    assign i_unnamed_c_compmm_m2495_vt_select_0_b = i_unnamed_c_compmm_m2495_join_q[0:0];

    // redist148_i_unnamed_c_compmm_m2495_vt_select_0_b_1(DELAY,29276)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist148_i_unnamed_c_compmm_m2495_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2495_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2495_vt_join(BITJOIN,11395)@233
    assign i_unnamed_c_compmm_m2495_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist148_i_unnamed_c_compmm_m2495_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_79_c_compmm_m2496(ADD,7263)@233
    assign i_add_i_i_i_i_i_i_79_c_compmm_m2496_a = {1'b0, i_unnamed_c_compmm_m2495_vt_join_q};
    assign i_add_i_i_i_i_i_i_79_c_compmm_m2496_b = {1'b0, redist910_i_conv_i_i_i_i_i_79_c_compmm_m2492_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_79_c_compmm_m2496_o = $unsigned(i_add_i_i_i_i_i_i_79_c_compmm_m2496_a) + $unsigned(i_add_i_i_i_i_i_i_79_c_compmm_m2496_b);
    assign i_add_i_i_i_i_i_i_79_c_compmm_m2496_q = i_add_i_i_i_i_i_i_79_c_compmm_m2496_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_79_c_compmm_m2496_sel_x(BITSELECT,2277)@233
    assign bgTrunc_i_add_i_i_i_i_i_i_79_c_compmm_m2496_sel_x_b = i_add_i_i_i_i_i_i_79_c_compmm_m2496_q[15:0];

    // i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_sel_x(BITSELECT,3938)@233
    assign i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_79_c_compmm_m2496_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_select_15(BITSELECT,8479)@233
    assign i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_select_15_b = i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_join(BITJOIN,8478)@233
    assign i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_select_15_b};

    // leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(MUX,27952)@233
    assign leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_join_q or leftShiftStage0Idx1_uid27951_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_80_c_compmm_m2516_vt_join_q;
            1'b1 : leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27951_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(MUX,27957)@233
    assign leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s or leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27956_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = leftShiftStage0_uid27953_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27956_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x(MUX,27962)@233
    assign leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s or leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27961_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = leftShiftStage1_uid27958_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27961_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28(BITSELECT,10156)@233
    assign i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28_b = leftShiftStage2_uid27963_i_shl_i_i_i_i_i_i_80_c_compmm_m0_shift_x_q[28:13];

    // redist275_i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28_b_1(DELAY,29403)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist275_i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_join(BITJOIN,10155)@234
    assign i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_join_q = {redist275_i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg95(REG,13390)@227 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg95_q <= $unsigned(redist839_sync_together4364_aunroll_x_in_i_valid_159_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_66180_c_compmm_m96(BLACKBOX,8670)@228
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66180_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_66180_c_compmm_m96 (
        .in_intel_reserved_ffwd_162_0(in_intel_reserved_ffwd_162_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg95_q),
        .out_dest_data_out_162_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_66180_c_compmm_m96_out_dest_data_out_162_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_offset(CONSTANT,31217)
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_offset_q = $unsigned(8'b01100101);

    // redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt(ADD,31218)
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_a = {1'b0, redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_q};
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_b = {1'b0, redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_o <= $unsigned(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_a) + $unsigned(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_b);
        end
    end
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_q = redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_o[8:0];

    // redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_inputreg0(DELAY,31213)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_inputreg0_q <= $unsigned(in_c1_eni5_161_tpl);
        end
    end

    // redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr(COUNTER,31216)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_i <= $unsigned(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_q = redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_i[7:0];

    // redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem(DUALMEM,31215)
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_ia = $unsigned(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_inputreg0_q);
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_aa = redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_wraddr_q;
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_ab = redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_aa),
        .data_a(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_ab),
        .q_b(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_q = redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_iq[15:0];

    // redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_outputreg0(DELAY,31214)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_outputreg0_q <= $unsigned(redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_mem_q);
        end
    end

    // redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt(ADD,31224)
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_a = {1'b0, redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_q};
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_b = {1'b0, redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_o <= $unsigned(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_a) + $unsigned(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_b);
        end
    end
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_q = redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_o[8:0];

    // redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_inputreg0(DELAY,31219)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_inputreg0_q <= $unsigned(in_c1_eni5_162_tpl);
        end
    end

    // redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr(COUNTER,31222)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_i <= $unsigned(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_q = redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_i[7:0];

    // redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem(DUALMEM,31221)
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_ia = $unsigned(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_inputreg0_q);
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_aa = redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_wraddr_q;
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_ab = redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_aa),
        .data_a(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_ab),
        .q_b(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_q = redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_iq[15:0];

    // redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_outputreg0(DELAY,31220)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_outputreg0_q <= $unsigned(redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_mem_q);
        end
    end

    // valid_fanout_reg96(REG,13391)@227 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg96_q <= $unsigned(redist839_sync_together4364_aunroll_x_in_i_valid_159_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_66179_c_compmm_m97(BLACKBOX,8666)@228
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66179_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_66179_c_compmm_m97 (
        .in_intel_reserved_ffwd_161_0(in_intel_reserved_ffwd_161_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg96_q),
        .out_dest_data_out_161_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_66179_c_compmm_m97_out_dest_data_out_161_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28951)@228 + 5
    // out q@234
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_66179_c_compmm_m97_out_dest_data_out_161_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_66180_c_compmm_m96_out_dest_data_out_162_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518(ADD,9052)@234
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod682_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_b = $unsigned({{5{i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_80_c_compmm_m2517_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_o[33:0];

    // rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x(MUX,20831)@234
    assign rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q or rightShiftStage0Idx1_uid20830_dupName_321_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q;
            1'b1 : rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20830_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x(MUX,20836)@234
    assign rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20835_dupName_321_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20832_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20835_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x(MUX,20841)@234
    assign rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20840_dupName_321_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20837_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20840_dupName_321_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2519_vt_select_20(BITSELECT,11410)@234
    assign i_unnamed_c_compmm_m2519_vt_select_20_b = rightShiftStage2_uid20842_dupName_321_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2519_vt_join(BITJOIN,11409)@234
    assign i_unnamed_c_compmm_m2519_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2519_vt_select_20_b};

    // i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x(BITSELECT,3810)@234
    assign i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x_b = i_unnamed_c_compmm_m2519_vt_join_q[15:0];

    // redist908_i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x_b_1(DELAY,30036)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist908_i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20851_dupName_322_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20850)@234
    assign rightShiftStage1Idx1Rng8_uid20851_dupName_322_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20853_dupName_322_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20852)@234
    assign rightShiftStage1Idx1_uid20853_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20851_dupName_322_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20846_dupName_322_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20845)@234
    assign rightShiftStage0Idx1Rng4_uid20846_dupName_322_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q[33:4];

    // rightShiftStage0Idx1_uid20848_dupName_322_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20847)@234
    assign rightShiftStage0Idx1_uid20848_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20846_dupName_322_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x(MUX,20849)@234
    assign rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q or rightShiftStage0Idx1_uid20848_dupName_322_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_80_i_c_compmm_m2518_q;
            1'b1 : rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20848_dupName_322_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x(MUX,20854)@234
    assign rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20853_dupName_322_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20850_dupName_322_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20853_dupName_322_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2521_vt_select_21(BITSELECT,11413)@234
    assign i_unnamed_c_compmm_m2521_vt_select_21_b = rightShiftStage1_uid20855_dupName_322_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2521_vt_join(BITJOIN,11412)@234
    assign i_unnamed_c_compmm_m2521_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2521_vt_select_21_b};

    // i_unnamed_c_compmm_m2522_sel_x(BITSELECT,6112)@234
    assign i_unnamed_c_compmm_m2522_sel_x_b = i_unnamed_c_compmm_m2521_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2523_BitSelect_for_a(BITSELECT,28576)@234
    assign i_unnamed_c_compmm_m2523_BitSelect_for_a_b = i_unnamed_c_compmm_m2522_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2523_join(BITJOIN,28577)@234
    assign i_unnamed_c_compmm_m2523_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2523_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2523_vt_select_0(BITSELECT,11418)@234
    assign i_unnamed_c_compmm_m2523_vt_select_0_b = i_unnamed_c_compmm_m2523_join_q[0:0];

    // redist146_i_unnamed_c_compmm_m2523_vt_select_0_b_1(DELAY,29274)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist146_i_unnamed_c_compmm_m2523_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2523_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2523_vt_join(BITJOIN,11417)@235
    assign i_unnamed_c_compmm_m2523_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist146_i_unnamed_c_compmm_m2523_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_80_c_compmm_m2524(ADD,7265)@235
    assign i_add_i_i_i_i_i_i_80_c_compmm_m2524_a = {1'b0, i_unnamed_c_compmm_m2523_vt_join_q};
    assign i_add_i_i_i_i_i_i_80_c_compmm_m2524_b = {1'b0, redist908_i_conv_i_i_i_i_i_80_c_compmm_m2520_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_80_c_compmm_m2524_o = $unsigned(i_add_i_i_i_i_i_i_80_c_compmm_m2524_a) + $unsigned(i_add_i_i_i_i_i_i_80_c_compmm_m2524_b);
    assign i_add_i_i_i_i_i_i_80_c_compmm_m2524_q = i_add_i_i_i_i_i_i_80_c_compmm_m2524_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_80_c_compmm_m2524_sel_x(BITSELECT,2279)@235
    assign bgTrunc_i_add_i_i_i_i_i_i_80_c_compmm_m2524_sel_x_b = i_add_i_i_i_i_i_i_80_c_compmm_m2524_q[15:0];

    // i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_sel_x(BITSELECT,3939)@235
    assign i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_80_c_compmm_m2524_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_select_15(BITSELECT,8483)@235
    assign i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_select_15_b = i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_join(BITJOIN,8482)@235
    assign i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_select_15_b};

    // leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(MUX,27970)@235
    assign leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_join_q or leftShiftStage0Idx1_uid27969_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_81_c_compmm_m2544_vt_join_q;
            1'b1 : leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27969_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(MUX,27975)@235
    assign leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s or leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27974_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = leftShiftStage0_uid27971_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27974_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x(MUX,27980)@235
    assign leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s or leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27979_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = leftShiftStage1_uid27976_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27979_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28(BITSELECT,10159)@235
    assign i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28_b = leftShiftStage2_uid27981_i_shl_i_i_i_i_i_i_81_c_compmm_m0_shift_x_q[28:13];

    // redist274_i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28_b_1(DELAY,29402)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist274_i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_join(BITJOIN,10158)@236
    assign i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_join_q = {redist274_i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg93(REG,13388)@229 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg93_q <= $unsigned(redist840_sync_together4364_aunroll_x_in_i_valid_161_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_66182_c_compmm_m94(BLACKBOX,8678)@230
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66182_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_66182_c_compmm_m94 (
        .in_intel_reserved_ffwd_164_0(in_intel_reserved_ffwd_164_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg93_q),
        .out_dest_data_out_164_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_66182_c_compmm_m94_out_dest_data_out_164_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_offset(CONSTANT,31229)
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_offset_q = $unsigned(8'b01100011);

    // redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt(ADD,31230)
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_a = {1'b0, redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_q};
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_b = {1'b0, redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_o <= $unsigned(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_a) + $unsigned(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_b);
        end
    end
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_q = redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_o[8:0];

    // redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_inputreg0(DELAY,31225)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_inputreg0_q <= $unsigned(in_c1_eni5_163_tpl);
        end
    end

    // redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr(COUNTER,31228)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_i <= $unsigned(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_q = redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_i[7:0];

    // redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem(DUALMEM,31227)
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_ia = $unsigned(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_inputreg0_q);
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_aa = redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_wraddr_q;
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_ab = redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_aa),
        .data_a(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_ab),
        .q_b(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_q = redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_iq[15:0];

    // redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_outputreg0(DELAY,31226)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_outputreg0_q <= $unsigned(redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_mem_q);
        end
    end

    // redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt(ADD,31236)
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_a = {1'b0, redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_q};
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_b = {1'b0, redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_o <= $unsigned(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_a) + $unsigned(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_b);
        end
    end
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_q = redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_o[8:0];

    // redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_inputreg0(DELAY,31231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_inputreg0_q <= $unsigned(in_c1_eni5_164_tpl);
        end
    end

    // redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr(COUNTER,31234)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_i <= $unsigned(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_q = redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_i[7:0];

    // redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem(DUALMEM,31233)
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_ia = $unsigned(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_inputreg0_q);
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_aa = redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_wraddr_q;
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_ab = redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_aa),
        .data_a(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_ab),
        .q_b(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_q = redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_iq[15:0];

    // redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_outputreg0(DELAY,31232)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_outputreg0_q <= $unsigned(redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_mem_q);
        end
    end

    // valid_fanout_reg94(REG,13389)@229 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg94_q <= $unsigned(redist840_sync_together4364_aunroll_x_in_i_valid_161_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_66181_c_compmm_m95(BLACKBOX,8674)@230
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66181_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_66181_c_compmm_m95 (
        .in_intel_reserved_ffwd_163_0(in_intel_reserved_ffwd_163_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg94_q),
        .out_dest_data_out_163_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_66181_c_compmm_m95_out_dest_data_out_163_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28952)@230 + 5
    // out q@236
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_66181_c_compmm_m95_out_dest_data_out_163_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_66182_c_compmm_m94_out_dest_data_out_164_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546(ADD,9053)@236
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod687_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_b = $unsigned({{5{i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_81_c_compmm_m2545_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_o[33:0];

    // rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x(MUX,20893)@236
    assign rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q or rightShiftStage0Idx1_uid20892_dupName_325_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q;
            1'b1 : rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20892_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x(MUX,20898)@236
    assign rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20897_dupName_325_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20894_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20897_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x(MUX,20903)@236
    assign rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20902_dupName_325_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20899_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20902_dupName_325_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2547_vt_select_20(BITSELECT,11432)@236
    assign i_unnamed_c_compmm_m2547_vt_select_20_b = rightShiftStage2_uid20904_dupName_325_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2547_vt_join(BITJOIN,11431)@236
    assign i_unnamed_c_compmm_m2547_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2547_vt_select_20_b};

    // i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x(BITSELECT,3811)@236
    assign i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x_b = i_unnamed_c_compmm_m2547_vt_join_q[15:0];

    // redist907_i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x_b_1(DELAY,30035)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist907_i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20913_dupName_326_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20912)@236
    assign rightShiftStage1Idx1Rng8_uid20913_dupName_326_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20915_dupName_326_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20914)@236
    assign rightShiftStage1Idx1_uid20915_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20913_dupName_326_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20908_dupName_326_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20907)@236
    assign rightShiftStage0Idx1Rng4_uid20908_dupName_326_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q[33:4];

    // rightShiftStage0Idx1_uid20910_dupName_326_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20909)@236
    assign rightShiftStage0Idx1_uid20910_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20908_dupName_326_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x(MUX,20911)@236
    assign rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q or rightShiftStage0Idx1_uid20910_dupName_326_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_81_i_c_compmm_m2546_q;
            1'b1 : rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20910_dupName_326_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x(MUX,20916)@236
    assign rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20915_dupName_326_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20912_dupName_326_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20915_dupName_326_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2549_vt_select_21(BITSELECT,11435)@236
    assign i_unnamed_c_compmm_m2549_vt_select_21_b = rightShiftStage1_uid20917_dupName_326_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2549_vt_join(BITJOIN,11434)@236
    assign i_unnamed_c_compmm_m2549_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2549_vt_select_21_b};

    // i_unnamed_c_compmm_m2550_sel_x(BITSELECT,6114)@236
    assign i_unnamed_c_compmm_m2550_sel_x_b = i_unnamed_c_compmm_m2549_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2551_BitSelect_for_a(BITSELECT,28580)@236
    assign i_unnamed_c_compmm_m2551_BitSelect_for_a_b = i_unnamed_c_compmm_m2550_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2551_join(BITJOIN,28581)@236
    assign i_unnamed_c_compmm_m2551_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2551_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2551_vt_select_0(BITSELECT,11440)@236
    assign i_unnamed_c_compmm_m2551_vt_select_0_b = i_unnamed_c_compmm_m2551_join_q[0:0];

    // redist144_i_unnamed_c_compmm_m2551_vt_select_0_b_1(DELAY,29272)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist144_i_unnamed_c_compmm_m2551_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2551_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2551_vt_join(BITJOIN,11439)@237
    assign i_unnamed_c_compmm_m2551_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist144_i_unnamed_c_compmm_m2551_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_81_c_compmm_m2552(ADD,7266)@237
    assign i_add_i_i_i_i_i_i_81_c_compmm_m2552_a = {1'b0, i_unnamed_c_compmm_m2551_vt_join_q};
    assign i_add_i_i_i_i_i_i_81_c_compmm_m2552_b = {1'b0, redist907_i_conv_i_i_i_i_i_81_c_compmm_m2548_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_81_c_compmm_m2552_o = $unsigned(i_add_i_i_i_i_i_i_81_c_compmm_m2552_a) + $unsigned(i_add_i_i_i_i_i_i_81_c_compmm_m2552_b);
    assign i_add_i_i_i_i_i_i_81_c_compmm_m2552_q = i_add_i_i_i_i_i_i_81_c_compmm_m2552_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_81_c_compmm_m2552_sel_x(BITSELECT,2280)@237
    assign bgTrunc_i_add_i_i_i_i_i_i_81_c_compmm_m2552_sel_x_b = i_add_i_i_i_i_i_i_81_c_compmm_m2552_q[15:0];

    // i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_sel_x(BITSELECT,3940)@237
    assign i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_81_c_compmm_m2552_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_select_15(BITSELECT,8487)@237
    assign i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_select_15_b = i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_join(BITJOIN,8486)@237
    assign i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_select_15_b};

    // leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(MUX,27988)@237
    assign leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_join_q or leftShiftStage0Idx1_uid27987_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_82_c_compmm_m2572_vt_join_q;
            1'b1 : leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid27987_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(MUX,27993)@237
    assign leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s or leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid27992_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = leftShiftStage0_uid27989_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid27992_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x(MUX,27998)@237
    assign leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s or leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid27997_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = leftShiftStage1_uid27994_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid27997_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28(BITSELECT,10162)@237
    assign i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28_b = leftShiftStage2_uid27999_i_shl_i_i_i_i_i_i_82_c_compmm_m0_shift_x_q[28:13];

    // redist273_i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28_b_1(DELAY,29401)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist273_i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_join(BITJOIN,10161)@238
    assign i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_join_q = {redist273_i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg91(REG,13386)@231 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg91_q <= $unsigned(redist841_sync_together4364_aunroll_x_in_i_valid_163_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_66184_c_compmm_m92(BLACKBOX,8686)@232
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66184_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_66184_c_compmm_m92 (
        .in_intel_reserved_ffwd_166_0(in_intel_reserved_ffwd_166_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg91_q),
        .out_dest_data_out_166_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_66184_c_compmm_m92_out_dest_data_out_166_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_offset(CONSTANT,31241)
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_offset_q = $unsigned(8'b01100001);

    // redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt(ADD,31242)
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_a = {1'b0, redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_q};
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_b = {1'b0, redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_o <= $unsigned(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_a) + $unsigned(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_b);
        end
    end
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_q = redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_o[8:0];

    // redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_inputreg0(DELAY,31237)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_inputreg0_q <= $unsigned(in_c1_eni5_165_tpl);
        end
    end

    // redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr(COUNTER,31240)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_i <= $unsigned(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_q = redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_i[7:0];

    // redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem(DUALMEM,31239)
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_ia = $unsigned(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_inputreg0_q);
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_aa = redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_wraddr_q;
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_ab = redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_aa),
        .data_a(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_ab),
        .q_b(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_q = redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_iq[15:0];

    // redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_outputreg0(DELAY,31238)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_outputreg0_q <= $unsigned(redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_mem_q);
        end
    end

    // redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt(ADD,31248)
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_a = {1'b0, redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_q};
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_b = {1'b0, redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_o <= $unsigned(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_a) + $unsigned(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_b);
        end
    end
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_q = redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_o[8:0];

    // redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_inputreg0(DELAY,31243)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_inputreg0_q <= $unsigned(in_c1_eni5_166_tpl);
        end
    end

    // redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr(COUNTER,31246)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_i <= $unsigned(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_q = redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_i[7:0];

    // redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem(DUALMEM,31245)
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_ia = $unsigned(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_inputreg0_q);
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_aa = redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_wraddr_q;
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_ab = redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_aa),
        .data_a(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_ab),
        .q_b(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_q = redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_iq[15:0];

    // redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_outputreg0(DELAY,31244)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_outputreg0_q <= $unsigned(redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_mem_q);
        end
    end

    // valid_fanout_reg92(REG,13387)@231 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg92_q <= $unsigned(redist841_sync_together4364_aunroll_x_in_i_valid_163_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_66183_c_compmm_m93(BLACKBOX,8682)@232
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66183_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_66183_c_compmm_m93 (
        .in_intel_reserved_ffwd_165_0(in_intel_reserved_ffwd_165_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg92_q),
        .out_dest_data_out_165_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_66183_c_compmm_m93_out_dest_data_out_165_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28953)@232 + 5
    // out q@238
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_66183_c_compmm_m93_out_dest_data_out_165_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_66184_c_compmm_m92_out_dest_data_out_166_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574(ADD,9054)@238
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod692_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_b = $unsigned({{5{i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_82_c_compmm_m2573_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_o[33:0];

    // rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x(MUX,20955)@238
    assign rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q or rightShiftStage0Idx1_uid20954_dupName_329_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q;
            1'b1 : rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20954_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x(MUX,20960)@238
    assign rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20959_dupName_329_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20956_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20959_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x(MUX,20965)@238
    assign rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20964_dupName_329_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20961_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20964_dupName_329_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2575_vt_select_20(BITSELECT,11454)@238
    assign i_unnamed_c_compmm_m2575_vt_select_20_b = rightShiftStage2_uid20966_dupName_329_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2575_vt_join(BITJOIN,11453)@238
    assign i_unnamed_c_compmm_m2575_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2575_vt_select_20_b};

    // i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x(BITSELECT,3812)@238
    assign i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x_b = i_unnamed_c_compmm_m2575_vt_join_q[15:0];

    // redist906_i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x_b_1(DELAY,30034)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist906_i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20975_dupName_330_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20974)@238
    assign rightShiftStage1Idx1Rng8_uid20975_dupName_330_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20977_dupName_330_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20976)@238
    assign rightShiftStage1Idx1_uid20977_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20975_dupName_330_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20970_dupName_330_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20969)@238
    assign rightShiftStage0Idx1Rng4_uid20970_dupName_330_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q[33:4];

    // rightShiftStage0Idx1_uid20972_dupName_330_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20971)@238
    assign rightShiftStage0Idx1_uid20972_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20970_dupName_330_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x(MUX,20973)@238
    assign rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q or rightShiftStage0Idx1_uid20972_dupName_330_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_82_i_c_compmm_m2574_q;
            1'b1 : rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20972_dupName_330_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x(MUX,20978)@238
    assign rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20977_dupName_330_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20974_dupName_330_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20977_dupName_330_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2577_vt_select_21(BITSELECT,11457)@238
    assign i_unnamed_c_compmm_m2577_vt_select_21_b = rightShiftStage1_uid20979_dupName_330_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2577_vt_join(BITJOIN,11456)@238
    assign i_unnamed_c_compmm_m2577_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2577_vt_select_21_b};

    // i_unnamed_c_compmm_m2578_sel_x(BITSELECT,6116)@238
    assign i_unnamed_c_compmm_m2578_sel_x_b = i_unnamed_c_compmm_m2577_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2579_BitSelect_for_a(BITSELECT,28584)@238
    assign i_unnamed_c_compmm_m2579_BitSelect_for_a_b = i_unnamed_c_compmm_m2578_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2579_join(BITJOIN,28585)@238
    assign i_unnamed_c_compmm_m2579_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2579_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2579_vt_select_0(BITSELECT,11462)@238
    assign i_unnamed_c_compmm_m2579_vt_select_0_b = i_unnamed_c_compmm_m2579_join_q[0:0];

    // redist142_i_unnamed_c_compmm_m2579_vt_select_0_b_1(DELAY,29270)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist142_i_unnamed_c_compmm_m2579_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2579_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2579_vt_join(BITJOIN,11461)@239
    assign i_unnamed_c_compmm_m2579_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist142_i_unnamed_c_compmm_m2579_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_82_c_compmm_m2580(ADD,7267)@239
    assign i_add_i_i_i_i_i_i_82_c_compmm_m2580_a = {1'b0, i_unnamed_c_compmm_m2579_vt_join_q};
    assign i_add_i_i_i_i_i_i_82_c_compmm_m2580_b = {1'b0, redist906_i_conv_i_i_i_i_i_82_c_compmm_m2576_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_82_c_compmm_m2580_o = $unsigned(i_add_i_i_i_i_i_i_82_c_compmm_m2580_a) + $unsigned(i_add_i_i_i_i_i_i_82_c_compmm_m2580_b);
    assign i_add_i_i_i_i_i_i_82_c_compmm_m2580_q = i_add_i_i_i_i_i_i_82_c_compmm_m2580_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_82_c_compmm_m2580_sel_x(BITSELECT,2281)@239
    assign bgTrunc_i_add_i_i_i_i_i_i_82_c_compmm_m2580_sel_x_b = i_add_i_i_i_i_i_i_82_c_compmm_m2580_q[15:0];

    // i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_sel_x(BITSELECT,3941)@239
    assign i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_82_c_compmm_m2580_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_select_15(BITSELECT,8491)@239
    assign i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_select_15_b = i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_join(BITJOIN,8490)@239
    assign i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_select_15_b};

    // leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(MUX,28006)@239
    assign leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_join_q or leftShiftStage0Idx1_uid28005_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_83_c_compmm_m2600_vt_join_q;
            1'b1 : leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28005_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(MUX,28011)@239
    assign leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s or leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28010_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = leftShiftStage0_uid28007_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28010_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x(MUX,28016)@239
    assign leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s or leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28015_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = leftShiftStage1_uid28012_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28015_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28(BITSELECT,10165)@239
    assign i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28_b = leftShiftStage2_uid28017_i_shl_i_i_i_i_i_i_83_c_compmm_m0_shift_x_q[28:13];

    // redist272_i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28_b_1(DELAY,29400)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist272_i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_join(BITJOIN,10164)@240
    assign i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_join_q = {redist272_i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg89(REG,13384)@233 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg89_q <= $unsigned(redist842_sync_together4364_aunroll_x_in_i_valid_165_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_66186_c_compmm_m90(BLACKBOX,8694)@234
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66186_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_66186_c_compmm_m90 (
        .in_intel_reserved_ffwd_168_0(in_intel_reserved_ffwd_168_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg89_q),
        .out_dest_data_out_168_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_66186_c_compmm_m90_out_dest_data_out_168_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_offset(CONSTANT,31253)
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_offset_q = $unsigned(8'b01011111);

    // redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt(ADD,31254)
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_a = {1'b0, redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_q};
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_b = {1'b0, redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_o <= $unsigned(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_a) + $unsigned(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_b);
        end
    end
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_q = redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_o[8:0];

    // redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_inputreg0(DELAY,31249)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_inputreg0_q <= $unsigned(in_c1_eni5_167_tpl);
        end
    end

    // redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr(COUNTER,31252)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_i <= $unsigned(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_q = redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_i[7:0];

    // redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem(DUALMEM,31251)
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_ia = $unsigned(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_inputreg0_q);
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_aa = redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_wraddr_q;
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_ab = redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_aa),
        .data_a(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_ab),
        .q_b(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_q = redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_iq[15:0];

    // redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_outputreg0(DELAY,31250)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_outputreg0_q <= $unsigned(redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_mem_q);
        end
    end

    // redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt(ADD,31260)
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_a = {1'b0, redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_q};
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_b = {1'b0, redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_o <= $unsigned(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_a) + $unsigned(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_b);
        end
    end
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_q = redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_o[8:0];

    // redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_inputreg0(DELAY,31255)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_inputreg0_q <= $unsigned(in_c1_eni5_168_tpl);
        end
    end

    // redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr(COUNTER,31258)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_i <= $unsigned(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_q = redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_i[7:0];

    // redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem(DUALMEM,31257)
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_ia = $unsigned(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_inputreg0_q);
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_aa = redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_wraddr_q;
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_ab = redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_aa),
        .data_a(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_ab),
        .q_b(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_q = redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_iq[15:0];

    // redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_outputreg0(DELAY,31256)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_outputreg0_q <= $unsigned(redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_mem_q);
        end
    end

    // valid_fanout_reg90(REG,13385)@233 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg90_q <= $unsigned(redist842_sync_together4364_aunroll_x_in_i_valid_165_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_66185_c_compmm_m91(BLACKBOX,8690)@234
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66185_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_66185_c_compmm_m91 (
        .in_intel_reserved_ffwd_167_0(in_intel_reserved_ffwd_167_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg90_q),
        .out_dest_data_out_167_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_66185_c_compmm_m91_out_dest_data_out_167_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28954)@234 + 5
    // out q@240
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_66185_c_compmm_m91_out_dest_data_out_167_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_66186_c_compmm_m90_out_dest_data_out_168_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602(ADD,9055)@240
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod697_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_b = $unsigned({{5{i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_83_c_compmm_m2601_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_o[33:0];

    // rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x(MUX,21017)@240
    assign rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q or rightShiftStage0Idx1_uid21016_dupName_333_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q;
            1'b1 : rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21016_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x(MUX,21022)@240
    assign rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21021_dupName_333_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21018_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21021_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x(MUX,21027)@240
    assign rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21026_dupName_333_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21023_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21026_dupName_333_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2603_vt_select_20(BITSELECT,11476)@240
    assign i_unnamed_c_compmm_m2603_vt_select_20_b = rightShiftStage2_uid21028_dupName_333_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2603_vt_join(BITJOIN,11475)@240
    assign i_unnamed_c_compmm_m2603_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2603_vt_select_20_b};

    // i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x(BITSELECT,3813)@240
    assign i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x_b = i_unnamed_c_compmm_m2603_vt_join_q[15:0];

    // redist905_i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x_b_1(DELAY,30033)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist905_i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21037_dupName_334_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21036)@240
    assign rightShiftStage1Idx1Rng8_uid21037_dupName_334_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21039_dupName_334_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21038)@240
    assign rightShiftStage1Idx1_uid21039_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21037_dupName_334_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21032_dupName_334_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21031)@240
    assign rightShiftStage0Idx1Rng4_uid21032_dupName_334_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q[33:4];

    // rightShiftStage0Idx1_uid21034_dupName_334_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21033)@240
    assign rightShiftStage0Idx1_uid21034_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21032_dupName_334_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x(MUX,21035)@240
    assign rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q or rightShiftStage0Idx1_uid21034_dupName_334_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_83_i_c_compmm_m2602_q;
            1'b1 : rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21034_dupName_334_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x(MUX,21040)@240
    assign rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21039_dupName_334_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21036_dupName_334_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21039_dupName_334_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2605_vt_select_21(BITSELECT,11479)@240
    assign i_unnamed_c_compmm_m2605_vt_select_21_b = rightShiftStage1_uid21041_dupName_334_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2605_vt_join(BITJOIN,11478)@240
    assign i_unnamed_c_compmm_m2605_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2605_vt_select_21_b};

    // i_unnamed_c_compmm_m2606_sel_x(BITSELECT,6118)@240
    assign i_unnamed_c_compmm_m2606_sel_x_b = i_unnamed_c_compmm_m2605_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2607_BitSelect_for_a(BITSELECT,28588)@240
    assign i_unnamed_c_compmm_m2607_BitSelect_for_a_b = i_unnamed_c_compmm_m2606_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2607_join(BITJOIN,28589)@240
    assign i_unnamed_c_compmm_m2607_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2607_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2607_vt_select_0(BITSELECT,11484)@240
    assign i_unnamed_c_compmm_m2607_vt_select_0_b = i_unnamed_c_compmm_m2607_join_q[0:0];

    // redist140_i_unnamed_c_compmm_m2607_vt_select_0_b_1(DELAY,29268)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist140_i_unnamed_c_compmm_m2607_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2607_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2607_vt_join(BITJOIN,11483)@241
    assign i_unnamed_c_compmm_m2607_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist140_i_unnamed_c_compmm_m2607_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_83_c_compmm_m2608(ADD,7268)@241
    assign i_add_i_i_i_i_i_i_83_c_compmm_m2608_a = {1'b0, i_unnamed_c_compmm_m2607_vt_join_q};
    assign i_add_i_i_i_i_i_i_83_c_compmm_m2608_b = {1'b0, redist905_i_conv_i_i_i_i_i_83_c_compmm_m2604_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_83_c_compmm_m2608_o = $unsigned(i_add_i_i_i_i_i_i_83_c_compmm_m2608_a) + $unsigned(i_add_i_i_i_i_i_i_83_c_compmm_m2608_b);
    assign i_add_i_i_i_i_i_i_83_c_compmm_m2608_q = i_add_i_i_i_i_i_i_83_c_compmm_m2608_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_83_c_compmm_m2608_sel_x(BITSELECT,2282)@241
    assign bgTrunc_i_add_i_i_i_i_i_i_83_c_compmm_m2608_sel_x_b = i_add_i_i_i_i_i_i_83_c_compmm_m2608_q[15:0];

    // i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_sel_x(BITSELECT,3942)@241
    assign i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_83_c_compmm_m2608_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_select_15(BITSELECT,8495)@241
    assign i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_select_15_b = i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_join(BITJOIN,8494)@241
    assign i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_select_15_b};

    // leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(MUX,28024)@241
    assign leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_join_q or leftShiftStage0Idx1_uid28023_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_84_c_compmm_m2628_vt_join_q;
            1'b1 : leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28023_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(MUX,28029)@241
    assign leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s or leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28028_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = leftShiftStage0_uid28025_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28028_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x(MUX,28034)@241
    assign leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s or leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28033_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = leftShiftStage1_uid28030_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28033_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28(BITSELECT,10168)@241
    assign i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28_b = leftShiftStage2_uid28035_i_shl_i_i_i_i_i_i_84_c_compmm_m0_shift_x_q[28:13];

    // redist271_i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28_b_1(DELAY,29399)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist271_i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_join(BITJOIN,10167)@242
    assign i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_join_q = {redist271_i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg87(REG,13382)@235 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg87_q <= $unsigned(redist843_sync_together4364_aunroll_x_in_i_valid_167_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_66188_c_compmm_m88(BLACKBOX,8706)@236
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66188_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_66188_c_compmm_m88 (
        .in_intel_reserved_ffwd_170_0(in_intel_reserved_ffwd_170_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg87_q),
        .out_dest_data_out_170_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_66188_c_compmm_m88_out_dest_data_out_170_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_offset(CONSTANT,31265)
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_offset_q = $unsigned(8'b01011101);

    // redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt(ADD,31266)
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_a = {1'b0, redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_q};
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_b = {1'b0, redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_o <= $unsigned(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_a) + $unsigned(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_b);
        end
    end
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_q = redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_o[8:0];

    // redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_inputreg0(DELAY,31261)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_inputreg0_q <= $unsigned(in_c1_eni5_169_tpl);
        end
    end

    // redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr(COUNTER,31264)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_i <= $unsigned(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_q = redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_i[7:0];

    // redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem(DUALMEM,31263)
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_ia = $unsigned(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_inputreg0_q);
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_aa = redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_wraddr_q;
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_ab = redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_aa),
        .data_a(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_ab),
        .q_b(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_q = redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_iq[15:0];

    // redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_outputreg0(DELAY,31262)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_outputreg0_q <= $unsigned(redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_mem_q);
        end
    end

    // redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt(ADD,31272)
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_a = {1'b0, redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_q};
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_b = {1'b0, redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_o <= $unsigned(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_a) + $unsigned(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_b);
        end
    end
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_q = redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_o[8:0];

    // redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_inputreg0(DELAY,31267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_inputreg0_q <= $unsigned(in_c1_eni5_170_tpl);
        end
    end

    // redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr(COUNTER,31270)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_i <= $unsigned(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_q = redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_i[7:0];

    // redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem(DUALMEM,31269)
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_ia = $unsigned(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_inputreg0_q);
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_aa = redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_wraddr_q;
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_ab = redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_aa),
        .data_a(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_ab),
        .q_b(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_q = redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_iq[15:0];

    // redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_outputreg0(DELAY,31268)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_outputreg0_q <= $unsigned(redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_mem_q);
        end
    end

    // valid_fanout_reg88(REG,13383)@235 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg88_q <= $unsigned(redist843_sync_together4364_aunroll_x_in_i_valid_167_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_66187_c_compmm_m89(BLACKBOX,8702)@236
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66187_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_66187_c_compmm_m89 (
        .in_intel_reserved_ffwd_169_0(in_intel_reserved_ffwd_169_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg88_q),
        .out_dest_data_out_169_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_66187_c_compmm_m89_out_dest_data_out_169_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28955)@236 + 5
    // out q@242
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_66187_c_compmm_m89_out_dest_data_out_169_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_66188_c_compmm_m88_out_dest_data_out_170_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630(ADD,9056)@242
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod702_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_b = $unsigned({{5{i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_84_c_compmm_m2629_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_o[33:0];

    // rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x(MUX,21079)@242
    assign rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q or rightShiftStage0Idx1_uid21078_dupName_337_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q;
            1'b1 : rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21078_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x(MUX,21084)@242
    assign rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21083_dupName_337_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21080_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21083_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x(MUX,21089)@242
    assign rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21088_dupName_337_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21085_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21088_dupName_337_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2631_vt_select_20(BITSELECT,11498)@242
    assign i_unnamed_c_compmm_m2631_vt_select_20_b = rightShiftStage2_uid21090_dupName_337_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2631_vt_join(BITJOIN,11497)@242
    assign i_unnamed_c_compmm_m2631_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2631_vt_select_20_b};

    // i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x(BITSELECT,3814)@242
    assign i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x_b = i_unnamed_c_compmm_m2631_vt_join_q[15:0];

    // redist904_i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x_b_1(DELAY,30032)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist904_i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21099_dupName_338_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21098)@242
    assign rightShiftStage1Idx1Rng8_uid21099_dupName_338_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21101_dupName_338_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21100)@242
    assign rightShiftStage1Idx1_uid21101_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21099_dupName_338_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21094_dupName_338_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21093)@242
    assign rightShiftStage0Idx1Rng4_uid21094_dupName_338_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q[33:4];

    // rightShiftStage0Idx1_uid21096_dupName_338_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21095)@242
    assign rightShiftStage0Idx1_uid21096_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21094_dupName_338_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x(MUX,21097)@242
    assign rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q or rightShiftStage0Idx1_uid21096_dupName_338_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_84_i_c_compmm_m2630_q;
            1'b1 : rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21096_dupName_338_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x(MUX,21102)@242
    assign rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21101_dupName_338_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21098_dupName_338_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21101_dupName_338_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2633_vt_select_21(BITSELECT,11501)@242
    assign i_unnamed_c_compmm_m2633_vt_select_21_b = rightShiftStage1_uid21103_dupName_338_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2633_vt_join(BITJOIN,11500)@242
    assign i_unnamed_c_compmm_m2633_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2633_vt_select_21_b};

    // i_unnamed_c_compmm_m2634_sel_x(BITSELECT,6120)@242
    assign i_unnamed_c_compmm_m2634_sel_x_b = i_unnamed_c_compmm_m2633_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2635_BitSelect_for_a(BITSELECT,28592)@242
    assign i_unnamed_c_compmm_m2635_BitSelect_for_a_b = i_unnamed_c_compmm_m2634_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2635_join(BITJOIN,28593)@242
    assign i_unnamed_c_compmm_m2635_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2635_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2635_vt_select_0(BITSELECT,11506)@242
    assign i_unnamed_c_compmm_m2635_vt_select_0_b = i_unnamed_c_compmm_m2635_join_q[0:0];

    // redist138_i_unnamed_c_compmm_m2635_vt_select_0_b_1(DELAY,29266)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist138_i_unnamed_c_compmm_m2635_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2635_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2635_vt_join(BITJOIN,11505)@243
    assign i_unnamed_c_compmm_m2635_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist138_i_unnamed_c_compmm_m2635_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_84_c_compmm_m2636(ADD,7269)@243
    assign i_add_i_i_i_i_i_i_84_c_compmm_m2636_a = {1'b0, i_unnamed_c_compmm_m2635_vt_join_q};
    assign i_add_i_i_i_i_i_i_84_c_compmm_m2636_b = {1'b0, redist904_i_conv_i_i_i_i_i_84_c_compmm_m2632_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_84_c_compmm_m2636_o = $unsigned(i_add_i_i_i_i_i_i_84_c_compmm_m2636_a) + $unsigned(i_add_i_i_i_i_i_i_84_c_compmm_m2636_b);
    assign i_add_i_i_i_i_i_i_84_c_compmm_m2636_q = i_add_i_i_i_i_i_i_84_c_compmm_m2636_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_84_c_compmm_m2636_sel_x(BITSELECT,2283)@243
    assign bgTrunc_i_add_i_i_i_i_i_i_84_c_compmm_m2636_sel_x_b = i_add_i_i_i_i_i_i_84_c_compmm_m2636_q[15:0];

    // i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_sel_x(BITSELECT,3943)@243
    assign i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_84_c_compmm_m2636_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_select_15(BITSELECT,8499)@243
    assign i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_select_15_b = i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_join(BITJOIN,8498)@243
    assign i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_select_15_b};

    // leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(MUX,28042)@243
    assign leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_join_q or leftShiftStage0Idx1_uid28041_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_85_c_compmm_m2656_vt_join_q;
            1'b1 : leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28041_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(MUX,28047)@243
    assign leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s or leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28046_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = leftShiftStage0_uid28043_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28046_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x(MUX,28052)@243
    assign leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s or leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28051_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = leftShiftStage1_uid28048_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28051_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28(BITSELECT,10171)@243
    assign i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28_b = leftShiftStage2_uid28053_i_shl_i_i_i_i_i_i_85_c_compmm_m0_shift_x_q[28:13];

    // redist270_i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28_b_1(DELAY,29398)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist270_i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_join(BITJOIN,10170)@244
    assign i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_join_q = {redist270_i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg85(REG,13380)@237 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg85_q <= $unsigned(redist844_sync_together4364_aunroll_x_in_i_valid_169_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_66190_c_compmm_m86(BLACKBOX,8714)@238
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66190_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_66190_c_compmm_m86 (
        .in_intel_reserved_ffwd_172_0(in_intel_reserved_ffwd_172_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg85_q),
        .out_dest_data_out_172_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_66190_c_compmm_m86_out_dest_data_out_172_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_offset(CONSTANT,31277)
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_offset_q = $unsigned(8'b01011011);

    // redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt(ADD,31278)
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_a = {1'b0, redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_q};
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_b = {1'b0, redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_o <= $unsigned(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_a) + $unsigned(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_b);
        end
    end
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_q = redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_o[8:0];

    // redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_inputreg0(DELAY,31273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_inputreg0_q <= $unsigned(in_c1_eni5_171_tpl);
        end
    end

    // redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr(COUNTER,31276)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_i <= $unsigned(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_q = redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_i[7:0];

    // redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem(DUALMEM,31275)
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_ia = $unsigned(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_inputreg0_q);
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_aa = redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_wraddr_q;
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_ab = redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_aa),
        .data_a(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_ab),
        .q_b(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_q = redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_iq[15:0];

    // redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_outputreg0(DELAY,31274)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_outputreg0_q <= $unsigned(redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_mem_q);
        end
    end

    // redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt(ADD,31284)
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_a = {1'b0, redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_q};
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_b = {1'b0, redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_o <= $unsigned(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_a) + $unsigned(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_b);
        end
    end
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_q = redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_o[8:0];

    // redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_inputreg0(DELAY,31279)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_inputreg0_q <= $unsigned(in_c1_eni5_172_tpl);
        end
    end

    // redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr(COUNTER,31282)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_i <= $unsigned(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_q = redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_i[7:0];

    // redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem(DUALMEM,31281)
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_ia = $unsigned(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_inputreg0_q);
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_aa = redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_wraddr_q;
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_ab = redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_aa),
        .data_a(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_ab),
        .q_b(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_q = redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_iq[15:0];

    // redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_outputreg0(DELAY,31280)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_outputreg0_q <= $unsigned(redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_mem_q);
        end
    end

    // valid_fanout_reg86(REG,13381)@237 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg86_q <= $unsigned(redist844_sync_together4364_aunroll_x_in_i_valid_169_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_66189_c_compmm_m87(BLACKBOX,8710)@238
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66189_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_66189_c_compmm_m87 (
        .in_intel_reserved_ffwd_171_0(in_intel_reserved_ffwd_171_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg86_q),
        .out_dest_data_out_171_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_66189_c_compmm_m87_out_dest_data_out_171_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28956)@238 + 5
    // out q@244
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_66189_c_compmm_m87_out_dest_data_out_171_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_66190_c_compmm_m86_out_dest_data_out_172_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658(ADD,9057)@244
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod707_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_b = $unsigned({{5{i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_85_c_compmm_m2657_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_o[33:0];

    // rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x(MUX,21141)@244
    assign rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q or rightShiftStage0Idx1_uid21140_dupName_341_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q;
            1'b1 : rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21140_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x(MUX,21146)@244
    assign rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21145_dupName_341_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21142_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21145_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x(MUX,21151)@244
    assign rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21150_dupName_341_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21147_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21150_dupName_341_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2659_vt_select_20(BITSELECT,11523)@244
    assign i_unnamed_c_compmm_m2659_vt_select_20_b = rightShiftStage2_uid21152_dupName_341_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2659_vt_join(BITJOIN,11522)@244
    assign i_unnamed_c_compmm_m2659_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2659_vt_select_20_b};

    // i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x(BITSELECT,3815)@244
    assign i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x_b = i_unnamed_c_compmm_m2659_vt_join_q[15:0];

    // redist903_i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x_b_1(DELAY,30031)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist903_i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21161_dupName_342_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21160)@244
    assign rightShiftStage1Idx1Rng8_uid21161_dupName_342_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21163_dupName_342_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21162)@244
    assign rightShiftStage1Idx1_uid21163_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21161_dupName_342_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21156_dupName_342_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21155)@244
    assign rightShiftStage0Idx1Rng4_uid21156_dupName_342_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q[33:4];

    // rightShiftStage0Idx1_uid21158_dupName_342_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21157)@244
    assign rightShiftStage0Idx1_uid21158_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21156_dupName_342_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x(MUX,21159)@244
    assign rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q or rightShiftStage0Idx1_uid21158_dupName_342_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_85_i_c_compmm_m2658_q;
            1'b1 : rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21158_dupName_342_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x(MUX,21164)@244
    assign rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21163_dupName_342_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21160_dupName_342_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21163_dupName_342_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2661_vt_select_21(BITSELECT,11529)@244
    assign i_unnamed_c_compmm_m2661_vt_select_21_b = rightShiftStage1_uid21165_dupName_342_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2661_vt_join(BITJOIN,11528)@244
    assign i_unnamed_c_compmm_m2661_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2661_vt_select_21_b};

    // i_unnamed_c_compmm_m2662_sel_x(BITSELECT,6123)@244
    assign i_unnamed_c_compmm_m2662_sel_x_b = i_unnamed_c_compmm_m2661_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2663_BitSelect_for_a(BITSELECT,28596)@244
    assign i_unnamed_c_compmm_m2663_BitSelect_for_a_b = i_unnamed_c_compmm_m2662_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2663_join(BITJOIN,28597)@244
    assign i_unnamed_c_compmm_m2663_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2663_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2663_vt_select_0(BITSELECT,11534)@244
    assign i_unnamed_c_compmm_m2663_vt_select_0_b = i_unnamed_c_compmm_m2663_join_q[0:0];

    // redist136_i_unnamed_c_compmm_m2663_vt_select_0_b_1(DELAY,29264)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist136_i_unnamed_c_compmm_m2663_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2663_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2663_vt_join(BITJOIN,11533)@245
    assign i_unnamed_c_compmm_m2663_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist136_i_unnamed_c_compmm_m2663_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_85_c_compmm_m2664(ADD,7270)@245
    assign i_add_i_i_i_i_i_i_85_c_compmm_m2664_a = {1'b0, i_unnamed_c_compmm_m2663_vt_join_q};
    assign i_add_i_i_i_i_i_i_85_c_compmm_m2664_b = {1'b0, redist903_i_conv_i_i_i_i_i_85_c_compmm_m2660_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_85_c_compmm_m2664_o = $unsigned(i_add_i_i_i_i_i_i_85_c_compmm_m2664_a) + $unsigned(i_add_i_i_i_i_i_i_85_c_compmm_m2664_b);
    assign i_add_i_i_i_i_i_i_85_c_compmm_m2664_q = i_add_i_i_i_i_i_i_85_c_compmm_m2664_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_85_c_compmm_m2664_sel_x(BITSELECT,2284)@245
    assign bgTrunc_i_add_i_i_i_i_i_i_85_c_compmm_m2664_sel_x_b = i_add_i_i_i_i_i_i_85_c_compmm_m2664_q[15:0];

    // i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_sel_x(BITSELECT,3944)@245
    assign i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_85_c_compmm_m2664_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_select_15(BITSELECT,8503)@245
    assign i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_select_15_b = i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_join(BITJOIN,8502)@245
    assign i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_select_15_b};

    // leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(MUX,28060)@245
    assign leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_join_q or leftShiftStage0Idx1_uid28059_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_86_c_compmm_m2684_vt_join_q;
            1'b1 : leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28059_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(MUX,28065)@245
    assign leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s or leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28064_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = leftShiftStage0_uid28061_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28064_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x(MUX,28070)@245
    assign leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s or leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28069_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = leftShiftStage1_uid28066_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28069_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28(BITSELECT,10174)@245
    assign i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28_b = leftShiftStage2_uid28071_i_shl_i_i_i_i_i_i_86_c_compmm_m0_shift_x_q[28:13];

    // redist269_i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28_b_1(DELAY,29397)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist269_i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_join(BITJOIN,10173)@246
    assign i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_join_q = {redist269_i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg83(REG,13378)@239 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg83_q <= $unsigned(redist845_sync_together4364_aunroll_x_in_i_valid_171_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_66192_c_compmm_m84(BLACKBOX,8722)@240
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66192_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_66192_c_compmm_m84 (
        .in_intel_reserved_ffwd_174_0(in_intel_reserved_ffwd_174_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg83_q),
        .out_dest_data_out_174_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_66192_c_compmm_m84_out_dest_data_out_174_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_offset(CONSTANT,31289)
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_offset_q = $unsigned(8'b01011001);

    // redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt(ADD,31290)
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_a = {1'b0, redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_q};
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_b = {1'b0, redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_o <= $unsigned(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_a) + $unsigned(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_b);
        end
    end
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_q = redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_o[8:0];

    // redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_inputreg0(DELAY,31285)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_inputreg0_q <= $unsigned(in_c1_eni5_173_tpl);
        end
    end

    // redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr(COUNTER,31288)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_i <= $unsigned(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_q = redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_i[7:0];

    // redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem(DUALMEM,31287)
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_ia = $unsigned(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_inputreg0_q);
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_aa = redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_wraddr_q;
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_ab = redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_aa),
        .data_a(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_ab),
        .q_b(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_q = redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_iq[15:0];

    // redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_outputreg0(DELAY,31286)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_outputreg0_q <= $unsigned(redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_mem_q);
        end
    end

    // redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt(ADD,31296)
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_a = {1'b0, redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_q};
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_b = {1'b0, redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_o <= $unsigned(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_a) + $unsigned(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_b);
        end
    end
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_q = redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_o[8:0];

    // redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_inputreg0(DELAY,31291)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_inputreg0_q <= $unsigned(in_c1_eni5_174_tpl);
        end
    end

    // redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr(COUNTER,31294)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_i <= $unsigned(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_q = redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_i[7:0];

    // redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem(DUALMEM,31293)
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_ia = $unsigned(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_inputreg0_q);
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_aa = redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_wraddr_q;
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_ab = redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_aa),
        .data_a(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_ab),
        .q_b(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_q = redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_iq[15:0];

    // redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_outputreg0(DELAY,31292)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_outputreg0_q <= $unsigned(redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_mem_q);
        end
    end

    // valid_fanout_reg84(REG,13379)@239 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg84_q <= $unsigned(redist845_sync_together4364_aunroll_x_in_i_valid_171_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_66191_c_compmm_m85(BLACKBOX,8718)@240
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66191_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_66191_c_compmm_m85 (
        .in_intel_reserved_ffwd_173_0(in_intel_reserved_ffwd_173_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg84_q),
        .out_dest_data_out_173_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_66191_c_compmm_m85_out_dest_data_out_173_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28957)@240 + 5
    // out q@246
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_66191_c_compmm_m85_out_dest_data_out_173_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_66192_c_compmm_m84_out_dest_data_out_174_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686(ADD,9058)@246
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod712_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_b = $unsigned({{5{i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_86_c_compmm_m2685_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_o[33:0];

    // rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x(MUX,21203)@246
    assign rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q or rightShiftStage0Idx1_uid21202_dupName_345_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q;
            1'b1 : rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21202_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x(MUX,21208)@246
    assign rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21207_dupName_345_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21204_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21207_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x(MUX,21213)@246
    assign rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21212_dupName_345_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21209_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21212_dupName_345_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2687_vt_select_20(BITSELECT,11553)@246
    assign i_unnamed_c_compmm_m2687_vt_select_20_b = rightShiftStage2_uid21214_dupName_345_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2687_vt_join(BITJOIN,11552)@246
    assign i_unnamed_c_compmm_m2687_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2687_vt_select_20_b};

    // i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x(BITSELECT,3816)@246
    assign i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x_b = i_unnamed_c_compmm_m2687_vt_join_q[15:0];

    // redist902_i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x_b_1(DELAY,30030)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist902_i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21223_dupName_346_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21222)@246
    assign rightShiftStage1Idx1Rng8_uid21223_dupName_346_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21225_dupName_346_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21224)@246
    assign rightShiftStage1Idx1_uid21225_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21223_dupName_346_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21218_dupName_346_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21217)@246
    assign rightShiftStage0Idx1Rng4_uid21218_dupName_346_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q[33:4];

    // rightShiftStage0Idx1_uid21220_dupName_346_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21219)@246
    assign rightShiftStage0Idx1_uid21220_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21218_dupName_346_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x(MUX,21221)@246
    assign rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q or rightShiftStage0Idx1_uid21220_dupName_346_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_86_i_c_compmm_m2686_q;
            1'b1 : rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21220_dupName_346_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x(MUX,21226)@246
    assign rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21225_dupName_346_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21222_dupName_346_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21225_dupName_346_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2689_vt_select_21(BITSELECT,11556)@246
    assign i_unnamed_c_compmm_m2689_vt_select_21_b = rightShiftStage1_uid21227_dupName_346_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2689_vt_join(BITJOIN,11555)@246
    assign i_unnamed_c_compmm_m2689_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2689_vt_select_21_b};

    // i_unnamed_c_compmm_m2690_sel_x(BITSELECT,6125)@246
    assign i_unnamed_c_compmm_m2690_sel_x_b = i_unnamed_c_compmm_m2689_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2691_BitSelect_for_a(BITSELECT,28602)@246
    assign i_unnamed_c_compmm_m2691_BitSelect_for_a_b = i_unnamed_c_compmm_m2690_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2691_join(BITJOIN,28603)@246
    assign i_unnamed_c_compmm_m2691_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2691_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2691_vt_select_0(BITSELECT,11561)@246
    assign i_unnamed_c_compmm_m2691_vt_select_0_b = i_unnamed_c_compmm_m2691_join_q[0:0];

    // redist134_i_unnamed_c_compmm_m2691_vt_select_0_b_1(DELAY,29262)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist134_i_unnamed_c_compmm_m2691_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2691_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2691_vt_join(BITJOIN,11560)@247
    assign i_unnamed_c_compmm_m2691_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist134_i_unnamed_c_compmm_m2691_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_86_c_compmm_m2692(ADD,7271)@247
    assign i_add_i_i_i_i_i_i_86_c_compmm_m2692_a = {1'b0, i_unnamed_c_compmm_m2691_vt_join_q};
    assign i_add_i_i_i_i_i_i_86_c_compmm_m2692_b = {1'b0, redist902_i_conv_i_i_i_i_i_86_c_compmm_m2688_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_86_c_compmm_m2692_o = $unsigned(i_add_i_i_i_i_i_i_86_c_compmm_m2692_a) + $unsigned(i_add_i_i_i_i_i_i_86_c_compmm_m2692_b);
    assign i_add_i_i_i_i_i_i_86_c_compmm_m2692_q = i_add_i_i_i_i_i_i_86_c_compmm_m2692_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_86_c_compmm_m2692_sel_x(BITSELECT,2285)@247
    assign bgTrunc_i_add_i_i_i_i_i_i_86_c_compmm_m2692_sel_x_b = i_add_i_i_i_i_i_i_86_c_compmm_m2692_q[15:0];

    // i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_sel_x(BITSELECT,3945)@247
    assign i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_86_c_compmm_m2692_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_select_15(BITSELECT,8507)@247
    assign i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_select_15_b = i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_join(BITJOIN,8506)@247
    assign i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_select_15_b};

    // leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(MUX,28078)@247
    assign leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_join_q or leftShiftStage0Idx1_uid28077_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_87_c_compmm_m2712_vt_join_q;
            1'b1 : leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28077_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(MUX,28083)@247
    assign leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s or leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28082_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = leftShiftStage0_uid28079_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28082_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x(MUX,28088)@247
    assign leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s or leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28087_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = leftShiftStage1_uid28084_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28087_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28(BITSELECT,10177)@247
    assign i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28_b = leftShiftStage2_uid28089_i_shl_i_i_i_i_i_i_87_c_compmm_m0_shift_x_q[28:13];

    // redist268_i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28_b_1(DELAY,29396)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist268_i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_join(BITJOIN,10176)@248
    assign i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_join_q = {redist268_i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg81(REG,13376)@241 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg81_q <= $unsigned(redist846_sync_together4364_aunroll_x_in_i_valid_173_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_66194_c_compmm_m82(BLACKBOX,8730)@242
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66194_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_66194_c_compmm_m82 (
        .in_intel_reserved_ffwd_176_0(in_intel_reserved_ffwd_176_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg81_q),
        .out_dest_data_out_176_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_66194_c_compmm_m82_out_dest_data_out_176_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_offset(CONSTANT,31301)
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_offset_q = $unsigned(8'b01010111);

    // redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt(ADD,31302)
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_a = {1'b0, redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_q};
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_b = {1'b0, redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_o <= $unsigned(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_a) + $unsigned(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_b);
        end
    end
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_q = redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_o[8:0];

    // redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_inputreg0(DELAY,31297)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_inputreg0_q <= $unsigned(in_c1_eni5_175_tpl);
        end
    end

    // redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr(COUNTER,31300)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_i <= $unsigned(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_q = redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_i[7:0];

    // redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem(DUALMEM,31299)
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_ia = $unsigned(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_inputreg0_q);
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_aa = redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_wraddr_q;
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_ab = redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_aa),
        .data_a(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_ab),
        .q_b(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_q = redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_iq[15:0];

    // redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_outputreg0(DELAY,31298)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_outputreg0_q <= $unsigned(redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_mem_q);
        end
    end

    // redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt(ADD,31308)
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_a = {1'b0, redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_q};
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_b = {1'b0, redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_o <= $unsigned(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_a) + $unsigned(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_b);
        end
    end
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_q = redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_o[8:0];

    // redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_inputreg0(DELAY,31303)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_inputreg0_q <= $unsigned(in_c1_eni5_176_tpl);
        end
    end

    // redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr(COUNTER,31306)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_i <= $unsigned(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_q = redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_i[7:0];

    // redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem(DUALMEM,31305)
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_ia = $unsigned(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_inputreg0_q);
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_aa = redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_wraddr_q;
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_ab = redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_aa),
        .data_a(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_ab),
        .q_b(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_q = redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_iq[15:0];

    // redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_outputreg0(DELAY,31304)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_outputreg0_q <= $unsigned(redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_mem_q);
        end
    end

    // valid_fanout_reg82(REG,13377)@241 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg82_q <= $unsigned(redist846_sync_together4364_aunroll_x_in_i_valid_173_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_66193_c_compmm_m83(BLACKBOX,8726)@242
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66193_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_66193_c_compmm_m83 (
        .in_intel_reserved_ffwd_175_0(in_intel_reserved_ffwd_175_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg82_q),
        .out_dest_data_out_175_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_66193_c_compmm_m83_out_dest_data_out_175_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28958)@242 + 5
    // out q@248
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_66193_c_compmm_m83_out_dest_data_out_175_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_66194_c_compmm_m82_out_dest_data_out_176_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714(ADD,9059)@248
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod717_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_b = $unsigned({{5{i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_87_c_compmm_m2713_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_o[33:0];

    // rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x(MUX,21265)@248
    assign rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q or rightShiftStage0Idx1_uid21264_dupName_349_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q;
            1'b1 : rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21264_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x(MUX,21270)@248
    assign rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21269_dupName_349_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21266_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21269_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x(MUX,21275)@248
    assign rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21274_dupName_349_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21271_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21274_dupName_349_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2715_vt_select_20(BITSELECT,11575)@248
    assign i_unnamed_c_compmm_m2715_vt_select_20_b = rightShiftStage2_uid21276_dupName_349_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2715_vt_join(BITJOIN,11574)@248
    assign i_unnamed_c_compmm_m2715_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2715_vt_select_20_b};

    // i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x(BITSELECT,3817)@248
    assign i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x_b = i_unnamed_c_compmm_m2715_vt_join_q[15:0];

    // redist901_i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x_b_1(DELAY,30029)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist901_i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21285_dupName_350_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21284)@248
    assign rightShiftStage1Idx1Rng8_uid21285_dupName_350_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21287_dupName_350_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21286)@248
    assign rightShiftStage1Idx1_uid21287_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21285_dupName_350_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21280_dupName_350_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21279)@248
    assign rightShiftStage0Idx1Rng4_uid21280_dupName_350_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q[33:4];

    // rightShiftStage0Idx1_uid21282_dupName_350_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21281)@248
    assign rightShiftStage0Idx1_uid21282_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21280_dupName_350_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x(MUX,21283)@248
    assign rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q or rightShiftStage0Idx1_uid21282_dupName_350_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_87_i_c_compmm_m2714_q;
            1'b1 : rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21282_dupName_350_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x(MUX,21288)@248
    assign rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21287_dupName_350_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21284_dupName_350_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21287_dupName_350_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2717_vt_select_21(BITSELECT,11578)@248
    assign i_unnamed_c_compmm_m2717_vt_select_21_b = rightShiftStage1_uid21289_dupName_350_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2717_vt_join(BITJOIN,11577)@248
    assign i_unnamed_c_compmm_m2717_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2717_vt_select_21_b};

    // i_unnamed_c_compmm_m2718_sel_x(BITSELECT,6127)@248
    assign i_unnamed_c_compmm_m2718_sel_x_b = i_unnamed_c_compmm_m2717_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2719_BitSelect_for_a(BITSELECT,28606)@248
    assign i_unnamed_c_compmm_m2719_BitSelect_for_a_b = i_unnamed_c_compmm_m2718_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2719_join(BITJOIN,28607)@248
    assign i_unnamed_c_compmm_m2719_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2719_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2719_vt_select_0(BITSELECT,11583)@248
    assign i_unnamed_c_compmm_m2719_vt_select_0_b = i_unnamed_c_compmm_m2719_join_q[0:0];

    // redist132_i_unnamed_c_compmm_m2719_vt_select_0_b_1(DELAY,29260)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist132_i_unnamed_c_compmm_m2719_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2719_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2719_vt_join(BITJOIN,11582)@249
    assign i_unnamed_c_compmm_m2719_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist132_i_unnamed_c_compmm_m2719_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_87_c_compmm_m2720(ADD,7272)@249
    assign i_add_i_i_i_i_i_i_87_c_compmm_m2720_a = {1'b0, i_unnamed_c_compmm_m2719_vt_join_q};
    assign i_add_i_i_i_i_i_i_87_c_compmm_m2720_b = {1'b0, redist901_i_conv_i_i_i_i_i_87_c_compmm_m2716_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_87_c_compmm_m2720_o = $unsigned(i_add_i_i_i_i_i_i_87_c_compmm_m2720_a) + $unsigned(i_add_i_i_i_i_i_i_87_c_compmm_m2720_b);
    assign i_add_i_i_i_i_i_i_87_c_compmm_m2720_q = i_add_i_i_i_i_i_i_87_c_compmm_m2720_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_87_c_compmm_m2720_sel_x(BITSELECT,2286)@249
    assign bgTrunc_i_add_i_i_i_i_i_i_87_c_compmm_m2720_sel_x_b = i_add_i_i_i_i_i_i_87_c_compmm_m2720_q[15:0];

    // i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_sel_x(BITSELECT,3946)@249
    assign i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_87_c_compmm_m2720_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_select_15(BITSELECT,8511)@249
    assign i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_select_15_b = i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_join(BITJOIN,8510)@249
    assign i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_select_15_b};

    // leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(MUX,28096)@249
    assign leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_join_q or leftShiftStage0Idx1_uid28095_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_88_c_compmm_m2740_vt_join_q;
            1'b1 : leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28095_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(MUX,28101)@249
    assign leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s or leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28100_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = leftShiftStage0_uid28097_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28100_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x(MUX,28106)@249
    assign leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s or leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28105_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = leftShiftStage1_uid28102_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28105_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28(BITSELECT,10180)@249
    assign i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28_b = leftShiftStage2_uid28107_i_shl_i_i_i_i_i_i_88_c_compmm_m0_shift_x_q[28:13];

    // redist267_i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28_b_1(DELAY,29395)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist267_i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_join(BITJOIN,10179)@250
    assign i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_join_q = {redist267_i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg79(REG,13374)@243 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg79_q <= $unsigned(redist847_sync_together4364_aunroll_x_in_i_valid_175_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_66196_c_compmm_m80(BLACKBOX,8738)@244
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66196_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_66196_c_compmm_m80 (
        .in_intel_reserved_ffwd_178_0(in_intel_reserved_ffwd_178_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg79_q),
        .out_dest_data_out_178_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_66196_c_compmm_m80_out_dest_data_out_178_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_offset(CONSTANT,31313)
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_offset_q = $unsigned(8'b01010101);

    // redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt(ADD,31314)
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_a = {1'b0, redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_q};
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_b = {1'b0, redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_o <= $unsigned(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_a) + $unsigned(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_b);
        end
    end
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_q = redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_o[8:0];

    // redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_inputreg0(DELAY,31309)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_inputreg0_q <= $unsigned(in_c1_eni5_177_tpl);
        end
    end

    // redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr(COUNTER,31312)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_i <= $unsigned(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_q = redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_i[7:0];

    // redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem(DUALMEM,31311)
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_ia = $unsigned(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_inputreg0_q);
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_aa = redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_wraddr_q;
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_ab = redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_aa),
        .data_a(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_ab),
        .q_b(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_q = redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_iq[15:0];

    // redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_outputreg0(DELAY,31310)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_outputreg0_q <= $unsigned(redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_mem_q);
        end
    end

    // redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt(ADD,31320)
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_a = {1'b0, redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_q};
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_b = {1'b0, redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_o <= $unsigned(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_a) + $unsigned(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_b);
        end
    end
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_q = redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_o[8:0];

    // redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_inputreg0(DELAY,31315)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_inputreg0_q <= $unsigned(in_c1_eni5_178_tpl);
        end
    end

    // redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr(COUNTER,31318)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_i <= $unsigned(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_q = redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_i[7:0];

    // redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem(DUALMEM,31317)
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_ia = $unsigned(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_inputreg0_q);
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_aa = redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_wraddr_q;
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_ab = redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_aa),
        .data_a(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_ab),
        .q_b(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_q = redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_iq[15:0];

    // redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_outputreg0(DELAY,31316)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_outputreg0_q <= $unsigned(redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_mem_q);
        end
    end

    // valid_fanout_reg80(REG,13375)@243 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg80_q <= $unsigned(redist847_sync_together4364_aunroll_x_in_i_valid_175_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_66195_c_compmm_m81(BLACKBOX,8734)@244
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66195_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_66195_c_compmm_m81 (
        .in_intel_reserved_ffwd_177_0(in_intel_reserved_ffwd_177_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg80_q),
        .out_dest_data_out_177_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_66195_c_compmm_m81_out_dest_data_out_177_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28959)@244 + 5
    // out q@250
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_66195_c_compmm_m81_out_dest_data_out_177_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_66196_c_compmm_m80_out_dest_data_out_178_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742(ADD,9060)@250
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod722_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_b = $unsigned({{5{i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_88_c_compmm_m2741_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_o[33:0];

    // rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x(MUX,21327)@250
    assign rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q or rightShiftStage0Idx1_uid21326_dupName_353_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q;
            1'b1 : rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21326_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x(MUX,21332)@250
    assign rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21331_dupName_353_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21328_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21331_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x(MUX,21337)@250
    assign rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21336_dupName_353_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21333_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21336_dupName_353_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2743_vt_select_20(BITSELECT,11597)@250
    assign i_unnamed_c_compmm_m2743_vt_select_20_b = rightShiftStage2_uid21338_dupName_353_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2743_vt_join(BITJOIN,11596)@250
    assign i_unnamed_c_compmm_m2743_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2743_vt_select_20_b};

    // i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x(BITSELECT,3818)@250
    assign i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x_b = i_unnamed_c_compmm_m2743_vt_join_q[15:0];

    // redist900_i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x_b_1(DELAY,30028)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist900_i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21347_dupName_354_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21346)@250
    assign rightShiftStage1Idx1Rng8_uid21347_dupName_354_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21349_dupName_354_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21348)@250
    assign rightShiftStage1Idx1_uid21349_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21347_dupName_354_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21342_dupName_354_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21341)@250
    assign rightShiftStage0Idx1Rng4_uid21342_dupName_354_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q[33:4];

    // rightShiftStage0Idx1_uid21344_dupName_354_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21343)@250
    assign rightShiftStage0Idx1_uid21344_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21342_dupName_354_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x(MUX,21345)@250
    assign rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q or rightShiftStage0Idx1_uid21344_dupName_354_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_88_i_c_compmm_m2742_q;
            1'b1 : rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21344_dupName_354_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x(MUX,21350)@250
    assign rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21349_dupName_354_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21346_dupName_354_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21349_dupName_354_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2745_vt_select_21(BITSELECT,11600)@250
    assign i_unnamed_c_compmm_m2745_vt_select_21_b = rightShiftStage1_uid21351_dupName_354_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2745_vt_join(BITJOIN,11599)@250
    assign i_unnamed_c_compmm_m2745_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2745_vt_select_21_b};

    // i_unnamed_c_compmm_m2746_sel_x(BITSELECT,6129)@250
    assign i_unnamed_c_compmm_m2746_sel_x_b = i_unnamed_c_compmm_m2745_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2747_BitSelect_for_a(BITSELECT,28610)@250
    assign i_unnamed_c_compmm_m2747_BitSelect_for_a_b = i_unnamed_c_compmm_m2746_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2747_join(BITJOIN,28611)@250
    assign i_unnamed_c_compmm_m2747_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2747_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2747_vt_select_0(BITSELECT,11605)@250
    assign i_unnamed_c_compmm_m2747_vt_select_0_b = i_unnamed_c_compmm_m2747_join_q[0:0];

    // redist130_i_unnamed_c_compmm_m2747_vt_select_0_b_1(DELAY,29258)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist130_i_unnamed_c_compmm_m2747_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2747_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2747_vt_join(BITJOIN,11604)@251
    assign i_unnamed_c_compmm_m2747_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist130_i_unnamed_c_compmm_m2747_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_88_c_compmm_m2748(ADD,7273)@251
    assign i_add_i_i_i_i_i_i_88_c_compmm_m2748_a = {1'b0, i_unnamed_c_compmm_m2747_vt_join_q};
    assign i_add_i_i_i_i_i_i_88_c_compmm_m2748_b = {1'b0, redist900_i_conv_i_i_i_i_i_88_c_compmm_m2744_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_88_c_compmm_m2748_o = $unsigned(i_add_i_i_i_i_i_i_88_c_compmm_m2748_a) + $unsigned(i_add_i_i_i_i_i_i_88_c_compmm_m2748_b);
    assign i_add_i_i_i_i_i_i_88_c_compmm_m2748_q = i_add_i_i_i_i_i_i_88_c_compmm_m2748_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_88_c_compmm_m2748_sel_x(BITSELECT,2287)@251
    assign bgTrunc_i_add_i_i_i_i_i_i_88_c_compmm_m2748_sel_x_b = i_add_i_i_i_i_i_i_88_c_compmm_m2748_q[15:0];

    // i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_sel_x(BITSELECT,3947)@251
    assign i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_88_c_compmm_m2748_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_select_15(BITSELECT,8515)@251
    assign i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_select_15_b = i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_join(BITJOIN,8514)@251
    assign i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_select_15_b};

    // leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(MUX,28114)@251
    assign leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_join_q or leftShiftStage0Idx1_uid28113_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_89_c_compmm_m2768_vt_join_q;
            1'b1 : leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28113_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(MUX,28119)@251
    assign leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s or leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28118_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = leftShiftStage0_uid28115_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28118_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x(MUX,28124)@251
    assign leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s or leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28123_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = leftShiftStage1_uid28120_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28123_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28(BITSELECT,10183)@251
    assign i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28_b = leftShiftStage2_uid28125_i_shl_i_i_i_i_i_i_89_c_compmm_m0_shift_x_q[28:13];

    // redist266_i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28_b_1(DELAY,29394)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist266_i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_join(BITJOIN,10182)@252
    assign i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_join_q = {redist266_i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg77(REG,13372)@245 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg77_q <= $unsigned(redist848_sync_together4364_aunroll_x_in_i_valid_177_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_66198_c_compmm_m78(BLACKBOX,8750)@246
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66198_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_66198_c_compmm_m78 (
        .in_intel_reserved_ffwd_180_0(in_intel_reserved_ffwd_180_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg77_q),
        .out_dest_data_out_180_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_66198_c_compmm_m78_out_dest_data_out_180_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_offset(CONSTANT,31325)
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_offset_q = $unsigned(8'b01010011);

    // redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt(ADD,31326)
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_a = {1'b0, redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_q};
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_b = {1'b0, redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_o <= $unsigned(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_a) + $unsigned(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_b);
        end
    end
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_q = redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_o[8:0];

    // redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_inputreg0(DELAY,31321)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_inputreg0_q <= $unsigned(in_c1_eni5_179_tpl);
        end
    end

    // redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr(COUNTER,31324)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_i <= $unsigned(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_q = redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_i[7:0];

    // redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem(DUALMEM,31323)
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_ia = $unsigned(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_inputreg0_q);
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_aa = redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_wraddr_q;
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_ab = redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_aa),
        .data_a(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_ab),
        .q_b(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_q = redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_iq[15:0];

    // redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_outputreg0(DELAY,31322)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_outputreg0_q <= $unsigned(redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_mem_q);
        end
    end

    // redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt(ADD,31332)
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_a = {1'b0, redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_q};
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_b = {1'b0, redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_o <= $unsigned(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_a) + $unsigned(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_b);
        end
    end
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_q = redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_o[8:0];

    // redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_inputreg0(DELAY,31327)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_inputreg0_q <= $unsigned(in_c1_eni5_180_tpl);
        end
    end

    // redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr(COUNTER,31330)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_i <= $unsigned(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_q = redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_i[7:0];

    // redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem(DUALMEM,31329)
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_ia = $unsigned(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_inputreg0_q);
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_aa = redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_wraddr_q;
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_ab = redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_aa),
        .data_a(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_ab),
        .q_b(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_q = redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_iq[15:0];

    // redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_outputreg0(DELAY,31328)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_outputreg0_q <= $unsigned(redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_mem_q);
        end
    end

    // valid_fanout_reg78(REG,13373)@245 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg78_q <= $unsigned(redist848_sync_together4364_aunroll_x_in_i_valid_177_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_66197_c_compmm_m79(BLACKBOX,8746)@246
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66197_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_66197_c_compmm_m79 (
        .in_intel_reserved_ffwd_179_0(in_intel_reserved_ffwd_179_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg78_q),
        .out_dest_data_out_179_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_66197_c_compmm_m79_out_dest_data_out_179_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28960)@246 + 5
    // out q@252
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_66197_c_compmm_m79_out_dest_data_out_179_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_66198_c_compmm_m78_out_dest_data_out_180_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770(ADD,9061)@252
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod727_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_b = $unsigned({{5{i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_89_c_compmm_m2769_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_o[33:0];

    // rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x(MUX,21389)@252
    assign rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q or rightShiftStage0Idx1_uid21388_dupName_357_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q;
            1'b1 : rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21388_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x(MUX,21394)@252
    assign rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21393_dupName_357_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21390_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21393_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x(MUX,21399)@252
    assign rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21398_dupName_357_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21395_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21398_dupName_357_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2771_vt_select_20(BITSELECT,11619)@252
    assign i_unnamed_c_compmm_m2771_vt_select_20_b = rightShiftStage2_uid21400_dupName_357_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2771_vt_join(BITJOIN,11618)@252
    assign i_unnamed_c_compmm_m2771_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2771_vt_select_20_b};

    // i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x(BITSELECT,3819)@252
    assign i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x_b = i_unnamed_c_compmm_m2771_vt_join_q[15:0];

    // redist899_i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x_b_1(DELAY,30027)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist899_i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21409_dupName_358_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21408)@252
    assign rightShiftStage1Idx1Rng8_uid21409_dupName_358_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21411_dupName_358_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21410)@252
    assign rightShiftStage1Idx1_uid21411_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21409_dupName_358_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21404_dupName_358_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21403)@252
    assign rightShiftStage0Idx1Rng4_uid21404_dupName_358_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q[33:4];

    // rightShiftStage0Idx1_uid21406_dupName_358_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21405)@252
    assign rightShiftStage0Idx1_uid21406_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21404_dupName_358_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x(MUX,21407)@252
    assign rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q or rightShiftStage0Idx1_uid21406_dupName_358_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_89_i_c_compmm_m2770_q;
            1'b1 : rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21406_dupName_358_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x(MUX,21412)@252
    assign rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21411_dupName_358_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21408_dupName_358_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21411_dupName_358_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2773_vt_select_21(BITSELECT,11622)@252
    assign i_unnamed_c_compmm_m2773_vt_select_21_b = rightShiftStage1_uid21413_dupName_358_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2773_vt_join(BITJOIN,11621)@252
    assign i_unnamed_c_compmm_m2773_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2773_vt_select_21_b};

    // i_unnamed_c_compmm_m2774_sel_x(BITSELECT,6131)@252
    assign i_unnamed_c_compmm_m2774_sel_x_b = i_unnamed_c_compmm_m2773_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2775_BitSelect_for_a(BITSELECT,28614)@252
    assign i_unnamed_c_compmm_m2775_BitSelect_for_a_b = i_unnamed_c_compmm_m2774_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2775_join(BITJOIN,28615)@252
    assign i_unnamed_c_compmm_m2775_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2775_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2775_vt_select_0(BITSELECT,11627)@252
    assign i_unnamed_c_compmm_m2775_vt_select_0_b = i_unnamed_c_compmm_m2775_join_q[0:0];

    // redist128_i_unnamed_c_compmm_m2775_vt_select_0_b_1(DELAY,29256)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist128_i_unnamed_c_compmm_m2775_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2775_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2775_vt_join(BITJOIN,11626)@253
    assign i_unnamed_c_compmm_m2775_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist128_i_unnamed_c_compmm_m2775_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_89_c_compmm_m2776(ADD,7274)@253
    assign i_add_i_i_i_i_i_i_89_c_compmm_m2776_a = {1'b0, i_unnamed_c_compmm_m2775_vt_join_q};
    assign i_add_i_i_i_i_i_i_89_c_compmm_m2776_b = {1'b0, redist899_i_conv_i_i_i_i_i_89_c_compmm_m2772_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_89_c_compmm_m2776_o = $unsigned(i_add_i_i_i_i_i_i_89_c_compmm_m2776_a) + $unsigned(i_add_i_i_i_i_i_i_89_c_compmm_m2776_b);
    assign i_add_i_i_i_i_i_i_89_c_compmm_m2776_q = i_add_i_i_i_i_i_i_89_c_compmm_m2776_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_89_c_compmm_m2776_sel_x(BITSELECT,2288)@253
    assign bgTrunc_i_add_i_i_i_i_i_i_89_c_compmm_m2776_sel_x_b = i_add_i_i_i_i_i_i_89_c_compmm_m2776_q[15:0];

    // i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_sel_x(BITSELECT,3949)@253
    assign i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_89_c_compmm_m2776_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_select_15(BITSELECT,8523)@253
    assign i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_select_15_b = i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_join(BITJOIN,8522)@253
    assign i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_select_15_b};

    // leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(MUX,28150)@253
    assign leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_join_q or leftShiftStage0Idx1_uid28149_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_90_c_compmm_m2796_vt_join_q;
            1'b1 : leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28149_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(MUX,28155)@253
    assign leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s or leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28154_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = leftShiftStage0_uid28151_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28154_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x(MUX,28160)@253
    assign leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s or leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28159_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = leftShiftStage1_uid28156_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28159_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28(BITSELECT,10189)@253
    assign i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28_b = leftShiftStage2_uid28161_i_shl_i_i_i_i_i_i_90_c_compmm_m0_shift_x_q[28:13];

    // redist264_i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28_b_1(DELAY,29392)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist264_i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_join(BITJOIN,10188)@254
    assign i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_join_q = {redist264_i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg75(REG,13370)@247 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg75_q <= $unsigned(redist849_sync_together4364_aunroll_x_in_i_valid_179_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_66200_c_compmm_m76(BLACKBOX,8758)@248
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66200_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_66200_c_compmm_m76 (
        .in_intel_reserved_ffwd_182_0(in_intel_reserved_ffwd_182_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg75_q),
        .out_dest_data_out_182_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_66200_c_compmm_m76_out_dest_data_out_182_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_offset(CONSTANT,31337)
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_offset_q = $unsigned(8'b01010001);

    // redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt(ADD,31338)
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_a = {1'b0, redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_q};
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_b = {1'b0, redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_o <= $unsigned(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_a) + $unsigned(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_b);
        end
    end
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_q = redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_o[8:0];

    // redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_inputreg0(DELAY,31333)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_inputreg0_q <= $unsigned(in_c1_eni5_181_tpl);
        end
    end

    // redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr(COUNTER,31336)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_i <= $unsigned(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_q = redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_i[7:0];

    // redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem(DUALMEM,31335)
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_ia = $unsigned(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_inputreg0_q);
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_aa = redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_wraddr_q;
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_ab = redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_aa),
        .data_a(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_ab),
        .q_b(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_q = redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_iq[15:0];

    // redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_outputreg0(DELAY,31334)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_outputreg0_q <= $unsigned(redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_mem_q);
        end
    end

    // redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt(ADD,31344)
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_a = {1'b0, redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_q};
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_b = {1'b0, redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_o <= $unsigned(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_a) + $unsigned(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_b);
        end
    end
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_q = redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_o[8:0];

    // redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_inputreg0(DELAY,31339)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_inputreg0_q <= $unsigned(in_c1_eni5_182_tpl);
        end
    end

    // redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr(COUNTER,31342)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_i <= $unsigned(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_q = redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_i[7:0];

    // redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem(DUALMEM,31341)
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_ia = $unsigned(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_inputreg0_q);
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_aa = redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_wraddr_q;
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_ab = redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_aa),
        .data_a(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_ab),
        .q_b(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_q = redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_iq[15:0];

    // redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_outputreg0(DELAY,31340)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_outputreg0_q <= $unsigned(redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_mem_q);
        end
    end

    // valid_fanout_reg76(REG,13371)@247 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg76_q <= $unsigned(redist849_sync_together4364_aunroll_x_in_i_valid_179_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_66199_c_compmm_m77(BLACKBOX,8754)@248
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66199_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_66199_c_compmm_m77 (
        .in_intel_reserved_ffwd_181_0(in_intel_reserved_ffwd_181_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg76_q),
        .out_dest_data_out_181_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_66199_c_compmm_m77_out_dest_data_out_181_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28961)@248 + 5
    // out q@254
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_66199_c_compmm_m77_out_dest_data_out_181_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_66200_c_compmm_m76_out_dest_data_out_182_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798(ADD,9063)@254
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod732_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_b = $unsigned({{5{i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_90_c_compmm_m2797_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_o[33:0];

    // rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x(MUX,21451)@254
    assign rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q or rightShiftStage0Idx1_uid21450_dupName_361_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q;
            1'b1 : rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21450_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x(MUX,21456)@254
    assign rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21455_dupName_361_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21452_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21455_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x(MUX,21461)@254
    assign rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21460_dupName_361_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21457_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21460_dupName_361_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2799_vt_select_20(BITSELECT,11644)@254
    assign i_unnamed_c_compmm_m2799_vt_select_20_b = rightShiftStage2_uid21462_dupName_361_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2799_vt_join(BITJOIN,11643)@254
    assign i_unnamed_c_compmm_m2799_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2799_vt_select_20_b};

    // i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x(BITSELECT,3821)@254
    assign i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x_b = i_unnamed_c_compmm_m2799_vt_join_q[15:0];

    // redist897_i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x_b_1(DELAY,30025)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist897_i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21471_dupName_362_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21470)@254
    assign rightShiftStage1Idx1Rng8_uid21471_dupName_362_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21473_dupName_362_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21472)@254
    assign rightShiftStage1Idx1_uid21473_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21471_dupName_362_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21466_dupName_362_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21465)@254
    assign rightShiftStage0Idx1Rng4_uid21466_dupName_362_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q[33:4];

    // rightShiftStage0Idx1_uid21468_dupName_362_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21467)@254
    assign rightShiftStage0Idx1_uid21468_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21466_dupName_362_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x(MUX,21469)@254
    assign rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q or rightShiftStage0Idx1_uid21468_dupName_362_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_90_i_c_compmm_m2798_q;
            1'b1 : rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21468_dupName_362_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x(MUX,21474)@254
    assign rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21473_dupName_362_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21470_dupName_362_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21473_dupName_362_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2801_vt_select_21(BITSELECT,11650)@254
    assign i_unnamed_c_compmm_m2801_vt_select_21_b = rightShiftStage1_uid21475_dupName_362_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2801_vt_join(BITJOIN,11649)@254
    assign i_unnamed_c_compmm_m2801_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2801_vt_select_21_b};

    // i_unnamed_c_compmm_m2802_sel_x(BITSELECT,6134)@254
    assign i_unnamed_c_compmm_m2802_sel_x_b = i_unnamed_c_compmm_m2801_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2803_BitSelect_for_a(BITSELECT,28618)@254
    assign i_unnamed_c_compmm_m2803_BitSelect_for_a_b = i_unnamed_c_compmm_m2802_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2803_join(BITJOIN,28619)@254
    assign i_unnamed_c_compmm_m2803_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2803_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2803_vt_select_0(BITSELECT,11655)@254
    assign i_unnamed_c_compmm_m2803_vt_select_0_b = i_unnamed_c_compmm_m2803_join_q[0:0];

    // redist126_i_unnamed_c_compmm_m2803_vt_select_0_b_1(DELAY,29254)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist126_i_unnamed_c_compmm_m2803_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2803_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2803_vt_join(BITJOIN,11654)@255
    assign i_unnamed_c_compmm_m2803_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist126_i_unnamed_c_compmm_m2803_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_90_c_compmm_m2804(ADD,7276)@255
    assign i_add_i_i_i_i_i_i_90_c_compmm_m2804_a = {1'b0, i_unnamed_c_compmm_m2803_vt_join_q};
    assign i_add_i_i_i_i_i_i_90_c_compmm_m2804_b = {1'b0, redist897_i_conv_i_i_i_i_i_90_c_compmm_m2800_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_90_c_compmm_m2804_o = $unsigned(i_add_i_i_i_i_i_i_90_c_compmm_m2804_a) + $unsigned(i_add_i_i_i_i_i_i_90_c_compmm_m2804_b);
    assign i_add_i_i_i_i_i_i_90_c_compmm_m2804_q = i_add_i_i_i_i_i_i_90_c_compmm_m2804_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_90_c_compmm_m2804_sel_x(BITSELECT,2290)@255
    assign bgTrunc_i_add_i_i_i_i_i_i_90_c_compmm_m2804_sel_x_b = i_add_i_i_i_i_i_i_90_c_compmm_m2804_q[15:0];

    // i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_sel_x(BITSELECT,3950)@255
    assign i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_90_c_compmm_m2804_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_select_15(BITSELECT,8527)@255
    assign i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_select_15_b = i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_join(BITJOIN,8526)@255
    assign i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_select_15_b};

    // leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(MUX,28168)@255
    assign leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_join_q or leftShiftStage0Idx1_uid28167_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_91_c_compmm_m2824_vt_join_q;
            1'b1 : leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28167_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(MUX,28173)@255
    assign leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s or leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28172_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = leftShiftStage0_uid28169_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28172_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x(MUX,28178)@255
    assign leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s or leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28177_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = leftShiftStage1_uid28174_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28177_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28(BITSELECT,10192)@255
    assign i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28_b = leftShiftStage2_uid28179_i_shl_i_i_i_i_i_i_91_c_compmm_m0_shift_x_q[28:13];

    // redist263_i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28_b_1(DELAY,29391)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist263_i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_join(BITJOIN,10191)@256
    assign i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_join_q = {redist263_i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg73(REG,13368)@249 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg73_q <= $unsigned(redist850_sync_together4364_aunroll_x_in_i_valid_181_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_66202_c_compmm_m74(BLACKBOX,8766)@250
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66202_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_66202_c_compmm_m74 (
        .in_intel_reserved_ffwd_184_0(in_intel_reserved_ffwd_184_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg73_q),
        .out_dest_data_out_184_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_66202_c_compmm_m74_out_dest_data_out_184_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_offset(CONSTANT,31349)
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_offset_q = $unsigned(8'b01001111);

    // redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt(ADD,31350)
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_a = {1'b0, redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_q};
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_b = {1'b0, redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_o <= $unsigned(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_a) + $unsigned(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_b);
        end
    end
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_q = redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_o[8:0];

    // redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_inputreg0(DELAY,31345)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_inputreg0_q <= $unsigned(in_c1_eni5_183_tpl);
        end
    end

    // redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr(COUNTER,31348)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_i <= $unsigned(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_q = redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_i[7:0];

    // redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem(DUALMEM,31347)
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_ia = $unsigned(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_inputreg0_q);
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_aa = redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_wraddr_q;
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_ab = redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_aa),
        .data_a(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_ab),
        .q_b(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_q = redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_iq[15:0];

    // redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_outputreg0(DELAY,31346)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_outputreg0_q <= $unsigned(redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_mem_q);
        end
    end

    // redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt(ADD,31356)
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_a = {1'b0, redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_q};
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_b = {1'b0, redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_o <= $unsigned(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_a) + $unsigned(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_b);
        end
    end
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_q = redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_o[8:0];

    // redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_inputreg0(DELAY,31351)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_inputreg0_q <= $unsigned(in_c1_eni5_184_tpl);
        end
    end

    // redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr(COUNTER,31354)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_i <= $unsigned(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_q = redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_i[7:0];

    // redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem(DUALMEM,31353)
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_ia = $unsigned(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_inputreg0_q);
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_aa = redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_wraddr_q;
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_ab = redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_aa),
        .data_a(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_ab),
        .q_b(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_q = redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_iq[15:0];

    // redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_outputreg0(DELAY,31352)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_outputreg0_q <= $unsigned(redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_mem_q);
        end
    end

    // valid_fanout_reg74(REG,13369)@249 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg74_q <= $unsigned(redist850_sync_together4364_aunroll_x_in_i_valid_181_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_66201_c_compmm_m75(BLACKBOX,8762)@250
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66201_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_66201_c_compmm_m75 (
        .in_intel_reserved_ffwd_183_0(in_intel_reserved_ffwd_183_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg74_q),
        .out_dest_data_out_183_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_66201_c_compmm_m75_out_dest_data_out_183_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28962)@250 + 5
    // out q@256
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_66201_c_compmm_m75_out_dest_data_out_183_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_66202_c_compmm_m74_out_dest_data_out_184_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826(ADD,9064)@256
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod737_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_b = $unsigned({{5{i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_91_c_compmm_m2825_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_o[33:0];

    // rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x(MUX,21513)@256
    assign rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q or rightShiftStage0Idx1_uid21512_dupName_365_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q;
            1'b1 : rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21512_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x(MUX,21518)@256
    assign rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21517_dupName_365_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21514_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21517_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x(MUX,21523)@256
    assign rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21522_dupName_365_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21519_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21522_dupName_365_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2827_vt_select_20(BITSELECT,11674)@256
    assign i_unnamed_c_compmm_m2827_vt_select_20_b = rightShiftStage2_uid21524_dupName_365_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2827_vt_join(BITJOIN,11673)@256
    assign i_unnamed_c_compmm_m2827_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2827_vt_select_20_b};

    // i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x(BITSELECT,3822)@256
    assign i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x_b = i_unnamed_c_compmm_m2827_vt_join_q[15:0];

    // redist896_i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x_b_1(DELAY,30024)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist896_i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21533_dupName_366_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21532)@256
    assign rightShiftStage1Idx1Rng8_uid21533_dupName_366_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21535_dupName_366_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21534)@256
    assign rightShiftStage1Idx1_uid21535_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21533_dupName_366_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21528_dupName_366_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21527)@256
    assign rightShiftStage0Idx1Rng4_uid21528_dupName_366_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q[33:4];

    // rightShiftStage0Idx1_uid21530_dupName_366_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21529)@256
    assign rightShiftStage0Idx1_uid21530_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21528_dupName_366_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x(MUX,21531)@256
    assign rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q or rightShiftStage0Idx1_uid21530_dupName_366_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_91_i_c_compmm_m2826_q;
            1'b1 : rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21530_dupName_366_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x(MUX,21536)@256
    assign rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21535_dupName_366_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21532_dupName_366_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21535_dupName_366_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2829_vt_select_21(BITSELECT,11677)@256
    assign i_unnamed_c_compmm_m2829_vt_select_21_b = rightShiftStage1_uid21537_dupName_366_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2829_vt_join(BITJOIN,11676)@256
    assign i_unnamed_c_compmm_m2829_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2829_vt_select_21_b};

    // i_unnamed_c_compmm_m2830_sel_x(BITSELECT,6136)@256
    assign i_unnamed_c_compmm_m2830_sel_x_b = i_unnamed_c_compmm_m2829_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2831_BitSelect_for_a(BITSELECT,28624)@256
    assign i_unnamed_c_compmm_m2831_BitSelect_for_a_b = i_unnamed_c_compmm_m2830_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2831_join(BITJOIN,28625)@256
    assign i_unnamed_c_compmm_m2831_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2831_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2831_vt_select_0(BITSELECT,11682)@256
    assign i_unnamed_c_compmm_m2831_vt_select_0_b = i_unnamed_c_compmm_m2831_join_q[0:0];

    // redist124_i_unnamed_c_compmm_m2831_vt_select_0_b_1(DELAY,29252)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist124_i_unnamed_c_compmm_m2831_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2831_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2831_vt_join(BITJOIN,11681)@257
    assign i_unnamed_c_compmm_m2831_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist124_i_unnamed_c_compmm_m2831_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_91_c_compmm_m2832(ADD,7277)@257
    assign i_add_i_i_i_i_i_i_91_c_compmm_m2832_a = {1'b0, i_unnamed_c_compmm_m2831_vt_join_q};
    assign i_add_i_i_i_i_i_i_91_c_compmm_m2832_b = {1'b0, redist896_i_conv_i_i_i_i_i_91_c_compmm_m2828_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_91_c_compmm_m2832_o = $unsigned(i_add_i_i_i_i_i_i_91_c_compmm_m2832_a) + $unsigned(i_add_i_i_i_i_i_i_91_c_compmm_m2832_b);
    assign i_add_i_i_i_i_i_i_91_c_compmm_m2832_q = i_add_i_i_i_i_i_i_91_c_compmm_m2832_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_91_c_compmm_m2832_sel_x(BITSELECT,2291)@257
    assign bgTrunc_i_add_i_i_i_i_i_i_91_c_compmm_m2832_sel_x_b = i_add_i_i_i_i_i_i_91_c_compmm_m2832_q[15:0];

    // i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_sel_x(BITSELECT,3951)@257
    assign i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_91_c_compmm_m2832_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_select_15(BITSELECT,8531)@257
    assign i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_select_15_b = i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_join(BITJOIN,8530)@257
    assign i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_select_15_b};

    // leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(MUX,28186)@257
    assign leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_join_q or leftShiftStage0Idx1_uid28185_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_92_c_compmm_m2852_vt_join_q;
            1'b1 : leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28185_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(MUX,28191)@257
    assign leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s or leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28190_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = leftShiftStage0_uid28187_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28190_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x(MUX,28196)@257
    assign leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s or leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28195_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = leftShiftStage1_uid28192_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28195_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28(BITSELECT,10195)@257
    assign i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28_b = leftShiftStage2_uid28197_i_shl_i_i_i_i_i_i_92_c_compmm_m0_shift_x_q[28:13];

    // redist262_i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28_b_1(DELAY,29390)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist262_i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_join(BITJOIN,10194)@258
    assign i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_join_q = {redist262_i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg71(REG,13366)@251 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg71_q <= $unsigned(redist851_sync_together4364_aunroll_x_in_i_valid_183_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_66204_c_compmm_m72(BLACKBOX,8774)@252
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66204_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_66204_c_compmm_m72 (
        .in_intel_reserved_ffwd_186_0(in_intel_reserved_ffwd_186_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg71_q),
        .out_dest_data_out_186_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_66204_c_compmm_m72_out_dest_data_out_186_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_offset(CONSTANT,31361)
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_offset_q = $unsigned(8'b01001101);

    // redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt(ADD,31362)
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_a = {1'b0, redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_q};
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_b = {1'b0, redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_o <= $unsigned(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_a) + $unsigned(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_b);
        end
    end
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_q = redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_o[8:0];

    // redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_inputreg0(DELAY,31357)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_inputreg0_q <= $unsigned(in_c1_eni5_185_tpl);
        end
    end

    // redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr(COUNTER,31360)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_i <= $unsigned(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_q = redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_i[7:0];

    // redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem(DUALMEM,31359)
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_ia = $unsigned(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_inputreg0_q);
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_aa = redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_wraddr_q;
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_ab = redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_aa),
        .data_a(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_ab),
        .q_b(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_q = redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_iq[15:0];

    // redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_outputreg0(DELAY,31358)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_outputreg0_q <= $unsigned(redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_mem_q);
        end
    end

    // redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt(ADD,31368)
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_a = {1'b0, redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_q};
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_b = {1'b0, redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_o <= $unsigned(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_a) + $unsigned(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_b);
        end
    end
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_q = redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_o[8:0];

    // redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_inputreg0(DELAY,31363)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_inputreg0_q <= $unsigned(in_c1_eni5_186_tpl);
        end
    end

    // redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr(COUNTER,31366)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_i <= $unsigned(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_q = redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_i[7:0];

    // redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem(DUALMEM,31365)
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_ia = $unsigned(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_inputreg0_q);
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_aa = redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_wraddr_q;
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_ab = redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_aa),
        .data_a(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_ab),
        .q_b(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_q = redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_iq[15:0];

    // redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_outputreg0(DELAY,31364)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_outputreg0_q <= $unsigned(redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_mem_q);
        end
    end

    // valid_fanout_reg72(REG,13367)@251 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg72_q <= $unsigned(redist851_sync_together4364_aunroll_x_in_i_valid_183_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_66203_c_compmm_m73(BLACKBOX,8770)@252
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66203_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_66203_c_compmm_m73 (
        .in_intel_reserved_ffwd_185_0(in_intel_reserved_ffwd_185_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg72_q),
        .out_dest_data_out_185_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_66203_c_compmm_m73_out_dest_data_out_185_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28963)@252 + 5
    // out q@258
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_66203_c_compmm_m73_out_dest_data_out_185_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_66204_c_compmm_m72_out_dest_data_out_186_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854(ADD,9065)@258
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod742_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_b = $unsigned({{5{i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_92_c_compmm_m2853_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_o[33:0];

    // rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x(MUX,21575)@258
    assign rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q or rightShiftStage0Idx1_uid21574_dupName_369_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q;
            1'b1 : rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21574_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x(MUX,21580)@258
    assign rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21579_dupName_369_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21576_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21579_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x(MUX,21585)@258
    assign rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21584_dupName_369_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21581_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21584_dupName_369_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2855_vt_select_20(BITSELECT,11696)@258
    assign i_unnamed_c_compmm_m2855_vt_select_20_b = rightShiftStage2_uid21586_dupName_369_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2855_vt_join(BITJOIN,11695)@258
    assign i_unnamed_c_compmm_m2855_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2855_vt_select_20_b};

    // i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x(BITSELECT,3823)@258
    assign i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x_b = i_unnamed_c_compmm_m2855_vt_join_q[15:0];

    // redist895_i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x_b_1(DELAY,30023)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist895_i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21595_dupName_370_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21594)@258
    assign rightShiftStage1Idx1Rng8_uid21595_dupName_370_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21597_dupName_370_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21596)@258
    assign rightShiftStage1Idx1_uid21597_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21595_dupName_370_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21590_dupName_370_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21589)@258
    assign rightShiftStage0Idx1Rng4_uid21590_dupName_370_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q[33:4];

    // rightShiftStage0Idx1_uid21592_dupName_370_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21591)@258
    assign rightShiftStage0Idx1_uid21592_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21590_dupName_370_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x(MUX,21593)@258
    assign rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q or rightShiftStage0Idx1_uid21592_dupName_370_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_92_i_c_compmm_m2854_q;
            1'b1 : rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21592_dupName_370_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x(MUX,21598)@258
    assign rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21597_dupName_370_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21594_dupName_370_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21597_dupName_370_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2857_vt_select_21(BITSELECT,11699)@258
    assign i_unnamed_c_compmm_m2857_vt_select_21_b = rightShiftStage1_uid21599_dupName_370_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2857_vt_join(BITJOIN,11698)@258
    assign i_unnamed_c_compmm_m2857_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2857_vt_select_21_b};

    // i_unnamed_c_compmm_m2858_sel_x(BITSELECT,6138)@258
    assign i_unnamed_c_compmm_m2858_sel_x_b = i_unnamed_c_compmm_m2857_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2859_BitSelect_for_a(BITSELECT,28628)@258
    assign i_unnamed_c_compmm_m2859_BitSelect_for_a_b = i_unnamed_c_compmm_m2858_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2859_join(BITJOIN,28629)@258
    assign i_unnamed_c_compmm_m2859_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2859_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2859_vt_select_0(BITSELECT,11704)@258
    assign i_unnamed_c_compmm_m2859_vt_select_0_b = i_unnamed_c_compmm_m2859_join_q[0:0];

    // redist122_i_unnamed_c_compmm_m2859_vt_select_0_b_1(DELAY,29250)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist122_i_unnamed_c_compmm_m2859_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2859_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2859_vt_join(BITJOIN,11703)@259
    assign i_unnamed_c_compmm_m2859_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist122_i_unnamed_c_compmm_m2859_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_92_c_compmm_m2860(ADD,7278)@259
    assign i_add_i_i_i_i_i_i_92_c_compmm_m2860_a = {1'b0, i_unnamed_c_compmm_m2859_vt_join_q};
    assign i_add_i_i_i_i_i_i_92_c_compmm_m2860_b = {1'b0, redist895_i_conv_i_i_i_i_i_92_c_compmm_m2856_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_92_c_compmm_m2860_o = $unsigned(i_add_i_i_i_i_i_i_92_c_compmm_m2860_a) + $unsigned(i_add_i_i_i_i_i_i_92_c_compmm_m2860_b);
    assign i_add_i_i_i_i_i_i_92_c_compmm_m2860_q = i_add_i_i_i_i_i_i_92_c_compmm_m2860_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_92_c_compmm_m2860_sel_x(BITSELECT,2292)@259
    assign bgTrunc_i_add_i_i_i_i_i_i_92_c_compmm_m2860_sel_x_b = i_add_i_i_i_i_i_i_92_c_compmm_m2860_q[15:0];

    // i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_sel_x(BITSELECT,3952)@259
    assign i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_92_c_compmm_m2860_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_select_15(BITSELECT,8535)@259
    assign i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_select_15_b = i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_join(BITJOIN,8534)@259
    assign i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_select_15_b};

    // leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(MUX,28204)@259
    assign leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_join_q or leftShiftStage0Idx1_uid28203_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_93_c_compmm_m2880_vt_join_q;
            1'b1 : leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28203_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(MUX,28209)@259
    assign leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s or leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28208_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = leftShiftStage0_uid28205_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28208_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x(MUX,28214)@259
    assign leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s or leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28213_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = leftShiftStage1_uid28210_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28213_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28(BITSELECT,10198)@259
    assign i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28_b = leftShiftStage2_uid28215_i_shl_i_i_i_i_i_i_93_c_compmm_m0_shift_x_q[28:13];

    // redist261_i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28_b_1(DELAY,29389)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist261_i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_join(BITJOIN,10197)@260
    assign i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_join_q = {redist261_i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg69(REG,13364)@253 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg69_q <= $unsigned(redist852_sync_together4364_aunroll_x_in_i_valid_185_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_66206_c_compmm_m70(BLACKBOX,8782)@254
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66206_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_66206_c_compmm_m70 (
        .in_intel_reserved_ffwd_188_0(in_intel_reserved_ffwd_188_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg69_q),
        .out_dest_data_out_188_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_66206_c_compmm_m70_out_dest_data_out_188_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_offset(CONSTANT,31373)
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_offset_q = $unsigned(8'b01001011);

    // redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt(ADD,31374)
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_a = {1'b0, redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_q};
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_b = {1'b0, redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_o <= $unsigned(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_a) + $unsigned(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_b);
        end
    end
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_q = redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_o[8:0];

    // redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_inputreg0(DELAY,31369)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_inputreg0_q <= $unsigned(in_c1_eni5_187_tpl);
        end
    end

    // redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr(COUNTER,31372)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_i <= $unsigned(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_q = redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_i[7:0];

    // redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem(DUALMEM,31371)
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_ia = $unsigned(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_inputreg0_q);
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_aa = redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_wraddr_q;
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_ab = redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_aa),
        .data_a(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_ab),
        .q_b(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_q = redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_iq[15:0];

    // redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_outputreg0(DELAY,31370)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_outputreg0_q <= $unsigned(redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_mem_q);
        end
    end

    // redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt(ADD,31380)
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_a = {1'b0, redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_q};
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_b = {1'b0, redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_o <= $unsigned(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_a) + $unsigned(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_b);
        end
    end
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_q = redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_o[8:0];

    // redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_inputreg0(DELAY,31375)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_inputreg0_q <= $unsigned(in_c1_eni5_188_tpl);
        end
    end

    // redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr(COUNTER,31378)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_i <= $unsigned(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_q = redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_i[7:0];

    // redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem(DUALMEM,31377)
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_ia = $unsigned(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_inputreg0_q);
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_aa = redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_wraddr_q;
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_ab = redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_aa),
        .data_a(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_ab),
        .q_b(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_q = redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_iq[15:0];

    // redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_outputreg0(DELAY,31376)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_outputreg0_q <= $unsigned(redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_mem_q);
        end
    end

    // valid_fanout_reg70(REG,13365)@253 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg70_q <= $unsigned(redist852_sync_together4364_aunroll_x_in_i_valid_185_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_66205_c_compmm_m71(BLACKBOX,8778)@254
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66205_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_66205_c_compmm_m71 (
        .in_intel_reserved_ffwd_187_0(in_intel_reserved_ffwd_187_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg70_q),
        .out_dest_data_out_187_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_66205_c_compmm_m71_out_dest_data_out_187_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28964)@254 + 5
    // out q@260
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_66205_c_compmm_m71_out_dest_data_out_187_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_66206_c_compmm_m70_out_dest_data_out_188_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882(ADD,9066)@260
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod747_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_b = $unsigned({{5{i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_93_c_compmm_m2881_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_o[33:0];

    // rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x(MUX,21637)@260
    assign rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q or rightShiftStage0Idx1_uid21636_dupName_373_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q;
            1'b1 : rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21636_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x(MUX,21642)@260
    assign rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21641_dupName_373_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21638_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21641_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x(MUX,21647)@260
    assign rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21646_dupName_373_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21643_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21646_dupName_373_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2883_vt_select_20(BITSELECT,11718)@260
    assign i_unnamed_c_compmm_m2883_vt_select_20_b = rightShiftStage2_uid21648_dupName_373_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2883_vt_join(BITJOIN,11717)@260
    assign i_unnamed_c_compmm_m2883_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2883_vt_select_20_b};

    // i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x(BITSELECT,3824)@260
    assign i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x_b = i_unnamed_c_compmm_m2883_vt_join_q[15:0];

    // redist894_i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x_b_1(DELAY,30022)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist894_i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21657_dupName_374_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21656)@260
    assign rightShiftStage1Idx1Rng8_uid21657_dupName_374_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21659_dupName_374_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21658)@260
    assign rightShiftStage1Idx1_uid21659_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21657_dupName_374_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21652_dupName_374_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21651)@260
    assign rightShiftStage0Idx1Rng4_uid21652_dupName_374_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q[33:4];

    // rightShiftStage0Idx1_uid21654_dupName_374_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21653)@260
    assign rightShiftStage0Idx1_uid21654_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21652_dupName_374_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x(MUX,21655)@260
    assign rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q or rightShiftStage0Idx1_uid21654_dupName_374_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_93_i_c_compmm_m2882_q;
            1'b1 : rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21654_dupName_374_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x(MUX,21660)@260
    assign rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21659_dupName_374_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21656_dupName_374_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21659_dupName_374_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2885_vt_select_21(BITSELECT,11721)@260
    assign i_unnamed_c_compmm_m2885_vt_select_21_b = rightShiftStage1_uid21661_dupName_374_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2885_vt_join(BITJOIN,11720)@260
    assign i_unnamed_c_compmm_m2885_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2885_vt_select_21_b};

    // i_unnamed_c_compmm_m2886_sel_x(BITSELECT,6140)@260
    assign i_unnamed_c_compmm_m2886_sel_x_b = i_unnamed_c_compmm_m2885_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2887_BitSelect_for_a(BITSELECT,28632)@260
    assign i_unnamed_c_compmm_m2887_BitSelect_for_a_b = i_unnamed_c_compmm_m2886_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2887_join(BITJOIN,28633)@260
    assign i_unnamed_c_compmm_m2887_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2887_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2887_vt_select_0(BITSELECT,11726)@260
    assign i_unnamed_c_compmm_m2887_vt_select_0_b = i_unnamed_c_compmm_m2887_join_q[0:0];

    // redist120_i_unnamed_c_compmm_m2887_vt_select_0_b_1(DELAY,29248)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist120_i_unnamed_c_compmm_m2887_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2887_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2887_vt_join(BITJOIN,11725)@261
    assign i_unnamed_c_compmm_m2887_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist120_i_unnamed_c_compmm_m2887_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_93_c_compmm_m2888(ADD,7279)@261
    assign i_add_i_i_i_i_i_i_93_c_compmm_m2888_a = {1'b0, i_unnamed_c_compmm_m2887_vt_join_q};
    assign i_add_i_i_i_i_i_i_93_c_compmm_m2888_b = {1'b0, redist894_i_conv_i_i_i_i_i_93_c_compmm_m2884_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_93_c_compmm_m2888_o = $unsigned(i_add_i_i_i_i_i_i_93_c_compmm_m2888_a) + $unsigned(i_add_i_i_i_i_i_i_93_c_compmm_m2888_b);
    assign i_add_i_i_i_i_i_i_93_c_compmm_m2888_q = i_add_i_i_i_i_i_i_93_c_compmm_m2888_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_93_c_compmm_m2888_sel_x(BITSELECT,2293)@261
    assign bgTrunc_i_add_i_i_i_i_i_i_93_c_compmm_m2888_sel_x_b = i_add_i_i_i_i_i_i_93_c_compmm_m2888_q[15:0];

    // i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_sel_x(BITSELECT,3953)@261
    assign i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_93_c_compmm_m2888_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_select_15(BITSELECT,8539)@261
    assign i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_select_15_b = i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_join(BITJOIN,8538)@261
    assign i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_select_15_b};

    // leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(MUX,28222)@261
    assign leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_join_q or leftShiftStage0Idx1_uid28221_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_94_c_compmm_m2908_vt_join_q;
            1'b1 : leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28221_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(MUX,28227)@261
    assign leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s or leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28226_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = leftShiftStage0_uid28223_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28226_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x(MUX,28232)@261
    assign leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s or leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28231_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = leftShiftStage1_uid28228_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28231_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28(BITSELECT,10201)@261
    assign i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28_b = leftShiftStage2_uid28233_i_shl_i_i_i_i_i_i_94_c_compmm_m0_shift_x_q[28:13];

    // redist260_i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28_b_1(DELAY,29388)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist260_i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_join(BITJOIN,10200)@262
    assign i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_join_q = {redist260_i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg67(REG,13362)@255 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg67_q <= $unsigned(redist853_sync_together4364_aunroll_x_in_i_valid_187_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_66208_c_compmm_m68(BLACKBOX,8794)@256
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66208_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_66208_c_compmm_m68 (
        .in_intel_reserved_ffwd_190_0(in_intel_reserved_ffwd_190_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg67_q),
        .out_dest_data_out_190_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_66208_c_compmm_m68_out_dest_data_out_190_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_offset(CONSTANT,31385)
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_offset_q = $unsigned(8'b01001001);

    // redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt(ADD,31386)
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_a = {1'b0, redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_q};
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_b = {1'b0, redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_o <= $unsigned(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_a) + $unsigned(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_b);
        end
    end
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_q = redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_o[8:0];

    // redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_inputreg0(DELAY,31381)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_inputreg0_q <= $unsigned(in_c1_eni5_189_tpl);
        end
    end

    // redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr(COUNTER,31384)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_i <= $unsigned(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_q = redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_i[7:0];

    // redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem(DUALMEM,31383)
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_ia = $unsigned(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_inputreg0_q);
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_aa = redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_wraddr_q;
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_ab = redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_aa),
        .data_a(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_ab),
        .q_b(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_q = redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_iq[15:0];

    // redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_outputreg0(DELAY,31382)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_outputreg0_q <= $unsigned(redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_mem_q);
        end
    end

    // redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt(ADD,31392)
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_a = {1'b0, redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_q};
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_b = {1'b0, redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_o <= $unsigned(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_a) + $unsigned(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_b);
        end
    end
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_q = redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_o[8:0];

    // redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_inputreg0(DELAY,31387)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_inputreg0_q <= $unsigned(in_c1_eni5_190_tpl);
        end
    end

    // redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr(COUNTER,31390)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_i <= $unsigned(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_q = redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_i[7:0];

    // redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem(DUALMEM,31389)
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_ia = $unsigned(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_inputreg0_q);
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_aa = redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_wraddr_q;
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_ab = redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_aa),
        .data_a(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_ab),
        .q_b(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_q = redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_iq[15:0];

    // redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_outputreg0(DELAY,31388)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_outputreg0_q <= $unsigned(redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_mem_q);
        end
    end

    // valid_fanout_reg68(REG,13363)@255 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg68_q <= $unsigned(redist853_sync_together4364_aunroll_x_in_i_valid_187_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_66207_c_compmm_m69(BLACKBOX,8790)@256
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66207_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_66207_c_compmm_m69 (
        .in_intel_reserved_ffwd_189_0(in_intel_reserved_ffwd_189_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg68_q),
        .out_dest_data_out_189_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_66207_c_compmm_m69_out_dest_data_out_189_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28965)@256 + 5
    // out q@262
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_66207_c_compmm_m69_out_dest_data_out_189_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_66208_c_compmm_m68_out_dest_data_out_190_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910(ADD,9067)@262
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod752_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_b = $unsigned({{5{i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_94_c_compmm_m2909_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_o[33:0];

    // rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x(MUX,21699)@262
    assign rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q or rightShiftStage0Idx1_uid21698_dupName_377_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q;
            1'b1 : rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21698_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x(MUX,21704)@262
    assign rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21703_dupName_377_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21700_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21703_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x(MUX,21709)@262
    assign rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21708_dupName_377_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21705_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21708_dupName_377_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2911_vt_select_20(BITSELECT,11743)@262
    assign i_unnamed_c_compmm_m2911_vt_select_20_b = rightShiftStage2_uid21710_dupName_377_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2911_vt_join(BITJOIN,11742)@262
    assign i_unnamed_c_compmm_m2911_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2911_vt_select_20_b};

    // i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x(BITSELECT,3825)@262
    assign i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x_b = i_unnamed_c_compmm_m2911_vt_join_q[15:0];

    // redist893_i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x_b_1(DELAY,30021)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist893_i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21719_dupName_378_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21718)@262
    assign rightShiftStage1Idx1Rng8_uid21719_dupName_378_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21721_dupName_378_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21720)@262
    assign rightShiftStage1Idx1_uid21721_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21719_dupName_378_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21714_dupName_378_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21713)@262
    assign rightShiftStage0Idx1Rng4_uid21714_dupName_378_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q[33:4];

    // rightShiftStage0Idx1_uid21716_dupName_378_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21715)@262
    assign rightShiftStage0Idx1_uid21716_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21714_dupName_378_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x(MUX,21717)@262
    assign rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q or rightShiftStage0Idx1_uid21716_dupName_378_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_94_i_c_compmm_m2910_q;
            1'b1 : rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21716_dupName_378_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x(MUX,21722)@262
    assign rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21721_dupName_378_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21718_dupName_378_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21721_dupName_378_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2913_vt_select_21(BITSELECT,11746)@262
    assign i_unnamed_c_compmm_m2913_vt_select_21_b = rightShiftStage1_uid21723_dupName_378_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2913_vt_join(BITJOIN,11745)@262
    assign i_unnamed_c_compmm_m2913_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2913_vt_select_21_b};

    // i_unnamed_c_compmm_m2914_sel_x(BITSELECT,6142)@262
    assign i_unnamed_c_compmm_m2914_sel_x_b = i_unnamed_c_compmm_m2913_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2915_BitSelect_for_a(BITSELECT,28636)@262
    assign i_unnamed_c_compmm_m2915_BitSelect_for_a_b = i_unnamed_c_compmm_m2914_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2915_join(BITJOIN,28637)@262
    assign i_unnamed_c_compmm_m2915_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2915_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2915_vt_select_0(BITSELECT,11751)@262
    assign i_unnamed_c_compmm_m2915_vt_select_0_b = i_unnamed_c_compmm_m2915_join_q[0:0];

    // redist118_i_unnamed_c_compmm_m2915_vt_select_0_b_1(DELAY,29246)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist118_i_unnamed_c_compmm_m2915_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2915_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2915_vt_join(BITJOIN,11750)@263
    assign i_unnamed_c_compmm_m2915_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist118_i_unnamed_c_compmm_m2915_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_94_c_compmm_m2916(ADD,7280)@263
    assign i_add_i_i_i_i_i_i_94_c_compmm_m2916_a = {1'b0, i_unnamed_c_compmm_m2915_vt_join_q};
    assign i_add_i_i_i_i_i_i_94_c_compmm_m2916_b = {1'b0, redist893_i_conv_i_i_i_i_i_94_c_compmm_m2912_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_94_c_compmm_m2916_o = $unsigned(i_add_i_i_i_i_i_i_94_c_compmm_m2916_a) + $unsigned(i_add_i_i_i_i_i_i_94_c_compmm_m2916_b);
    assign i_add_i_i_i_i_i_i_94_c_compmm_m2916_q = i_add_i_i_i_i_i_i_94_c_compmm_m2916_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_94_c_compmm_m2916_sel_x(BITSELECT,2294)@263
    assign bgTrunc_i_add_i_i_i_i_i_i_94_c_compmm_m2916_sel_x_b = i_add_i_i_i_i_i_i_94_c_compmm_m2916_q[15:0];

    // i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_sel_x(BITSELECT,3954)@263
    assign i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_94_c_compmm_m2916_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_select_15(BITSELECT,8543)@263
    assign i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_select_15_b = i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_join(BITJOIN,8542)@263
    assign i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_select_15_b};

    // leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(MUX,28240)@263
    assign leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_join_q or leftShiftStage0Idx1_uid28239_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_95_c_compmm_m2936_vt_join_q;
            1'b1 : leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28239_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(MUX,28245)@263
    assign leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s or leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28244_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = leftShiftStage0_uid28241_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28244_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x(MUX,28250)@263
    assign leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s or leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28249_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = leftShiftStage1_uid28246_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28249_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28(BITSELECT,10204)@263
    assign i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28_b = leftShiftStage2_uid28251_i_shl_i_i_i_i_i_i_95_c_compmm_m0_shift_x_q[28:13];

    // redist259_i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28_b_1(DELAY,29387)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist259_i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_join(BITJOIN,10203)@264
    assign i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_join_q = {redist259_i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg65(REG,13360)@257 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg65_q <= $unsigned(redist854_sync_together4364_aunroll_x_in_i_valid_189_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_66210_c_compmm_m66(BLACKBOX,8802)@258
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66210_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_66210_c_compmm_m66 (
        .in_intel_reserved_ffwd_192_0(in_intel_reserved_ffwd_192_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg65_q),
        .out_dest_data_out_192_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_66210_c_compmm_m66_out_dest_data_out_192_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_offset(CONSTANT,31397)
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_offset_q = $unsigned(8'b01000111);

    // redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt(ADD,31398)
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_a = {1'b0, redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_q};
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_b = {1'b0, redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_o <= $unsigned(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_a) + $unsigned(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_b);
        end
    end
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_q = redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_o[8:0];

    // redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_inputreg0(DELAY,31393)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_inputreg0_q <= $unsigned(in_c1_eni5_191_tpl);
        end
    end

    // redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr(COUNTER,31396)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_i <= $unsigned(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_q = redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_i[7:0];

    // redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem(DUALMEM,31395)
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_ia = $unsigned(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_inputreg0_q);
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_aa = redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_wraddr_q;
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_ab = redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_aa),
        .data_a(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_ab),
        .q_b(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_q = redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_iq[15:0];

    // redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_outputreg0(DELAY,31394)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_outputreg0_q <= $unsigned(redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_mem_q);
        end
    end

    // redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt(ADD,31404)
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_a = {1'b0, redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_q};
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_b = {1'b0, redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_o <= $unsigned(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_a) + $unsigned(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_b);
        end
    end
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_q = redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_o[8:0];

    // redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_inputreg0(DELAY,31399)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_inputreg0_q <= $unsigned(in_c1_eni5_192_tpl);
        end
    end

    // redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr(COUNTER,31402)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_i <= $unsigned(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_q = redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_i[7:0];

    // redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem(DUALMEM,31401)
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_ia = $unsigned(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_inputreg0_q);
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_aa = redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_wraddr_q;
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_ab = redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_aa),
        .data_a(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_ab),
        .q_b(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_q = redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_iq[15:0];

    // redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_outputreg0(DELAY,31400)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_outputreg0_q <= $unsigned(redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_mem_q);
        end
    end

    // valid_fanout_reg66(REG,13361)@257 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg66_q <= $unsigned(redist854_sync_together4364_aunroll_x_in_i_valid_189_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_66209_c_compmm_m67(BLACKBOX,8798)@258
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_66209_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_66209_c_compmm_m67 (
        .in_intel_reserved_ffwd_191_0(in_intel_reserved_ffwd_191_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg66_q),
        .out_dest_data_out_191_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_66209_c_compmm_m67_out_dest_data_out_191_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28966)@258 + 5
    // out q@264
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_66209_c_compmm_m67_out_dest_data_out_191_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_66210_c_compmm_m66_out_dest_data_out_192_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938(ADD,9068)@264
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod757_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_b = $unsigned({{5{i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_95_c_compmm_m2937_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_o[33:0];

    // rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x(MUX,21761)@264
    assign rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q or rightShiftStage0Idx1_uid21760_dupName_381_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q;
            1'b1 : rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21760_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x(MUX,21766)@264
    assign rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21765_dupName_381_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21762_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21765_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x(MUX,21771)@264
    assign rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21770_dupName_381_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21767_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21770_dupName_381_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2939_vt_select_20(BITSELECT,11770)@264
    assign i_unnamed_c_compmm_m2939_vt_select_20_b = rightShiftStage2_uid21772_dupName_381_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2939_vt_join(BITJOIN,11769)@264
    assign i_unnamed_c_compmm_m2939_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2939_vt_select_20_b};

    // i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x(BITSELECT,3826)@264
    assign i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x_b = i_unnamed_c_compmm_m2939_vt_join_q[15:0];

    // redist892_i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x_b_1(DELAY,30020)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist892_i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21781_dupName_382_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21780)@264
    assign rightShiftStage1Idx1Rng8_uid21781_dupName_382_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21783_dupName_382_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21782)@264
    assign rightShiftStage1Idx1_uid21783_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21781_dupName_382_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21776_dupName_382_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21775)@264
    assign rightShiftStage0Idx1Rng4_uid21776_dupName_382_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q[33:4];

    // rightShiftStage0Idx1_uid21778_dupName_382_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21777)@264
    assign rightShiftStage0Idx1_uid21778_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21776_dupName_382_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x(MUX,21779)@264
    assign rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q or rightShiftStage0Idx1_uid21778_dupName_382_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_95_i_c_compmm_m2938_q;
            1'b1 : rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21778_dupName_382_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x(MUX,21784)@264
    assign rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21783_dupName_382_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21780_dupName_382_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21783_dupName_382_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2941_vt_select_21(BITSELECT,11776)@264
    assign i_unnamed_c_compmm_m2941_vt_select_21_b = rightShiftStage1_uid21785_dupName_382_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2941_vt_join(BITJOIN,11775)@264
    assign i_unnamed_c_compmm_m2941_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2941_vt_select_21_b};

    // i_unnamed_c_compmm_m2942_sel_x(BITSELECT,6145)@264
    assign i_unnamed_c_compmm_m2942_sel_x_b = i_unnamed_c_compmm_m2941_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2943_BitSelect_for_a(BITSELECT,28642)@264
    assign i_unnamed_c_compmm_m2943_BitSelect_for_a_b = i_unnamed_c_compmm_m2942_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2943_join(BITJOIN,28643)@264
    assign i_unnamed_c_compmm_m2943_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2943_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2943_vt_select_0(BITSELECT,11781)@264
    assign i_unnamed_c_compmm_m2943_vt_select_0_b = i_unnamed_c_compmm_m2943_join_q[0:0];

    // redist115_i_unnamed_c_compmm_m2943_vt_select_0_b_1(DELAY,29243)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist115_i_unnamed_c_compmm_m2943_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2943_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2943_vt_join(BITJOIN,11780)@265
    assign i_unnamed_c_compmm_m2943_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist115_i_unnamed_c_compmm_m2943_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_95_c_compmm_m2944(ADD,7281)@265
    assign i_add_i_i_i_i_i_i_95_c_compmm_m2944_a = {1'b0, i_unnamed_c_compmm_m2943_vt_join_q};
    assign i_add_i_i_i_i_i_i_95_c_compmm_m2944_b = {1'b0, redist892_i_conv_i_i_i_i_i_95_c_compmm_m2940_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_95_c_compmm_m2944_o = $unsigned(i_add_i_i_i_i_i_i_95_c_compmm_m2944_a) + $unsigned(i_add_i_i_i_i_i_i_95_c_compmm_m2944_b);
    assign i_add_i_i_i_i_i_i_95_c_compmm_m2944_q = i_add_i_i_i_i_i_i_95_c_compmm_m2944_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_95_c_compmm_m2944_sel_x(BITSELECT,2295)@265
    assign bgTrunc_i_add_i_i_i_i_i_i_95_c_compmm_m2944_sel_x_b = i_add_i_i_i_i_i_i_95_c_compmm_m2944_q[15:0];

    // i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_sel_x(BITSELECT,3955)@265
    assign i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_95_c_compmm_m2944_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_select_15(BITSELECT,8547)@265
    assign i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_select_15_b = i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_join(BITJOIN,8546)@265
    assign i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_select_15_b};

    // leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(MUX,28258)@265
    assign leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_join_q or leftShiftStage0Idx1_uid28257_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_96_c_compmm_m2965_vt_join_q;
            1'b1 : leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28257_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(MUX,28263)@265
    assign leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s or leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28262_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = leftShiftStage0_uid28259_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28262_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x(MUX,28268)@265
    assign leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s or leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28267_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = leftShiftStage1_uid28264_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28267_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28(BITSELECT,10207)@265
    assign i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28_b = leftShiftStage2_uid28269_i_shl_i_i_i_i_i_i_96_c_compmm_m0_shift_x_q[28:13];

    // redist258_i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28_b_1(DELAY,29386)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist258_i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_join(BITJOIN,10206)@266
    assign i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_join_q = {redist258_i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg63(REG,13358)@259 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg63_q <= $unsigned(redist855_sync_together4364_aunroll_x_in_i_valid_191_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_67212_c_compmm_m64(BLACKBOX,8611)@260
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67212_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_67212_c_compmm_m64 (
        .in_intel_reserved_ffwd_194_0(in_intel_reserved_ffwd_194_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg63_q),
        .out_dest_data_out_194_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_67212_c_compmm_m64_out_dest_data_out_194_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_offset(CONSTANT,31409)
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_offset_q = $unsigned(8'b01000101);

    // redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt(ADD,31410)
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_a = {1'b0, redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_q};
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_b = {1'b0, redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_o <= $unsigned(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_a) + $unsigned(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_b);
        end
    end
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_q = redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_o[8:0];

    // redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_inputreg0(DELAY,31405)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_inputreg0_q <= $unsigned(in_c1_eni5_193_tpl);
        end
    end

    // redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr(COUNTER,31408)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_i <= $unsigned(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_q = redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_i[7:0];

    // redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem(DUALMEM,31407)
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_ia = $unsigned(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_inputreg0_q);
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_aa = redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_wraddr_q;
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_ab = redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_aa),
        .data_a(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_ab),
        .q_b(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_q = redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_iq[15:0];

    // redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_outputreg0(DELAY,31406)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_outputreg0_q <= $unsigned(redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_mem_q);
        end
    end

    // redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt(ADD,31416)
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_a = {1'b0, redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_q};
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_b = {1'b0, redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_o <= $unsigned(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_a) + $unsigned(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_b);
        end
    end
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_q = redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_o[8:0];

    // redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_inputreg0(DELAY,31411)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_inputreg0_q <= $unsigned(in_c1_eni5_194_tpl);
        end
    end

    // redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr(COUNTER,31414)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_i <= $unsigned(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_q = redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_i[7:0];

    // redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem(DUALMEM,31413)
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_ia = $unsigned(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_inputreg0_q);
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_aa = redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_wraddr_q;
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_ab = redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_aa),
        .data_a(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_ab),
        .q_b(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_q = redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_iq[15:0];

    // redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_outputreg0(DELAY,31412)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_outputreg0_q <= $unsigned(redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_mem_q);
        end
    end

    // valid_fanout_reg64(REG,13359)@259 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg64_q <= $unsigned(redist855_sync_together4364_aunroll_x_in_i_valid_191_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_67211_c_compmm_m65(BLACKBOX,8567)@260
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67211_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_67211_c_compmm_m65 (
        .in_intel_reserved_ffwd_193_0(in_intel_reserved_ffwd_193_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg64_q),
        .out_dest_data_out_193_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_67211_c_compmm_m65_out_dest_data_out_193_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28967)@260 + 5
    // out q@266
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_67211_c_compmm_m65_out_dest_data_out_193_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_67212_c_compmm_m64_out_dest_data_out_194_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967(ADD,9069)@266
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod762_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_b = $unsigned({{5{i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_96_c_compmm_m2966_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_o[33:0];

    // rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x(MUX,21823)@266
    assign rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q or rightShiftStage0Idx1_uid21822_dupName_385_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q;
            1'b1 : rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21822_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x(MUX,21828)@266
    assign rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21827_dupName_385_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21824_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21827_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x(MUX,21833)@266
    assign rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21832_dupName_385_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21829_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21832_dupName_385_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2968_vt_select_20(BITSELECT,11795)@266
    assign i_unnamed_c_compmm_m2968_vt_select_20_b = rightShiftStage2_uid21834_dupName_385_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2968_vt_join(BITJOIN,11794)@266
    assign i_unnamed_c_compmm_m2968_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2968_vt_select_20_b};

    // i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x(BITSELECT,3827)@266
    assign i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x_b = i_unnamed_c_compmm_m2968_vt_join_q[15:0];

    // redist891_i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x_b_1(DELAY,30019)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist891_i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21843_dupName_386_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21842)@266
    assign rightShiftStage1Idx1Rng8_uid21843_dupName_386_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21845_dupName_386_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21844)@266
    assign rightShiftStage1Idx1_uid21845_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21843_dupName_386_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21838_dupName_386_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21837)@266
    assign rightShiftStage0Idx1Rng4_uid21838_dupName_386_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q[33:4];

    // rightShiftStage0Idx1_uid21840_dupName_386_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21839)@266
    assign rightShiftStage0Idx1_uid21840_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21838_dupName_386_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x(MUX,21841)@266
    assign rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q or rightShiftStage0Idx1_uid21840_dupName_386_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_96_i_c_compmm_m2967_q;
            1'b1 : rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21840_dupName_386_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x(MUX,21846)@266
    assign rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21845_dupName_386_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21842_dupName_386_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21845_dupName_386_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2970_vt_select_21(BITSELECT,11798)@266
    assign i_unnamed_c_compmm_m2970_vt_select_21_b = rightShiftStage1_uid21847_dupName_386_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2970_vt_join(BITJOIN,11797)@266
    assign i_unnamed_c_compmm_m2970_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2970_vt_select_21_b};

    // i_unnamed_c_compmm_m2971_sel_x(BITSELECT,6147)@266
    assign i_unnamed_c_compmm_m2971_sel_x_b = i_unnamed_c_compmm_m2970_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2972_BitSelect_for_a(BITSELECT,28646)@266
    assign i_unnamed_c_compmm_m2972_BitSelect_for_a_b = i_unnamed_c_compmm_m2971_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2972_join(BITJOIN,28647)@266
    assign i_unnamed_c_compmm_m2972_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2972_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2972_vt_select_0(BITSELECT,11803)@266
    assign i_unnamed_c_compmm_m2972_vt_select_0_b = i_unnamed_c_compmm_m2972_join_q[0:0];

    // redist113_i_unnamed_c_compmm_m2972_vt_select_0_b_1(DELAY,29241)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist113_i_unnamed_c_compmm_m2972_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2972_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2972_vt_join(BITJOIN,11802)@267
    assign i_unnamed_c_compmm_m2972_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist113_i_unnamed_c_compmm_m2972_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_96_c_compmm_m2973(ADD,7282)@267
    assign i_add_i_i_i_i_i_i_96_c_compmm_m2973_a = {1'b0, i_unnamed_c_compmm_m2972_vt_join_q};
    assign i_add_i_i_i_i_i_i_96_c_compmm_m2973_b = {1'b0, redist891_i_conv_i_i_i_i_i_96_c_compmm_m2969_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_96_c_compmm_m2973_o = $unsigned(i_add_i_i_i_i_i_i_96_c_compmm_m2973_a) + $unsigned(i_add_i_i_i_i_i_i_96_c_compmm_m2973_b);
    assign i_add_i_i_i_i_i_i_96_c_compmm_m2973_q = i_add_i_i_i_i_i_i_96_c_compmm_m2973_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_96_c_compmm_m2973_sel_x(BITSELECT,2296)@267
    assign bgTrunc_i_add_i_i_i_i_i_i_96_c_compmm_m2973_sel_x_b = i_add_i_i_i_i_i_i_96_c_compmm_m2973_q[15:0];

    // i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_sel_x(BITSELECT,3956)@267
    assign i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_96_c_compmm_m2973_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_select_15(BITSELECT,8551)@267
    assign i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_select_15_b = i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_join(BITJOIN,8550)@267
    assign i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_select_15_b};

    // leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(MUX,28276)@267
    assign leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_join_q or leftShiftStage0Idx1_uid28275_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_97_c_compmm_m2993_vt_join_q;
            1'b1 : leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28275_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(MUX,28281)@267
    assign leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s or leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28280_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = leftShiftStage0_uid28277_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28280_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x(MUX,28286)@267
    assign leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s or leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28285_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = leftShiftStage1_uid28282_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28285_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28(BITSELECT,10210)@267
    assign i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28_b = leftShiftStage2_uid28287_i_shl_i_i_i_i_i_i_97_c_compmm_m0_shift_x_q[28:13];

    // redist257_i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28_b_1(DELAY,29385)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist257_i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_join(BITJOIN,10209)@268
    assign i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_join_q = {redist257_i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg61(REG,13356)@261 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg61_q <= $unsigned(redist856_sync_together4364_aunroll_x_in_i_valid_193_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_67214_c_compmm_m62(BLACKBOX,8699)@262
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67214_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_67214_c_compmm_m62 (
        .in_intel_reserved_ffwd_196_0(in_intel_reserved_ffwd_196_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg61_q),
        .out_dest_data_out_196_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_67214_c_compmm_m62_out_dest_data_out_196_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_offset(CONSTANT,31421)
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_offset_q = $unsigned(8'b01000011);

    // redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt(ADD,31422)
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_a = {1'b0, redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_q};
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_b = {1'b0, redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_o <= $unsigned(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_a) + $unsigned(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_b);
        end
    end
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_q = redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_o[8:0];

    // redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_inputreg0(DELAY,31417)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_inputreg0_q <= $unsigned(in_c1_eni5_195_tpl);
        end
    end

    // redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr(COUNTER,31420)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_i <= $unsigned(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_q = redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_i[7:0];

    // redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem(DUALMEM,31419)
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_ia = $unsigned(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_inputreg0_q);
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_aa = redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_wraddr_q;
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_ab = redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_aa),
        .data_a(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_ab),
        .q_b(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_q = redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_iq[15:0];

    // redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_outputreg0(DELAY,31418)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_outputreg0_q <= $unsigned(redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_mem_q);
        end
    end

    // redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt(ADD,31428)
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_a = {1'b0, redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_q};
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_b = {1'b0, redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_o <= $unsigned(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_a) + $unsigned(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_b);
        end
    end
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_q = redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_o[8:0];

    // redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_inputreg0(DELAY,31423)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_inputreg0_q <= $unsigned(in_c1_eni5_196_tpl);
        end
    end

    // redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr(COUNTER,31426)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_i <= $unsigned(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_q = redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_i[7:0];

    // redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem(DUALMEM,31425)
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_ia = $unsigned(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_inputreg0_q);
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_aa = redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_wraddr_q;
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_ab = redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_aa),
        .data_a(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_ab),
        .q_b(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_q = redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_iq[15:0];

    // redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_outputreg0(DELAY,31424)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_outputreg0_q <= $unsigned(redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_mem_q);
        end
    end

    // valid_fanout_reg62(REG,13357)@261 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg62_q <= $unsigned(redist856_sync_together4364_aunroll_x_in_i_valid_193_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_67213_c_compmm_m63(BLACKBOX,8655)@262
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67213_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_67213_c_compmm_m63 (
        .in_intel_reserved_ffwd_195_0(in_intel_reserved_ffwd_195_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg62_q),
        .out_dest_data_out_195_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_67213_c_compmm_m63_out_dest_data_out_195_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28968)@262 + 5
    // out q@268
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_67213_c_compmm_m63_out_dest_data_out_195_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_67214_c_compmm_m62_out_dest_data_out_196_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995(ADD,9070)@268
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod767_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_b = $unsigned({{5{i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_97_c_compmm_m2994_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_o[33:0];

    // rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x(MUX,21885)@268
    assign rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q or rightShiftStage0Idx1_uid21884_dupName_389_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q;
            1'b1 : rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21884_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x(MUX,21890)@268
    assign rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21889_dupName_389_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21886_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21889_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x(MUX,21895)@268
    assign rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21894_dupName_389_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21891_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21894_dupName_389_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2996_vt_select_20(BITSELECT,11817)@268
    assign i_unnamed_c_compmm_m2996_vt_select_20_b = rightShiftStage2_uid21896_dupName_389_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2996_vt_join(BITJOIN,11816)@268
    assign i_unnamed_c_compmm_m2996_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2996_vt_select_20_b};

    // i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x(BITSELECT,3828)@268
    assign i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x_b = i_unnamed_c_compmm_m2996_vt_join_q[15:0];

    // redist890_i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x_b_1(DELAY,30018)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist890_i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21905_dupName_390_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21904)@268
    assign rightShiftStage1Idx1Rng8_uid21905_dupName_390_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21907_dupName_390_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21906)@268
    assign rightShiftStage1Idx1_uid21907_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21905_dupName_390_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21900_dupName_390_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21899)@268
    assign rightShiftStage0Idx1Rng4_uid21900_dupName_390_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q[33:4];

    // rightShiftStage0Idx1_uid21902_dupName_390_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21901)@268
    assign rightShiftStage0Idx1_uid21902_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21900_dupName_390_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x(MUX,21903)@268
    assign rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q or rightShiftStage0Idx1_uid21902_dupName_390_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_97_i_c_compmm_m2995_q;
            1'b1 : rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21902_dupName_390_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x(MUX,21908)@268
    assign rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21907_dupName_390_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21904_dupName_390_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21907_dupName_390_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2998_vt_select_21(BITSELECT,11820)@268
    assign i_unnamed_c_compmm_m2998_vt_select_21_b = rightShiftStage1_uid21909_dupName_390_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2998_vt_join(BITJOIN,11819)@268
    assign i_unnamed_c_compmm_m2998_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2998_vt_select_21_b};

    // i_unnamed_c_compmm_m2999_sel_x(BITSELECT,6149)@268
    assign i_unnamed_c_compmm_m2999_sel_x_b = i_unnamed_c_compmm_m2998_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3000_BitSelect_for_a(BITSELECT,28650)@268
    assign i_unnamed_c_compmm_m3000_BitSelect_for_a_b = i_unnamed_c_compmm_m2999_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3000_join(BITJOIN,28651)@268
    assign i_unnamed_c_compmm_m3000_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3000_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3000_vt_select_0(BITSELECT,11825)@268
    assign i_unnamed_c_compmm_m3000_vt_select_0_b = i_unnamed_c_compmm_m3000_join_q[0:0];

    // redist111_i_unnamed_c_compmm_m3000_vt_select_0_b_1(DELAY,29239)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist111_i_unnamed_c_compmm_m3000_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3000_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3000_vt_join(BITJOIN,11824)@269
    assign i_unnamed_c_compmm_m3000_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist111_i_unnamed_c_compmm_m3000_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_97_c_compmm_m3001(ADD,7283)@269
    assign i_add_i_i_i_i_i_i_97_c_compmm_m3001_a = {1'b0, i_unnamed_c_compmm_m3000_vt_join_q};
    assign i_add_i_i_i_i_i_i_97_c_compmm_m3001_b = {1'b0, redist890_i_conv_i_i_i_i_i_97_c_compmm_m2997_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_97_c_compmm_m3001_o = $unsigned(i_add_i_i_i_i_i_i_97_c_compmm_m3001_a) + $unsigned(i_add_i_i_i_i_i_i_97_c_compmm_m3001_b);
    assign i_add_i_i_i_i_i_i_97_c_compmm_m3001_q = i_add_i_i_i_i_i_i_97_c_compmm_m3001_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_97_c_compmm_m3001_sel_x(BITSELECT,2297)@269
    assign bgTrunc_i_add_i_i_i_i_i_i_97_c_compmm_m3001_sel_x_b = i_add_i_i_i_i_i_i_97_c_compmm_m3001_q[15:0];

    // i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_sel_x(BITSELECT,3957)@269
    assign i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_97_c_compmm_m3001_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_select_15(BITSELECT,8555)@269
    assign i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_select_15_b = i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_join(BITJOIN,8554)@269
    assign i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_select_15_b};

    // leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(MUX,28294)@269
    assign leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_join_q or leftShiftStage0Idx1_uid28293_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_98_c_compmm_m3021_vt_join_q;
            1'b1 : leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28293_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(MUX,28299)@269
    assign leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s or leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28298_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = leftShiftStage0_uid28295_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28298_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x(MUX,28304)@269
    assign leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s or leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28303_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = leftShiftStage1_uid28300_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28303_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28(BITSELECT,10213)@269
    assign i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28_b = leftShiftStage2_uid28305_i_shl_i_i_i_i_i_i_98_c_compmm_m0_shift_x_q[28:13];

    // redist256_i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28_b_1(DELAY,29384)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist256_i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_join(BITJOIN,10212)@270
    assign i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_join_q = {redist256_i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg59(REG,13354)@263 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg59_q <= $unsigned(redist857_sync_together4364_aunroll_x_in_i_valid_195_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_67216_c_compmm_m60(BLACKBOX,8787)@264
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67216_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_67216_c_compmm_m60 (
        .in_intel_reserved_ffwd_198_0(in_intel_reserved_ffwd_198_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg59_q),
        .out_dest_data_out_198_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_67216_c_compmm_m60_out_dest_data_out_198_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_offset(CONSTANT,31433)
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_offset_q = $unsigned(8'b01000001);

    // redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt(ADD,31434)
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_a = {1'b0, redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_q};
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_b = {1'b0, redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_o <= $unsigned(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_a) + $unsigned(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_b);
        end
    end
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_q = redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_o[8:0];

    // redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_inputreg0(DELAY,31429)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_inputreg0_q <= $unsigned(in_c1_eni5_197_tpl);
        end
    end

    // redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr(COUNTER,31432)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_i <= $unsigned(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_q = redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_i[7:0];

    // redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem(DUALMEM,31431)
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_ia = $unsigned(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_inputreg0_q);
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_aa = redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_wraddr_q;
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_ab = redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_aa),
        .data_a(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_ab),
        .q_b(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_q = redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_iq[15:0];

    // redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_outputreg0(DELAY,31430)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_outputreg0_q <= $unsigned(redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_mem_q);
        end
    end

    // redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt(ADD,31440)
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_a = {1'b0, redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_q};
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_b = {1'b0, redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_o <= $unsigned(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_a) + $unsigned(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_b);
        end
    end
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_q = redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_o[8:0];

    // redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_inputreg0(DELAY,31435)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_inputreg0_q <= $unsigned(in_c1_eni5_198_tpl);
        end
    end

    // redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr(COUNTER,31438)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_i <= $unsigned(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_q = redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_i[7:0];

    // redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem(DUALMEM,31437)
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_ia = $unsigned(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_inputreg0_q);
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_aa = redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_wraddr_q;
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_ab = redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_aa),
        .data_a(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_ab),
        .q_b(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_q = redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_iq[15:0];

    // redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_outputreg0(DELAY,31436)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_outputreg0_q <= $unsigned(redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_mem_q);
        end
    end

    // valid_fanout_reg60(REG,13355)@263 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg60_q <= $unsigned(redist857_sync_together4364_aunroll_x_in_i_valid_195_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_67215_c_compmm_m61(BLACKBOX,8743)@264
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67215_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_67215_c_compmm_m61 (
        .in_intel_reserved_ffwd_197_0(in_intel_reserved_ffwd_197_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg60_q),
        .out_dest_data_out_197_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_67215_c_compmm_m61_out_dest_data_out_197_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28969)@264 + 5
    // out q@270
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_67215_c_compmm_m61_out_dest_data_out_197_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_67216_c_compmm_m60_out_dest_data_out_198_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023(ADD,9071)@270
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod772_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_b = $unsigned({{5{i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_98_c_compmm_m3022_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_o[33:0];

    // rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x(MUX,21947)@270
    assign rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q or rightShiftStage0Idx1_uid21946_dupName_393_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q;
            1'b1 : rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21946_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x(MUX,21952)@270
    assign rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21951_dupName_393_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21948_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21951_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x(MUX,21957)@270
    assign rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21956_dupName_393_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21953_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21956_dupName_393_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3024_vt_select_20(BITSELECT,11839)@270
    assign i_unnamed_c_compmm_m3024_vt_select_20_b = rightShiftStage2_uid21958_dupName_393_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3024_vt_join(BITJOIN,11838)@270
    assign i_unnamed_c_compmm_m3024_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3024_vt_select_20_b};

    // i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x(BITSELECT,3829)@270
    assign i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x_b = i_unnamed_c_compmm_m3024_vt_join_q[15:0];

    // redist889_i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x_b_1(DELAY,30017)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist889_i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21967_dupName_394_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21966)@270
    assign rightShiftStage1Idx1Rng8_uid21967_dupName_394_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21969_dupName_394_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21968)@270
    assign rightShiftStage1Idx1_uid21969_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21967_dupName_394_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21962_dupName_394_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21961)@270
    assign rightShiftStage0Idx1Rng4_uid21962_dupName_394_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q[33:4];

    // rightShiftStage0Idx1_uid21964_dupName_394_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21963)@270
    assign rightShiftStage0Idx1_uid21964_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21962_dupName_394_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x(MUX,21965)@270
    assign rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q or rightShiftStage0Idx1_uid21964_dupName_394_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_98_i_c_compmm_m3023_q;
            1'b1 : rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21964_dupName_394_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x(MUX,21970)@270
    assign rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21969_dupName_394_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21966_dupName_394_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21969_dupName_394_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3026_vt_select_21(BITSELECT,11842)@270
    assign i_unnamed_c_compmm_m3026_vt_select_21_b = rightShiftStage1_uid21971_dupName_394_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3026_vt_join(BITJOIN,11841)@270
    assign i_unnamed_c_compmm_m3026_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3026_vt_select_21_b};

    // i_unnamed_c_compmm_m3027_sel_x(BITSELECT,6151)@270
    assign i_unnamed_c_compmm_m3027_sel_x_b = i_unnamed_c_compmm_m3026_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3028_BitSelect_for_a(BITSELECT,28654)@270
    assign i_unnamed_c_compmm_m3028_BitSelect_for_a_b = i_unnamed_c_compmm_m3027_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3028_join(BITJOIN,28655)@270
    assign i_unnamed_c_compmm_m3028_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3028_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3028_vt_select_0(BITSELECT,11847)@270
    assign i_unnamed_c_compmm_m3028_vt_select_0_b = i_unnamed_c_compmm_m3028_join_q[0:0];

    // redist109_i_unnamed_c_compmm_m3028_vt_select_0_b_1(DELAY,29237)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist109_i_unnamed_c_compmm_m3028_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3028_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3028_vt_join(BITJOIN,11846)@271
    assign i_unnamed_c_compmm_m3028_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist109_i_unnamed_c_compmm_m3028_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_98_c_compmm_m3029(ADD,7284)@271
    assign i_add_i_i_i_i_i_i_98_c_compmm_m3029_a = {1'b0, i_unnamed_c_compmm_m3028_vt_join_q};
    assign i_add_i_i_i_i_i_i_98_c_compmm_m3029_b = {1'b0, redist889_i_conv_i_i_i_i_i_98_c_compmm_m3025_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_98_c_compmm_m3029_o = $unsigned(i_add_i_i_i_i_i_i_98_c_compmm_m3029_a) + $unsigned(i_add_i_i_i_i_i_i_98_c_compmm_m3029_b);
    assign i_add_i_i_i_i_i_i_98_c_compmm_m3029_q = i_add_i_i_i_i_i_i_98_c_compmm_m3029_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x(BITSELECT,2298)@271
    assign bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x_b = i_add_i_i_i_i_i_i_98_c_compmm_m3029_q[15:0];

    // redist1142_bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x_b_1(DELAY,30270)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1142_bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x_b_1_q <= $unsigned(bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x_b);
        end
    end

    // i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_sel_x(BITSELECT,3958)@272
    assign i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_sel_x_b = {13'b0000000000000, redist1142_bgTrunc_i_add_i_i_i_i_i_i_98_c_compmm_m3029_sel_x_b_1_q[15:0]};

    // i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_select_15(BITSELECT,8559)@272
    assign i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_select_15_b = i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_join(BITJOIN,8558)@272
    assign i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_select_15_b};

    // leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(MUX,28312)@272
    assign leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_join_q or leftShiftStage0Idx1_uid28311_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_99_c_compmm_m3049_vt_join_q;
            1'b1 : leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid28311_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(MUX,28317)@272
    assign leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s or leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid28316_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = leftShiftStage0_uid28313_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid28316_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x(MUX,28322)@272
    assign leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s or leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid28321_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = leftShiftStage1_uid28318_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid28321_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_select_28(BITSELECT,10216)@272
    assign i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_select_28_b = leftShiftStage2_uid28323_i_shl_i_i_i_i_i_i_99_c_compmm_m0_shift_x_q[28:13];

    // i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_join(BITJOIN,10215)@272
    assign i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_join_q = {i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_select_28_b, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg57(REG,13352)@265 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg57_q <= $unsigned(redist858_sync_together4364_aunroll_x_in_i_valid_197_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_67218_c_compmm_m58(BLACKBOX,8811)@266
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67218_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_67218_c_compmm_m58 (
        .in_intel_reserved_ffwd_200_0(in_intel_reserved_ffwd_200_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg57_q),
        .out_dest_data_out_200_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_67218_c_compmm_m58_out_dest_data_out_200_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_offset(CONSTANT,31445)
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_offset_q = $unsigned(8'b00111111);

    // redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt(ADD,31446)
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_a = {1'b0, redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_q};
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_b = {1'b0, redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_o <= $unsigned(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_a) + $unsigned(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_b);
        end
    end
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_q = redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_o[8:0];

    // redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_inputreg0(DELAY,31441)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_inputreg0_q <= $unsigned(in_c1_eni5_199_tpl);
        end
    end

    // redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr(COUNTER,31444)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_i <= $unsigned(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_q = redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_i[7:0];

    // redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem(DUALMEM,31443)
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_ia = $unsigned(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_inputreg0_q);
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_aa = redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_wraddr_q;
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_ab = redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_aa),
        .data_a(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_ab),
        .q_b(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_q = redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_iq[15:0];

    // redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_outputreg0(DELAY,31442)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_outputreg0_q <= $unsigned(redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_mem_q);
        end
    end

    // redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt(ADD,31452)
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_a = {1'b0, redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_q};
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_b = {1'b0, redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_o <= $unsigned(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_a) + $unsigned(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_b);
        end
    end
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_q = redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_o[8:0];

    // redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_inputreg0(DELAY,31447)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_inputreg0_q <= $unsigned(in_c1_eni5_200_tpl);
        end
    end

    // redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr(COUNTER,31450)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_i <= $unsigned(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_q = redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_i[7:0];

    // redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem(DUALMEM,31449)
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_ia = $unsigned(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_inputreg0_q);
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_aa = redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_wraddr_q;
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_ab = redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_aa),
        .data_a(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_ab),
        .q_b(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_q = redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_iq[15:0];

    // redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_outputreg0(DELAY,31448)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_outputreg0_q <= $unsigned(redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_mem_q);
        end
    end

    // valid_fanout_reg58(REG,13353)@265 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg58_q <= $unsigned(redist858_sync_together4364_aunroll_x_in_i_valid_197_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_67217_c_compmm_m59(BLACKBOX,8807)@266
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67217_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_67217_c_compmm_m59 (
        .in_intel_reserved_ffwd_199_0(in_intel_reserved_ffwd_199_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg58_q),
        .out_dest_data_out_199_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_67217_c_compmm_m59_out_dest_data_out_199_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28970)@266 + 5
    // out q@272
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_67217_c_compmm_m59_out_dest_data_out_199_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_67218_c_compmm_m58_out_dest_data_out_200_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051(ADD,9072)@272
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod777_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_b = $unsigned({{5{i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_99_c_compmm_m3050_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_o[33:0];

    // rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x(MUX,22009)@272
    assign rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q or rightShiftStage0Idx1_uid22008_dupName_397_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q;
            1'b1 : rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22008_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x(MUX,22014)@272
    assign rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22013_dupName_397_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22010_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22013_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x(MUX,22019)@272
    assign rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22018_dupName_397_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22015_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22018_dupName_397_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3052_vt_select_20(BITSELECT,11861)@272
    assign i_unnamed_c_compmm_m3052_vt_select_20_b = rightShiftStage2_uid22020_dupName_397_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3052_vt_join(BITJOIN,11860)@272
    assign i_unnamed_c_compmm_m3052_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3052_vt_select_20_b};

    // i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x(BITSELECT,3830)@272
    assign i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x_b = i_unnamed_c_compmm_m3052_vt_join_q[15:0];

    // redist888_i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x_b_1(DELAY,30016)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist888_i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22029_dupName_398_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22028)@272
    assign rightShiftStage1Idx1Rng8_uid22029_dupName_398_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22031_dupName_398_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22030)@272
    assign rightShiftStage1Idx1_uid22031_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22029_dupName_398_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22024_dupName_398_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22023)@272
    assign rightShiftStage0Idx1Rng4_uid22024_dupName_398_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q[33:4];

    // rightShiftStage0Idx1_uid22026_dupName_398_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22025)@272
    assign rightShiftStage0Idx1_uid22026_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22024_dupName_398_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x(MUX,22027)@272
    assign rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q or rightShiftStage0Idx1_uid22026_dupName_398_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_99_i_c_compmm_m3051_q;
            1'b1 : rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22026_dupName_398_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x(MUX,22032)@272
    assign rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22031_dupName_398_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22028_dupName_398_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22031_dupName_398_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3054_vt_select_21(BITSELECT,11864)@272
    assign i_unnamed_c_compmm_m3054_vt_select_21_b = rightShiftStage1_uid22033_dupName_398_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3054_vt_join(BITJOIN,11863)@272
    assign i_unnamed_c_compmm_m3054_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3054_vt_select_21_b};

    // i_unnamed_c_compmm_m3055_sel_x(BITSELECT,6153)@272
    assign i_unnamed_c_compmm_m3055_sel_x_b = i_unnamed_c_compmm_m3054_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3056_BitSelect_for_a(BITSELECT,28658)@272
    assign i_unnamed_c_compmm_m3056_BitSelect_for_a_b = i_unnamed_c_compmm_m3055_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3056_join(BITJOIN,28659)@272
    assign i_unnamed_c_compmm_m3056_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3056_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3056_vt_select_0(BITSELECT,11869)@272
    assign i_unnamed_c_compmm_m3056_vt_select_0_b = i_unnamed_c_compmm_m3056_join_q[0:0];

    // redist107_i_unnamed_c_compmm_m3056_vt_select_0_b_1(DELAY,29235)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist107_i_unnamed_c_compmm_m3056_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3056_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3056_vt_join(BITJOIN,11868)@273
    assign i_unnamed_c_compmm_m3056_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist107_i_unnamed_c_compmm_m3056_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_99_c_compmm_m3057(ADD,7285)@273
    assign i_add_i_i_i_i_i_i_99_c_compmm_m3057_a = {1'b0, i_unnamed_c_compmm_m3056_vt_join_q};
    assign i_add_i_i_i_i_i_i_99_c_compmm_m3057_b = {1'b0, redist888_i_conv_i_i_i_i_i_99_c_compmm_m3053_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_99_c_compmm_m3057_o = $unsigned(i_add_i_i_i_i_i_i_99_c_compmm_m3057_a) + $unsigned(i_add_i_i_i_i_i_i_99_c_compmm_m3057_b);
    assign i_add_i_i_i_i_i_i_99_c_compmm_m3057_q = i_add_i_i_i_i_i_i_99_c_compmm_m3057_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_99_c_compmm_m3057_sel_x(BITSELECT,2299)@273
    assign bgTrunc_i_add_i_i_i_i_i_i_99_c_compmm_m3057_sel_x_b = i_add_i_i_i_i_i_i_99_c_compmm_m3057_q[15:0];

    // i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_sel_x(BITSELECT,3833)@273
    assign i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_99_c_compmm_m3057_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_select_15(BITSELECT,8059)@273
    assign i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_select_15_b = i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_join(BITJOIN,8058)@273
    assign i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_select_15_b};

    // leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(MUX,26062)@273
    assign leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_join_q or leftShiftStage0Idx1_uid26061_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_100_c_compmm_m3077_vt_join_q;
            1'b1 : leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26061_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(MUX,26067)@273
    assign leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s or leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26066_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = leftShiftStage0_uid26063_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26066_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x(MUX,26072)@273
    assign leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s or leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26071_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = leftShiftStage1_uid26068_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26071_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28(BITSELECT,9841)@273
    assign i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28_b = leftShiftStage2_uid26073_i_shl_i_i_i_i_i_i_100_c_compmm_m0_shift_x_q[28:13];

    // redist375_i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28_b_1(DELAY,29503)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist375_i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_join(BITJOIN,9840)@274
    assign i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_join_q = {redist375_i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg55(REG,13350)@267 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg55_q <= $unsigned(redist859_sync_together4364_aunroll_x_in_i_valid_199_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_67220_c_compmm_m56(BLACKBOX,8819)@268
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67220_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_67220_c_compmm_m56 (
        .in_intel_reserved_ffwd_202_0(in_intel_reserved_ffwd_202_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg55_q),
        .out_dest_data_out_202_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_67220_c_compmm_m56_out_dest_data_out_202_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_offset(CONSTANT,31457)
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_offset_q = $unsigned(8'b00111101);

    // redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt(ADD,31458)
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_a = {1'b0, redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_q};
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_b = {1'b0, redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_o <= $unsigned(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_a) + $unsigned(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_b);
        end
    end
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_q = redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_o[8:0];

    // redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_inputreg0(DELAY,31453)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_inputreg0_q <= $unsigned(in_c1_eni5_201_tpl);
        end
    end

    // redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr(COUNTER,31456)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_i <= $unsigned(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_q = redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_i[7:0];

    // redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem(DUALMEM,31455)
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_ia = $unsigned(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_inputreg0_q);
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_aa = redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_wraddr_q;
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_ab = redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_aa),
        .data_a(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_ab),
        .q_b(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_q = redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_iq[15:0];

    // redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_outputreg0(DELAY,31454)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_outputreg0_q <= $unsigned(redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_mem_q);
        end
    end

    // redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt(ADD,31464)
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_a = {1'b0, redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_q};
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_b = {1'b0, redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_o <= $unsigned(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_a) + $unsigned(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_b);
        end
    end
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_q = redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_o[8:0];

    // redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_inputreg0(DELAY,31459)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_inputreg0_q <= $unsigned(in_c1_eni5_202_tpl);
        end
    end

    // redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr(COUNTER,31462)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_i <= $unsigned(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_q = redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_i[7:0];

    // redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem(DUALMEM,31461)
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_ia = $unsigned(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_inputreg0_q);
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_aa = redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_wraddr_q;
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_ab = redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_aa),
        .data_a(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_ab),
        .q_b(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_q = redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_iq[15:0];

    // redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_outputreg0(DELAY,31460)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_outputreg0_q <= $unsigned(redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_mem_q);
        end
    end

    // valid_fanout_reg56(REG,13351)@267 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg56_q <= $unsigned(redist859_sync_together4364_aunroll_x_in_i_valid_199_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_67219_c_compmm_m57(BLACKBOX,8815)@268
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67219_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_67219_c_compmm_m57 (
        .in_intel_reserved_ffwd_201_0(in_intel_reserved_ffwd_201_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg56_q),
        .out_dest_data_out_201_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_67219_c_compmm_m57_out_dest_data_out_201_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28971)@268 + 5
    // out q@274
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_67219_c_compmm_m57_out_dest_data_out_201_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_67220_c_compmm_m56_out_dest_data_out_202_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079(ADD,8947)@274
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod782_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_b = $unsigned({{5{i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_100_c_compmm_m3078_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_o[33:0];

    // rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x(MUX,22071)@274
    assign rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q or rightShiftStage0Idx1_uid22070_dupName_401_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q;
            1'b1 : rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22070_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x(MUX,22076)@274
    assign rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22075_dupName_401_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22072_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22075_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x(MUX,22081)@274
    assign rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22080_dupName_401_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22077_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22080_dupName_401_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3080_vt_select_20(BITSELECT,11889)@274
    assign i_unnamed_c_compmm_m3080_vt_select_20_b = rightShiftStage2_uid22082_dupName_401_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3080_vt_join(BITJOIN,11888)@274
    assign i_unnamed_c_compmm_m3080_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3080_vt_select_20_b};

    // i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x(BITSELECT,3705)@274
    assign i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x_b = i_unnamed_c_compmm_m3080_vt_join_q[15:0];

    // redist1013_i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x_b_1(DELAY,30141)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1013_i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22091_dupName_402_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22090)@274
    assign rightShiftStage1Idx1Rng8_uid22091_dupName_402_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22093_dupName_402_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22092)@274
    assign rightShiftStage1Idx1_uid22093_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22091_dupName_402_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22086_dupName_402_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22085)@274
    assign rightShiftStage0Idx1Rng4_uid22086_dupName_402_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q[33:4];

    // rightShiftStage0Idx1_uid22088_dupName_402_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22087)@274
    assign rightShiftStage0Idx1_uid22088_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22086_dupName_402_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x(MUX,22089)@274
    assign rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q or rightShiftStage0Idx1_uid22088_dupName_402_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_100_i_c_compmm_m3079_q;
            1'b1 : rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22088_dupName_402_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x(MUX,22094)@274
    assign rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22093_dupName_402_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22090_dupName_402_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22093_dupName_402_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3082_vt_select_21(BITSELECT,11892)@274
    assign i_unnamed_c_compmm_m3082_vt_select_21_b = rightShiftStage1_uid22095_dupName_402_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3082_vt_join(BITJOIN,11891)@274
    assign i_unnamed_c_compmm_m3082_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3082_vt_select_21_b};

    // i_unnamed_c_compmm_m3083_sel_x(BITSELECT,6156)@274
    assign i_unnamed_c_compmm_m3083_sel_x_b = i_unnamed_c_compmm_m3082_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3084_BitSelect_for_a(BITSELECT,28662)@274
    assign i_unnamed_c_compmm_m3084_BitSelect_for_a_b = i_unnamed_c_compmm_m3083_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3084_join(BITJOIN,28663)@274
    assign i_unnamed_c_compmm_m3084_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3084_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3084_vt_select_0(BITSELECT,11897)@274
    assign i_unnamed_c_compmm_m3084_vt_select_0_b = i_unnamed_c_compmm_m3084_join_q[0:0];

    // redist105_i_unnamed_c_compmm_m3084_vt_select_0_b_1(DELAY,29233)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist105_i_unnamed_c_compmm_m3084_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3084_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3084_vt_join(BITJOIN,11896)@275
    assign i_unnamed_c_compmm_m3084_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist105_i_unnamed_c_compmm_m3084_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_100_c_compmm_m3085(ADD,7160)@275
    assign i_add_i_i_i_i_i_i_100_c_compmm_m3085_a = {1'b0, i_unnamed_c_compmm_m3084_vt_join_q};
    assign i_add_i_i_i_i_i_i_100_c_compmm_m3085_b = {1'b0, redist1013_i_conv_i_i_i_i_i_100_c_compmm_m3081_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_100_c_compmm_m3085_o = $unsigned(i_add_i_i_i_i_i_i_100_c_compmm_m3085_a) + $unsigned(i_add_i_i_i_i_i_i_100_c_compmm_m3085_b);
    assign i_add_i_i_i_i_i_i_100_c_compmm_m3085_q = i_add_i_i_i_i_i_i_100_c_compmm_m3085_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_100_c_compmm_m3085_sel_x(BITSELECT,2174)@275
    assign bgTrunc_i_add_i_i_i_i_i_i_100_c_compmm_m3085_sel_x_b = i_add_i_i_i_i_i_i_100_c_compmm_m3085_q[15:0];

    // i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_sel_x(BITSELECT,3834)@275
    assign i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_100_c_compmm_m3085_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_select_15(BITSELECT,8063)@275
    assign i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_select_15_b = i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_join(BITJOIN,8062)@275
    assign i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_select_15_b};

    // leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(MUX,26080)@275
    assign leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_join_q or leftShiftStage0Idx1_uid26079_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_101_c_compmm_m3105_vt_join_q;
            1'b1 : leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26079_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(MUX,26085)@275
    assign leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s or leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26084_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = leftShiftStage0_uid26081_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26084_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x(MUX,26090)@275
    assign leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s or leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26089_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = leftShiftStage1_uid26086_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26089_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28(BITSELECT,9844)@275
    assign i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28_b = leftShiftStage2_uid26091_i_shl_i_i_i_i_i_i_101_c_compmm_m0_shift_x_q[28:13];

    // redist374_i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28_b_1(DELAY,29502)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist374_i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_join(BITJOIN,9843)@276
    assign i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_join_q = {redist374_i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg53(REG,13348)@269 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg53_q <= $unsigned(redist860_sync_together4364_aunroll_x_in_i_valid_201_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_67222_c_compmm_m54(BLACKBOX,8575)@270
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67222_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_67222_c_compmm_m54 (
        .in_intel_reserved_ffwd_204_0(in_intel_reserved_ffwd_204_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg53_q),
        .out_dest_data_out_204_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_67222_c_compmm_m54_out_dest_data_out_204_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_offset(CONSTANT,31469)
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_offset_q = $unsigned(8'b00111011);

    // redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt(ADD,31470)
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_a = {1'b0, redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_q};
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_b = {1'b0, redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_o <= $unsigned(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_a) + $unsigned(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_b);
        end
    end
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_q = redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_o[8:0];

    // redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_inputreg0(DELAY,31465)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_inputreg0_q <= $unsigned(in_c1_eni5_203_tpl);
        end
    end

    // redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr(COUNTER,31468)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_i <= $unsigned(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_q = redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_i[7:0];

    // redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem(DUALMEM,31467)
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_ia = $unsigned(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_inputreg0_q);
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_aa = redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_wraddr_q;
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_ab = redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_aa),
        .data_a(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_ab),
        .q_b(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_q = redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_iq[15:0];

    // redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_outputreg0(DELAY,31466)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_outputreg0_q <= $unsigned(redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_mem_q);
        end
    end

    // redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt(ADD,31476)
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_a = {1'b0, redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_q};
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_b = {1'b0, redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_o <= $unsigned(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_a) + $unsigned(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_b);
        end
    end
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_q = redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_o[8:0];

    // redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_inputreg0(DELAY,31471)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_inputreg0_q <= $unsigned(in_c1_eni5_204_tpl);
        end
    end

    // redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr(COUNTER,31474)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_i <= $unsigned(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_q = redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_i[7:0];

    // redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem(DUALMEM,31473)
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_ia = $unsigned(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_inputreg0_q);
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_aa = redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_wraddr_q;
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_ab = redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_aa),
        .data_a(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_ab),
        .q_b(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_q = redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_iq[15:0];

    // redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_outputreg0(DELAY,31472)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_outputreg0_q <= $unsigned(redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_mem_q);
        end
    end

    // valid_fanout_reg54(REG,13349)@269 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg54_q <= $unsigned(redist860_sync_together4364_aunroll_x_in_i_valid_201_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_67221_c_compmm_m55(BLACKBOX,8571)@270
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67221_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_67221_c_compmm_m55 (
        .in_intel_reserved_ffwd_203_0(in_intel_reserved_ffwd_203_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg54_q),
        .out_dest_data_out_203_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_67221_c_compmm_m55_out_dest_data_out_203_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28972)@270 + 5
    // out q@276
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_67221_c_compmm_m55_out_dest_data_out_203_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_67222_c_compmm_m54_out_dest_data_out_204_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107(ADD,8948)@276
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod787_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_b = $unsigned({{5{i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_101_c_compmm_m3106_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_o[33:0];

    // rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x(MUX,22133)@276
    assign rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q or rightShiftStage0Idx1_uid22132_dupName_405_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q;
            1'b1 : rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22132_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x(MUX,22138)@276
    assign rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22137_dupName_405_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22134_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22137_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x(MUX,22143)@276
    assign rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22142_dupName_405_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22139_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22142_dupName_405_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3108_vt_select_20(BITSELECT,11916)@276
    assign i_unnamed_c_compmm_m3108_vt_select_20_b = rightShiftStage2_uid22144_dupName_405_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3108_vt_join(BITJOIN,11915)@276
    assign i_unnamed_c_compmm_m3108_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3108_vt_select_20_b};

    // i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x(BITSELECT,3706)@276
    assign i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x_b = i_unnamed_c_compmm_m3108_vt_join_q[15:0];

    // redist1012_i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x_b_1(DELAY,30140)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1012_i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22153_dupName_406_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22152)@276
    assign rightShiftStage1Idx1Rng8_uid22153_dupName_406_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22155_dupName_406_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22154)@276
    assign rightShiftStage1Idx1_uid22155_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22153_dupName_406_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22148_dupName_406_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22147)@276
    assign rightShiftStage0Idx1Rng4_uid22148_dupName_406_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q[33:4];

    // rightShiftStage0Idx1_uid22150_dupName_406_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22149)@276
    assign rightShiftStage0Idx1_uid22150_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22148_dupName_406_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x(MUX,22151)@276
    assign rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q or rightShiftStage0Idx1_uid22150_dupName_406_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_101_i_c_compmm_m3107_q;
            1'b1 : rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22150_dupName_406_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x(MUX,22156)@276
    assign rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22155_dupName_406_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22152_dupName_406_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22155_dupName_406_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3110_vt_select_21(BITSELECT,11919)@276
    assign i_unnamed_c_compmm_m3110_vt_select_21_b = rightShiftStage1_uid22157_dupName_406_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3110_vt_join(BITJOIN,11918)@276
    assign i_unnamed_c_compmm_m3110_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3110_vt_select_21_b};

    // i_unnamed_c_compmm_m3111_sel_x(BITSELECT,6158)@276
    assign i_unnamed_c_compmm_m3111_sel_x_b = i_unnamed_c_compmm_m3110_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3112_BitSelect_for_a(BITSELECT,28668)@276
    assign i_unnamed_c_compmm_m3112_BitSelect_for_a_b = i_unnamed_c_compmm_m3111_sel_x_b[0:0];

    // redist0_i_unnamed_c_compmm_m3112_BitSelect_for_a_b_1(DELAY,29128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist0_i_unnamed_c_compmm_m3112_BitSelect_for_a_b_1_q <= $unsigned(i_unnamed_c_compmm_m3112_BitSelect_for_a_b);
        end
    end

    // i_unnamed_c_compmm_m3112_join(BITJOIN,28669)@277
    assign i_unnamed_c_compmm_m3112_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, redist0_i_unnamed_c_compmm_m3112_BitSelect_for_a_b_1_q};

    // i_unnamed_c_compmm_m3112_vt_select_0(BITSELECT,11924)@277
    assign i_unnamed_c_compmm_m3112_vt_select_0_b = i_unnamed_c_compmm_m3112_join_q[0:0];

    // i_unnamed_c_compmm_m3112_vt_join(BITJOIN,11923)@277
    assign i_unnamed_c_compmm_m3112_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, i_unnamed_c_compmm_m3112_vt_select_0_b};

    // i_add_i_i_i_i_i_i_101_c_compmm_m3113(ADD,7161)@277
    assign i_add_i_i_i_i_i_i_101_c_compmm_m3113_a = {1'b0, i_unnamed_c_compmm_m3112_vt_join_q};
    assign i_add_i_i_i_i_i_i_101_c_compmm_m3113_b = {1'b0, redist1012_i_conv_i_i_i_i_i_101_c_compmm_m3109_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_101_c_compmm_m3113_o = $unsigned(i_add_i_i_i_i_i_i_101_c_compmm_m3113_a) + $unsigned(i_add_i_i_i_i_i_i_101_c_compmm_m3113_b);
    assign i_add_i_i_i_i_i_i_101_c_compmm_m3113_q = i_add_i_i_i_i_i_i_101_c_compmm_m3113_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x(BITSELECT,2175)@277
    assign bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x_b = i_add_i_i_i_i_i_i_101_c_compmm_m3113_q[15:0];

    // redist1146_bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x_b_1(DELAY,30274)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1146_bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x_b_1_q <= $unsigned(bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x_b);
        end
    end

    // i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_sel_x(BITSELECT,3835)@278
    assign i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_sel_x_b = {13'b0000000000000, redist1146_bgTrunc_i_add_i_i_i_i_i_i_101_c_compmm_m3113_sel_x_b_1_q[15:0]};

    // i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_select_15(BITSELECT,8067)@278
    assign i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_select_15_b = i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_join(BITJOIN,8066)@278
    assign i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_select_15_b};

    // leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(MUX,26098)@278
    assign leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_join_q or leftShiftStage0Idx1_uid26097_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_102_c_compmm_m3133_vt_join_q;
            1'b1 : leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26097_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(MUX,26103)@278
    assign leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s or leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26102_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = leftShiftStage0_uid26099_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26102_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x(MUX,26108)@278
    assign leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s or leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26107_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = leftShiftStage1_uid26104_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26107_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_select_28(BITSELECT,9847)@278
    assign i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_select_28_b = leftShiftStage2_uid26109_i_shl_i_i_i_i_i_i_102_c_compmm_m0_shift_x_q[28:13];

    // i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_join(BITJOIN,9846)@278
    assign i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_join_q = {i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_select_28_b, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg51(REG,13346)@271 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg51_q <= $unsigned(redist861_sync_together4364_aunroll_x_in_i_valid_203_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_67224_c_compmm_m52(BLACKBOX,8583)@272
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67224_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_67224_c_compmm_m52 (
        .in_intel_reserved_ffwd_206_0(in_intel_reserved_ffwd_206_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg51_q),
        .out_dest_data_out_206_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_67224_c_compmm_m52_out_dest_data_out_206_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_offset(CONSTANT,31481)
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_offset_q = $unsigned(8'b00111001);

    // redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt(ADD,31482)
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_a = {1'b0, redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_q};
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_b = {1'b0, redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_o <= $unsigned(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_a) + $unsigned(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_b);
        end
    end
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_q = redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_o[8:0];

    // redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_inputreg0(DELAY,31477)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_inputreg0_q <= $unsigned(in_c1_eni5_205_tpl);
        end
    end

    // redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr(COUNTER,31480)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_i <= $unsigned(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_q = redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_i[7:0];

    // redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem(DUALMEM,31479)
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_ia = $unsigned(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_inputreg0_q);
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_aa = redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_wraddr_q;
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_ab = redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_aa),
        .data_a(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_ab),
        .q_b(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_q = redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_iq[15:0];

    // redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_outputreg0(DELAY,31478)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_outputreg0_q <= $unsigned(redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_mem_q);
        end
    end

    // redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt(ADD,31488)
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_a = {1'b0, redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_q};
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_b = {1'b0, redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_o <= $unsigned(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_a) + $unsigned(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_b);
        end
    end
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_q = redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_o[8:0];

    // redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_inputreg0(DELAY,31483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_inputreg0_q <= $unsigned(in_c1_eni5_206_tpl);
        end
    end

    // redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr(COUNTER,31486)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_i <= $unsigned(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_q = redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_i[7:0];

    // redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem(DUALMEM,31485)
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_ia = $unsigned(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_inputreg0_q);
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_aa = redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_wraddr_q;
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_ab = redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_aa),
        .data_a(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_ab),
        .q_b(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_q = redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_iq[15:0];

    // redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_outputreg0(DELAY,31484)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_outputreg0_q <= $unsigned(redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_mem_q);
        end
    end

    // valid_fanout_reg52(REG,13347)@271 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg52_q <= $unsigned(redist861_sync_together4364_aunroll_x_in_i_valid_203_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_67223_c_compmm_m53(BLACKBOX,8579)@272
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67223_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_67223_c_compmm_m53 (
        .in_intel_reserved_ffwd_205_0(in_intel_reserved_ffwd_205_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg52_q),
        .out_dest_data_out_205_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_67223_c_compmm_m53_out_dest_data_out_205_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28973)@272 + 5
    // out q@278
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_67223_c_compmm_m53_out_dest_data_out_205_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_67224_c_compmm_m52_out_dest_data_out_206_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135(ADD,8949)@278
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod792_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_b = $unsigned({{5{i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_102_c_compmm_m3134_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_o[33:0];

    // rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x(MUX,22195)@278
    assign rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q or rightShiftStage0Idx1_uid22194_dupName_409_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q;
            1'b1 : rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22194_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x(MUX,22200)@278
    assign rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22199_dupName_409_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22196_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22199_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x(MUX,22205)@278
    assign rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22204_dupName_409_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22201_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22204_dupName_409_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3136_vt_select_20(BITSELECT,11938)@278
    assign i_unnamed_c_compmm_m3136_vt_select_20_b = rightShiftStage2_uid22206_dupName_409_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3136_vt_join(BITJOIN,11937)@278
    assign i_unnamed_c_compmm_m3136_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3136_vt_select_20_b};

    // i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x(BITSELECT,3707)@278
    assign i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x_b = i_unnamed_c_compmm_m3136_vt_join_q[15:0];

    // redist1011_i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x_b_1(DELAY,30139)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1011_i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22215_dupName_410_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22214)@278
    assign rightShiftStage1Idx1Rng8_uid22215_dupName_410_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22217_dupName_410_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22216)@278
    assign rightShiftStage1Idx1_uid22217_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22215_dupName_410_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22210_dupName_410_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22209)@278
    assign rightShiftStage0Idx1Rng4_uid22210_dupName_410_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q[33:4];

    // rightShiftStage0Idx1_uid22212_dupName_410_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22211)@278
    assign rightShiftStage0Idx1_uid22212_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22210_dupName_410_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x(MUX,22213)@278
    assign rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q or rightShiftStage0Idx1_uid22212_dupName_410_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_102_i_c_compmm_m3135_q;
            1'b1 : rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22212_dupName_410_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x(MUX,22218)@278
    assign rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22217_dupName_410_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22214_dupName_410_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22217_dupName_410_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3138_vt_select_21(BITSELECT,11941)@278
    assign i_unnamed_c_compmm_m3138_vt_select_21_b = rightShiftStage1_uid22219_dupName_410_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3138_vt_join(BITJOIN,11940)@278
    assign i_unnamed_c_compmm_m3138_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3138_vt_select_21_b};

    // i_unnamed_c_compmm_m3139_sel_x(BITSELECT,6160)@278
    assign i_unnamed_c_compmm_m3139_sel_x_b = i_unnamed_c_compmm_m3138_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3140_BitSelect_for_a(BITSELECT,28672)@278
    assign i_unnamed_c_compmm_m3140_BitSelect_for_a_b = i_unnamed_c_compmm_m3139_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3140_join(BITJOIN,28673)@278
    assign i_unnamed_c_compmm_m3140_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3140_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3140_vt_select_0(BITSELECT,11946)@278
    assign i_unnamed_c_compmm_m3140_vt_select_0_b = i_unnamed_c_compmm_m3140_join_q[0:0];

    // redist101_i_unnamed_c_compmm_m3140_vt_select_0_b_1(DELAY,29229)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist101_i_unnamed_c_compmm_m3140_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3140_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3140_vt_join(BITJOIN,11945)@279
    assign i_unnamed_c_compmm_m3140_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist101_i_unnamed_c_compmm_m3140_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_102_c_compmm_m3141(ADD,7162)@279
    assign i_add_i_i_i_i_i_i_102_c_compmm_m3141_a = {1'b0, i_unnamed_c_compmm_m3140_vt_join_q};
    assign i_add_i_i_i_i_i_i_102_c_compmm_m3141_b = {1'b0, redist1011_i_conv_i_i_i_i_i_102_c_compmm_m3137_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_102_c_compmm_m3141_o = $unsigned(i_add_i_i_i_i_i_i_102_c_compmm_m3141_a) + $unsigned(i_add_i_i_i_i_i_i_102_c_compmm_m3141_b);
    assign i_add_i_i_i_i_i_i_102_c_compmm_m3141_q = i_add_i_i_i_i_i_i_102_c_compmm_m3141_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x(BITSELECT,2176)@279
    assign bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x_b = i_add_i_i_i_i_i_i_102_c_compmm_m3141_q[15:0];

    // redist1145_bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x_b_1(DELAY,30273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1145_bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x_b_1_q <= $unsigned(bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x_b);
        end
    end

    // i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_sel_x(BITSELECT,3836)@280
    assign i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_sel_x_b = {13'b0000000000000, redist1145_bgTrunc_i_add_i_i_i_i_i_i_102_c_compmm_m3141_sel_x_b_1_q[15:0]};

    // i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_select_15(BITSELECT,8071)@280
    assign i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_select_15_b = i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_join(BITJOIN,8070)@280
    assign i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_select_15_b};

    // leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(MUX,26116)@280
    assign leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_join_q or leftShiftStage0Idx1_uid26115_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_103_c_compmm_m3161_vt_join_q;
            1'b1 : leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26115_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(MUX,26121)@280
    assign leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s or leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26120_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = leftShiftStage0_uid26117_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26120_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x(MUX,26126)@280
    assign leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s or leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26125_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = leftShiftStage1_uid26122_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26125_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_select_28(BITSELECT,9850)@280
    assign i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_select_28_b = leftShiftStage2_uid26127_i_shl_i_i_i_i_i_i_103_c_compmm_m0_shift_x_q[28:13];

    // i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_join(BITJOIN,9849)@280
    assign i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_join_q = {i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_select_28_b, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg49(REG,13344)@273 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg49_q <= $unsigned(redist862_sync_together4364_aunroll_x_in_i_valid_205_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_67226_c_compmm_m50(BLACKBOX,8591)@274
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67226_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_67226_c_compmm_m50 (
        .in_intel_reserved_ffwd_208_0(in_intel_reserved_ffwd_208_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg49_q),
        .out_dest_data_out_208_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_67226_c_compmm_m50_out_dest_data_out_208_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_offset(CONSTANT,31493)
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_offset_q = $unsigned(8'b00110111);

    // redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt(ADD,31494)
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_a = {1'b0, redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_q};
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_b = {1'b0, redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_o <= $unsigned(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_a) + $unsigned(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_b);
        end
    end
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_q = redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_o[8:0];

    // redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_inputreg0(DELAY,31489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_inputreg0_q <= $unsigned(in_c1_eni5_207_tpl);
        end
    end

    // redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr(COUNTER,31492)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_i <= $unsigned(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_q = redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_i[7:0];

    // redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem(DUALMEM,31491)
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_ia = $unsigned(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_inputreg0_q);
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_aa = redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_wraddr_q;
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_ab = redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_aa),
        .data_a(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_ab),
        .q_b(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_q = redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_iq[15:0];

    // redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_outputreg0(DELAY,31490)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_outputreg0_q <= $unsigned(redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_mem_q);
        end
    end

    // redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt(ADD,31500)
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_a = {1'b0, redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_q};
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_b = {1'b0, redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_o <= $unsigned(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_a) + $unsigned(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_b);
        end
    end
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_q = redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_o[8:0];

    // redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_inputreg0(DELAY,31495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_inputreg0_q <= $unsigned(in_c1_eni5_208_tpl);
        end
    end

    // redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr(COUNTER,31498)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_i <= $unsigned(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_q = redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_i[7:0];

    // redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem(DUALMEM,31497)
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_ia = $unsigned(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_inputreg0_q);
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_aa = redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_wraddr_q;
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_ab = redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_aa),
        .data_a(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_ab),
        .q_b(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_q = redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_iq[15:0];

    // redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_outputreg0(DELAY,31496)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_outputreg0_q <= $unsigned(redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_mem_q);
        end
    end

    // valid_fanout_reg50(REG,13345)@273 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg50_q <= $unsigned(redist862_sync_together4364_aunroll_x_in_i_valid_205_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_67225_c_compmm_m51(BLACKBOX,8587)@274
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67225_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_67225_c_compmm_m51 (
        .in_intel_reserved_ffwd_207_0(in_intel_reserved_ffwd_207_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg50_q),
        .out_dest_data_out_207_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_67225_c_compmm_m51_out_dest_data_out_207_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28974)@274 + 5
    // out q@280
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_67225_c_compmm_m51_out_dest_data_out_207_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_67226_c_compmm_m50_out_dest_data_out_208_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163(ADD,8950)@280
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod797_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_b = $unsigned({{5{i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_103_c_compmm_m3162_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_o[33:0];

    // rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x(MUX,22257)@280
    assign rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q or rightShiftStage0Idx1_uid22256_dupName_413_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q;
            1'b1 : rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22256_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x(MUX,22262)@280
    assign rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22261_dupName_413_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22258_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22261_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x(MUX,22267)@280
    assign rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22266_dupName_413_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22263_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22266_dupName_413_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3164_vt_select_20(BITSELECT,11960)@280
    assign i_unnamed_c_compmm_m3164_vt_select_20_b = rightShiftStage2_uid22268_dupName_413_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3164_vt_join(BITJOIN,11959)@280
    assign i_unnamed_c_compmm_m3164_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3164_vt_select_20_b};

    // i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x(BITSELECT,3708)@280
    assign i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x_b = i_unnamed_c_compmm_m3164_vt_join_q[15:0];

    // redist1010_i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x_b_1(DELAY,30138)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1010_i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22277_dupName_414_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22276)@280
    assign rightShiftStage1Idx1Rng8_uid22277_dupName_414_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22279_dupName_414_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22278)@280
    assign rightShiftStage1Idx1_uid22279_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22277_dupName_414_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22272_dupName_414_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22271)@280
    assign rightShiftStage0Idx1Rng4_uid22272_dupName_414_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q[33:4];

    // rightShiftStage0Idx1_uid22274_dupName_414_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22273)@280
    assign rightShiftStage0Idx1_uid22274_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22272_dupName_414_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x(MUX,22275)@280
    assign rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q or rightShiftStage0Idx1_uid22274_dupName_414_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_103_i_c_compmm_m3163_q;
            1'b1 : rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22274_dupName_414_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x(MUX,22280)@280
    assign rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22279_dupName_414_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22276_dupName_414_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22279_dupName_414_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3166_vt_select_21(BITSELECT,11963)@280
    assign i_unnamed_c_compmm_m3166_vt_select_21_b = rightShiftStage1_uid22281_dupName_414_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3166_vt_join(BITJOIN,11962)@280
    assign i_unnamed_c_compmm_m3166_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3166_vt_select_21_b};

    // i_unnamed_c_compmm_m3167_sel_x(BITSELECT,6162)@280
    assign i_unnamed_c_compmm_m3167_sel_x_b = i_unnamed_c_compmm_m3166_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3168_BitSelect_for_a(BITSELECT,28676)@280
    assign i_unnamed_c_compmm_m3168_BitSelect_for_a_b = i_unnamed_c_compmm_m3167_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3168_join(BITJOIN,28677)@280
    assign i_unnamed_c_compmm_m3168_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3168_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3168_vt_select_0(BITSELECT,11968)@280
    assign i_unnamed_c_compmm_m3168_vt_select_0_b = i_unnamed_c_compmm_m3168_join_q[0:0];

    // redist99_i_unnamed_c_compmm_m3168_vt_select_0_b_1(DELAY,29227)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist99_i_unnamed_c_compmm_m3168_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3168_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3168_vt_join(BITJOIN,11967)@281
    assign i_unnamed_c_compmm_m3168_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist99_i_unnamed_c_compmm_m3168_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_103_c_compmm_m3169(ADD,7163)@281
    assign i_add_i_i_i_i_i_i_103_c_compmm_m3169_a = {1'b0, i_unnamed_c_compmm_m3168_vt_join_q};
    assign i_add_i_i_i_i_i_i_103_c_compmm_m3169_b = {1'b0, redist1010_i_conv_i_i_i_i_i_103_c_compmm_m3165_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_103_c_compmm_m3169_o = $unsigned(i_add_i_i_i_i_i_i_103_c_compmm_m3169_a) + $unsigned(i_add_i_i_i_i_i_i_103_c_compmm_m3169_b);
    assign i_add_i_i_i_i_i_i_103_c_compmm_m3169_q = i_add_i_i_i_i_i_i_103_c_compmm_m3169_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x(BITSELECT,2177)@281
    assign bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x_b = i_add_i_i_i_i_i_i_103_c_compmm_m3169_q[15:0];

    // redist1144_bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x_b_1(DELAY,30272)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1144_bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x_b_1_q <= $unsigned(bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x_b);
        end
    end

    // i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_sel_x(BITSELECT,3837)@282
    assign i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_sel_x_b = {13'b0000000000000, redist1144_bgTrunc_i_add_i_i_i_i_i_i_103_c_compmm_m3169_sel_x_b_1_q[15:0]};

    // i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_select_15(BITSELECT,8075)@282
    assign i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_select_15_b = i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_join(BITJOIN,8074)@282
    assign i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_select_15_b};

    // leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(MUX,26134)@282
    assign leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_join_q or leftShiftStage0Idx1_uid26133_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_104_c_compmm_m3189_vt_join_q;
            1'b1 : leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26133_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(MUX,26139)@282
    assign leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s or leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26138_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = leftShiftStage0_uid26135_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26138_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x(MUX,26144)@282
    assign leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s or leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26143_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = leftShiftStage1_uid26140_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26143_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_select_28(BITSELECT,9853)@282
    assign i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_select_28_b = leftShiftStage2_uid26145_i_shl_i_i_i_i_i_i_104_c_compmm_m0_shift_x_q[28:13];

    // i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_join(BITJOIN,9852)@282
    assign i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_join_q = {i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_select_28_b, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg47(REG,13342)@275 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg47_q <= $unsigned(redist863_sync_together4364_aunroll_x_in_i_valid_207_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_67228_c_compmm_m48(BLACKBOX,8599)@276
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67228_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_67228_c_compmm_m48 (
        .in_intel_reserved_ffwd_210_0(in_intel_reserved_ffwd_210_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg47_q),
        .out_dest_data_out_210_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_67228_c_compmm_m48_out_dest_data_out_210_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_offset(CONSTANT,31505)
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_offset_q = $unsigned(8'b00110101);

    // redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt(ADD,31506)
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_a = {1'b0, redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_q};
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_b = {1'b0, redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_o <= $unsigned(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_a) + $unsigned(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_b);
        end
    end
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_q = redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_o[8:0];

    // redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_inputreg0(DELAY,31501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_inputreg0_q <= $unsigned(in_c1_eni5_209_tpl);
        end
    end

    // redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr(COUNTER,31504)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_i <= $unsigned(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_q = redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_i[7:0];

    // redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem(DUALMEM,31503)
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_ia = $unsigned(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_inputreg0_q);
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_aa = redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_wraddr_q;
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_ab = redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_aa),
        .data_a(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_ab),
        .q_b(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_q = redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_iq[15:0];

    // redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_outputreg0(DELAY,31502)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_outputreg0_q <= $unsigned(redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_mem_q);
        end
    end

    // redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt(ADD,31512)
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_a = {1'b0, redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_q};
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_b = {1'b0, redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_o <= $unsigned(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_a) + $unsigned(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_b);
        end
    end
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_q = redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_o[8:0];

    // redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_inputreg0(DELAY,31507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_inputreg0_q <= $unsigned(in_c1_eni5_210_tpl);
        end
    end

    // redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr(COUNTER,31510)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_i <= $unsigned(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_q = redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_i[7:0];

    // redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem(DUALMEM,31509)
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_ia = $unsigned(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_inputreg0_q);
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_aa = redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_wraddr_q;
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_ab = redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_aa),
        .data_a(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_ab),
        .q_b(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_q = redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_iq[15:0];

    // redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_outputreg0(DELAY,31508)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_outputreg0_q <= $unsigned(redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_mem_q);
        end
    end

    // valid_fanout_reg48(REG,13343)@275 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg48_q <= $unsigned(redist863_sync_together4364_aunroll_x_in_i_valid_207_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_67227_c_compmm_m49(BLACKBOX,8595)@276
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67227_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_67227_c_compmm_m49 (
        .in_intel_reserved_ffwd_209_0(in_intel_reserved_ffwd_209_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg48_q),
        .out_dest_data_out_209_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_67227_c_compmm_m49_out_dest_data_out_209_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28975)@276 + 5
    // out q@282
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_67227_c_compmm_m49_out_dest_data_out_209_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_67228_c_compmm_m48_out_dest_data_out_210_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191(ADD,8951)@282
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod802_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_b = $unsigned({{5{i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_104_c_compmm_m3190_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_o[33:0];

    // rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x(MUX,22319)@282
    assign rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q or rightShiftStage0Idx1_uid22318_dupName_417_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q;
            1'b1 : rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22318_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x(MUX,22324)@282
    assign rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22323_dupName_417_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22320_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22323_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x(MUX,22329)@282
    assign rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22328_dupName_417_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22325_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22328_dupName_417_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3192_vt_select_20(BITSELECT,11985)@282
    assign i_unnamed_c_compmm_m3192_vt_select_20_b = rightShiftStage2_uid22330_dupName_417_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3192_vt_join(BITJOIN,11984)@282
    assign i_unnamed_c_compmm_m3192_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3192_vt_select_20_b};

    // i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x(BITSELECT,3709)@282
    assign i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x_b = i_unnamed_c_compmm_m3192_vt_join_q[15:0];

    // redist1009_i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x_b_1(DELAY,30137)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1009_i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22339_dupName_418_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22338)@282
    assign rightShiftStage1Idx1Rng8_uid22339_dupName_418_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22341_dupName_418_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22340)@282
    assign rightShiftStage1Idx1_uid22341_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22339_dupName_418_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22334_dupName_418_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22333)@282
    assign rightShiftStage0Idx1Rng4_uid22334_dupName_418_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q[33:4];

    // rightShiftStage0Idx1_uid22336_dupName_418_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22335)@282
    assign rightShiftStage0Idx1_uid22336_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22334_dupName_418_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x(MUX,22337)@282
    assign rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q or rightShiftStage0Idx1_uid22336_dupName_418_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_104_i_c_compmm_m3191_q;
            1'b1 : rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22336_dupName_418_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x(MUX,22342)@282
    assign rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22341_dupName_418_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22338_dupName_418_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22341_dupName_418_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3194_vt_select_21(BITSELECT,11988)@282
    assign i_unnamed_c_compmm_m3194_vt_select_21_b = rightShiftStage1_uid22343_dupName_418_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3194_vt_join(BITJOIN,11987)@282
    assign i_unnamed_c_compmm_m3194_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3194_vt_select_21_b};

    // i_unnamed_c_compmm_m3195_sel_x(BITSELECT,6164)@282
    assign i_unnamed_c_compmm_m3195_sel_x_b = i_unnamed_c_compmm_m3194_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3196_BitSelect_for_a(BITSELECT,28680)@282
    assign i_unnamed_c_compmm_m3196_BitSelect_for_a_b = i_unnamed_c_compmm_m3195_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3196_join(BITJOIN,28681)@282
    assign i_unnamed_c_compmm_m3196_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3196_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3196_vt_select_0(BITSELECT,11993)@282
    assign i_unnamed_c_compmm_m3196_vt_select_0_b = i_unnamed_c_compmm_m3196_join_q[0:0];

    // redist97_i_unnamed_c_compmm_m3196_vt_select_0_b_1(DELAY,29225)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist97_i_unnamed_c_compmm_m3196_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3196_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3196_vt_join(BITJOIN,11992)@283
    assign i_unnamed_c_compmm_m3196_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist97_i_unnamed_c_compmm_m3196_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_104_c_compmm_m3197(ADD,7164)@283
    assign i_add_i_i_i_i_i_i_104_c_compmm_m3197_a = {1'b0, i_unnamed_c_compmm_m3196_vt_join_q};
    assign i_add_i_i_i_i_i_i_104_c_compmm_m3197_b = {1'b0, redist1009_i_conv_i_i_i_i_i_104_c_compmm_m3193_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_104_c_compmm_m3197_o = $unsigned(i_add_i_i_i_i_i_i_104_c_compmm_m3197_a) + $unsigned(i_add_i_i_i_i_i_i_104_c_compmm_m3197_b);
    assign i_add_i_i_i_i_i_i_104_c_compmm_m3197_q = i_add_i_i_i_i_i_i_104_c_compmm_m3197_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_104_c_compmm_m3197_sel_x(BITSELECT,2178)@283
    assign bgTrunc_i_add_i_i_i_i_i_i_104_c_compmm_m3197_sel_x_b = i_add_i_i_i_i_i_i_104_c_compmm_m3197_q[15:0];

    // i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_sel_x(BITSELECT,3838)@283
    assign i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_104_c_compmm_m3197_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_select_15(BITSELECT,8079)@283
    assign i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_select_15_b = i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_join(BITJOIN,8078)@283
    assign i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_select_15_b};

    // leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(MUX,26152)@283
    assign leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_join_q or leftShiftStage0Idx1_uid26151_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_105_c_compmm_m3217_vt_join_q;
            1'b1 : leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26151_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(MUX,26157)@283
    assign leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s or leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26156_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = leftShiftStage0_uid26153_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26156_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x(MUX,26162)@283
    assign leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s or leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26161_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = leftShiftStage1_uid26158_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26161_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28(BITSELECT,9856)@283
    assign i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28_b = leftShiftStage2_uid26163_i_shl_i_i_i_i_i_i_105_c_compmm_m0_shift_x_q[28:13];

    // redist373_i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28_b_1(DELAY,29501)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist373_i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_join(BITJOIN,9855)@284
    assign i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_join_q = {redist373_i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg45(REG,13340)@277 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg45_q <= $unsigned(redist864_sync_together4364_aunroll_x_in_i_valid_209_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_67230_c_compmm_m46(BLACKBOX,8607)@278
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67230_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_67230_c_compmm_m46 (
        .in_intel_reserved_ffwd_212_0(in_intel_reserved_ffwd_212_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg45_q),
        .out_dest_data_out_212_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_67230_c_compmm_m46_out_dest_data_out_212_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_offset(CONSTANT,31517)
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_offset_q = $unsigned(8'b00110011);

    // redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt(ADD,31518)
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_a = {1'b0, redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_q};
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_b = {1'b0, redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_o <= $unsigned(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_a) + $unsigned(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_b);
        end
    end
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_q = redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_o[8:0];

    // redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_inputreg0(DELAY,31513)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_inputreg0_q <= $unsigned(in_c1_eni5_211_tpl);
        end
    end

    // redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr(COUNTER,31516)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_i <= $unsigned(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_q = redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_i[7:0];

    // redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem(DUALMEM,31515)
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_ia = $unsigned(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_inputreg0_q);
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_aa = redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_wraddr_q;
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_ab = redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_aa),
        .data_a(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_ab),
        .q_b(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_q = redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_iq[15:0];

    // redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_outputreg0(DELAY,31514)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_outputreg0_q <= $unsigned(redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_mem_q);
        end
    end

    // redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt(ADD,31524)
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_a = {1'b0, redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_q};
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_b = {1'b0, redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_o <= $unsigned(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_a) + $unsigned(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_b);
        end
    end
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_q = redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_o[8:0];

    // redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_inputreg0(DELAY,31519)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_inputreg0_q <= $unsigned(in_c1_eni5_212_tpl);
        end
    end

    // redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr(COUNTER,31522)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_i <= $unsigned(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_q = redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_i[7:0];

    // redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem(DUALMEM,31521)
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_ia = $unsigned(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_inputreg0_q);
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_aa = redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_wraddr_q;
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_ab = redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_aa),
        .data_a(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_ab),
        .q_b(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_q = redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_iq[15:0];

    // redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_outputreg0(DELAY,31520)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_outputreg0_q <= $unsigned(redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_mem_q);
        end
    end

    // valid_fanout_reg46(REG,13341)@277 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg46_q <= $unsigned(redist864_sync_together4364_aunroll_x_in_i_valid_209_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_67229_c_compmm_m47(BLACKBOX,8603)@278
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67229_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_67229_c_compmm_m47 (
        .in_intel_reserved_ffwd_211_0(in_intel_reserved_ffwd_211_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg46_q),
        .out_dest_data_out_211_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_67229_c_compmm_m47_out_dest_data_out_211_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28976)@278 + 5
    // out q@284
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_67229_c_compmm_m47_out_dest_data_out_211_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_67230_c_compmm_m46_out_dest_data_out_212_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219(ADD,8952)@284
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod807_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_b = $unsigned({{5{i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_105_c_compmm_m3218_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_o[33:0];

    // rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x(MUX,22381)@284
    assign rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q or rightShiftStage0Idx1_uid22380_dupName_421_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q;
            1'b1 : rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22380_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x(MUX,22386)@284
    assign rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22385_dupName_421_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22382_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22385_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x(MUX,22391)@284
    assign rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22390_dupName_421_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22387_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22390_dupName_421_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3220_vt_select_20(BITSELECT,12015)@284
    assign i_unnamed_c_compmm_m3220_vt_select_20_b = rightShiftStage2_uid22392_dupName_421_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3220_vt_join(BITJOIN,12014)@284
    assign i_unnamed_c_compmm_m3220_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3220_vt_select_20_b};

    // i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x(BITSELECT,3710)@284
    assign i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x_b = i_unnamed_c_compmm_m3220_vt_join_q[15:0];

    // redist1008_i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x_b_1(DELAY,30136)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1008_i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22401_dupName_422_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22400)@284
    assign rightShiftStage1Idx1Rng8_uid22401_dupName_422_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22403_dupName_422_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22402)@284
    assign rightShiftStage1Idx1_uid22403_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22401_dupName_422_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22396_dupName_422_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22395)@284
    assign rightShiftStage0Idx1Rng4_uid22396_dupName_422_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q[33:4];

    // rightShiftStage0Idx1_uid22398_dupName_422_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22397)@284
    assign rightShiftStage0Idx1_uid22398_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22396_dupName_422_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x(MUX,22399)@284
    assign rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q or rightShiftStage0Idx1_uid22398_dupName_422_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_105_i_c_compmm_m3219_q;
            1'b1 : rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22398_dupName_422_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x(MUX,22404)@284
    assign rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22403_dupName_422_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22400_dupName_422_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22403_dupName_422_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3222_vt_select_21(BITSELECT,12018)@284
    assign i_unnamed_c_compmm_m3222_vt_select_21_b = rightShiftStage1_uid22405_dupName_422_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3222_vt_join(BITJOIN,12017)@284
    assign i_unnamed_c_compmm_m3222_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3222_vt_select_21_b};

    // i_unnamed_c_compmm_m3223_sel_x(BITSELECT,6167)@284
    assign i_unnamed_c_compmm_m3223_sel_x_b = i_unnamed_c_compmm_m3222_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3224_BitSelect_for_a(BITSELECT,28686)@284
    assign i_unnamed_c_compmm_m3224_BitSelect_for_a_b = i_unnamed_c_compmm_m3223_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3224_join(BITJOIN,28687)@284
    assign i_unnamed_c_compmm_m3224_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3224_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3224_vt_select_0(BITSELECT,12023)@284
    assign i_unnamed_c_compmm_m3224_vt_select_0_b = i_unnamed_c_compmm_m3224_join_q[0:0];

    // redist94_i_unnamed_c_compmm_m3224_vt_select_0_b_1(DELAY,29222)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist94_i_unnamed_c_compmm_m3224_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3224_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3224_vt_join(BITJOIN,12022)@285
    assign i_unnamed_c_compmm_m3224_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist94_i_unnamed_c_compmm_m3224_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_105_c_compmm_m3225(ADD,7165)@285
    assign i_add_i_i_i_i_i_i_105_c_compmm_m3225_a = {1'b0, i_unnamed_c_compmm_m3224_vt_join_q};
    assign i_add_i_i_i_i_i_i_105_c_compmm_m3225_b = {1'b0, redist1008_i_conv_i_i_i_i_i_105_c_compmm_m3221_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_105_c_compmm_m3225_o = $unsigned(i_add_i_i_i_i_i_i_105_c_compmm_m3225_a) + $unsigned(i_add_i_i_i_i_i_i_105_c_compmm_m3225_b);
    assign i_add_i_i_i_i_i_i_105_c_compmm_m3225_q = i_add_i_i_i_i_i_i_105_c_compmm_m3225_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_105_c_compmm_m3225_sel_x(BITSELECT,2179)@285
    assign bgTrunc_i_add_i_i_i_i_i_i_105_c_compmm_m3225_sel_x_b = i_add_i_i_i_i_i_i_105_c_compmm_m3225_q[15:0];

    // i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_sel_x(BITSELECT,3839)@285
    assign i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_105_c_compmm_m3225_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_select_15(BITSELECT,8083)@285
    assign i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_select_15_b = i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_join(BITJOIN,8082)@285
    assign i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_select_15_b};

    // leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(MUX,26170)@285
    assign leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_join_q or leftShiftStage0Idx1_uid26169_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_106_c_compmm_m3245_vt_join_q;
            1'b1 : leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26169_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(MUX,26175)@285
    assign leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s or leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26174_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = leftShiftStage0_uid26171_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26174_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x(MUX,26180)@285
    assign leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s or leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26179_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = leftShiftStage1_uid26176_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26179_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28(BITSELECT,9859)@285
    assign i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28_b = leftShiftStage2_uid26181_i_shl_i_i_i_i_i_i_106_c_compmm_m0_shift_x_q[28:13];

    // redist372_i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28_b_1(DELAY,29500)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist372_i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_join(BITJOIN,9858)@286
    assign i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_join_q = {redist372_i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg43(REG,13338)@279 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg43_q <= $unsigned(redist865_sync_together4364_aunroll_x_in_i_valid_211_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_67232_c_compmm_m44(BLACKBOX,8619)@280
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67232_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_67232_c_compmm_m44 (
        .in_intel_reserved_ffwd_214_0(in_intel_reserved_ffwd_214_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg43_q),
        .out_dest_data_out_214_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_67232_c_compmm_m44_out_dest_data_out_214_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_offset(CONSTANT,31529)
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_offset_q = $unsigned(8'b00110001);

    // redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt(ADD,31530)
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_a = {1'b0, redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_q};
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_b = {1'b0, redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_o <= $unsigned(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_a) + $unsigned(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_b);
        end
    end
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_q = redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_o[8:0];

    // redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_inputreg0(DELAY,31525)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_inputreg0_q <= $unsigned(in_c1_eni5_213_tpl);
        end
    end

    // redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr(COUNTER,31528)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_i <= $unsigned(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_q = redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_i[7:0];

    // redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem(DUALMEM,31527)
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_ia = $unsigned(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_inputreg0_q);
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_aa = redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_wraddr_q;
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_ab = redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_aa),
        .data_a(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_ab),
        .q_b(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_q = redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_iq[15:0];

    // redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_outputreg0(DELAY,31526)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_outputreg0_q <= $unsigned(redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_mem_q);
        end
    end

    // redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt(ADD,31536)
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_a = {1'b0, redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_q};
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_b = {1'b0, redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_o <= $unsigned(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_a) + $unsigned(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_b);
        end
    end
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_q = redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_o[8:0];

    // redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_inputreg0(DELAY,31531)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_inputreg0_q <= $unsigned(in_c1_eni5_214_tpl);
        end
    end

    // redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr(COUNTER,31534)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_i <= $unsigned(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_q = redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_i[7:0];

    // redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem(DUALMEM,31533)
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_ia = $unsigned(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_inputreg0_q);
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_aa = redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_wraddr_q;
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_ab = redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_aa),
        .data_a(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_ab),
        .q_b(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_q = redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_iq[15:0];

    // redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_outputreg0(DELAY,31532)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_outputreg0_q <= $unsigned(redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_mem_q);
        end
    end

    // valid_fanout_reg44(REG,13339)@279 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg44_q <= $unsigned(redist865_sync_together4364_aunroll_x_in_i_valid_211_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_67231_c_compmm_m45(BLACKBOX,8615)@280
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67231_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_67231_c_compmm_m45 (
        .in_intel_reserved_ffwd_213_0(in_intel_reserved_ffwd_213_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg44_q),
        .out_dest_data_out_213_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_67231_c_compmm_m45_out_dest_data_out_213_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28977)@280 + 5
    // out q@286
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_67231_c_compmm_m45_out_dest_data_out_213_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_67232_c_compmm_m44_out_dest_data_out_214_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247(ADD,8953)@286
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod812_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_b = $unsigned({{5{i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_106_c_compmm_m3246_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_o[33:0];

    // rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x(MUX,22443)@286
    assign rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q or rightShiftStage0Idx1_uid22442_dupName_425_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q;
            1'b1 : rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22442_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x(MUX,22448)@286
    assign rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22447_dupName_425_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22444_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22447_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x(MUX,22453)@286
    assign rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22452_dupName_425_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22449_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22452_dupName_425_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3248_vt_select_20(BITSELECT,12037)@286
    assign i_unnamed_c_compmm_m3248_vt_select_20_b = rightShiftStage2_uid22454_dupName_425_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3248_vt_join(BITJOIN,12036)@286
    assign i_unnamed_c_compmm_m3248_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3248_vt_select_20_b};

    // i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x(BITSELECT,3711)@286
    assign i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x_b = i_unnamed_c_compmm_m3248_vt_join_q[15:0];

    // redist1007_i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x_b_1(DELAY,30135)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1007_i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22463_dupName_426_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22462)@286
    assign rightShiftStage1Idx1Rng8_uid22463_dupName_426_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22465_dupName_426_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22464)@286
    assign rightShiftStage1Idx1_uid22465_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22463_dupName_426_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22458_dupName_426_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22457)@286
    assign rightShiftStage0Idx1Rng4_uid22458_dupName_426_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q[33:4];

    // rightShiftStage0Idx1_uid22460_dupName_426_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22459)@286
    assign rightShiftStage0Idx1_uid22460_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22458_dupName_426_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x(MUX,22461)@286
    assign rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q or rightShiftStage0Idx1_uid22460_dupName_426_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_106_i_c_compmm_m3247_q;
            1'b1 : rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22460_dupName_426_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x(MUX,22466)@286
    assign rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22465_dupName_426_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22462_dupName_426_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22465_dupName_426_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3250_vt_select_21(BITSELECT,12040)@286
    assign i_unnamed_c_compmm_m3250_vt_select_21_b = rightShiftStage1_uid22467_dupName_426_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3250_vt_join(BITJOIN,12039)@286
    assign i_unnamed_c_compmm_m3250_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3250_vt_select_21_b};

    // i_unnamed_c_compmm_m3251_sel_x(BITSELECT,6169)@286
    assign i_unnamed_c_compmm_m3251_sel_x_b = i_unnamed_c_compmm_m3250_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3252_BitSelect_for_a(BITSELECT,28690)@286
    assign i_unnamed_c_compmm_m3252_BitSelect_for_a_b = i_unnamed_c_compmm_m3251_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3252_join(BITJOIN,28691)@286
    assign i_unnamed_c_compmm_m3252_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3252_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3252_vt_select_0(BITSELECT,12045)@286
    assign i_unnamed_c_compmm_m3252_vt_select_0_b = i_unnamed_c_compmm_m3252_join_q[0:0];

    // redist92_i_unnamed_c_compmm_m3252_vt_select_0_b_1(DELAY,29220)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist92_i_unnamed_c_compmm_m3252_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3252_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3252_vt_join(BITJOIN,12044)@287
    assign i_unnamed_c_compmm_m3252_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist92_i_unnamed_c_compmm_m3252_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_106_c_compmm_m3253(ADD,7166)@287
    assign i_add_i_i_i_i_i_i_106_c_compmm_m3253_a = {1'b0, i_unnamed_c_compmm_m3252_vt_join_q};
    assign i_add_i_i_i_i_i_i_106_c_compmm_m3253_b = {1'b0, redist1007_i_conv_i_i_i_i_i_106_c_compmm_m3249_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_106_c_compmm_m3253_o = $unsigned(i_add_i_i_i_i_i_i_106_c_compmm_m3253_a) + $unsigned(i_add_i_i_i_i_i_i_106_c_compmm_m3253_b);
    assign i_add_i_i_i_i_i_i_106_c_compmm_m3253_q = i_add_i_i_i_i_i_i_106_c_compmm_m3253_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_106_c_compmm_m3253_sel_x(BITSELECT,2180)@287
    assign bgTrunc_i_add_i_i_i_i_i_i_106_c_compmm_m3253_sel_x_b = i_add_i_i_i_i_i_i_106_c_compmm_m3253_q[15:0];

    // i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_sel_x(BITSELECT,3840)@287
    assign i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_106_c_compmm_m3253_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_select_15(BITSELECT,8087)@287
    assign i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_select_15_b = i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_join(BITJOIN,8086)@287
    assign i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_select_15_b};

    // leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(MUX,26188)@287
    assign leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_join_q or leftShiftStage0Idx1_uid26187_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_107_c_compmm_m3273_vt_join_q;
            1'b1 : leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26187_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(MUX,26193)@287
    assign leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s or leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26192_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = leftShiftStage0_uid26189_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26192_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x(MUX,26198)@287
    assign leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s or leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26197_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = leftShiftStage1_uid26194_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26197_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28(BITSELECT,9862)@287
    assign i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28_b = leftShiftStage2_uid26199_i_shl_i_i_i_i_i_i_107_c_compmm_m0_shift_x_q[28:13];

    // redist371_i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28_b_1(DELAY,29499)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist371_i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_join(BITJOIN,9861)@288
    assign i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_join_q = {redist371_i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg41(REG,13336)@281 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg41_q <= $unsigned(redist866_sync_together4364_aunroll_x_in_i_valid_213_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_67234_c_compmm_m42(BLACKBOX,8627)@282
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67234_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_67234_c_compmm_m42 (
        .in_intel_reserved_ffwd_216_0(in_intel_reserved_ffwd_216_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg41_q),
        .out_dest_data_out_216_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_67234_c_compmm_m42_out_dest_data_out_216_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_offset(CONSTANT,31541)
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_offset_q = $unsigned(8'b00101111);

    // redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt(ADD,31542)
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_a = {1'b0, redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_q};
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_b = {1'b0, redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_o <= $unsigned(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_a) + $unsigned(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_b);
        end
    end
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_q = redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_o[8:0];

    // redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_inputreg0(DELAY,31537)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_inputreg0_q <= $unsigned(in_c1_eni5_215_tpl);
        end
    end

    // redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr(COUNTER,31540)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_i <= $unsigned(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_q = redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_i[7:0];

    // redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem(DUALMEM,31539)
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_ia = $unsigned(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_inputreg0_q);
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_aa = redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_wraddr_q;
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_ab = redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_aa),
        .data_a(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_ab),
        .q_b(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_q = redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_iq[15:0];

    // redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_outputreg0(DELAY,31538)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_outputreg0_q <= $unsigned(redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_mem_q);
        end
    end

    // redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt(ADD,31548)
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_a = {1'b0, redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_q};
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_b = {1'b0, redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_o <= $unsigned(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_a) + $unsigned(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_b);
        end
    end
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_q = redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_o[8:0];

    // redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_inputreg0(DELAY,31543)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_inputreg0_q <= $unsigned(in_c1_eni5_216_tpl);
        end
    end

    // redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr(COUNTER,31546)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_i <= $unsigned(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_q = redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_i[7:0];

    // redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem(DUALMEM,31545)
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_ia = $unsigned(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_inputreg0_q);
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_aa = redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_wraddr_q;
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_ab = redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_aa),
        .data_a(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_ab),
        .q_b(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_q = redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_iq[15:0];

    // redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_outputreg0(DELAY,31544)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_outputreg0_q <= $unsigned(redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_mem_q);
        end
    end

    // valid_fanout_reg42(REG,13337)@281 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg42_q <= $unsigned(redist866_sync_together4364_aunroll_x_in_i_valid_213_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_67233_c_compmm_m43(BLACKBOX,8623)@282
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67233_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_67233_c_compmm_m43 (
        .in_intel_reserved_ffwd_215_0(in_intel_reserved_ffwd_215_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg42_q),
        .out_dest_data_out_215_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_67233_c_compmm_m43_out_dest_data_out_215_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28978)@282 + 5
    // out q@288
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_67233_c_compmm_m43_out_dest_data_out_215_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_67234_c_compmm_m42_out_dest_data_out_216_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275(ADD,8954)@288
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod817_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_b = $unsigned({{5{i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_107_c_compmm_m3274_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_o[33:0];

    // rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x(MUX,22505)@288
    assign rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q or rightShiftStage0Idx1_uid22504_dupName_429_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q;
            1'b1 : rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22504_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x(MUX,22510)@288
    assign rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22509_dupName_429_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22506_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22509_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x(MUX,22515)@288
    assign rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22514_dupName_429_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22511_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22514_dupName_429_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3276_vt_select_20(BITSELECT,12059)@288
    assign i_unnamed_c_compmm_m3276_vt_select_20_b = rightShiftStage2_uid22516_dupName_429_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3276_vt_join(BITJOIN,12058)@288
    assign i_unnamed_c_compmm_m3276_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3276_vt_select_20_b};

    // i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x(BITSELECT,3712)@288
    assign i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x_b = i_unnamed_c_compmm_m3276_vt_join_q[15:0];

    // redist1006_i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x_b_1(DELAY,30134)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1006_i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22525_dupName_430_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22524)@288
    assign rightShiftStage1Idx1Rng8_uid22525_dupName_430_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22527_dupName_430_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22526)@288
    assign rightShiftStage1Idx1_uid22527_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22525_dupName_430_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22520_dupName_430_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22519)@288
    assign rightShiftStage0Idx1Rng4_uid22520_dupName_430_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q[33:4];

    // rightShiftStage0Idx1_uid22522_dupName_430_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22521)@288
    assign rightShiftStage0Idx1_uid22522_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22520_dupName_430_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x(MUX,22523)@288
    assign rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q or rightShiftStage0Idx1_uid22522_dupName_430_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_107_i_c_compmm_m3275_q;
            1'b1 : rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22522_dupName_430_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x(MUX,22528)@288
    assign rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22527_dupName_430_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22524_dupName_430_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22527_dupName_430_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3278_vt_select_21(BITSELECT,12062)@288
    assign i_unnamed_c_compmm_m3278_vt_select_21_b = rightShiftStage1_uid22529_dupName_430_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3278_vt_join(BITJOIN,12061)@288
    assign i_unnamed_c_compmm_m3278_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3278_vt_select_21_b};

    // i_unnamed_c_compmm_m3279_sel_x(BITSELECT,6171)@288
    assign i_unnamed_c_compmm_m3279_sel_x_b = i_unnamed_c_compmm_m3278_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3280_BitSelect_for_a(BITSELECT,28694)@288
    assign i_unnamed_c_compmm_m3280_BitSelect_for_a_b = i_unnamed_c_compmm_m3279_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3280_join(BITJOIN,28695)@288
    assign i_unnamed_c_compmm_m3280_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3280_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3280_vt_select_0(BITSELECT,12067)@288
    assign i_unnamed_c_compmm_m3280_vt_select_0_b = i_unnamed_c_compmm_m3280_join_q[0:0];

    // redist90_i_unnamed_c_compmm_m3280_vt_select_0_b_1(DELAY,29218)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist90_i_unnamed_c_compmm_m3280_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3280_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3280_vt_join(BITJOIN,12066)@289
    assign i_unnamed_c_compmm_m3280_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist90_i_unnamed_c_compmm_m3280_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_107_c_compmm_m3281(ADD,7167)@289
    assign i_add_i_i_i_i_i_i_107_c_compmm_m3281_a = {1'b0, i_unnamed_c_compmm_m3280_vt_join_q};
    assign i_add_i_i_i_i_i_i_107_c_compmm_m3281_b = {1'b0, redist1006_i_conv_i_i_i_i_i_107_c_compmm_m3277_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_107_c_compmm_m3281_o = $unsigned(i_add_i_i_i_i_i_i_107_c_compmm_m3281_a) + $unsigned(i_add_i_i_i_i_i_i_107_c_compmm_m3281_b);
    assign i_add_i_i_i_i_i_i_107_c_compmm_m3281_q = i_add_i_i_i_i_i_i_107_c_compmm_m3281_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_107_c_compmm_m3281_sel_x(BITSELECT,2181)@289
    assign bgTrunc_i_add_i_i_i_i_i_i_107_c_compmm_m3281_sel_x_b = i_add_i_i_i_i_i_i_107_c_compmm_m3281_q[15:0];

    // i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_sel_x(BITSELECT,3841)@289
    assign i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_107_c_compmm_m3281_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_select_15(BITSELECT,8091)@289
    assign i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_select_15_b = i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_join(BITJOIN,8090)@289
    assign i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_select_15_b};

    // leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(MUX,26206)@289
    assign leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_join_q or leftShiftStage0Idx1_uid26205_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_108_c_compmm_m3301_vt_join_q;
            1'b1 : leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26205_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(MUX,26211)@289
    assign leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s or leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26210_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = leftShiftStage0_uid26207_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26210_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x(MUX,26216)@289
    assign leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s or leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26215_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = leftShiftStage1_uid26212_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26215_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28(BITSELECT,9865)@289
    assign i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28_b = leftShiftStage2_uid26217_i_shl_i_i_i_i_i_i_108_c_compmm_m0_shift_x_q[28:13];

    // redist370_i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28_b_1(DELAY,29498)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist370_i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_join(BITJOIN,9864)@290
    assign i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_join_q = {redist370_i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg39(REG,13334)@283 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg39_q <= $unsigned(redist867_sync_together4364_aunroll_x_in_i_valid_215_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_67236_c_compmm_m40(BLACKBOX,8635)@284
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67236_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_67236_c_compmm_m40 (
        .in_intel_reserved_ffwd_218_0(in_intel_reserved_ffwd_218_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg39_q),
        .out_dest_data_out_218_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_67236_c_compmm_m40_out_dest_data_out_218_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_offset(CONSTANT,31553)
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_offset_q = $unsigned(8'b00101101);

    // redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt(ADD,31554)
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_a = {1'b0, redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_q};
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_b = {1'b0, redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_o <= $unsigned(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_a) + $unsigned(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_b);
        end
    end
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_q = redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_o[8:0];

    // redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_inputreg0(DELAY,31549)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_inputreg0_q <= $unsigned(in_c1_eni5_217_tpl);
        end
    end

    // redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr(COUNTER,31552)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_i <= $unsigned(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_q = redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_i[7:0];

    // redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem(DUALMEM,31551)
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_ia = $unsigned(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_inputreg0_q);
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_aa = redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_wraddr_q;
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_ab = redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_aa),
        .data_a(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_ab),
        .q_b(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_q = redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_iq[15:0];

    // redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_outputreg0(DELAY,31550)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_outputreg0_q <= $unsigned(redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_mem_q);
        end
    end

    // redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt(ADD,31560)
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_a = {1'b0, redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_q};
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_b = {1'b0, redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_o <= $unsigned(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_a) + $unsigned(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_b);
        end
    end
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_q = redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_o[8:0];

    // redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_inputreg0(DELAY,31555)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_inputreg0_q <= $unsigned(in_c1_eni5_218_tpl);
        end
    end

    // redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr(COUNTER,31558)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_i <= $unsigned(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_q = redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_i[7:0];

    // redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem(DUALMEM,31557)
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_ia = $unsigned(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_inputreg0_q);
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_aa = redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_wraddr_q;
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_ab = redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_aa),
        .data_a(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_ab),
        .q_b(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_q = redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_iq[15:0];

    // redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_outputreg0(DELAY,31556)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_outputreg0_q <= $unsigned(redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_mem_q);
        end
    end

    // valid_fanout_reg40(REG,13335)@283 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg40_q <= $unsigned(redist867_sync_together4364_aunroll_x_in_i_valid_215_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_67235_c_compmm_m41(BLACKBOX,8631)@284
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67235_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_67235_c_compmm_m41 (
        .in_intel_reserved_ffwd_217_0(in_intel_reserved_ffwd_217_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg40_q),
        .out_dest_data_out_217_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_67235_c_compmm_m41_out_dest_data_out_217_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28979)@284 + 5
    // out q@290
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_67235_c_compmm_m41_out_dest_data_out_217_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_67236_c_compmm_m40_out_dest_data_out_218_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303(ADD,8955)@290
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod822_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_b = $unsigned({{5{i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_108_c_compmm_m3302_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_o[33:0];

    // rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x(MUX,22567)@290
    assign rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q or rightShiftStage0Idx1_uid22566_dupName_433_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q;
            1'b1 : rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22566_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x(MUX,22572)@290
    assign rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22571_dupName_433_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22568_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22571_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x(MUX,22577)@290
    assign rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22576_dupName_433_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22573_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22576_dupName_433_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3304_vt_select_20(BITSELECT,12081)@290
    assign i_unnamed_c_compmm_m3304_vt_select_20_b = rightShiftStage2_uid22578_dupName_433_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3304_vt_join(BITJOIN,12080)@290
    assign i_unnamed_c_compmm_m3304_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3304_vt_select_20_b};

    // i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x(BITSELECT,3713)@290
    assign i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x_b = i_unnamed_c_compmm_m3304_vt_join_q[15:0];

    // redist1005_i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x_b_1(DELAY,30133)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1005_i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22587_dupName_434_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22586)@290
    assign rightShiftStage1Idx1Rng8_uid22587_dupName_434_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22589_dupName_434_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22588)@290
    assign rightShiftStage1Idx1_uid22589_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22587_dupName_434_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22582_dupName_434_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22581)@290
    assign rightShiftStage0Idx1Rng4_uid22582_dupName_434_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q[33:4];

    // rightShiftStage0Idx1_uid22584_dupName_434_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22583)@290
    assign rightShiftStage0Idx1_uid22584_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22582_dupName_434_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x(MUX,22585)@290
    assign rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q or rightShiftStage0Idx1_uid22584_dupName_434_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_108_i_c_compmm_m3303_q;
            1'b1 : rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22584_dupName_434_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x(MUX,22590)@290
    assign rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22589_dupName_434_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22586_dupName_434_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22589_dupName_434_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3306_vt_select_21(BITSELECT,12084)@290
    assign i_unnamed_c_compmm_m3306_vt_select_21_b = rightShiftStage1_uid22591_dupName_434_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3306_vt_join(BITJOIN,12083)@290
    assign i_unnamed_c_compmm_m3306_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3306_vt_select_21_b};

    // i_unnamed_c_compmm_m3307_sel_x(BITSELECT,6173)@290
    assign i_unnamed_c_compmm_m3307_sel_x_b = i_unnamed_c_compmm_m3306_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3308_BitSelect_for_a(BITSELECT,28698)@290
    assign i_unnamed_c_compmm_m3308_BitSelect_for_a_b = i_unnamed_c_compmm_m3307_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3308_join(BITJOIN,28699)@290
    assign i_unnamed_c_compmm_m3308_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3308_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3308_vt_select_0(BITSELECT,12089)@290
    assign i_unnamed_c_compmm_m3308_vt_select_0_b = i_unnamed_c_compmm_m3308_join_q[0:0];

    // redist88_i_unnamed_c_compmm_m3308_vt_select_0_b_1(DELAY,29216)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist88_i_unnamed_c_compmm_m3308_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3308_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3308_vt_join(BITJOIN,12088)@291
    assign i_unnamed_c_compmm_m3308_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist88_i_unnamed_c_compmm_m3308_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_108_c_compmm_m3309(ADD,7168)@291
    assign i_add_i_i_i_i_i_i_108_c_compmm_m3309_a = {1'b0, i_unnamed_c_compmm_m3308_vt_join_q};
    assign i_add_i_i_i_i_i_i_108_c_compmm_m3309_b = {1'b0, redist1005_i_conv_i_i_i_i_i_108_c_compmm_m3305_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_108_c_compmm_m3309_o = $unsigned(i_add_i_i_i_i_i_i_108_c_compmm_m3309_a) + $unsigned(i_add_i_i_i_i_i_i_108_c_compmm_m3309_b);
    assign i_add_i_i_i_i_i_i_108_c_compmm_m3309_q = i_add_i_i_i_i_i_i_108_c_compmm_m3309_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_108_c_compmm_m3309_sel_x(BITSELECT,2182)@291
    assign bgTrunc_i_add_i_i_i_i_i_i_108_c_compmm_m3309_sel_x_b = i_add_i_i_i_i_i_i_108_c_compmm_m3309_q[15:0];

    // i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_sel_x(BITSELECT,3842)@291
    assign i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_108_c_compmm_m3309_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_select_15(BITSELECT,8095)@291
    assign i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_select_15_b = i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_join(BITJOIN,8094)@291
    assign i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_select_15_b};

    // leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(MUX,26224)@291
    assign leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_join_q or leftShiftStage0Idx1_uid26223_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_109_c_compmm_m3329_vt_join_q;
            1'b1 : leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26223_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(MUX,26229)@291
    assign leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s or leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26228_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = leftShiftStage0_uid26225_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26228_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x(MUX,26234)@291
    assign leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s or leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26233_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = leftShiftStage1_uid26230_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26233_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28(BITSELECT,9868)@291
    assign i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28_b = leftShiftStage2_uid26235_i_shl_i_i_i_i_i_i_109_c_compmm_m0_shift_x_q[28:13];

    // redist369_i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28_b_1(DELAY,29497)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist369_i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_join(BITJOIN,9867)@292
    assign i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_join_q = {redist369_i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg37(REG,13332)@285 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg37_q <= $unsigned(redist868_sync_together4364_aunroll_x_in_i_valid_217_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_67238_c_compmm_m38(BLACKBOX,8643)@286
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67238_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_67238_c_compmm_m38 (
        .in_intel_reserved_ffwd_220_0(in_intel_reserved_ffwd_220_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg37_q),
        .out_dest_data_out_220_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_67238_c_compmm_m38_out_dest_data_out_220_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_offset(CONSTANT,31565)
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_offset_q = $unsigned(8'b00101011);

    // redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt(ADD,31566)
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_a = {1'b0, redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_q};
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_b = {1'b0, redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_o <= $unsigned(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_a) + $unsigned(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_b);
        end
    end
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_q = redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_o[8:0];

    // redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_inputreg0(DELAY,31561)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_inputreg0_q <= $unsigned(in_c1_eni5_219_tpl);
        end
    end

    // redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr(COUNTER,31564)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_i <= $unsigned(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_q = redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_i[7:0];

    // redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem(DUALMEM,31563)
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_ia = $unsigned(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_inputreg0_q);
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_aa = redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_wraddr_q;
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_ab = redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_aa),
        .data_a(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_ab),
        .q_b(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_q = redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_iq[15:0];

    // redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_outputreg0(DELAY,31562)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_outputreg0_q <= $unsigned(redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_mem_q);
        end
    end

    // redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt(ADD,31572)
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_a = {1'b0, redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_q};
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_b = {1'b0, redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_o <= $unsigned(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_a) + $unsigned(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_b);
        end
    end
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_q = redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_o[8:0];

    // redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_inputreg0(DELAY,31567)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_inputreg0_q <= $unsigned(in_c1_eni5_220_tpl);
        end
    end

    // redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr(COUNTER,31570)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_i <= $unsigned(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_q = redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_i[7:0];

    // redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem(DUALMEM,31569)
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_ia = $unsigned(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_inputreg0_q);
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_aa = redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_wraddr_q;
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_ab = redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_aa),
        .data_a(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_ab),
        .q_b(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_q = redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_iq[15:0];

    // redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_outputreg0(DELAY,31568)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_outputreg0_q <= $unsigned(redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_mem_q);
        end
    end

    // valid_fanout_reg38(REG,13333)@285 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg38_q <= $unsigned(redist868_sync_together4364_aunroll_x_in_i_valid_217_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_67237_c_compmm_m39(BLACKBOX,8639)@286
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67237_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_67237_c_compmm_m39 (
        .in_intel_reserved_ffwd_219_0(in_intel_reserved_ffwd_219_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg38_q),
        .out_dest_data_out_219_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_67237_c_compmm_m39_out_dest_data_out_219_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28980)@286 + 5
    // out q@292
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_67237_c_compmm_m39_out_dest_data_out_219_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_67238_c_compmm_m38_out_dest_data_out_220_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331(ADD,8956)@292
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod827_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_b = $unsigned({{5{i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_109_c_compmm_m3330_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_o[33:0];

    // rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x(MUX,22629)@292
    assign rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q or rightShiftStage0Idx1_uid22628_dupName_437_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q;
            1'b1 : rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22628_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x(MUX,22634)@292
    assign rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22633_dupName_437_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22630_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22633_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x(MUX,22639)@292
    assign rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22638_dupName_437_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22635_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22638_dupName_437_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3332_vt_select_20(BITSELECT,12103)@292
    assign i_unnamed_c_compmm_m3332_vt_select_20_b = rightShiftStage2_uid22640_dupName_437_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3332_vt_join(BITJOIN,12102)@292
    assign i_unnamed_c_compmm_m3332_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3332_vt_select_20_b};

    // i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x(BITSELECT,3714)@292
    assign i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x_b = i_unnamed_c_compmm_m3332_vt_join_q[15:0];

    // redist1004_i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x_b_1(DELAY,30132)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1004_i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22649_dupName_438_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22648)@292
    assign rightShiftStage1Idx1Rng8_uid22649_dupName_438_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22651_dupName_438_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22650)@292
    assign rightShiftStage1Idx1_uid22651_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22649_dupName_438_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22644_dupName_438_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22643)@292
    assign rightShiftStage0Idx1Rng4_uid22644_dupName_438_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q[33:4];

    // rightShiftStage0Idx1_uid22646_dupName_438_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22645)@292
    assign rightShiftStage0Idx1_uid22646_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22644_dupName_438_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x(MUX,22647)@292
    assign rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q or rightShiftStage0Idx1_uid22646_dupName_438_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_109_i_c_compmm_m3331_q;
            1'b1 : rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22646_dupName_438_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x(MUX,22652)@292
    assign rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22651_dupName_438_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22648_dupName_438_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22651_dupName_438_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3334_vt_select_21(BITSELECT,12106)@292
    assign i_unnamed_c_compmm_m3334_vt_select_21_b = rightShiftStage1_uid22653_dupName_438_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3334_vt_join(BITJOIN,12105)@292
    assign i_unnamed_c_compmm_m3334_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3334_vt_select_21_b};

    // i_unnamed_c_compmm_m3335_sel_x(BITSELECT,6175)@292
    assign i_unnamed_c_compmm_m3335_sel_x_b = i_unnamed_c_compmm_m3334_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3336_BitSelect_for_a(BITSELECT,28702)@292
    assign i_unnamed_c_compmm_m3336_BitSelect_for_a_b = i_unnamed_c_compmm_m3335_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3336_join(BITJOIN,28703)@292
    assign i_unnamed_c_compmm_m3336_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3336_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3336_vt_select_0(BITSELECT,12111)@292
    assign i_unnamed_c_compmm_m3336_vt_select_0_b = i_unnamed_c_compmm_m3336_join_q[0:0];

    // redist86_i_unnamed_c_compmm_m3336_vt_select_0_b_1(DELAY,29214)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist86_i_unnamed_c_compmm_m3336_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3336_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3336_vt_join(BITJOIN,12110)@293
    assign i_unnamed_c_compmm_m3336_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist86_i_unnamed_c_compmm_m3336_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_109_c_compmm_m3337(ADD,7169)@293
    assign i_add_i_i_i_i_i_i_109_c_compmm_m3337_a = {1'b0, i_unnamed_c_compmm_m3336_vt_join_q};
    assign i_add_i_i_i_i_i_i_109_c_compmm_m3337_b = {1'b0, redist1004_i_conv_i_i_i_i_i_109_c_compmm_m3333_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_109_c_compmm_m3337_o = $unsigned(i_add_i_i_i_i_i_i_109_c_compmm_m3337_a) + $unsigned(i_add_i_i_i_i_i_i_109_c_compmm_m3337_b);
    assign i_add_i_i_i_i_i_i_109_c_compmm_m3337_q = i_add_i_i_i_i_i_i_109_c_compmm_m3337_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_109_c_compmm_m3337_sel_x(BITSELECT,2183)@293
    assign bgTrunc_i_add_i_i_i_i_i_i_109_c_compmm_m3337_sel_x_b = i_add_i_i_i_i_i_i_109_c_compmm_m3337_q[15:0];

    // i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_sel_x(BITSELECT,3844)@293
    assign i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_109_c_compmm_m3337_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_select_15(BITSELECT,8103)@293
    assign i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_select_15_b = i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_join(BITJOIN,8102)@293
    assign i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_select_15_b};

    // leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(MUX,26260)@293
    assign leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_join_q or leftShiftStage0Idx1_uid26259_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_110_c_compmm_m3357_vt_join_q;
            1'b1 : leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26259_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(MUX,26265)@293
    assign leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s or leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26264_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = leftShiftStage0_uid26261_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26264_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x(MUX,26270)@293
    assign leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s or leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26269_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = leftShiftStage1_uid26266_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26269_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28(BITSELECT,9874)@293
    assign i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28_b = leftShiftStage2_uid26271_i_shl_i_i_i_i_i_i_110_c_compmm_m0_shift_x_q[28:13];

    // redist368_i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28_b_1(DELAY,29496)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist368_i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_join(BITJOIN,9873)@294
    assign i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_join_q = {redist368_i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg35(REG,13330)@287 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg35_q <= $unsigned(redist869_sync_together4364_aunroll_x_in_i_valid_219_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_67240_c_compmm_m36(BLACKBOX,8651)@288
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67240_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_67240_c_compmm_m36 (
        .in_intel_reserved_ffwd_222_0(in_intel_reserved_ffwd_222_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg35_q),
        .out_dest_data_out_222_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_67240_c_compmm_m36_out_dest_data_out_222_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_offset(CONSTANT,31577)
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_offset_q = $unsigned(8'b00101001);

    // redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt(ADD,31578)
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_a = {1'b0, redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_q};
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_b = {1'b0, redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_o <= $unsigned(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_a) + $unsigned(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_b);
        end
    end
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_q = redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_o[8:0];

    // redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_inputreg0(DELAY,31573)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_inputreg0_q <= $unsigned(in_c1_eni5_221_tpl);
        end
    end

    // redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr(COUNTER,31576)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_i <= $unsigned(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_q = redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_i[7:0];

    // redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem(DUALMEM,31575)
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_ia = $unsigned(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_inputreg0_q);
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_aa = redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_wraddr_q;
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_ab = redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_aa),
        .data_a(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_ab),
        .q_b(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_q = redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_iq[15:0];

    // redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_outputreg0(DELAY,31574)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_outputreg0_q <= $unsigned(redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_mem_q);
        end
    end

    // redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt(ADD,31584)
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_a = {1'b0, redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_q};
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_b = {1'b0, redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_o <= $unsigned(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_a) + $unsigned(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_b);
        end
    end
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_q = redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_o[8:0];

    // redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_inputreg0(DELAY,31579)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_inputreg0_q <= $unsigned(in_c1_eni5_222_tpl);
        end
    end

    // redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr(COUNTER,31582)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_i <= $unsigned(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_q = redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_i[7:0];

    // redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem(DUALMEM,31581)
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_ia = $unsigned(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_inputreg0_q);
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_aa = redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_wraddr_q;
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_ab = redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_aa),
        .data_a(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_ab),
        .q_b(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_q = redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_iq[15:0];

    // redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_outputreg0(DELAY,31580)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_outputreg0_q <= $unsigned(redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_mem_q);
        end
    end

    // valid_fanout_reg36(REG,13331)@287 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg36_q <= $unsigned(redist869_sync_together4364_aunroll_x_in_i_valid_219_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_67239_c_compmm_m37(BLACKBOX,8647)@288
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67239_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_67239_c_compmm_m37 (
        .in_intel_reserved_ffwd_221_0(in_intel_reserved_ffwd_221_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg36_q),
        .out_dest_data_out_221_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_67239_c_compmm_m37_out_dest_data_out_221_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28981)@288 + 5
    // out q@294
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_67239_c_compmm_m37_out_dest_data_out_221_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_67240_c_compmm_m36_out_dest_data_out_222_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359(ADD,8958)@294
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod832_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_b = $unsigned({{5{i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_110_c_compmm_m3358_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_o[33:0];

    // rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x(MUX,22691)@294
    assign rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q or rightShiftStage0Idx1_uid22690_dupName_441_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q;
            1'b1 : rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22690_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x(MUX,22696)@294
    assign rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22695_dupName_441_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22692_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22695_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x(MUX,22701)@294
    assign rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22700_dupName_441_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22697_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22700_dupName_441_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3360_vt_select_20(BITSELECT,12131)@294
    assign i_unnamed_c_compmm_m3360_vt_select_20_b = rightShiftStage2_uid22702_dupName_441_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3360_vt_join(BITJOIN,12130)@294
    assign i_unnamed_c_compmm_m3360_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3360_vt_select_20_b};

    // i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x(BITSELECT,3716)@294
    assign i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x_b = i_unnamed_c_compmm_m3360_vt_join_q[15:0];

    // redist1002_i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x_b_1(DELAY,30130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1002_i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22711_dupName_442_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22710)@294
    assign rightShiftStage1Idx1Rng8_uid22711_dupName_442_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22713_dupName_442_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22712)@294
    assign rightShiftStage1Idx1_uid22713_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22711_dupName_442_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22706_dupName_442_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22705)@294
    assign rightShiftStage0Idx1Rng4_uid22706_dupName_442_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q[33:4];

    // rightShiftStage0Idx1_uid22708_dupName_442_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22707)@294
    assign rightShiftStage0Idx1_uid22708_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22706_dupName_442_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x(MUX,22709)@294
    assign rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q or rightShiftStage0Idx1_uid22708_dupName_442_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_110_i_c_compmm_m3359_q;
            1'b1 : rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22708_dupName_442_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x(MUX,22714)@294
    assign rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22713_dupName_442_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22710_dupName_442_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22713_dupName_442_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3362_vt_select_21(BITSELECT,12134)@294
    assign i_unnamed_c_compmm_m3362_vt_select_21_b = rightShiftStage1_uid22715_dupName_442_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3362_vt_join(BITJOIN,12133)@294
    assign i_unnamed_c_compmm_m3362_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3362_vt_select_21_b};

    // i_unnamed_c_compmm_m3363_sel_x(BITSELECT,6178)@294
    assign i_unnamed_c_compmm_m3363_sel_x_b = i_unnamed_c_compmm_m3362_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3364_BitSelect_for_a(BITSELECT,28706)@294
    assign i_unnamed_c_compmm_m3364_BitSelect_for_a_b = i_unnamed_c_compmm_m3363_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3364_join(BITJOIN,28707)@294
    assign i_unnamed_c_compmm_m3364_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3364_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3364_vt_select_0(BITSELECT,12139)@294
    assign i_unnamed_c_compmm_m3364_vt_select_0_b = i_unnamed_c_compmm_m3364_join_q[0:0];

    // redist84_i_unnamed_c_compmm_m3364_vt_select_0_b_1(DELAY,29212)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist84_i_unnamed_c_compmm_m3364_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3364_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3364_vt_join(BITJOIN,12138)@295
    assign i_unnamed_c_compmm_m3364_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist84_i_unnamed_c_compmm_m3364_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_110_c_compmm_m3365(ADD,7171)@295
    assign i_add_i_i_i_i_i_i_110_c_compmm_m3365_a = {1'b0, i_unnamed_c_compmm_m3364_vt_join_q};
    assign i_add_i_i_i_i_i_i_110_c_compmm_m3365_b = {1'b0, redist1002_i_conv_i_i_i_i_i_110_c_compmm_m3361_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_110_c_compmm_m3365_o = $unsigned(i_add_i_i_i_i_i_i_110_c_compmm_m3365_a) + $unsigned(i_add_i_i_i_i_i_i_110_c_compmm_m3365_b);
    assign i_add_i_i_i_i_i_i_110_c_compmm_m3365_q = i_add_i_i_i_i_i_i_110_c_compmm_m3365_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_110_c_compmm_m3365_sel_x(BITSELECT,2185)@295
    assign bgTrunc_i_add_i_i_i_i_i_i_110_c_compmm_m3365_sel_x_b = i_add_i_i_i_i_i_i_110_c_compmm_m3365_q[15:0];

    // i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_sel_x(BITSELECT,3845)@295
    assign i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_110_c_compmm_m3365_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_select_15(BITSELECT,8107)@295
    assign i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_select_15_b = i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_join(BITJOIN,8106)@295
    assign i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_select_15_b};

    // leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(MUX,26278)@295
    assign leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_join_q or leftShiftStage0Idx1_uid26277_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_111_c_compmm_m3385_vt_join_q;
            1'b1 : leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26277_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(MUX,26283)@295
    assign leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s or leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26282_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = leftShiftStage0_uid26279_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26282_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x(MUX,26288)@295
    assign leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s or leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26287_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = leftShiftStage1_uid26284_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26287_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28(BITSELECT,9877)@295
    assign i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28_b = leftShiftStage2_uid26289_i_shl_i_i_i_i_i_i_111_c_compmm_m0_shift_x_q[28:13];

    // redist367_i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28_b_1(DELAY,29495)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist367_i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_join(BITJOIN,9876)@296
    assign i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_join_q = {redist367_i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg33(REG,13328)@289 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg33_q <= $unsigned(redist870_sync_together4364_aunroll_x_in_i_valid_221_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_67242_c_compmm_m34(BLACKBOX,8663)@290
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67242_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_67242_c_compmm_m34 (
        .in_intel_reserved_ffwd_224_0(in_intel_reserved_ffwd_224_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg33_q),
        .out_dest_data_out_224_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_67242_c_compmm_m34_out_dest_data_out_224_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_offset(CONSTANT,31589)
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_offset_q = $unsigned(8'b00100111);

    // redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt(ADD,31590)
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_a = {1'b0, redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_q};
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_b = {1'b0, redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_o <= $unsigned(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_a) + $unsigned(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_b);
        end
    end
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_q = redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_o[8:0];

    // redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_inputreg0(DELAY,31585)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_inputreg0_q <= $unsigned(in_c1_eni5_223_tpl);
        end
    end

    // redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr(COUNTER,31588)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_i <= $unsigned(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_q = redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_i[7:0];

    // redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem(DUALMEM,31587)
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_ia = $unsigned(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_inputreg0_q);
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_aa = redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_wraddr_q;
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_ab = redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_aa),
        .data_a(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_ab),
        .q_b(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_q = redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_iq[15:0];

    // redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_outputreg0(DELAY,31586)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_outputreg0_q <= $unsigned(redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_mem_q);
        end
    end

    // redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt(ADD,31596)
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_a = {1'b0, redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_q};
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_b = {1'b0, redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_o <= $unsigned(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_a) + $unsigned(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_b);
        end
    end
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_q = redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_o[8:0];

    // redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_inputreg0(DELAY,31591)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_inputreg0_q <= $unsigned(in_c1_eni5_224_tpl);
        end
    end

    // redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr(COUNTER,31594)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_i <= $unsigned(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_q = redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_i[7:0];

    // redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem(DUALMEM,31593)
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_ia = $unsigned(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_inputreg0_q);
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_aa = redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_wraddr_q;
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_ab = redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_aa),
        .data_a(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_ab),
        .q_b(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_q = redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_iq[15:0];

    // redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_outputreg0(DELAY,31592)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_outputreg0_q <= $unsigned(redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_mem_q);
        end
    end

    // valid_fanout_reg34(REG,13329)@289 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg34_q <= $unsigned(redist870_sync_together4364_aunroll_x_in_i_valid_221_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_67241_c_compmm_m35(BLACKBOX,8659)@290
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67241_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_67241_c_compmm_m35 (
        .in_intel_reserved_ffwd_223_0(in_intel_reserved_ffwd_223_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg34_q),
        .out_dest_data_out_223_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_67241_c_compmm_m35_out_dest_data_out_223_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28982)@290 + 5
    // out q@296
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_67241_c_compmm_m35_out_dest_data_out_223_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_67242_c_compmm_m34_out_dest_data_out_224_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387(ADD,8959)@296
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod837_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_b = $unsigned({{5{i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_111_c_compmm_m3386_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_o[33:0];

    // rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x(MUX,22753)@296
    assign rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q or rightShiftStage0Idx1_uid22752_dupName_445_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q;
            1'b1 : rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22752_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x(MUX,22758)@296
    assign rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22757_dupName_445_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22754_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22757_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x(MUX,22763)@296
    assign rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22762_dupName_445_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22759_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22762_dupName_445_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3388_vt_select_20(BITSELECT,12158)@296
    assign i_unnamed_c_compmm_m3388_vt_select_20_b = rightShiftStage2_uid22764_dupName_445_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3388_vt_join(BITJOIN,12157)@296
    assign i_unnamed_c_compmm_m3388_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3388_vt_select_20_b};

    // i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x(BITSELECT,3717)@296
    assign i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x_b = i_unnamed_c_compmm_m3388_vt_join_q[15:0];

    // redist1001_i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x_b_1(DELAY,30129)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1001_i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22773_dupName_446_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22772)@296
    assign rightShiftStage1Idx1Rng8_uid22773_dupName_446_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22775_dupName_446_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22774)@296
    assign rightShiftStage1Idx1_uid22775_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22773_dupName_446_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22768_dupName_446_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22767)@296
    assign rightShiftStage0Idx1Rng4_uid22768_dupName_446_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q[33:4];

    // rightShiftStage0Idx1_uid22770_dupName_446_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22769)@296
    assign rightShiftStage0Idx1_uid22770_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22768_dupName_446_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x(MUX,22771)@296
    assign rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q or rightShiftStage0Idx1_uid22770_dupName_446_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_111_i_c_compmm_m3387_q;
            1'b1 : rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22770_dupName_446_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x(MUX,22776)@296
    assign rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22775_dupName_446_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22772_dupName_446_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22775_dupName_446_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3390_vt_select_21(BITSELECT,12161)@296
    assign i_unnamed_c_compmm_m3390_vt_select_21_b = rightShiftStage1_uid22777_dupName_446_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3390_vt_join(BITJOIN,12160)@296
    assign i_unnamed_c_compmm_m3390_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3390_vt_select_21_b};

    // i_unnamed_c_compmm_m3391_sel_x(BITSELECT,6180)@296
    assign i_unnamed_c_compmm_m3391_sel_x_b = i_unnamed_c_compmm_m3390_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3392_BitSelect_for_a(BITSELECT,28712)@296
    assign i_unnamed_c_compmm_m3392_BitSelect_for_a_b = i_unnamed_c_compmm_m3391_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3392_join(BITJOIN,28713)@296
    assign i_unnamed_c_compmm_m3392_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3392_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3392_vt_select_0(BITSELECT,12166)@296
    assign i_unnamed_c_compmm_m3392_vt_select_0_b = i_unnamed_c_compmm_m3392_join_q[0:0];

    // redist81_i_unnamed_c_compmm_m3392_vt_select_0_b_1(DELAY,29209)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist81_i_unnamed_c_compmm_m3392_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3392_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3392_vt_join(BITJOIN,12165)@297
    assign i_unnamed_c_compmm_m3392_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist81_i_unnamed_c_compmm_m3392_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_111_c_compmm_m3393(ADD,7172)@297
    assign i_add_i_i_i_i_i_i_111_c_compmm_m3393_a = {1'b0, i_unnamed_c_compmm_m3392_vt_join_q};
    assign i_add_i_i_i_i_i_i_111_c_compmm_m3393_b = {1'b0, redist1001_i_conv_i_i_i_i_i_111_c_compmm_m3389_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_111_c_compmm_m3393_o = $unsigned(i_add_i_i_i_i_i_i_111_c_compmm_m3393_a) + $unsigned(i_add_i_i_i_i_i_i_111_c_compmm_m3393_b);
    assign i_add_i_i_i_i_i_i_111_c_compmm_m3393_q = i_add_i_i_i_i_i_i_111_c_compmm_m3393_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_111_c_compmm_m3393_sel_x(BITSELECT,2186)@297
    assign bgTrunc_i_add_i_i_i_i_i_i_111_c_compmm_m3393_sel_x_b = i_add_i_i_i_i_i_i_111_c_compmm_m3393_q[15:0];

    // i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_sel_x(BITSELECT,3846)@297
    assign i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_111_c_compmm_m3393_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_select_15(BITSELECT,8111)@297
    assign i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_select_15_b = i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_join(BITJOIN,8110)@297
    assign i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_select_15_b};

    // leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(MUX,26296)@297
    assign leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_join_q or leftShiftStage0Idx1_uid26295_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_112_c_compmm_m3413_vt_join_q;
            1'b1 : leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26295_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(MUX,26301)@297
    assign leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s or leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26300_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = leftShiftStage0_uid26297_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26300_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x(MUX,26306)@297
    assign leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s or leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26305_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = leftShiftStage1_uid26302_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26305_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28(BITSELECT,9880)@297
    assign i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28_b = leftShiftStage2_uid26307_i_shl_i_i_i_i_i_i_112_c_compmm_m0_shift_x_q[28:13];

    // redist366_i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28_b_1(DELAY,29494)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist366_i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_join(BITJOIN,9879)@298
    assign i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_join_q = {redist366_i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg31(REG,13326)@291 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg31_q <= $unsigned(redist871_sync_together4364_aunroll_x_in_i_valid_223_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_67244_c_compmm_m32(BLACKBOX,8671)@292
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67244_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_67244_c_compmm_m32 (
        .in_intel_reserved_ffwd_226_0(in_intel_reserved_ffwd_226_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg31_q),
        .out_dest_data_out_226_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_67244_c_compmm_m32_out_dest_data_out_226_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_offset(CONSTANT,31601)
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_offset_q = $unsigned(8'b00100101);

    // redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt(ADD,31602)
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_a = {1'b0, redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_q};
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_b = {1'b0, redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_o <= $unsigned(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_a) + $unsigned(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_b);
        end
    end
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_q = redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_o[8:0];

    // redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_inputreg0(DELAY,31597)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_inputreg0_q <= $unsigned(in_c1_eni5_225_tpl);
        end
    end

    // redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr(COUNTER,31600)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_i <= $unsigned(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_q = redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_i[7:0];

    // redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem(DUALMEM,31599)
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_ia = $unsigned(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_inputreg0_q);
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_aa = redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_wraddr_q;
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_ab = redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_aa),
        .data_a(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_ab),
        .q_b(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_q = redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_iq[15:0];

    // redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_outputreg0(DELAY,31598)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_outputreg0_q <= $unsigned(redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_mem_q);
        end
    end

    // redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt(ADD,31608)
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_a = {1'b0, redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_q};
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_b = {1'b0, redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_o <= $unsigned(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_a) + $unsigned(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_b);
        end
    end
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_q = redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_o[8:0];

    // redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_inputreg0(DELAY,31603)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_inputreg0_q <= $unsigned(in_c1_eni5_226_tpl);
        end
    end

    // redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr(COUNTER,31606)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_i <= $unsigned(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_q = redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_i[7:0];

    // redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem(DUALMEM,31605)
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_ia = $unsigned(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_inputreg0_q);
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_aa = redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_wraddr_q;
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_ab = redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_aa),
        .data_a(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_ab),
        .q_b(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_q = redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_iq[15:0];

    // redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_outputreg0(DELAY,31604)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_outputreg0_q <= $unsigned(redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_mem_q);
        end
    end

    // valid_fanout_reg32(REG,13327)@291 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg32_q <= $unsigned(redist871_sync_together4364_aunroll_x_in_i_valid_223_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_67243_c_compmm_m33(BLACKBOX,8667)@292
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67243_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_67243_c_compmm_m33 (
        .in_intel_reserved_ffwd_225_0(in_intel_reserved_ffwd_225_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg32_q),
        .out_dest_data_out_225_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_67243_c_compmm_m33_out_dest_data_out_225_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28983)@292 + 5
    // out q@298
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_67243_c_compmm_m33_out_dest_data_out_225_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_67244_c_compmm_m32_out_dest_data_out_226_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415(ADD,8960)@298
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod842_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_b = $unsigned({{5{i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_112_c_compmm_m3414_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_o[33:0];

    // rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x(MUX,22815)@298
    assign rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q or rightShiftStage0Idx1_uid22814_dupName_449_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q;
            1'b1 : rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22814_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x(MUX,22820)@298
    assign rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22819_dupName_449_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22816_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22819_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x(MUX,22825)@298
    assign rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22824_dupName_449_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22821_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22824_dupName_449_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3416_vt_select_20(BITSELECT,12180)@298
    assign i_unnamed_c_compmm_m3416_vt_select_20_b = rightShiftStage2_uid22826_dupName_449_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3416_vt_join(BITJOIN,12179)@298
    assign i_unnamed_c_compmm_m3416_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3416_vt_select_20_b};

    // i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x(BITSELECT,3718)@298
    assign i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x_b = i_unnamed_c_compmm_m3416_vt_join_q[15:0];

    // redist1000_i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x_b_1(DELAY,30128)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1000_i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22835_dupName_450_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22834)@298
    assign rightShiftStage1Idx1Rng8_uid22835_dupName_450_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22837_dupName_450_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22836)@298
    assign rightShiftStage1Idx1_uid22837_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22835_dupName_450_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22830_dupName_450_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22829)@298
    assign rightShiftStage0Idx1Rng4_uid22830_dupName_450_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q[33:4];

    // rightShiftStage0Idx1_uid22832_dupName_450_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22831)@298
    assign rightShiftStage0Idx1_uid22832_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22830_dupName_450_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x(MUX,22833)@298
    assign rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q or rightShiftStage0Idx1_uid22832_dupName_450_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_112_i_c_compmm_m3415_q;
            1'b1 : rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22832_dupName_450_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x(MUX,22838)@298
    assign rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22837_dupName_450_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22834_dupName_450_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22837_dupName_450_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3418_vt_select_21(BITSELECT,12183)@298
    assign i_unnamed_c_compmm_m3418_vt_select_21_b = rightShiftStage1_uid22839_dupName_450_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3418_vt_join(BITJOIN,12182)@298
    assign i_unnamed_c_compmm_m3418_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3418_vt_select_21_b};

    // i_unnamed_c_compmm_m3419_sel_x(BITSELECT,6182)@298
    assign i_unnamed_c_compmm_m3419_sel_x_b = i_unnamed_c_compmm_m3418_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3420_BitSelect_for_a(BITSELECT,28716)@298
    assign i_unnamed_c_compmm_m3420_BitSelect_for_a_b = i_unnamed_c_compmm_m3419_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3420_join(BITJOIN,28717)@298
    assign i_unnamed_c_compmm_m3420_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3420_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3420_vt_select_0(BITSELECT,12188)@298
    assign i_unnamed_c_compmm_m3420_vt_select_0_b = i_unnamed_c_compmm_m3420_join_q[0:0];

    // redist79_i_unnamed_c_compmm_m3420_vt_select_0_b_1(DELAY,29207)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist79_i_unnamed_c_compmm_m3420_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3420_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3420_vt_join(BITJOIN,12187)@299
    assign i_unnamed_c_compmm_m3420_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist79_i_unnamed_c_compmm_m3420_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_112_c_compmm_m3421(ADD,7173)@299
    assign i_add_i_i_i_i_i_i_112_c_compmm_m3421_a = {1'b0, i_unnamed_c_compmm_m3420_vt_join_q};
    assign i_add_i_i_i_i_i_i_112_c_compmm_m3421_b = {1'b0, redist1000_i_conv_i_i_i_i_i_112_c_compmm_m3417_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_112_c_compmm_m3421_o = $unsigned(i_add_i_i_i_i_i_i_112_c_compmm_m3421_a) + $unsigned(i_add_i_i_i_i_i_i_112_c_compmm_m3421_b);
    assign i_add_i_i_i_i_i_i_112_c_compmm_m3421_q = i_add_i_i_i_i_i_i_112_c_compmm_m3421_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_112_c_compmm_m3421_sel_x(BITSELECT,2187)@299
    assign bgTrunc_i_add_i_i_i_i_i_i_112_c_compmm_m3421_sel_x_b = i_add_i_i_i_i_i_i_112_c_compmm_m3421_q[15:0];

    // i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_sel_x(BITSELECT,3847)@299
    assign i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_112_c_compmm_m3421_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_select_15(BITSELECT,8115)@299
    assign i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_select_15_b = i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_join(BITJOIN,8114)@299
    assign i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_select_15_b};

    // leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(MUX,26314)@299
    assign leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_join_q or leftShiftStage0Idx1_uid26313_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_113_c_compmm_m3441_vt_join_q;
            1'b1 : leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26313_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(MUX,26319)@299
    assign leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s or leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26318_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = leftShiftStage0_uid26315_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26318_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x(MUX,26324)@299
    assign leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s or leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26323_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = leftShiftStage1_uid26320_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26323_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28(BITSELECT,9883)@299
    assign i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28_b = leftShiftStage2_uid26325_i_shl_i_i_i_i_i_i_113_c_compmm_m0_shift_x_q[28:13];

    // redist365_i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28_b_1(DELAY,29493)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist365_i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_join(BITJOIN,9882)@300
    assign i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_join_q = {redist365_i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg29(REG,13324)@293 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg29_q <= $unsigned(redist872_sync_together4364_aunroll_x_in_i_valid_225_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_67246_c_compmm_m30(BLACKBOX,8679)@294
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67246_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_67246_c_compmm_m30 (
        .in_intel_reserved_ffwd_228_0(in_intel_reserved_ffwd_228_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg29_q),
        .out_dest_data_out_228_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_67246_c_compmm_m30_out_dest_data_out_228_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_offset(CONSTANT,31613)
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_offset_q = $unsigned(8'b00100011);

    // redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt(ADD,31614)
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_a = {1'b0, redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_q};
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_b = {1'b0, redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_o <= $unsigned(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_a) + $unsigned(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_b);
        end
    end
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_q = redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_o[8:0];

    // redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_inputreg0(DELAY,31609)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_inputreg0_q <= $unsigned(in_c1_eni5_227_tpl);
        end
    end

    // redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr(COUNTER,31612)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_i <= $unsigned(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_q = redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_i[7:0];

    // redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem(DUALMEM,31611)
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_ia = $unsigned(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_inputreg0_q);
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_aa = redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_wraddr_q;
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_ab = redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_aa),
        .data_a(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_ab),
        .q_b(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_q = redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_iq[15:0];

    // redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_outputreg0(DELAY,31610)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_outputreg0_q <= $unsigned(redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_mem_q);
        end
    end

    // redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt(ADD,31620)
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_a = {1'b0, redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_q};
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_b = {1'b0, redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_o <= $unsigned(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_a) + $unsigned(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_b);
        end
    end
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_q = redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_o[8:0];

    // redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_inputreg0(DELAY,31615)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_inputreg0_q <= $unsigned(in_c1_eni5_228_tpl);
        end
    end

    // redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr(COUNTER,31618)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_i <= $unsigned(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_q = redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_i[7:0];

    // redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem(DUALMEM,31617)
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_ia = $unsigned(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_inputreg0_q);
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_aa = redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_wraddr_q;
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_ab = redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_aa),
        .data_a(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_ab),
        .q_b(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_q = redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_iq[15:0];

    // redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_outputreg0(DELAY,31616)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_outputreg0_q <= $unsigned(redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_mem_q);
        end
    end

    // valid_fanout_reg30(REG,13325)@293 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg30_q <= $unsigned(redist872_sync_together4364_aunroll_x_in_i_valid_225_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_67245_c_compmm_m31(BLACKBOX,8675)@294
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67245_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_67245_c_compmm_m31 (
        .in_intel_reserved_ffwd_227_0(in_intel_reserved_ffwd_227_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg30_q),
        .out_dest_data_out_227_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_67245_c_compmm_m31_out_dest_data_out_227_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28984)@294 + 5
    // out q@300
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_67245_c_compmm_m31_out_dest_data_out_227_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_67246_c_compmm_m30_out_dest_data_out_228_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443(ADD,8961)@300
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod847_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_b = $unsigned({{5{i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_113_c_compmm_m3442_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_o[33:0];

    // rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x(MUX,22877)@300
    assign rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q or rightShiftStage0Idx1_uid22876_dupName_453_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q;
            1'b1 : rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22876_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x(MUX,22882)@300
    assign rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22881_dupName_453_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22878_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22881_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x(MUX,22887)@300
    assign rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22886_dupName_453_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22883_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22886_dupName_453_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3444_vt_select_20(BITSELECT,12202)@300
    assign i_unnamed_c_compmm_m3444_vt_select_20_b = rightShiftStage2_uid22888_dupName_453_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3444_vt_join(BITJOIN,12201)@300
    assign i_unnamed_c_compmm_m3444_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3444_vt_select_20_b};

    // i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x(BITSELECT,3719)@300
    assign i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x_b = i_unnamed_c_compmm_m3444_vt_join_q[15:0];

    // redist999_i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x_b_1(DELAY,30127)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist999_i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22897_dupName_454_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22896)@300
    assign rightShiftStage1Idx1Rng8_uid22897_dupName_454_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22899_dupName_454_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22898)@300
    assign rightShiftStage1Idx1_uid22899_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22897_dupName_454_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22892_dupName_454_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22891)@300
    assign rightShiftStage0Idx1Rng4_uid22892_dupName_454_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q[33:4];

    // rightShiftStage0Idx1_uid22894_dupName_454_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22893)@300
    assign rightShiftStage0Idx1_uid22894_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22892_dupName_454_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x(MUX,22895)@300
    assign rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q or rightShiftStage0Idx1_uid22894_dupName_454_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_113_i_c_compmm_m3443_q;
            1'b1 : rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22894_dupName_454_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x(MUX,22900)@300
    assign rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22899_dupName_454_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22896_dupName_454_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22899_dupName_454_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3446_vt_select_21(BITSELECT,12205)@300
    assign i_unnamed_c_compmm_m3446_vt_select_21_b = rightShiftStage1_uid22901_dupName_454_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3446_vt_join(BITJOIN,12204)@300
    assign i_unnamed_c_compmm_m3446_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3446_vt_select_21_b};

    // i_unnamed_c_compmm_m3447_sel_x(BITSELECT,6184)@300
    assign i_unnamed_c_compmm_m3447_sel_x_b = i_unnamed_c_compmm_m3446_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3448_BitSelect_for_a(BITSELECT,28720)@300
    assign i_unnamed_c_compmm_m3448_BitSelect_for_a_b = i_unnamed_c_compmm_m3447_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3448_join(BITJOIN,28721)@300
    assign i_unnamed_c_compmm_m3448_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3448_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3448_vt_select_0(BITSELECT,12210)@300
    assign i_unnamed_c_compmm_m3448_vt_select_0_b = i_unnamed_c_compmm_m3448_join_q[0:0];

    // redist77_i_unnamed_c_compmm_m3448_vt_select_0_b_1(DELAY,29205)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist77_i_unnamed_c_compmm_m3448_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3448_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3448_vt_join(BITJOIN,12209)@301
    assign i_unnamed_c_compmm_m3448_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist77_i_unnamed_c_compmm_m3448_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_113_c_compmm_m3449(ADD,7174)@301
    assign i_add_i_i_i_i_i_i_113_c_compmm_m3449_a = {1'b0, i_unnamed_c_compmm_m3448_vt_join_q};
    assign i_add_i_i_i_i_i_i_113_c_compmm_m3449_b = {1'b0, redist999_i_conv_i_i_i_i_i_113_c_compmm_m3445_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_113_c_compmm_m3449_o = $unsigned(i_add_i_i_i_i_i_i_113_c_compmm_m3449_a) + $unsigned(i_add_i_i_i_i_i_i_113_c_compmm_m3449_b);
    assign i_add_i_i_i_i_i_i_113_c_compmm_m3449_q = i_add_i_i_i_i_i_i_113_c_compmm_m3449_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_113_c_compmm_m3449_sel_x(BITSELECT,2188)@301
    assign bgTrunc_i_add_i_i_i_i_i_i_113_c_compmm_m3449_sel_x_b = i_add_i_i_i_i_i_i_113_c_compmm_m3449_q[15:0];

    // i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_sel_x(BITSELECT,3848)@301
    assign i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_113_c_compmm_m3449_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_select_15(BITSELECT,8119)@301
    assign i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_select_15_b = i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_join(BITJOIN,8118)@301
    assign i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_select_15_b};

    // leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(MUX,26332)@301
    assign leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_join_q or leftShiftStage0Idx1_uid26331_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_114_c_compmm_m3469_vt_join_q;
            1'b1 : leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26331_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(MUX,26337)@301
    assign leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s or leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26336_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = leftShiftStage0_uid26333_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26336_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x(MUX,26342)@301
    assign leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s or leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26341_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = leftShiftStage1_uid26338_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26341_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28(BITSELECT,9886)@301
    assign i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28_b = leftShiftStage2_uid26343_i_shl_i_i_i_i_i_i_114_c_compmm_m0_shift_x_q[28:13];

    // redist364_i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28_b_1(DELAY,29492)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist364_i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_join(BITJOIN,9885)@302
    assign i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_join_q = {redist364_i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg27(REG,13322)@295 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg27_q <= $unsigned(redist873_sync_together4364_aunroll_x_in_i_valid_227_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_67248_c_compmm_m28(BLACKBOX,8687)@296
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67248_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_67248_c_compmm_m28 (
        .in_intel_reserved_ffwd_230_0(in_intel_reserved_ffwd_230_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg27_q),
        .out_dest_data_out_230_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_67248_c_compmm_m28_out_dest_data_out_230_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_offset(CONSTANT,31625)
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_offset_q = $unsigned(8'b00100001);

    // redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt(ADD,31626)
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_a = {1'b0, redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_q};
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_b = {1'b0, redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_o <= $unsigned(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_a) + $unsigned(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_b);
        end
    end
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_q = redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_o[8:0];

    // redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_inputreg0(DELAY,31621)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_inputreg0_q <= $unsigned(in_c1_eni5_229_tpl);
        end
    end

    // redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr(COUNTER,31624)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_i <= $unsigned(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_q = redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_i[7:0];

    // redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem(DUALMEM,31623)
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_ia = $unsigned(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_inputreg0_q);
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_aa = redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_wraddr_q;
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_ab = redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_aa),
        .data_a(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_ab),
        .q_b(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_q = redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_iq[15:0];

    // redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_outputreg0(DELAY,31622)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_outputreg0_q <= $unsigned(redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_mem_q);
        end
    end

    // redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt(ADD,31632)
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_a = {1'b0, redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_q};
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_b = {1'b0, redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_o <= $unsigned(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_a) + $unsigned(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_b);
        end
    end
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_q = redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_o[8:0];

    // redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_inputreg0(DELAY,31627)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_inputreg0_q <= $unsigned(in_c1_eni5_230_tpl);
        end
    end

    // redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr(COUNTER,31630)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_i <= $unsigned(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_q = redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_i[7:0];

    // redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem(DUALMEM,31629)
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_ia = $unsigned(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_inputreg0_q);
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_aa = redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_wraddr_q;
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_ab = redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_aa),
        .data_a(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_ab),
        .q_b(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_q = redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_iq[15:0];

    // redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_outputreg0(DELAY,31628)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_outputreg0_q <= $unsigned(redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_mem_q);
        end
    end

    // valid_fanout_reg28(REG,13323)@295 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg28_q <= $unsigned(redist873_sync_together4364_aunroll_x_in_i_valid_227_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_67247_c_compmm_m29(BLACKBOX,8683)@296
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67247_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_67247_c_compmm_m29 (
        .in_intel_reserved_ffwd_229_0(in_intel_reserved_ffwd_229_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg28_q),
        .out_dest_data_out_229_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_67247_c_compmm_m29_out_dest_data_out_229_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28985)@296 + 5
    // out q@302
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_67247_c_compmm_m29_out_dest_data_out_229_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_67248_c_compmm_m28_out_dest_data_out_230_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471(ADD,8962)@302
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod852_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_b = $unsigned({{5{i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_114_c_compmm_m3470_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_o[33:0];

    // rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x(MUX,22939)@302
    assign rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q or rightShiftStage0Idx1_uid22938_dupName_457_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q;
            1'b1 : rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22938_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x(MUX,22944)@302
    assign rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22943_dupName_457_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22940_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22943_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x(MUX,22949)@302
    assign rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22948_dupName_457_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22945_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22948_dupName_457_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3472_vt_select_20(BITSELECT,12227)@302
    assign i_unnamed_c_compmm_m3472_vt_select_20_b = rightShiftStage2_uid22950_dupName_457_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3472_vt_join(BITJOIN,12226)@302
    assign i_unnamed_c_compmm_m3472_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3472_vt_select_20_b};

    // i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x(BITSELECT,3720)@302
    assign i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x_b = i_unnamed_c_compmm_m3472_vt_join_q[15:0];

    // redist998_i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x_b_1(DELAY,30126)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist998_i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22959_dupName_458_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22958)@302
    assign rightShiftStage1Idx1Rng8_uid22959_dupName_458_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22961_dupName_458_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22960)@302
    assign rightShiftStage1Idx1_uid22961_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22959_dupName_458_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22954_dupName_458_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22953)@302
    assign rightShiftStage0Idx1Rng4_uid22954_dupName_458_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q[33:4];

    // rightShiftStage0Idx1_uid22956_dupName_458_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22955)@302
    assign rightShiftStage0Idx1_uid22956_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22954_dupName_458_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x(MUX,22957)@302
    assign rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q or rightShiftStage0Idx1_uid22956_dupName_458_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_114_i_c_compmm_m3471_q;
            1'b1 : rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22956_dupName_458_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x(MUX,22962)@302
    assign rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22961_dupName_458_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22958_dupName_458_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22961_dupName_458_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3474_vt_select_21(BITSELECT,12230)@302
    assign i_unnamed_c_compmm_m3474_vt_select_21_b = rightShiftStage1_uid22963_dupName_458_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3474_vt_join(BITJOIN,12229)@302
    assign i_unnamed_c_compmm_m3474_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3474_vt_select_21_b};

    // i_unnamed_c_compmm_m3475_sel_x(BITSELECT,6186)@302
    assign i_unnamed_c_compmm_m3475_sel_x_b = i_unnamed_c_compmm_m3474_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3476_BitSelect_for_a(BITSELECT,28724)@302
    assign i_unnamed_c_compmm_m3476_BitSelect_for_a_b = i_unnamed_c_compmm_m3475_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3476_join(BITJOIN,28725)@302
    assign i_unnamed_c_compmm_m3476_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3476_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3476_vt_select_0(BITSELECT,12235)@302
    assign i_unnamed_c_compmm_m3476_vt_select_0_b = i_unnamed_c_compmm_m3476_join_q[0:0];

    // redist75_i_unnamed_c_compmm_m3476_vt_select_0_b_1(DELAY,29203)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist75_i_unnamed_c_compmm_m3476_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3476_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3476_vt_join(BITJOIN,12234)@303
    assign i_unnamed_c_compmm_m3476_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist75_i_unnamed_c_compmm_m3476_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_114_c_compmm_m3477(ADD,7175)@303
    assign i_add_i_i_i_i_i_i_114_c_compmm_m3477_a = {1'b0, i_unnamed_c_compmm_m3476_vt_join_q};
    assign i_add_i_i_i_i_i_i_114_c_compmm_m3477_b = {1'b0, redist998_i_conv_i_i_i_i_i_114_c_compmm_m3473_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_114_c_compmm_m3477_o = $unsigned(i_add_i_i_i_i_i_i_114_c_compmm_m3477_a) + $unsigned(i_add_i_i_i_i_i_i_114_c_compmm_m3477_b);
    assign i_add_i_i_i_i_i_i_114_c_compmm_m3477_q = i_add_i_i_i_i_i_i_114_c_compmm_m3477_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_114_c_compmm_m3477_sel_x(BITSELECT,2189)@303
    assign bgTrunc_i_add_i_i_i_i_i_i_114_c_compmm_m3477_sel_x_b = i_add_i_i_i_i_i_i_114_c_compmm_m3477_q[15:0];

    // i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_sel_x(BITSELECT,3849)@303
    assign i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_114_c_compmm_m3477_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_select_15(BITSELECT,8123)@303
    assign i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_select_15_b = i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_join(BITJOIN,8122)@303
    assign i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_select_15_b};

    // leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(MUX,26350)@303
    assign leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_join_q or leftShiftStage0Idx1_uid26349_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_115_c_compmm_m3497_vt_join_q;
            1'b1 : leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26349_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(MUX,26355)@303
    assign leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s or leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26354_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = leftShiftStage0_uid26351_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26354_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x(MUX,26360)@303
    assign leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s or leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26359_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = leftShiftStage1_uid26356_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26359_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28(BITSELECT,9889)@303
    assign i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28_b = leftShiftStage2_uid26361_i_shl_i_i_i_i_i_i_115_c_compmm_m0_shift_x_q[28:13];

    // redist363_i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28_b_1(DELAY,29491)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist363_i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_join(BITJOIN,9888)@304
    assign i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_join_q = {redist363_i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg25(REG,13320)@297 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg25_q <= $unsigned(redist874_sync_together4364_aunroll_x_in_i_valid_229_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_67250_c_compmm_m26(BLACKBOX,8695)@298
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67250_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_67250_c_compmm_m26 (
        .in_intel_reserved_ffwd_232_0(in_intel_reserved_ffwd_232_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg25_q),
        .out_dest_data_out_232_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_67250_c_compmm_m26_out_dest_data_out_232_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_offset(CONSTANT,31637)
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_offset_q = $unsigned(8'b00011111);

    // redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt(ADD,31638)
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_a = {1'b0, redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_q};
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_b = {1'b0, redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_o <= $unsigned(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_a) + $unsigned(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_b);
        end
    end
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_q = redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_o[8:0];

    // redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_inputreg0(DELAY,31633)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_inputreg0_q <= $unsigned(in_c1_eni5_231_tpl);
        end
    end

    // redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr(COUNTER,31636)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_i <= $unsigned(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_q = redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_i[7:0];

    // redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem(DUALMEM,31635)
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_ia = $unsigned(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_inputreg0_q);
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_aa = redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_wraddr_q;
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_ab = redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_aa),
        .data_a(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_ab),
        .q_b(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_q = redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_iq[15:0];

    // redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_outputreg0(DELAY,31634)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_outputreg0_q <= $unsigned(redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_mem_q);
        end
    end

    // redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt(ADD,31644)
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_a = {1'b0, redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_q};
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_b = {1'b0, redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_o <= $unsigned(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_a) + $unsigned(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_b);
        end
    end
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_q = redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_o[8:0];

    // redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_inputreg0(DELAY,31639)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_inputreg0_q <= $unsigned(in_c1_eni5_232_tpl);
        end
    end

    // redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr(COUNTER,31642)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_i <= $unsigned(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_q = redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_i[7:0];

    // redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem(DUALMEM,31641)
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_ia = $unsigned(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_inputreg0_q);
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_aa = redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_wraddr_q;
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_ab = redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_aa),
        .data_a(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_ab),
        .q_b(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_q = redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_iq[15:0];

    // redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_outputreg0(DELAY,31640)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_outputreg0_q <= $unsigned(redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_mem_q);
        end
    end

    // valid_fanout_reg26(REG,13321)@297 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg26_q <= $unsigned(redist874_sync_together4364_aunroll_x_in_i_valid_229_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_67249_c_compmm_m27(BLACKBOX,8691)@298
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67249_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_67249_c_compmm_m27 (
        .in_intel_reserved_ffwd_231_0(in_intel_reserved_ffwd_231_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg26_q),
        .out_dest_data_out_231_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_67249_c_compmm_m27_out_dest_data_out_231_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28986)@298 + 5
    // out q@304
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_67249_c_compmm_m27_out_dest_data_out_231_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_67250_c_compmm_m26_out_dest_data_out_232_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499(ADD,8963)@304
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod857_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_b = $unsigned({{5{i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_115_c_compmm_m3498_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_o[33:0];

    // rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x(MUX,23001)@304
    assign rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q or rightShiftStage0Idx1_uid23000_dupName_461_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q;
            1'b1 : rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23000_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x(MUX,23006)@304
    assign rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23005_dupName_461_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23002_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23005_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x(MUX,23011)@304
    assign rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23010_dupName_461_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23007_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23010_dupName_461_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3500_vt_select_20(BITSELECT,12257)@304
    assign i_unnamed_c_compmm_m3500_vt_select_20_b = rightShiftStage2_uid23012_dupName_461_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3500_vt_join(BITJOIN,12256)@304
    assign i_unnamed_c_compmm_m3500_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3500_vt_select_20_b};

    // i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x(BITSELECT,3721)@304
    assign i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x_b = i_unnamed_c_compmm_m3500_vt_join_q[15:0];

    // redist997_i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x_b_1(DELAY,30125)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist997_i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23021_dupName_462_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23020)@304
    assign rightShiftStage1Idx1Rng8_uid23021_dupName_462_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23023_dupName_462_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23022)@304
    assign rightShiftStage1Idx1_uid23023_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23021_dupName_462_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23016_dupName_462_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23015)@304
    assign rightShiftStage0Idx1Rng4_uid23016_dupName_462_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q[33:4];

    // rightShiftStage0Idx1_uid23018_dupName_462_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23017)@304
    assign rightShiftStage0Idx1_uid23018_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23016_dupName_462_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x(MUX,23019)@304
    assign rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q or rightShiftStage0Idx1_uid23018_dupName_462_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_115_i_c_compmm_m3499_q;
            1'b1 : rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23018_dupName_462_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x(MUX,23024)@304
    assign rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23023_dupName_462_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23020_dupName_462_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23023_dupName_462_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3502_vt_select_21(BITSELECT,12260)@304
    assign i_unnamed_c_compmm_m3502_vt_select_21_b = rightShiftStage1_uid23025_dupName_462_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3502_vt_join(BITJOIN,12259)@304
    assign i_unnamed_c_compmm_m3502_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3502_vt_select_21_b};

    // i_unnamed_c_compmm_m3503_sel_x(BITSELECT,6189)@304
    assign i_unnamed_c_compmm_m3503_sel_x_b = i_unnamed_c_compmm_m3502_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3504_BitSelect_for_a(BITSELECT,28730)@304
    assign i_unnamed_c_compmm_m3504_BitSelect_for_a_b = i_unnamed_c_compmm_m3503_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3504_join(BITJOIN,28731)@304
    assign i_unnamed_c_compmm_m3504_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3504_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3504_vt_select_0(BITSELECT,12265)@304
    assign i_unnamed_c_compmm_m3504_vt_select_0_b = i_unnamed_c_compmm_m3504_join_q[0:0];

    // redist72_i_unnamed_c_compmm_m3504_vt_select_0_b_1(DELAY,29200)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist72_i_unnamed_c_compmm_m3504_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3504_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3504_vt_join(BITJOIN,12264)@305
    assign i_unnamed_c_compmm_m3504_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist72_i_unnamed_c_compmm_m3504_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_115_c_compmm_m3505(ADD,7176)@305
    assign i_add_i_i_i_i_i_i_115_c_compmm_m3505_a = {1'b0, i_unnamed_c_compmm_m3504_vt_join_q};
    assign i_add_i_i_i_i_i_i_115_c_compmm_m3505_b = {1'b0, redist997_i_conv_i_i_i_i_i_115_c_compmm_m3501_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_115_c_compmm_m3505_o = $unsigned(i_add_i_i_i_i_i_i_115_c_compmm_m3505_a) + $unsigned(i_add_i_i_i_i_i_i_115_c_compmm_m3505_b);
    assign i_add_i_i_i_i_i_i_115_c_compmm_m3505_q = i_add_i_i_i_i_i_i_115_c_compmm_m3505_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_115_c_compmm_m3505_sel_x(BITSELECT,2190)@305
    assign bgTrunc_i_add_i_i_i_i_i_i_115_c_compmm_m3505_sel_x_b = i_add_i_i_i_i_i_i_115_c_compmm_m3505_q[15:0];

    // i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_sel_x(BITSELECT,3850)@305
    assign i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_115_c_compmm_m3505_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_select_15(BITSELECT,8127)@305
    assign i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_select_15_b = i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_join(BITJOIN,8126)@305
    assign i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_select_15_b};

    // leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(MUX,26368)@305
    assign leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_join_q or leftShiftStage0Idx1_uid26367_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_116_c_compmm_m3525_vt_join_q;
            1'b1 : leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26367_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(MUX,26373)@305
    assign leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s or leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26372_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = leftShiftStage0_uid26369_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26372_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x(MUX,26378)@305
    assign leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s or leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26377_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = leftShiftStage1_uid26374_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26377_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28(BITSELECT,9892)@305
    assign i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28_b = leftShiftStage2_uid26379_i_shl_i_i_i_i_i_i_116_c_compmm_m0_shift_x_q[28:13];

    // redist362_i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28_b_1(DELAY,29490)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist362_i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_join(BITJOIN,9891)@306
    assign i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_join_q = {redist362_i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg23(REG,13318)@299 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg23_q <= $unsigned(redist875_sync_together4364_aunroll_x_in_i_valid_231_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_67252_c_compmm_m24(BLACKBOX,8707)@300
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67252_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_67252_c_compmm_m24 (
        .in_intel_reserved_ffwd_234_0(in_intel_reserved_ffwd_234_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg23_q),
        .out_dest_data_out_234_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_67252_c_compmm_m24_out_dest_data_out_234_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_offset(CONSTANT,31649)
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_offset_q = $unsigned(8'b00011101);

    // redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt(ADD,31650)
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_a = {1'b0, redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_q};
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_b = {1'b0, redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_o <= $unsigned(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_a) + $unsigned(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_b);
        end
    end
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_q = redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_o[8:0];

    // redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_inputreg0(DELAY,31645)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_inputreg0_q <= $unsigned(in_c1_eni5_233_tpl);
        end
    end

    // redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr(COUNTER,31648)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_i <= $unsigned(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_q = redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_i[7:0];

    // redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem(DUALMEM,31647)
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_ia = $unsigned(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_inputreg0_q);
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_aa = redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_wraddr_q;
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_ab = redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_aa),
        .data_a(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_ab),
        .q_b(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_q = redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_iq[15:0];

    // redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_outputreg0(DELAY,31646)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_outputreg0_q <= $unsigned(redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_mem_q);
        end
    end

    // redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt(ADD,31656)
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_a = {1'b0, redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_q};
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_b = {1'b0, redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_o <= $unsigned(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_a) + $unsigned(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_b);
        end
    end
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_q = redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_o[8:0];

    // redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_inputreg0(DELAY,31651)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_inputreg0_q <= $unsigned(in_c1_eni5_234_tpl);
        end
    end

    // redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr(COUNTER,31654)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_i <= $unsigned(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_q = redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_i[7:0];

    // redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem(DUALMEM,31653)
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_ia = $unsigned(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_inputreg0_q);
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_aa = redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_wraddr_q;
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_ab = redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_aa),
        .data_a(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_ab),
        .q_b(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_q = redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_iq[15:0];

    // redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_outputreg0(DELAY,31652)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_outputreg0_q <= $unsigned(redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_mem_q);
        end
    end

    // valid_fanout_reg24(REG,13319)@299 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg24_q <= $unsigned(redist875_sync_together4364_aunroll_x_in_i_valid_231_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_67251_c_compmm_m25(BLACKBOX,8703)@300
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67251_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_67251_c_compmm_m25 (
        .in_intel_reserved_ffwd_233_0(in_intel_reserved_ffwd_233_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg24_q),
        .out_dest_data_out_233_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_67251_c_compmm_m25_out_dest_data_out_233_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28987)@300 + 5
    // out q@306
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_67251_c_compmm_m25_out_dest_data_out_233_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_67252_c_compmm_m24_out_dest_data_out_234_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527(ADD,8964)@306
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod862_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_b = $unsigned({{5{i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_116_c_compmm_m3526_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_o[33:0];

    // rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x(MUX,23063)@306
    assign rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q or rightShiftStage0Idx1_uid23062_dupName_465_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q;
            1'b1 : rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23062_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x(MUX,23068)@306
    assign rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23067_dupName_465_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23064_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23067_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x(MUX,23073)@306
    assign rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23072_dupName_465_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23069_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23072_dupName_465_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3528_vt_select_20(BITSELECT,12279)@306
    assign i_unnamed_c_compmm_m3528_vt_select_20_b = rightShiftStage2_uid23074_dupName_465_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3528_vt_join(BITJOIN,12278)@306
    assign i_unnamed_c_compmm_m3528_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3528_vt_select_20_b};

    // i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x(BITSELECT,3722)@306
    assign i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x_b = i_unnamed_c_compmm_m3528_vt_join_q[15:0];

    // redist996_i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x_b_1(DELAY,30124)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist996_i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23083_dupName_466_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23082)@306
    assign rightShiftStage1Idx1Rng8_uid23083_dupName_466_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23085_dupName_466_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23084)@306
    assign rightShiftStage1Idx1_uid23085_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23083_dupName_466_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23078_dupName_466_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23077)@306
    assign rightShiftStage0Idx1Rng4_uid23078_dupName_466_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q[33:4];

    // rightShiftStage0Idx1_uid23080_dupName_466_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23079)@306
    assign rightShiftStage0Idx1_uid23080_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23078_dupName_466_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x(MUX,23081)@306
    assign rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q or rightShiftStage0Idx1_uid23080_dupName_466_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_116_i_c_compmm_m3527_q;
            1'b1 : rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23080_dupName_466_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x(MUX,23086)@306
    assign rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23085_dupName_466_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23082_dupName_466_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23085_dupName_466_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3530_vt_select_21(BITSELECT,12282)@306
    assign i_unnamed_c_compmm_m3530_vt_select_21_b = rightShiftStage1_uid23087_dupName_466_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3530_vt_join(BITJOIN,12281)@306
    assign i_unnamed_c_compmm_m3530_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3530_vt_select_21_b};

    // i_unnamed_c_compmm_m3531_sel_x(BITSELECT,6191)@306
    assign i_unnamed_c_compmm_m3531_sel_x_b = i_unnamed_c_compmm_m3530_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3532_BitSelect_for_a(BITSELECT,28734)@306
    assign i_unnamed_c_compmm_m3532_BitSelect_for_a_b = i_unnamed_c_compmm_m3531_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3532_join(BITJOIN,28735)@306
    assign i_unnamed_c_compmm_m3532_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3532_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3532_vt_select_0(BITSELECT,12287)@306
    assign i_unnamed_c_compmm_m3532_vt_select_0_b = i_unnamed_c_compmm_m3532_join_q[0:0];

    // redist70_i_unnamed_c_compmm_m3532_vt_select_0_b_1(DELAY,29198)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist70_i_unnamed_c_compmm_m3532_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3532_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3532_vt_join(BITJOIN,12286)@307
    assign i_unnamed_c_compmm_m3532_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist70_i_unnamed_c_compmm_m3532_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_116_c_compmm_m3533(ADD,7177)@307
    assign i_add_i_i_i_i_i_i_116_c_compmm_m3533_a = {1'b0, i_unnamed_c_compmm_m3532_vt_join_q};
    assign i_add_i_i_i_i_i_i_116_c_compmm_m3533_b = {1'b0, redist996_i_conv_i_i_i_i_i_116_c_compmm_m3529_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_116_c_compmm_m3533_o = $unsigned(i_add_i_i_i_i_i_i_116_c_compmm_m3533_a) + $unsigned(i_add_i_i_i_i_i_i_116_c_compmm_m3533_b);
    assign i_add_i_i_i_i_i_i_116_c_compmm_m3533_q = i_add_i_i_i_i_i_i_116_c_compmm_m3533_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_116_c_compmm_m3533_sel_x(BITSELECT,2191)@307
    assign bgTrunc_i_add_i_i_i_i_i_i_116_c_compmm_m3533_sel_x_b = i_add_i_i_i_i_i_i_116_c_compmm_m3533_q[15:0];

    // i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_sel_x(BITSELECT,3851)@307
    assign i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_116_c_compmm_m3533_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_select_15(BITSELECT,8131)@307
    assign i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_select_15_b = i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_join(BITJOIN,8130)@307
    assign i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_select_15_b};

    // leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(MUX,26386)@307
    assign leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_join_q or leftShiftStage0Idx1_uid26385_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_117_c_compmm_m3553_vt_join_q;
            1'b1 : leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26385_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(MUX,26391)@307
    assign leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s or leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26390_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = leftShiftStage0_uid26387_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26390_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x(MUX,26396)@307
    assign leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s or leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26395_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = leftShiftStage1_uid26392_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26395_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28(BITSELECT,9895)@307
    assign i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28_b = leftShiftStage2_uid26397_i_shl_i_i_i_i_i_i_117_c_compmm_m0_shift_x_q[28:13];

    // redist361_i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28_b_1(DELAY,29489)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist361_i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_join(BITJOIN,9894)@308
    assign i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_join_q = {redist361_i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg21(REG,13316)@301 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg21_q <= $unsigned(redist876_sync_together4364_aunroll_x_in_i_valid_233_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_67254_c_compmm_m22(BLACKBOX,8715)@302
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67254_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_67254_c_compmm_m22 (
        .in_intel_reserved_ffwd_236_0(in_intel_reserved_ffwd_236_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg21_q),
        .out_dest_data_out_236_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_67254_c_compmm_m22_out_dest_data_out_236_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_offset(CONSTANT,31661)
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_offset_q = $unsigned(8'b00011011);

    // redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt(ADD,31662)
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_a = {1'b0, redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_q};
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_b = {1'b0, redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_o <= $unsigned(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_a) + $unsigned(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_b);
        end
    end
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_q = redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_o[8:0];

    // redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_inputreg0(DELAY,31657)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_inputreg0_q <= $unsigned(in_c1_eni5_235_tpl);
        end
    end

    // redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr(COUNTER,31660)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_i <= $unsigned(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_q = redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_i[7:0];

    // redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem(DUALMEM,31659)
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_ia = $unsigned(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_inputreg0_q);
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_aa = redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_wraddr_q;
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_ab = redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_aa),
        .data_a(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_ab),
        .q_b(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_q = redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_iq[15:0];

    // redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_outputreg0(DELAY,31658)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_outputreg0_q <= $unsigned(redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_mem_q);
        end
    end

    // redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt(ADD,31668)
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_a = {1'b0, redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_q};
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_b = {1'b0, redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_o <= $unsigned(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_a) + $unsigned(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_b);
        end
    end
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_q = redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_o[8:0];

    // redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_inputreg0(DELAY,31663)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_inputreg0_q <= $unsigned(in_c1_eni5_236_tpl);
        end
    end

    // redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr(COUNTER,31666)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_i <= $unsigned(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_q = redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_i[7:0];

    // redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem(DUALMEM,31665)
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_ia = $unsigned(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_inputreg0_q);
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_aa = redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_wraddr_q;
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_ab = redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_aa),
        .data_a(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_ab),
        .q_b(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_q = redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_iq[15:0];

    // redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_outputreg0(DELAY,31664)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_outputreg0_q <= $unsigned(redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_mem_q);
        end
    end

    // valid_fanout_reg22(REG,13317)@301 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg22_q <= $unsigned(redist876_sync_together4364_aunroll_x_in_i_valid_233_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_67253_c_compmm_m23(BLACKBOX,8711)@302
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67253_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_67253_c_compmm_m23 (
        .in_intel_reserved_ffwd_235_0(in_intel_reserved_ffwd_235_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg22_q),
        .out_dest_data_out_235_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_67253_c_compmm_m23_out_dest_data_out_235_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28988)@302 + 5
    // out q@308
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_67253_c_compmm_m23_out_dest_data_out_235_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_67254_c_compmm_m22_out_dest_data_out_236_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555(ADD,8965)@308
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod867_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_b = $unsigned({{5{i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_117_c_compmm_m3554_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_o[33:0];

    // rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x(MUX,23125)@308
    assign rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q or rightShiftStage0Idx1_uid23124_dupName_469_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q;
            1'b1 : rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23124_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x(MUX,23130)@308
    assign rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23129_dupName_469_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23126_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23129_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x(MUX,23135)@308
    assign rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23134_dupName_469_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23131_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23134_dupName_469_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3556_vt_select_20(BITSELECT,12301)@308
    assign i_unnamed_c_compmm_m3556_vt_select_20_b = rightShiftStage2_uid23136_dupName_469_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3556_vt_join(BITJOIN,12300)@308
    assign i_unnamed_c_compmm_m3556_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3556_vt_select_20_b};

    // i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x(BITSELECT,3723)@308
    assign i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x_b = i_unnamed_c_compmm_m3556_vt_join_q[15:0];

    // redist995_i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x_b_1(DELAY,30123)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist995_i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23145_dupName_470_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23144)@308
    assign rightShiftStage1Idx1Rng8_uid23145_dupName_470_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23147_dupName_470_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23146)@308
    assign rightShiftStage1Idx1_uid23147_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23145_dupName_470_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23140_dupName_470_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23139)@308
    assign rightShiftStage0Idx1Rng4_uid23140_dupName_470_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q[33:4];

    // rightShiftStage0Idx1_uid23142_dupName_470_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23141)@308
    assign rightShiftStage0Idx1_uid23142_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23140_dupName_470_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x(MUX,23143)@308
    assign rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q or rightShiftStage0Idx1_uid23142_dupName_470_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_117_i_c_compmm_m3555_q;
            1'b1 : rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23142_dupName_470_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x(MUX,23148)@308
    assign rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23147_dupName_470_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23144_dupName_470_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23147_dupName_470_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3558_vt_select_21(BITSELECT,12304)@308
    assign i_unnamed_c_compmm_m3558_vt_select_21_b = rightShiftStage1_uid23149_dupName_470_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3558_vt_join(BITJOIN,12303)@308
    assign i_unnamed_c_compmm_m3558_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3558_vt_select_21_b};

    // i_unnamed_c_compmm_m3559_sel_x(BITSELECT,6193)@308
    assign i_unnamed_c_compmm_m3559_sel_x_b = i_unnamed_c_compmm_m3558_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3560_BitSelect_for_a(BITSELECT,28738)@308
    assign i_unnamed_c_compmm_m3560_BitSelect_for_a_b = i_unnamed_c_compmm_m3559_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3560_join(BITJOIN,28739)@308
    assign i_unnamed_c_compmm_m3560_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3560_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3560_vt_select_0(BITSELECT,12309)@308
    assign i_unnamed_c_compmm_m3560_vt_select_0_b = i_unnamed_c_compmm_m3560_join_q[0:0];

    // redist68_i_unnamed_c_compmm_m3560_vt_select_0_b_1(DELAY,29196)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist68_i_unnamed_c_compmm_m3560_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3560_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3560_vt_join(BITJOIN,12308)@309
    assign i_unnamed_c_compmm_m3560_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist68_i_unnamed_c_compmm_m3560_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_117_c_compmm_m3561(ADD,7178)@309
    assign i_add_i_i_i_i_i_i_117_c_compmm_m3561_a = {1'b0, i_unnamed_c_compmm_m3560_vt_join_q};
    assign i_add_i_i_i_i_i_i_117_c_compmm_m3561_b = {1'b0, redist995_i_conv_i_i_i_i_i_117_c_compmm_m3557_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_117_c_compmm_m3561_o = $unsigned(i_add_i_i_i_i_i_i_117_c_compmm_m3561_a) + $unsigned(i_add_i_i_i_i_i_i_117_c_compmm_m3561_b);
    assign i_add_i_i_i_i_i_i_117_c_compmm_m3561_q = i_add_i_i_i_i_i_i_117_c_compmm_m3561_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_117_c_compmm_m3561_sel_x(BITSELECT,2192)@309
    assign bgTrunc_i_add_i_i_i_i_i_i_117_c_compmm_m3561_sel_x_b = i_add_i_i_i_i_i_i_117_c_compmm_m3561_q[15:0];

    // i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_sel_x(BITSELECT,3852)@309
    assign i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_117_c_compmm_m3561_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_select_15(BITSELECT,8135)@309
    assign i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_select_15_b = i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_join(BITJOIN,8134)@309
    assign i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_select_15_b};

    // leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(MUX,26404)@309
    assign leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_join_q or leftShiftStage0Idx1_uid26403_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_118_c_compmm_m3581_vt_join_q;
            1'b1 : leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26403_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(MUX,26409)@309
    assign leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s or leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26408_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = leftShiftStage0_uid26405_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26408_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x(MUX,26414)@309
    assign leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s or leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26413_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = leftShiftStage1_uid26410_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26413_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28(BITSELECT,9898)@309
    assign i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28_b = leftShiftStage2_uid26415_i_shl_i_i_i_i_i_i_118_c_compmm_m0_shift_x_q[28:13];

    // redist360_i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28_b_1(DELAY,29488)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist360_i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_join(BITJOIN,9897)@310
    assign i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_join_q = {redist360_i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg19(REG,13314)@303 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg19_q <= $unsigned(redist877_sync_together4364_aunroll_x_in_i_valid_235_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_67256_c_compmm_m20(BLACKBOX,8723)@304
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67256_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_67256_c_compmm_m20 (
        .in_intel_reserved_ffwd_238_0(in_intel_reserved_ffwd_238_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg19_q),
        .out_dest_data_out_238_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_67256_c_compmm_m20_out_dest_data_out_238_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_offset(CONSTANT,31673)
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_offset_q = $unsigned(8'b00011001);

    // redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt(ADD,31674)
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_a = {1'b0, redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_q};
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_b = {1'b0, redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_o <= $unsigned(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_a) + $unsigned(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_b);
        end
    end
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_q = redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_o[8:0];

    // redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_inputreg0(DELAY,31669)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_inputreg0_q <= $unsigned(in_c1_eni5_237_tpl);
        end
    end

    // redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr(COUNTER,31672)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_i <= $unsigned(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_q = redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_i[7:0];

    // redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem(DUALMEM,31671)
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_ia = $unsigned(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_inputreg0_q);
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_aa = redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_wraddr_q;
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_ab = redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_aa),
        .data_a(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_ab),
        .q_b(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_q = redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_iq[15:0];

    // redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_outputreg0(DELAY,31670)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_outputreg0_q <= $unsigned(redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_mem_q);
        end
    end

    // redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt(ADD,31680)
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_a = {1'b0, redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_q};
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_b = {1'b0, redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_o <= $unsigned(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_a) + $unsigned(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_b);
        end
    end
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_q = redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_o[8:0];

    // redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_inputreg0(DELAY,31675)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_inputreg0_q <= $unsigned(in_c1_eni5_238_tpl);
        end
    end

    // redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr(COUNTER,31678)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_i <= $unsigned(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_q = redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_i[7:0];

    // redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem(DUALMEM,31677)
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_ia = $unsigned(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_inputreg0_q);
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_aa = redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_wraddr_q;
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_ab = redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_aa),
        .data_a(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_ab),
        .q_b(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_q = redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_iq[15:0];

    // redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_outputreg0(DELAY,31676)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_outputreg0_q <= $unsigned(redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_mem_q);
        end
    end

    // valid_fanout_reg20(REG,13315)@303 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg20_q <= $unsigned(redist877_sync_together4364_aunroll_x_in_i_valid_235_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_67255_c_compmm_m21(BLACKBOX,8719)@304
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67255_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_67255_c_compmm_m21 (
        .in_intel_reserved_ffwd_237_0(in_intel_reserved_ffwd_237_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg20_q),
        .out_dest_data_out_237_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_67255_c_compmm_m21_out_dest_data_out_237_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28989)@304 + 5
    // out q@310
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_67255_c_compmm_m21_out_dest_data_out_237_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_67256_c_compmm_m20_out_dest_data_out_238_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583(ADD,8966)@310
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod872_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_b = $unsigned({{5{i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_118_c_compmm_m3582_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_o[33:0];

    // rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x(MUX,23187)@310
    assign rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q or rightShiftStage0Idx1_uid23186_dupName_473_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q;
            1'b1 : rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23186_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x(MUX,23192)@310
    assign rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23191_dupName_473_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23188_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23191_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x(MUX,23197)@310
    assign rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23196_dupName_473_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23193_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23196_dupName_473_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3584_vt_select_20(BITSELECT,12323)@310
    assign i_unnamed_c_compmm_m3584_vt_select_20_b = rightShiftStage2_uid23198_dupName_473_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3584_vt_join(BITJOIN,12322)@310
    assign i_unnamed_c_compmm_m3584_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3584_vt_select_20_b};

    // i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x(BITSELECT,3724)@310
    assign i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x_b = i_unnamed_c_compmm_m3584_vt_join_q[15:0];

    // redist994_i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x_b_1(DELAY,30122)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist994_i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23207_dupName_474_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23206)@310
    assign rightShiftStage1Idx1Rng8_uid23207_dupName_474_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23209_dupName_474_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23208)@310
    assign rightShiftStage1Idx1_uid23209_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23207_dupName_474_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23202_dupName_474_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23201)@310
    assign rightShiftStage0Idx1Rng4_uid23202_dupName_474_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q[33:4];

    // rightShiftStage0Idx1_uid23204_dupName_474_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23203)@310
    assign rightShiftStage0Idx1_uid23204_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23202_dupName_474_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x(MUX,23205)@310
    assign rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q or rightShiftStage0Idx1_uid23204_dupName_474_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_118_i_c_compmm_m3583_q;
            1'b1 : rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23204_dupName_474_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x(MUX,23210)@310
    assign rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23209_dupName_474_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23206_dupName_474_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23209_dupName_474_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3586_vt_select_21(BITSELECT,12326)@310
    assign i_unnamed_c_compmm_m3586_vt_select_21_b = rightShiftStage1_uid23211_dupName_474_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3586_vt_join(BITJOIN,12325)@310
    assign i_unnamed_c_compmm_m3586_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3586_vt_select_21_b};

    // i_unnamed_c_compmm_m3587_sel_x(BITSELECT,6195)@310
    assign i_unnamed_c_compmm_m3587_sel_x_b = i_unnamed_c_compmm_m3586_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3588_BitSelect_for_a(BITSELECT,28742)@310
    assign i_unnamed_c_compmm_m3588_BitSelect_for_a_b = i_unnamed_c_compmm_m3587_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3588_join(BITJOIN,28743)@310
    assign i_unnamed_c_compmm_m3588_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3588_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3588_vt_select_0(BITSELECT,12331)@310
    assign i_unnamed_c_compmm_m3588_vt_select_0_b = i_unnamed_c_compmm_m3588_join_q[0:0];

    // redist66_i_unnamed_c_compmm_m3588_vt_select_0_b_1(DELAY,29194)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist66_i_unnamed_c_compmm_m3588_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3588_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3588_vt_join(BITJOIN,12330)@311
    assign i_unnamed_c_compmm_m3588_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist66_i_unnamed_c_compmm_m3588_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_118_c_compmm_m3589(ADD,7179)@311
    assign i_add_i_i_i_i_i_i_118_c_compmm_m3589_a = {1'b0, i_unnamed_c_compmm_m3588_vt_join_q};
    assign i_add_i_i_i_i_i_i_118_c_compmm_m3589_b = {1'b0, redist994_i_conv_i_i_i_i_i_118_c_compmm_m3585_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_118_c_compmm_m3589_o = $unsigned(i_add_i_i_i_i_i_i_118_c_compmm_m3589_a) + $unsigned(i_add_i_i_i_i_i_i_118_c_compmm_m3589_b);
    assign i_add_i_i_i_i_i_i_118_c_compmm_m3589_q = i_add_i_i_i_i_i_i_118_c_compmm_m3589_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_118_c_compmm_m3589_sel_x(BITSELECT,2193)@311
    assign bgTrunc_i_add_i_i_i_i_i_i_118_c_compmm_m3589_sel_x_b = i_add_i_i_i_i_i_i_118_c_compmm_m3589_q[15:0];

    // i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_sel_x(BITSELECT,3853)@311
    assign i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_118_c_compmm_m3589_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_select_15(BITSELECT,8139)@311
    assign i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_select_15_b = i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_join(BITJOIN,8138)@311
    assign i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_select_15_b};

    // leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(MUX,26422)@311
    assign leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_join_q or leftShiftStage0Idx1_uid26421_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_119_c_compmm_m3609_vt_join_q;
            1'b1 : leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26421_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(MUX,26427)@311
    assign leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s or leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26426_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = leftShiftStage0_uid26423_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26426_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x(MUX,26432)@311
    assign leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s or leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26431_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = leftShiftStage1_uid26428_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26431_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28(BITSELECT,9901)@311
    assign i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28_b = leftShiftStage2_uid26433_i_shl_i_i_i_i_i_i_119_c_compmm_m0_shift_x_q[28:13];

    // redist359_i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28_b_1(DELAY,29487)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist359_i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_join(BITJOIN,9900)@312
    assign i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_join_q = {redist359_i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg17(REG,13312)@305 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg17_q <= $unsigned(redist878_sync_together4364_aunroll_x_in_i_valid_237_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_67258_c_compmm_m18(BLACKBOX,8731)@306
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67258_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_67258_c_compmm_m18 (
        .in_intel_reserved_ffwd_240_0(in_intel_reserved_ffwd_240_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg17_q),
        .out_dest_data_out_240_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_67258_c_compmm_m18_out_dest_data_out_240_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_offset(CONSTANT,31685)
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_offset_q = $unsigned(8'b00010111);

    // redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt(ADD,31686)
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_a = {1'b0, redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_q};
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_b = {1'b0, redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_o <= $unsigned(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_a) + $unsigned(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_b);
        end
    end
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_q = redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_o[8:0];

    // redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_inputreg0(DELAY,31681)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_inputreg0_q <= $unsigned(in_c1_eni5_239_tpl);
        end
    end

    // redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr(COUNTER,31684)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_i <= $unsigned(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_q = redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_i[7:0];

    // redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem(DUALMEM,31683)
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_ia = $unsigned(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_inputreg0_q);
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_aa = redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_wraddr_q;
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_ab = redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_aa),
        .data_a(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_ab),
        .q_b(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_q = redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_iq[15:0];

    // redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_outputreg0(DELAY,31682)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_outputreg0_q <= $unsigned(redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_mem_q);
        end
    end

    // redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt(ADD,31692)
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_a = {1'b0, redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_q};
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_b = {1'b0, redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_o <= $unsigned(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_a) + $unsigned(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_b);
        end
    end
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_q = redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_o[8:0];

    // redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_inputreg0(DELAY,31687)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_inputreg0_q <= $unsigned(in_c1_eni5_240_tpl);
        end
    end

    // redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr(COUNTER,31690)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_i <= $unsigned(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_q = redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_i[7:0];

    // redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem(DUALMEM,31689)
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_ia = $unsigned(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_inputreg0_q);
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_aa = redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_wraddr_q;
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_ab = redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_aa),
        .data_a(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_ab),
        .q_b(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_q = redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_iq[15:0];

    // redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_outputreg0(DELAY,31688)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_outputreg0_q <= $unsigned(redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_mem_q);
        end
    end

    // valid_fanout_reg18(REG,13313)@305 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg18_q <= $unsigned(redist878_sync_together4364_aunroll_x_in_i_valid_237_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_67257_c_compmm_m19(BLACKBOX,8727)@306
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67257_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_67257_c_compmm_m19 (
        .in_intel_reserved_ffwd_239_0(in_intel_reserved_ffwd_239_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg18_q),
        .out_dest_data_out_239_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_67257_c_compmm_m19_out_dest_data_out_239_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28990)@306 + 5
    // out q@312
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_67257_c_compmm_m19_out_dest_data_out_239_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_67258_c_compmm_m18_out_dest_data_out_240_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611(ADD,8967)@312
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod877_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_b = $unsigned({{5{i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_119_c_compmm_m3610_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_o[33:0];

    // rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x(MUX,23249)@312
    assign rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q or rightShiftStage0Idx1_uid23248_dupName_477_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q;
            1'b1 : rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23248_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x(MUX,23254)@312
    assign rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23253_dupName_477_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23250_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23253_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x(MUX,23259)@312
    assign rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23258_dupName_477_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23255_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23258_dupName_477_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3612_vt_select_20(BITSELECT,12345)@312
    assign i_unnamed_c_compmm_m3612_vt_select_20_b = rightShiftStage2_uid23260_dupName_477_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3612_vt_join(BITJOIN,12344)@312
    assign i_unnamed_c_compmm_m3612_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3612_vt_select_20_b};

    // i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x(BITSELECT,3725)@312
    assign i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x_b = i_unnamed_c_compmm_m3612_vt_join_q[15:0];

    // redist993_i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x_b_1(DELAY,30121)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist993_i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23269_dupName_478_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23268)@312
    assign rightShiftStage1Idx1Rng8_uid23269_dupName_478_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23271_dupName_478_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23270)@312
    assign rightShiftStage1Idx1_uid23271_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23269_dupName_478_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23264_dupName_478_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23263)@312
    assign rightShiftStage0Idx1Rng4_uid23264_dupName_478_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q[33:4];

    // rightShiftStage0Idx1_uid23266_dupName_478_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23265)@312
    assign rightShiftStage0Idx1_uid23266_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23264_dupName_478_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x(MUX,23267)@312
    assign rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q or rightShiftStage0Idx1_uid23266_dupName_478_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_119_i_c_compmm_m3611_q;
            1'b1 : rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23266_dupName_478_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x(MUX,23272)@312
    assign rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23271_dupName_478_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23268_dupName_478_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23271_dupName_478_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3614_vt_select_21(BITSELECT,12348)@312
    assign i_unnamed_c_compmm_m3614_vt_select_21_b = rightShiftStage1_uid23273_dupName_478_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3614_vt_join(BITJOIN,12347)@312
    assign i_unnamed_c_compmm_m3614_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3614_vt_select_21_b};

    // i_unnamed_c_compmm_m3615_sel_x(BITSELECT,6197)@312
    assign i_unnamed_c_compmm_m3615_sel_x_b = i_unnamed_c_compmm_m3614_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3616_BitSelect_for_a(BITSELECT,28746)@312
    assign i_unnamed_c_compmm_m3616_BitSelect_for_a_b = i_unnamed_c_compmm_m3615_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3616_join(BITJOIN,28747)@312
    assign i_unnamed_c_compmm_m3616_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3616_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3616_vt_select_0(BITSELECT,12353)@312
    assign i_unnamed_c_compmm_m3616_vt_select_0_b = i_unnamed_c_compmm_m3616_join_q[0:0];

    // redist64_i_unnamed_c_compmm_m3616_vt_select_0_b_1(DELAY,29192)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist64_i_unnamed_c_compmm_m3616_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3616_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3616_vt_join(BITJOIN,12352)@313
    assign i_unnamed_c_compmm_m3616_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist64_i_unnamed_c_compmm_m3616_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_119_c_compmm_m3617(ADD,7180)@313
    assign i_add_i_i_i_i_i_i_119_c_compmm_m3617_a = {1'b0, i_unnamed_c_compmm_m3616_vt_join_q};
    assign i_add_i_i_i_i_i_i_119_c_compmm_m3617_b = {1'b0, redist993_i_conv_i_i_i_i_i_119_c_compmm_m3613_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_119_c_compmm_m3617_o = $unsigned(i_add_i_i_i_i_i_i_119_c_compmm_m3617_a) + $unsigned(i_add_i_i_i_i_i_i_119_c_compmm_m3617_b);
    assign i_add_i_i_i_i_i_i_119_c_compmm_m3617_q = i_add_i_i_i_i_i_i_119_c_compmm_m3617_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_119_c_compmm_m3617_sel_x(BITSELECT,2194)@313
    assign bgTrunc_i_add_i_i_i_i_i_i_119_c_compmm_m3617_sel_x_b = i_add_i_i_i_i_i_i_119_c_compmm_m3617_q[15:0];

    // i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_sel_x(BITSELECT,3855)@313
    assign i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_119_c_compmm_m3617_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_select_15(BITSELECT,8147)@313
    assign i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_select_15_b = i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_join(BITJOIN,8146)@313
    assign i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_select_15_b};

    // leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(MUX,26458)@313
    assign leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_join_q or leftShiftStage0Idx1_uid26457_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_120_c_compmm_m3637_vt_join_q;
            1'b1 : leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26457_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(MUX,26463)@313
    assign leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s or leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26462_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = leftShiftStage0_uid26459_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26462_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x(MUX,26468)@313
    assign leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s or leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26467_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = leftShiftStage1_uid26464_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26467_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28(BITSELECT,9907)@313
    assign i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28_b = leftShiftStage2_uid26469_i_shl_i_i_i_i_i_i_120_c_compmm_m0_shift_x_q[28:13];

    // redist357_i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28_b_1(DELAY,29485)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist357_i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_join(BITJOIN,9906)@314
    assign i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_join_q = {redist357_i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg15(REG,13310)@307 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg15_q <= $unsigned(redist879_sync_together4364_aunroll_x_in_i_valid_239_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_67260_c_compmm_m16(BLACKBOX,8739)@308
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67260_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_67260_c_compmm_m16 (
        .in_intel_reserved_ffwd_242_0(in_intel_reserved_ffwd_242_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg15_q),
        .out_dest_data_out_242_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_67260_c_compmm_m16_out_dest_data_out_242_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_offset(CONSTANT,31697)
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_offset_q = $unsigned(8'b00010101);

    // redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt(ADD,31698)
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_a = {1'b0, redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_q};
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_b = {1'b0, redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_o <= $unsigned(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_a) + $unsigned(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_b);
        end
    end
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_q = redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_o[8:0];

    // redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_inputreg0(DELAY,31693)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_inputreg0_q <= $unsigned(in_c1_eni5_241_tpl);
        end
    end

    // redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr(COUNTER,31696)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_i <= $unsigned(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_q = redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_i[7:0];

    // redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem(DUALMEM,31695)
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_ia = $unsigned(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_inputreg0_q);
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_aa = redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_wraddr_q;
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_ab = redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_aa),
        .data_a(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_ab),
        .q_b(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_q = redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_iq[15:0];

    // redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_outputreg0(DELAY,31694)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_outputreg0_q <= $unsigned(redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_mem_q);
        end
    end

    // redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt(ADD,31704)
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_a = {1'b0, redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_q};
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_b = {1'b0, redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_o <= $unsigned(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_a) + $unsigned(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_b);
        end
    end
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_q = redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_o[8:0];

    // redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_inputreg0(DELAY,31699)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_inputreg0_q <= $unsigned(in_c1_eni5_242_tpl);
        end
    end

    // redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr(COUNTER,31702)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_i <= $unsigned(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_q = redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_i[7:0];

    // redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem(DUALMEM,31701)
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_ia = $unsigned(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_inputreg0_q);
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_aa = redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_wraddr_q;
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_ab = redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_aa),
        .data_a(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_ab),
        .q_b(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_q = redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_iq[15:0];

    // redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_outputreg0(DELAY,31700)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_outputreg0_q <= $unsigned(redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_mem_q);
        end
    end

    // valid_fanout_reg16(REG,13311)@307 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg16_q <= $unsigned(redist879_sync_together4364_aunroll_x_in_i_valid_239_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_67259_c_compmm_m17(BLACKBOX,8735)@308
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67259_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_67259_c_compmm_m17 (
        .in_intel_reserved_ffwd_241_0(in_intel_reserved_ffwd_241_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg16_q),
        .out_dest_data_out_241_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_67259_c_compmm_m17_out_dest_data_out_241_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28991)@308 + 5
    // out q@314
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_67259_c_compmm_m17_out_dest_data_out_241_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_67260_c_compmm_m16_out_dest_data_out_242_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639(ADD,8969)@314
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod882_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_b = $unsigned({{5{i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_120_c_compmm_m3638_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_o[33:0];

    // rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x(MUX,23311)@314
    assign rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q or rightShiftStage0Idx1_uid23310_dupName_481_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q;
            1'b1 : rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23310_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x(MUX,23316)@314
    assign rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23315_dupName_481_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23312_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23315_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x(MUX,23321)@314
    assign rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23320_dupName_481_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23317_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23320_dupName_481_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3640_vt_select_20(BITSELECT,12373)@314
    assign i_unnamed_c_compmm_m3640_vt_select_20_b = rightShiftStage2_uid23322_dupName_481_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3640_vt_join(BITJOIN,12372)@314
    assign i_unnamed_c_compmm_m3640_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3640_vt_select_20_b};

    // i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x(BITSELECT,3727)@314
    assign i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x_b = i_unnamed_c_compmm_m3640_vt_join_q[15:0];

    // redist991_i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x_b_1(DELAY,30119)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist991_i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23331_dupName_482_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23330)@314
    assign rightShiftStage1Idx1Rng8_uid23331_dupName_482_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23333_dupName_482_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23332)@314
    assign rightShiftStage1Idx1_uid23333_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23331_dupName_482_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23326_dupName_482_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23325)@314
    assign rightShiftStage0Idx1Rng4_uid23326_dupName_482_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q[33:4];

    // rightShiftStage0Idx1_uid23328_dupName_482_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23327)@314
    assign rightShiftStage0Idx1_uid23328_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23326_dupName_482_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x(MUX,23329)@314
    assign rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q or rightShiftStage0Idx1_uid23328_dupName_482_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_120_i_c_compmm_m3639_q;
            1'b1 : rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23328_dupName_482_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x(MUX,23334)@314
    assign rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23333_dupName_482_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23330_dupName_482_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23333_dupName_482_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3642_vt_select_21(BITSELECT,12376)@314
    assign i_unnamed_c_compmm_m3642_vt_select_21_b = rightShiftStage1_uid23335_dupName_482_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3642_vt_join(BITJOIN,12375)@314
    assign i_unnamed_c_compmm_m3642_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3642_vt_select_21_b};

    // i_unnamed_c_compmm_m3643_sel_x(BITSELECT,6200)@314
    assign i_unnamed_c_compmm_m3643_sel_x_b = i_unnamed_c_compmm_m3642_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3644_BitSelect_for_a(BITSELECT,28750)@314
    assign i_unnamed_c_compmm_m3644_BitSelect_for_a_b = i_unnamed_c_compmm_m3643_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3644_join(BITJOIN,28751)@314
    assign i_unnamed_c_compmm_m3644_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3644_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3644_vt_select_0(BITSELECT,12381)@314
    assign i_unnamed_c_compmm_m3644_vt_select_0_b = i_unnamed_c_compmm_m3644_join_q[0:0];

    // redist62_i_unnamed_c_compmm_m3644_vt_select_0_b_1(DELAY,29190)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist62_i_unnamed_c_compmm_m3644_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3644_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3644_vt_join(BITJOIN,12380)@315
    assign i_unnamed_c_compmm_m3644_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist62_i_unnamed_c_compmm_m3644_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_120_c_compmm_m3645(ADD,7182)@315
    assign i_add_i_i_i_i_i_i_120_c_compmm_m3645_a = {1'b0, i_unnamed_c_compmm_m3644_vt_join_q};
    assign i_add_i_i_i_i_i_i_120_c_compmm_m3645_b = {1'b0, redist991_i_conv_i_i_i_i_i_120_c_compmm_m3641_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_120_c_compmm_m3645_o = $unsigned(i_add_i_i_i_i_i_i_120_c_compmm_m3645_a) + $unsigned(i_add_i_i_i_i_i_i_120_c_compmm_m3645_b);
    assign i_add_i_i_i_i_i_i_120_c_compmm_m3645_q = i_add_i_i_i_i_i_i_120_c_compmm_m3645_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_120_c_compmm_m3645_sel_x(BITSELECT,2196)@315
    assign bgTrunc_i_add_i_i_i_i_i_i_120_c_compmm_m3645_sel_x_b = i_add_i_i_i_i_i_i_120_c_compmm_m3645_q[15:0];

    // i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_sel_x(BITSELECT,3856)@315
    assign i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_120_c_compmm_m3645_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_select_15(BITSELECT,8151)@315
    assign i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_select_15_b = i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_join(BITJOIN,8150)@315
    assign i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_select_15_b};

    // leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(MUX,26476)@315
    assign leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_join_q or leftShiftStage0Idx1_uid26475_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_121_c_compmm_m3665_vt_join_q;
            1'b1 : leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26475_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(MUX,26481)@315
    assign leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s or leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26480_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = leftShiftStage0_uid26477_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26480_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x(MUX,26486)@315
    assign leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s or leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26485_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = leftShiftStage1_uid26482_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26485_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28(BITSELECT,9910)@315
    assign i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28_b = leftShiftStage2_uid26487_i_shl_i_i_i_i_i_i_121_c_compmm_m0_shift_x_q[28:13];

    // redist356_i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28_b_1(DELAY,29484)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist356_i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_join(BITJOIN,9909)@316
    assign i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_join_q = {redist356_i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg13(REG,13308)@309 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg13_q <= $unsigned(redist880_sync_together4364_aunroll_x_in_i_valid_241_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_67262_c_compmm_m14(BLACKBOX,8751)@310
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67262_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_67262_c_compmm_m14 (
        .in_intel_reserved_ffwd_244_0(in_intel_reserved_ffwd_244_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg13_q),
        .out_dest_data_out_244_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_67262_c_compmm_m14_out_dest_data_out_244_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_offset(CONSTANT,31709)
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_offset_q = $unsigned(8'b00010011);

    // redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt(ADD,31710)
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_a = {1'b0, redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_q};
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_b = {1'b0, redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_o <= $unsigned(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_a) + $unsigned(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_b);
        end
    end
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_q = redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_o[8:0];

    // redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_inputreg0(DELAY,31705)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_inputreg0_q <= $unsigned(in_c1_eni5_243_tpl);
        end
    end

    // redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr(COUNTER,31708)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_i <= $unsigned(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_q = redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_i[7:0];

    // redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem(DUALMEM,31707)
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_ia = $unsigned(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_inputreg0_q);
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_aa = redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_wraddr_q;
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_ab = redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_aa),
        .data_a(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_ab),
        .q_b(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_q = redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_iq[15:0];

    // redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_outputreg0(DELAY,31706)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_outputreg0_q <= $unsigned(redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_mem_q);
        end
    end

    // redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt(ADD,31716)
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_a = {1'b0, redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_q};
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_b = {1'b0, redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_o <= $unsigned(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_a) + $unsigned(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_b);
        end
    end
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_q = redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_o[8:0];

    // redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_inputreg0(DELAY,31711)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_inputreg0_q <= $unsigned(in_c1_eni5_244_tpl);
        end
    end

    // redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr(COUNTER,31714)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_i <= $unsigned(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_q = redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_i[7:0];

    // redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem(DUALMEM,31713)
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_ia = $unsigned(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_inputreg0_q);
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_aa = redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_wraddr_q;
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_ab = redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_aa),
        .data_a(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_ab),
        .q_b(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_q = redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_iq[15:0];

    // redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_outputreg0(DELAY,31712)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_outputreg0_q <= $unsigned(redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_mem_q);
        end
    end

    // valid_fanout_reg14(REG,13309)@309 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg14_q <= $unsigned(redist880_sync_together4364_aunroll_x_in_i_valid_241_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_67261_c_compmm_m15(BLACKBOX,8747)@310
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67261_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_67261_c_compmm_m15 (
        .in_intel_reserved_ffwd_243_0(in_intel_reserved_ffwd_243_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg14_q),
        .out_dest_data_out_243_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_67261_c_compmm_m15_out_dest_data_out_243_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28992)@310 + 5
    // out q@316
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_67261_c_compmm_m15_out_dest_data_out_243_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_67262_c_compmm_m14_out_dest_data_out_244_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667(ADD,8970)@316
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod887_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_b = $unsigned({{5{i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_121_c_compmm_m3666_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_o[33:0];

    // rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x(MUX,23373)@316
    assign rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q or rightShiftStage0Idx1_uid23372_dupName_485_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q;
            1'b1 : rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23372_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x(MUX,23378)@316
    assign rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23377_dupName_485_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23374_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23377_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x(MUX,23383)@316
    assign rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23382_dupName_485_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23379_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23382_dupName_485_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3668_vt_select_20(BITSELECT,12400)@316
    assign i_unnamed_c_compmm_m3668_vt_select_20_b = rightShiftStage2_uid23384_dupName_485_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3668_vt_join(BITJOIN,12399)@316
    assign i_unnamed_c_compmm_m3668_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3668_vt_select_20_b};

    // i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x(BITSELECT,3728)@316
    assign i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x_b = i_unnamed_c_compmm_m3668_vt_join_q[15:0];

    // redist990_i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x_b_1(DELAY,30118)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist990_i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23393_dupName_486_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23392)@316
    assign rightShiftStage1Idx1Rng8_uid23393_dupName_486_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23395_dupName_486_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23394)@316
    assign rightShiftStage1Idx1_uid23395_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23393_dupName_486_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23388_dupName_486_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23387)@316
    assign rightShiftStage0Idx1Rng4_uid23388_dupName_486_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q[33:4];

    // rightShiftStage0Idx1_uid23390_dupName_486_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23389)@316
    assign rightShiftStage0Idx1_uid23390_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23388_dupName_486_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x(MUX,23391)@316
    assign rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q or rightShiftStage0Idx1_uid23390_dupName_486_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_121_i_c_compmm_m3667_q;
            1'b1 : rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23390_dupName_486_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x(MUX,23396)@316
    assign rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23395_dupName_486_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23392_dupName_486_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23395_dupName_486_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3670_vt_select_21(BITSELECT,12403)@316
    assign i_unnamed_c_compmm_m3670_vt_select_21_b = rightShiftStage1_uid23397_dupName_486_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3670_vt_join(BITJOIN,12402)@316
    assign i_unnamed_c_compmm_m3670_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3670_vt_select_21_b};

    // i_unnamed_c_compmm_m3671_sel_x(BITSELECT,6202)@316
    assign i_unnamed_c_compmm_m3671_sel_x_b = i_unnamed_c_compmm_m3670_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3672_BitSelect_for_a(BITSELECT,28756)@316
    assign i_unnamed_c_compmm_m3672_BitSelect_for_a_b = i_unnamed_c_compmm_m3671_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3672_join(BITJOIN,28757)@316
    assign i_unnamed_c_compmm_m3672_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3672_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3672_vt_select_0(BITSELECT,12408)@316
    assign i_unnamed_c_compmm_m3672_vt_select_0_b = i_unnamed_c_compmm_m3672_join_q[0:0];

    // redist59_i_unnamed_c_compmm_m3672_vt_select_0_b_1(DELAY,29187)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist59_i_unnamed_c_compmm_m3672_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3672_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3672_vt_join(BITJOIN,12407)@317
    assign i_unnamed_c_compmm_m3672_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist59_i_unnamed_c_compmm_m3672_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_121_c_compmm_m3673(ADD,7183)@317
    assign i_add_i_i_i_i_i_i_121_c_compmm_m3673_a = {1'b0, i_unnamed_c_compmm_m3672_vt_join_q};
    assign i_add_i_i_i_i_i_i_121_c_compmm_m3673_b = {1'b0, redist990_i_conv_i_i_i_i_i_121_c_compmm_m3669_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_121_c_compmm_m3673_o = $unsigned(i_add_i_i_i_i_i_i_121_c_compmm_m3673_a) + $unsigned(i_add_i_i_i_i_i_i_121_c_compmm_m3673_b);
    assign i_add_i_i_i_i_i_i_121_c_compmm_m3673_q = i_add_i_i_i_i_i_i_121_c_compmm_m3673_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_121_c_compmm_m3673_sel_x(BITSELECT,2197)@317
    assign bgTrunc_i_add_i_i_i_i_i_i_121_c_compmm_m3673_sel_x_b = i_add_i_i_i_i_i_i_121_c_compmm_m3673_q[15:0];

    // i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_sel_x(BITSELECT,3857)@317
    assign i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_121_c_compmm_m3673_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_select_15(BITSELECT,8155)@317
    assign i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_select_15_b = i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_join(BITJOIN,8154)@317
    assign i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_select_15_b};

    // leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(MUX,26494)@317
    assign leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_join_q or leftShiftStage0Idx1_uid26493_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_122_c_compmm_m3693_vt_join_q;
            1'b1 : leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26493_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(MUX,26499)@317
    assign leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s or leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26498_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = leftShiftStage0_uid26495_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26498_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x(MUX,26504)@317
    assign leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s or leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26503_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = leftShiftStage1_uid26500_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26503_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28(BITSELECT,9913)@317
    assign i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28_b = leftShiftStage2_uid26505_i_shl_i_i_i_i_i_i_122_c_compmm_m0_shift_x_q[28:13];

    // redist355_i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28_b_1(DELAY,29483)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist355_i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_join(BITJOIN,9912)@318
    assign i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_join_q = {redist355_i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg11(REG,13306)@311 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg11_q <= $unsigned(redist881_sync_together4364_aunroll_x_in_i_valid_243_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_67264_c_compmm_m12(BLACKBOX,8759)@312
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67264_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_67264_c_compmm_m12 (
        .in_intel_reserved_ffwd_246_0(in_intel_reserved_ffwd_246_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg11_q),
        .out_dest_data_out_246_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_67264_c_compmm_m12_out_dest_data_out_246_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_offset(CONSTANT,31721)
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_offset_q = $unsigned(8'b00010001);

    // redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt(ADD,31722)
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_a = {1'b0, redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_q};
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_b = {1'b0, redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_o <= $unsigned(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_a) + $unsigned(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_b);
        end
    end
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_q = redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_o[8:0];

    // redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_inputreg0(DELAY,31717)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_inputreg0_q <= $unsigned(in_c1_eni5_245_tpl);
        end
    end

    // redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr(COUNTER,31720)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_i <= $unsigned(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_q = redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_i[7:0];

    // redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem(DUALMEM,31719)
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_ia = $unsigned(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_inputreg0_q);
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_aa = redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_wraddr_q;
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_ab = redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_aa),
        .data_a(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_ab),
        .q_b(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_q = redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_iq[15:0];

    // redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_outputreg0(DELAY,31718)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_outputreg0_q <= $unsigned(redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_mem_q);
        end
    end

    // redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt(ADD,31728)
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_a = {1'b0, redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_q};
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_b = {1'b0, redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_o <= $unsigned(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_a) + $unsigned(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_b);
        end
    end
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_q = redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_o[8:0];

    // redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_inputreg0(DELAY,31723)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_inputreg0_q <= $unsigned(in_c1_eni5_246_tpl);
        end
    end

    // redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr(COUNTER,31726)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_i <= $unsigned(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_q = redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_i[7:0];

    // redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem(DUALMEM,31725)
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_ia = $unsigned(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_inputreg0_q);
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_aa = redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_wraddr_q;
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_ab = redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_aa),
        .data_a(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_ab),
        .q_b(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_q = redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_iq[15:0];

    // redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_outputreg0(DELAY,31724)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_outputreg0_q <= $unsigned(redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_mem_q);
        end
    end

    // valid_fanout_reg12(REG,13307)@311 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg12_q <= $unsigned(redist881_sync_together4364_aunroll_x_in_i_valid_243_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_67263_c_compmm_m13(BLACKBOX,8755)@312
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67263_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_67263_c_compmm_m13 (
        .in_intel_reserved_ffwd_245_0(in_intel_reserved_ffwd_245_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg12_q),
        .out_dest_data_out_245_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_67263_c_compmm_m13_out_dest_data_out_245_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28993)@312 + 5
    // out q@318
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_67263_c_compmm_m13_out_dest_data_out_245_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_67264_c_compmm_m12_out_dest_data_out_246_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695(ADD,8971)@318
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod892_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_b = $unsigned({{5{i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_122_c_compmm_m3694_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_o[33:0];

    // rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x(MUX,23435)@318
    assign rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q or rightShiftStage0Idx1_uid23434_dupName_489_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q;
            1'b1 : rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23434_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x(MUX,23440)@318
    assign rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23439_dupName_489_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23436_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23439_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x(MUX,23445)@318
    assign rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23444_dupName_489_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23441_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23444_dupName_489_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3696_vt_select_20(BITSELECT,12422)@318
    assign i_unnamed_c_compmm_m3696_vt_select_20_b = rightShiftStage2_uid23446_dupName_489_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3696_vt_join(BITJOIN,12421)@318
    assign i_unnamed_c_compmm_m3696_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3696_vt_select_20_b};

    // i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x(BITSELECT,3729)@318
    assign i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x_b = i_unnamed_c_compmm_m3696_vt_join_q[15:0];

    // redist989_i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x_b_1(DELAY,30117)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist989_i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23455_dupName_490_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23454)@318
    assign rightShiftStage1Idx1Rng8_uid23455_dupName_490_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23457_dupName_490_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23456)@318
    assign rightShiftStage1Idx1_uid23457_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23455_dupName_490_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23450_dupName_490_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23449)@318
    assign rightShiftStage0Idx1Rng4_uid23450_dupName_490_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q[33:4];

    // rightShiftStage0Idx1_uid23452_dupName_490_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23451)@318
    assign rightShiftStage0Idx1_uid23452_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23450_dupName_490_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x(MUX,23453)@318
    assign rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q or rightShiftStage0Idx1_uid23452_dupName_490_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_122_i_c_compmm_m3695_q;
            1'b1 : rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23452_dupName_490_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x(MUX,23458)@318
    assign rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23457_dupName_490_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23454_dupName_490_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23457_dupName_490_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3698_vt_select_21(BITSELECT,12425)@318
    assign i_unnamed_c_compmm_m3698_vt_select_21_b = rightShiftStage1_uid23459_dupName_490_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3698_vt_join(BITJOIN,12424)@318
    assign i_unnamed_c_compmm_m3698_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3698_vt_select_21_b};

    // i_unnamed_c_compmm_m3699_sel_x(BITSELECT,6204)@318
    assign i_unnamed_c_compmm_m3699_sel_x_b = i_unnamed_c_compmm_m3698_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3700_BitSelect_for_a(BITSELECT,28760)@318
    assign i_unnamed_c_compmm_m3700_BitSelect_for_a_b = i_unnamed_c_compmm_m3699_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3700_join(BITJOIN,28761)@318
    assign i_unnamed_c_compmm_m3700_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3700_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3700_vt_select_0(BITSELECT,12430)@318
    assign i_unnamed_c_compmm_m3700_vt_select_0_b = i_unnamed_c_compmm_m3700_join_q[0:0];

    // redist57_i_unnamed_c_compmm_m3700_vt_select_0_b_1(DELAY,29185)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist57_i_unnamed_c_compmm_m3700_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3700_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3700_vt_join(BITJOIN,12429)@319
    assign i_unnamed_c_compmm_m3700_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist57_i_unnamed_c_compmm_m3700_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_122_c_compmm_m3701(ADD,7184)@319
    assign i_add_i_i_i_i_i_i_122_c_compmm_m3701_a = {1'b0, i_unnamed_c_compmm_m3700_vt_join_q};
    assign i_add_i_i_i_i_i_i_122_c_compmm_m3701_b = {1'b0, redist989_i_conv_i_i_i_i_i_122_c_compmm_m3697_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_122_c_compmm_m3701_o = $unsigned(i_add_i_i_i_i_i_i_122_c_compmm_m3701_a) + $unsigned(i_add_i_i_i_i_i_i_122_c_compmm_m3701_b);
    assign i_add_i_i_i_i_i_i_122_c_compmm_m3701_q = i_add_i_i_i_i_i_i_122_c_compmm_m3701_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_122_c_compmm_m3701_sel_x(BITSELECT,2198)@319
    assign bgTrunc_i_add_i_i_i_i_i_i_122_c_compmm_m3701_sel_x_b = i_add_i_i_i_i_i_i_122_c_compmm_m3701_q[15:0];

    // i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_sel_x(BITSELECT,3858)@319
    assign i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_122_c_compmm_m3701_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_select_15(BITSELECT,8159)@319
    assign i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_select_15_b = i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_join(BITJOIN,8158)@319
    assign i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_select_15_b};

    // leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(MUX,26512)@319
    assign leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_join_q or leftShiftStage0Idx1_uid26511_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_123_c_compmm_m3721_vt_join_q;
            1'b1 : leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26511_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(MUX,26517)@319
    assign leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s or leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26516_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = leftShiftStage0_uid26513_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26516_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x(MUX,26522)@319
    assign leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s or leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26521_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = leftShiftStage1_uid26518_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26521_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28(BITSELECT,9916)@319
    assign i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28_b = leftShiftStage2_uid26523_i_shl_i_i_i_i_i_i_123_c_compmm_m0_shift_x_q[28:13];

    // redist354_i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28_b_1(DELAY,29482)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist354_i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_join(BITJOIN,9915)@320
    assign i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_join_q = {redist354_i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg9(REG,13304)@313 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg9_q <= $unsigned(redist882_sync_together4364_aunroll_x_in_i_valid_245_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_67266_c_compmm_m10(BLACKBOX,8767)@314
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67266_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_67266_c_compmm_m10 (
        .in_intel_reserved_ffwd_248_0(in_intel_reserved_ffwd_248_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg9_q),
        .out_dest_data_out_248_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_67266_c_compmm_m10_out_dest_data_out_248_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_offset(CONSTANT,31733)
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_offset_q = $unsigned(8'b00001111);

    // redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt(ADD,31734)
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_a = {1'b0, redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_q};
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_b = {1'b0, redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_o <= $unsigned(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_a) + $unsigned(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_b);
        end
    end
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_q = redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_o[8:0];

    // redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_inputreg0(DELAY,31729)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_inputreg0_q <= $unsigned(in_c1_eni5_247_tpl);
        end
    end

    // redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr(COUNTER,31732)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_i <= $unsigned(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_q = redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_i[7:0];

    // redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem(DUALMEM,31731)
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_ia = $unsigned(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_inputreg0_q);
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_aa = redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_wraddr_q;
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_ab = redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_aa),
        .data_a(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_ab),
        .q_b(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_q = redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_iq[15:0];

    // redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_outputreg0(DELAY,31730)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_outputreg0_q <= $unsigned(redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_mem_q);
        end
    end

    // redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt(ADD,31740)
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_a = {1'b0, redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_q};
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_b = {1'b0, redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_o <= $unsigned(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_a) + $unsigned(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_b);
        end
    end
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_q = redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_o[8:0];

    // redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_inputreg0(DELAY,31735)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_inputreg0_q <= $unsigned(in_c1_eni5_248_tpl);
        end
    end

    // redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr(COUNTER,31738)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_i <= $unsigned(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_q = redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_i[7:0];

    // redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem(DUALMEM,31737)
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_ia = $unsigned(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_inputreg0_q);
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_aa = redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_wraddr_q;
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_ab = redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_aa),
        .data_a(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_ab),
        .q_b(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_q = redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_iq[15:0];

    // redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_outputreg0(DELAY,31736)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_outputreg0_q <= $unsigned(redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_mem_q);
        end
    end

    // valid_fanout_reg10(REG,13305)@313 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg10_q <= $unsigned(redist882_sync_together4364_aunroll_x_in_i_valid_245_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_67265_c_compmm_m11(BLACKBOX,8763)@314
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67265_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_67265_c_compmm_m11 (
        .in_intel_reserved_ffwd_247_0(in_intel_reserved_ffwd_247_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg10_q),
        .out_dest_data_out_247_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_67265_c_compmm_m11_out_dest_data_out_247_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28994)@314 + 5
    // out q@320
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_67265_c_compmm_m11_out_dest_data_out_247_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_67266_c_compmm_m10_out_dest_data_out_248_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723(ADD,8972)@320
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod897_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_b = $unsigned({{5{i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_123_c_compmm_m3722_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_o[33:0];

    // rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x(MUX,23497)@320
    assign rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q or rightShiftStage0Idx1_uid23496_dupName_493_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q;
            1'b1 : rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23496_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x(MUX,23502)@320
    assign rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23501_dupName_493_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23498_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23501_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x(MUX,23507)@320
    assign rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23506_dupName_493_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23503_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23506_dupName_493_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3724_vt_select_20(BITSELECT,12444)@320
    assign i_unnamed_c_compmm_m3724_vt_select_20_b = rightShiftStage2_uid23508_dupName_493_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3724_vt_join(BITJOIN,12443)@320
    assign i_unnamed_c_compmm_m3724_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3724_vt_select_20_b};

    // i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x(BITSELECT,3730)@320
    assign i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x_b = i_unnamed_c_compmm_m3724_vt_join_q[15:0];

    // redist988_i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x_b_1(DELAY,30116)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist988_i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23517_dupName_494_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23516)@320
    assign rightShiftStage1Idx1Rng8_uid23517_dupName_494_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23519_dupName_494_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23518)@320
    assign rightShiftStage1Idx1_uid23519_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23517_dupName_494_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23512_dupName_494_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23511)@320
    assign rightShiftStage0Idx1Rng4_uid23512_dupName_494_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q[33:4];

    // rightShiftStage0Idx1_uid23514_dupName_494_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23513)@320
    assign rightShiftStage0Idx1_uid23514_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23512_dupName_494_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x(MUX,23515)@320
    assign rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q or rightShiftStage0Idx1_uid23514_dupName_494_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_123_i_c_compmm_m3723_q;
            1'b1 : rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23514_dupName_494_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x(MUX,23520)@320
    assign rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23519_dupName_494_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23516_dupName_494_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23519_dupName_494_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3726_vt_select_21(BITSELECT,12447)@320
    assign i_unnamed_c_compmm_m3726_vt_select_21_b = rightShiftStage1_uid23521_dupName_494_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3726_vt_join(BITJOIN,12446)@320
    assign i_unnamed_c_compmm_m3726_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3726_vt_select_21_b};

    // i_unnamed_c_compmm_m3727_sel_x(BITSELECT,6206)@320
    assign i_unnamed_c_compmm_m3727_sel_x_b = i_unnamed_c_compmm_m3726_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3728_BitSelect_for_a(BITSELECT,28764)@320
    assign i_unnamed_c_compmm_m3728_BitSelect_for_a_b = i_unnamed_c_compmm_m3727_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3728_join(BITJOIN,28765)@320
    assign i_unnamed_c_compmm_m3728_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3728_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3728_vt_select_0(BITSELECT,12452)@320
    assign i_unnamed_c_compmm_m3728_vt_select_0_b = i_unnamed_c_compmm_m3728_join_q[0:0];

    // redist55_i_unnamed_c_compmm_m3728_vt_select_0_b_1(DELAY,29183)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist55_i_unnamed_c_compmm_m3728_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3728_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3728_vt_join(BITJOIN,12451)@321
    assign i_unnamed_c_compmm_m3728_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist55_i_unnamed_c_compmm_m3728_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_123_c_compmm_m3729(ADD,7185)@321
    assign i_add_i_i_i_i_i_i_123_c_compmm_m3729_a = {1'b0, i_unnamed_c_compmm_m3728_vt_join_q};
    assign i_add_i_i_i_i_i_i_123_c_compmm_m3729_b = {1'b0, redist988_i_conv_i_i_i_i_i_123_c_compmm_m3725_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_123_c_compmm_m3729_o = $unsigned(i_add_i_i_i_i_i_i_123_c_compmm_m3729_a) + $unsigned(i_add_i_i_i_i_i_i_123_c_compmm_m3729_b);
    assign i_add_i_i_i_i_i_i_123_c_compmm_m3729_q = i_add_i_i_i_i_i_i_123_c_compmm_m3729_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_123_c_compmm_m3729_sel_x(BITSELECT,2199)@321
    assign bgTrunc_i_add_i_i_i_i_i_i_123_c_compmm_m3729_sel_x_b = i_add_i_i_i_i_i_i_123_c_compmm_m3729_q[15:0];

    // i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_sel_x(BITSELECT,3859)@321
    assign i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_123_c_compmm_m3729_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_select_15(BITSELECT,8163)@321
    assign i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_select_15_b = i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_join(BITJOIN,8162)@321
    assign i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_select_15_b};

    // leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(MUX,26530)@321
    assign leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_join_q or leftShiftStage0Idx1_uid26529_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_124_c_compmm_m3749_vt_join_q;
            1'b1 : leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26529_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(MUX,26535)@321
    assign leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s or leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26534_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = leftShiftStage0_uid26531_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26534_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x(MUX,26540)@321
    assign leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s or leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26539_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = leftShiftStage1_uid26536_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26539_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28(BITSELECT,9919)@321
    assign i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28_b = leftShiftStage2_uid26541_i_shl_i_i_i_i_i_i_124_c_compmm_m0_shift_x_q[28:13];

    // redist353_i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28_b_1(DELAY,29481)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist353_i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_join(BITJOIN,9918)@322
    assign i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_join_q = {redist353_i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg7(REG,13302)@315 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg7_q <= $unsigned(redist883_sync_together4364_aunroll_x_in_i_valid_247_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_67268_c_compmm_m8(BLACKBOX,8775)@316
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67268_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_67268_c_compmm_m8 (
        .in_intel_reserved_ffwd_250_0(in_intel_reserved_ffwd_250_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg7_q),
        .out_dest_data_out_250_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_67268_c_compmm_m8_out_dest_data_out_250_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_offset(CONSTANT,31745)
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_offset_q = $unsigned(8'b00001101);

    // redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt(ADD,31746)
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_a = {1'b0, redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_q};
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_b = {1'b0, redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_o <= $unsigned(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_a) + $unsigned(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_b);
        end
    end
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_q = redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_o[8:0];

    // redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_inputreg0(DELAY,31741)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_inputreg0_q <= $unsigned(in_c1_eni5_249_tpl);
        end
    end

    // redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr(COUNTER,31744)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_i <= $unsigned(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_q = redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_i[7:0];

    // redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem(DUALMEM,31743)
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_ia = $unsigned(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_inputreg0_q);
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_aa = redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_wraddr_q;
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_ab = redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_aa),
        .data_a(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_ab),
        .q_b(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_q = redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_iq[15:0];

    // redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_outputreg0(DELAY,31742)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_outputreg0_q <= $unsigned(redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_mem_q);
        end
    end

    // redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt(ADD,31752)
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_a = {1'b0, redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_q};
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_b = {1'b0, redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_o <= $unsigned(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_a) + $unsigned(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_b);
        end
    end
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_q = redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_o[8:0];

    // redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_inputreg0(DELAY,31747)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_inputreg0_q <= $unsigned(in_c1_eni5_250_tpl);
        end
    end

    // redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr(COUNTER,31750)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_i <= $unsigned(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_q = redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_i[7:0];

    // redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem(DUALMEM,31749)
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_ia = $unsigned(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_inputreg0_q);
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_aa = redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_wraddr_q;
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_ab = redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_aa),
        .data_a(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_ab),
        .q_b(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_q = redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_iq[15:0];

    // redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_outputreg0(DELAY,31748)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_outputreg0_q <= $unsigned(redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_mem_q);
        end
    end

    // valid_fanout_reg8(REG,13303)@315 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg8_q <= $unsigned(redist883_sync_together4364_aunroll_x_in_i_valid_247_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_67267_c_compmm_m9(BLACKBOX,8771)@316
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67267_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_67267_c_compmm_m9 (
        .in_intel_reserved_ffwd_249_0(in_intel_reserved_ffwd_249_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg8_q),
        .out_dest_data_out_249_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_67267_c_compmm_m9_out_dest_data_out_249_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28995)@316 + 5
    // out q@322
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_67267_c_compmm_m9_out_dest_data_out_249_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_67268_c_compmm_m8_out_dest_data_out_250_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751(ADD,8973)@322
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod902_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_b = $unsigned({{5{i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_124_c_compmm_m3750_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_o[33:0];

    // rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x(MUX,23559)@322
    assign rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q or rightShiftStage0Idx1_uid23558_dupName_497_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q;
            1'b1 : rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23558_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x(MUX,23564)@322
    assign rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23563_dupName_497_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23560_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23563_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x(MUX,23569)@322
    assign rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23568_dupName_497_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23565_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23568_dupName_497_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3752_vt_select_20(BITSELECT,12469)@322
    assign i_unnamed_c_compmm_m3752_vt_select_20_b = rightShiftStage2_uid23570_dupName_497_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3752_vt_join(BITJOIN,12468)@322
    assign i_unnamed_c_compmm_m3752_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3752_vt_select_20_b};

    // i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x(BITSELECT,3731)@322
    assign i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x_b = i_unnamed_c_compmm_m3752_vt_join_q[15:0];

    // redist987_i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x_b_1(DELAY,30115)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist987_i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23579_dupName_498_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23578)@322
    assign rightShiftStage1Idx1Rng8_uid23579_dupName_498_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23581_dupName_498_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23580)@322
    assign rightShiftStage1Idx1_uid23581_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23579_dupName_498_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23574_dupName_498_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23573)@322
    assign rightShiftStage0Idx1Rng4_uid23574_dupName_498_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q[33:4];

    // rightShiftStage0Idx1_uid23576_dupName_498_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23575)@322
    assign rightShiftStage0Idx1_uid23576_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23574_dupName_498_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x(MUX,23577)@322
    assign rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q or rightShiftStage0Idx1_uid23576_dupName_498_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_124_i_c_compmm_m3751_q;
            1'b1 : rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23576_dupName_498_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x(MUX,23582)@322
    assign rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23581_dupName_498_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23578_dupName_498_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23581_dupName_498_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3754_vt_select_21(BITSELECT,12472)@322
    assign i_unnamed_c_compmm_m3754_vt_select_21_b = rightShiftStage1_uid23583_dupName_498_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3754_vt_join(BITJOIN,12471)@322
    assign i_unnamed_c_compmm_m3754_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3754_vt_select_21_b};

    // i_unnamed_c_compmm_m3755_sel_x(BITSELECT,6208)@322
    assign i_unnamed_c_compmm_m3755_sel_x_b = i_unnamed_c_compmm_m3754_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3756_BitSelect_for_a(BITSELECT,28768)@322
    assign i_unnamed_c_compmm_m3756_BitSelect_for_a_b = i_unnamed_c_compmm_m3755_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3756_join(BITJOIN,28769)@322
    assign i_unnamed_c_compmm_m3756_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3756_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3756_vt_select_0(BITSELECT,12477)@322
    assign i_unnamed_c_compmm_m3756_vt_select_0_b = i_unnamed_c_compmm_m3756_join_q[0:0];

    // redist53_i_unnamed_c_compmm_m3756_vt_select_0_b_1(DELAY,29181)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist53_i_unnamed_c_compmm_m3756_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3756_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3756_vt_join(BITJOIN,12476)@323
    assign i_unnamed_c_compmm_m3756_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist53_i_unnamed_c_compmm_m3756_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_124_c_compmm_m3757(ADD,7186)@323
    assign i_add_i_i_i_i_i_i_124_c_compmm_m3757_a = {1'b0, i_unnamed_c_compmm_m3756_vt_join_q};
    assign i_add_i_i_i_i_i_i_124_c_compmm_m3757_b = {1'b0, redist987_i_conv_i_i_i_i_i_124_c_compmm_m3753_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_124_c_compmm_m3757_o = $unsigned(i_add_i_i_i_i_i_i_124_c_compmm_m3757_a) + $unsigned(i_add_i_i_i_i_i_i_124_c_compmm_m3757_b);
    assign i_add_i_i_i_i_i_i_124_c_compmm_m3757_q = i_add_i_i_i_i_i_i_124_c_compmm_m3757_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_124_c_compmm_m3757_sel_x(BITSELECT,2200)@323
    assign bgTrunc_i_add_i_i_i_i_i_i_124_c_compmm_m3757_sel_x_b = i_add_i_i_i_i_i_i_124_c_compmm_m3757_q[15:0];

    // i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_sel_x(BITSELECT,3860)@323
    assign i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_124_c_compmm_m3757_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_select_15(BITSELECT,8167)@323
    assign i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_select_15_b = i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_join(BITJOIN,8166)@323
    assign i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_select_15_b};

    // leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(MUX,26548)@323
    assign leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_join_q or leftShiftStage0Idx1_uid26547_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_125_c_compmm_m3777_vt_join_q;
            1'b1 : leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26547_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(MUX,26553)@323
    assign leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s or leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26552_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = leftShiftStage0_uid26549_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26552_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x(MUX,26558)@323
    assign leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s or leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26557_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = leftShiftStage1_uid26554_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26557_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28(BITSELECT,9922)@323
    assign i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28_b = leftShiftStage2_uid26559_i_shl_i_i_i_i_i_i_125_c_compmm_m0_shift_x_q[28:13];

    // redist352_i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28_b_1(DELAY,29480)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist352_i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_join(BITJOIN,9921)@324
    assign i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_join_q = {redist352_i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg5(REG,13300)@317 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg5_q <= $unsigned(redist884_sync_together4364_aunroll_x_in_i_valid_249_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_67270_c_compmm_m6(BLACKBOX,8783)@318
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67270_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_67270_c_compmm_m6 (
        .in_intel_reserved_ffwd_252_0(in_intel_reserved_ffwd_252_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg5_q),
        .out_dest_data_out_252_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_67270_c_compmm_m6_out_dest_data_out_252_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_offset(CONSTANT,31757)
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_offset_q = $unsigned(8'b00001011);

    // redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt(ADD,31758)
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_a = {1'b0, redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_q};
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_b = {1'b0, redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_o <= $unsigned(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_a) + $unsigned(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_b);
        end
    end
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_q = redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_o[8:0];

    // redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_inputreg0(DELAY,31753)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_inputreg0_q <= $unsigned(in_c1_eni5_251_tpl);
        end
    end

    // redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr(COUNTER,31756)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_i <= $unsigned(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_q = redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_i[7:0];

    // redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem(DUALMEM,31755)
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_ia = $unsigned(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_inputreg0_q);
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_aa = redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_wraddr_q;
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_ab = redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_aa),
        .data_a(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_ab),
        .q_b(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_q = redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_iq[15:0];

    // redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_outputreg0(DELAY,31754)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_outputreg0_q <= $unsigned(redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_mem_q);
        end
    end

    // redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt(ADD,31764)
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_a = {1'b0, redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_q};
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_b = {1'b0, redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_o <= $unsigned(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_a) + $unsigned(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_b);
        end
    end
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_q = redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_o[8:0];

    // redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_inputreg0(DELAY,31759)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_inputreg0_q <= $unsigned(in_c1_eni5_252_tpl);
        end
    end

    // redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr(COUNTER,31762)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_i <= $unsigned(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_q = redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_i[7:0];

    // redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem(DUALMEM,31761)
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_ia = $unsigned(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_inputreg0_q);
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_aa = redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_wraddr_q;
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_ab = redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_aa),
        .data_a(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_ab),
        .q_b(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_q = redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_iq[15:0];

    // redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_outputreg0(DELAY,31760)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_outputreg0_q <= $unsigned(redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_mem_q);
        end
    end

    // valid_fanout_reg6(REG,13301)@317 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg6_q <= $unsigned(redist884_sync_together4364_aunroll_x_in_i_valid_249_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_67269_c_compmm_m7(BLACKBOX,8779)@318
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67269_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_67269_c_compmm_m7 (
        .in_intel_reserved_ffwd_251_0(in_intel_reserved_ffwd_251_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg6_q),
        .out_dest_data_out_251_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_67269_c_compmm_m7_out_dest_data_out_251_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28996)@318 + 5
    // out q@324
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_67269_c_compmm_m7_out_dest_data_out_251_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_67270_c_compmm_m6_out_dest_data_out_252_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779(ADD,8974)@324
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod907_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_b = $unsigned({{5{i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_125_c_compmm_m3778_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_o[33:0];

    // rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x(MUX,23621)@324
    assign rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q or rightShiftStage0Idx1_uid23620_dupName_501_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q;
            1'b1 : rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23620_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x(MUX,23626)@324
    assign rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23625_dupName_501_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23622_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23625_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x(MUX,23631)@324
    assign rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23630_dupName_501_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23627_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23630_dupName_501_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3780_vt_select_20(BITSELECT,12499)@324
    assign i_unnamed_c_compmm_m3780_vt_select_20_b = rightShiftStage2_uid23632_dupName_501_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3780_vt_join(BITJOIN,12498)@324
    assign i_unnamed_c_compmm_m3780_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3780_vt_select_20_b};

    // i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x(BITSELECT,3732)@324
    assign i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x_b = i_unnamed_c_compmm_m3780_vt_join_q[15:0];

    // redist986_i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x_b_1(DELAY,30114)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist986_i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23641_dupName_502_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23640)@324
    assign rightShiftStage1Idx1Rng8_uid23641_dupName_502_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23643_dupName_502_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23642)@324
    assign rightShiftStage1Idx1_uid23643_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23641_dupName_502_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23636_dupName_502_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23635)@324
    assign rightShiftStage0Idx1Rng4_uid23636_dupName_502_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q[33:4];

    // rightShiftStage0Idx1_uid23638_dupName_502_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23637)@324
    assign rightShiftStage0Idx1_uid23638_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23636_dupName_502_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x(MUX,23639)@324
    assign rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q or rightShiftStage0Idx1_uid23638_dupName_502_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_125_i_c_compmm_m3779_q;
            1'b1 : rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23638_dupName_502_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x(MUX,23644)@324
    assign rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23643_dupName_502_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23640_dupName_502_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23643_dupName_502_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3782_vt_select_21(BITSELECT,12502)@324
    assign i_unnamed_c_compmm_m3782_vt_select_21_b = rightShiftStage1_uid23645_dupName_502_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3782_vt_join(BITJOIN,12501)@324
    assign i_unnamed_c_compmm_m3782_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3782_vt_select_21_b};

    // i_unnamed_c_compmm_m3783_sel_x(BITSELECT,6211)@324
    assign i_unnamed_c_compmm_m3783_sel_x_b = i_unnamed_c_compmm_m3782_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3784_BitSelect_for_a(BITSELECT,28774)@324
    assign i_unnamed_c_compmm_m3784_BitSelect_for_a_b = i_unnamed_c_compmm_m3783_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3784_join(BITJOIN,28775)@324
    assign i_unnamed_c_compmm_m3784_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3784_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3784_vt_select_0(BITSELECT,12507)@324
    assign i_unnamed_c_compmm_m3784_vt_select_0_b = i_unnamed_c_compmm_m3784_join_q[0:0];

    // redist50_i_unnamed_c_compmm_m3784_vt_select_0_b_1(DELAY,29178)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist50_i_unnamed_c_compmm_m3784_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3784_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3784_vt_join(BITJOIN,12506)@325
    assign i_unnamed_c_compmm_m3784_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist50_i_unnamed_c_compmm_m3784_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_125_c_compmm_m3785(ADD,7187)@325
    assign i_add_i_i_i_i_i_i_125_c_compmm_m3785_a = {1'b0, i_unnamed_c_compmm_m3784_vt_join_q};
    assign i_add_i_i_i_i_i_i_125_c_compmm_m3785_b = {1'b0, redist986_i_conv_i_i_i_i_i_125_c_compmm_m3781_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_125_c_compmm_m3785_o = $unsigned(i_add_i_i_i_i_i_i_125_c_compmm_m3785_a) + $unsigned(i_add_i_i_i_i_i_i_125_c_compmm_m3785_b);
    assign i_add_i_i_i_i_i_i_125_c_compmm_m3785_q = i_add_i_i_i_i_i_i_125_c_compmm_m3785_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_125_c_compmm_m3785_sel_x(BITSELECT,2201)@325
    assign bgTrunc_i_add_i_i_i_i_i_i_125_c_compmm_m3785_sel_x_b = i_add_i_i_i_i_i_i_125_c_compmm_m3785_q[15:0];

    // i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_sel_x(BITSELECT,3861)@325
    assign i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_125_c_compmm_m3785_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_select_15(BITSELECT,8171)@325
    assign i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_select_15_b = i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_join(BITJOIN,8170)@325
    assign i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_select_15_b};

    // leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(MUX,26566)@325
    assign leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_join_q or leftShiftStage0Idx1_uid26565_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_126_c_compmm_m3805_vt_join_q;
            1'b1 : leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26565_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(MUX,26571)@325
    assign leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s or leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26570_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = leftShiftStage0_uid26567_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26570_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x(MUX,26576)@325
    assign leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s or leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26575_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = leftShiftStage1_uid26572_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26575_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28(BITSELECT,9925)@325
    assign i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28_b = leftShiftStage2_uid26577_i_shl_i_i_i_i_i_i_126_c_compmm_m0_shift_x_q[28:13];

    // redist351_i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28_b_1(DELAY,29479)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist351_i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_join(BITJOIN,9924)@326
    assign i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_join_q = {redist351_i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg3(REG,13298)@319 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg3_q <= $unsigned(redist885_sync_together4364_aunroll_x_in_i_valid_251_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_67272_c_compmm_m4(BLACKBOX,8795)@320
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67272_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_67272_c_compmm_m4 (
        .in_intel_reserved_ffwd_254_0(in_intel_reserved_ffwd_254_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg3_q),
        .out_dest_data_out_254_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_67272_c_compmm_m4_out_dest_data_out_254_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_offset(CONSTANT,31769)
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_offset_q = $unsigned(8'b00001001);

    // redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt(ADD,31770)
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_a = {1'b0, redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_q};
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_b = {1'b0, redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_o <= $unsigned(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_a) + $unsigned(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_b);
        end
    end
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_q = redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_o[8:0];

    // redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_inputreg0(DELAY,31765)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_inputreg0_q <= $unsigned(in_c1_eni5_253_tpl);
        end
    end

    // redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr(COUNTER,31768)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_i <= $unsigned(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_q = redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_i[7:0];

    // redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem(DUALMEM,31767)
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_ia = $unsigned(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_inputreg0_q);
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_aa = redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_wraddr_q;
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_ab = redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_aa),
        .data_a(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_ab),
        .q_b(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_q = redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_iq[15:0];

    // redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_outputreg0(DELAY,31766)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_outputreg0_q <= $unsigned(redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_mem_q);
        end
    end

    // redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt(ADD,31776)
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_a = {1'b0, redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_q};
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_b = {1'b0, redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_o <= $unsigned(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_a) + $unsigned(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_b);
        end
    end
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_q = redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_o[8:0];

    // redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_inputreg0(DELAY,31771)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_inputreg0_q <= $unsigned(in_c1_eni5_254_tpl);
        end
    end

    // redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr(COUNTER,31774)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_i <= $unsigned(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_q = redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_i[7:0];

    // redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem(DUALMEM,31773)
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_ia = $unsigned(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_inputreg0_q);
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_aa = redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_wraddr_q;
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_ab = redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_aa),
        .data_a(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_ab),
        .q_b(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_q = redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_iq[15:0];

    // redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_outputreg0(DELAY,31772)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_outputreg0_q <= $unsigned(redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_mem_q);
        end
    end

    // valid_fanout_reg4(REG,13299)@319 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg4_q <= $unsigned(redist885_sync_together4364_aunroll_x_in_i_valid_251_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_67271_c_compmm_m5(BLACKBOX,8791)@320
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67271_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_67271_c_compmm_m5 (
        .in_intel_reserved_ffwd_253_0(in_intel_reserved_ffwd_253_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg4_q),
        .out_dest_data_out_253_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_67271_c_compmm_m5_out_dest_data_out_253_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28997)@320 + 5
    // out q@326
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_67271_c_compmm_m5_out_dest_data_out_253_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_67272_c_compmm_m4_out_dest_data_out_254_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807(ADD,8975)@326
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod912_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_b = $unsigned({{5{i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_126_c_compmm_m3806_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_o[33:0];

    // rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x(MUX,23683)@326
    assign rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q or rightShiftStage0Idx1_uid23682_dupName_505_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q;
            1'b1 : rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23682_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x(MUX,23688)@326
    assign rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23687_dupName_505_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23684_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23687_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x(MUX,23693)@326
    assign rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23692_dupName_505_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23689_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23692_dupName_505_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3808_vt_select_20(BITSELECT,12521)@326
    assign i_unnamed_c_compmm_m3808_vt_select_20_b = rightShiftStage2_uid23694_dupName_505_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3808_vt_join(BITJOIN,12520)@326
    assign i_unnamed_c_compmm_m3808_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3808_vt_select_20_b};

    // i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x(BITSELECT,3733)@326
    assign i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x_b = i_unnamed_c_compmm_m3808_vt_join_q[15:0];

    // redist985_i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x_b_1(DELAY,30113)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist985_i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23703_dupName_506_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23702)@326
    assign rightShiftStage1Idx1Rng8_uid23703_dupName_506_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23705_dupName_506_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23704)@326
    assign rightShiftStage1Idx1_uid23705_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23703_dupName_506_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23698_dupName_506_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23697)@326
    assign rightShiftStage0Idx1Rng4_uid23698_dupName_506_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q[33:4];

    // rightShiftStage0Idx1_uid23700_dupName_506_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23699)@326
    assign rightShiftStage0Idx1_uid23700_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23698_dupName_506_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x(MUX,23701)@326
    assign rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q or rightShiftStage0Idx1_uid23700_dupName_506_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_126_i_c_compmm_m3807_q;
            1'b1 : rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23700_dupName_506_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x(MUX,23706)@326
    assign rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23705_dupName_506_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23702_dupName_506_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23705_dupName_506_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3810_vt_select_21(BITSELECT,12524)@326
    assign i_unnamed_c_compmm_m3810_vt_select_21_b = rightShiftStage1_uid23707_dupName_506_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3810_vt_join(BITJOIN,12523)@326
    assign i_unnamed_c_compmm_m3810_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3810_vt_select_21_b};

    // i_unnamed_c_compmm_m3811_sel_x(BITSELECT,6213)@326
    assign i_unnamed_c_compmm_m3811_sel_x_b = i_unnamed_c_compmm_m3810_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3812_BitSelect_for_a(BITSELECT,28778)@326
    assign i_unnamed_c_compmm_m3812_BitSelect_for_a_b = i_unnamed_c_compmm_m3811_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3812_join(BITJOIN,28779)@326
    assign i_unnamed_c_compmm_m3812_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3812_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3812_vt_select_0(BITSELECT,12529)@326
    assign i_unnamed_c_compmm_m3812_vt_select_0_b = i_unnamed_c_compmm_m3812_join_q[0:0];

    // redist48_i_unnamed_c_compmm_m3812_vt_select_0_b_1(DELAY,29176)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist48_i_unnamed_c_compmm_m3812_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3812_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3812_vt_join(BITJOIN,12528)@327
    assign i_unnamed_c_compmm_m3812_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist48_i_unnamed_c_compmm_m3812_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_126_c_compmm_m3813(ADD,7188)@327
    assign i_add_i_i_i_i_i_i_126_c_compmm_m3813_a = {1'b0, i_unnamed_c_compmm_m3812_vt_join_q};
    assign i_add_i_i_i_i_i_i_126_c_compmm_m3813_b = {1'b0, redist985_i_conv_i_i_i_i_i_126_c_compmm_m3809_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_126_c_compmm_m3813_o = $unsigned(i_add_i_i_i_i_i_i_126_c_compmm_m3813_a) + $unsigned(i_add_i_i_i_i_i_i_126_c_compmm_m3813_b);
    assign i_add_i_i_i_i_i_i_126_c_compmm_m3813_q = i_add_i_i_i_i_i_i_126_c_compmm_m3813_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_126_c_compmm_m3813_sel_x(BITSELECT,2202)@327
    assign bgTrunc_i_add_i_i_i_i_i_i_126_c_compmm_m3813_sel_x_b = i_add_i_i_i_i_i_i_126_c_compmm_m3813_q[15:0];

    // i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_sel_x(BITSELECT,3862)@327
    assign i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i_i_126_c_compmm_m3813_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_select_15(BITSELECT,8175)@327
    assign i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_select_15_b = i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_sel_x_b[15:0];

    // i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_join(BITJOIN,8174)@327
    assign i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_select_15_b};

    // leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(MUX,26584)@327
    assign leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_join_q or leftShiftStage0Idx1_uid26583_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i_i246_127_c_compmm_m3833_vt_join_q;
            1'b1 : leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26583_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(MUX,26589)@327
    assign leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s or leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26588_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = leftShiftStage0_uid26585_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26588_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x(MUX,26594)@327
    assign leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s or leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26593_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = leftShiftStage1_uid26590_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26593_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28(BITSELECT,9928)@327
    assign i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28_b = leftShiftStage2_uid26595_i_shl_i_i_i_i_i_i_127_c_compmm_m0_shift_x_q[28:13];

    // redist350_i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28_b_1(DELAY,29478)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist350_i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_join(BITJOIN,9927)@328
    assign i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_join_q = {redist350_i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // valid_fanout_reg1(REG,13296)@321 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg1_q <= $unsigned(redist886_sync_together4364_aunroll_x_in_i_valid_253_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_67274_c_compmm_m2(BLACKBOX,8803)@322
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67274_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_67274_c_compmm_m2 (
        .in_intel_reserved_ffwd_256_0(in_intel_reserved_ffwd_256_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg1_q),
        .out_dest_data_out_256_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_67274_c_compmm_m2_out_dest_data_out_256_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_offset(CONSTANT,31781)
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_offset_q = $unsigned(8'b00000111);

    // redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt(ADD,31782)
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_a = {1'b0, redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_q};
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_b = {1'b0, redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_o <= $unsigned(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_a) + $unsigned(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_b);
        end
    end
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_q = redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_o[8:0];

    // redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_inputreg0(DELAY,31777)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_inputreg0_q <= $unsigned(in_c1_eni5_255_tpl);
        end
    end

    // redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr(COUNTER,31780)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_i <= $unsigned(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_q = redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_i[7:0];

    // redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem(DUALMEM,31779)
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_ia = $unsigned(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_inputreg0_q);
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_aa = redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_wraddr_q;
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_ab = redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_aa),
        .data_a(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_ab),
        .q_b(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_q = redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_iq[15:0];

    // redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_outputreg0(DELAY,31778)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_outputreg0_q <= $unsigned(redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_mem_q);
        end
    end

    // redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt(ADD,31788)
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_a = {1'b0, redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_q};
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_b = {1'b0, redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_o <= $unsigned(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_a) + $unsigned(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_b);
        end
    end
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_q = redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_o[8:0];

    // redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_inputreg0(DELAY,31783)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_inputreg0_q <= $unsigned(in_c1_eni5_256_tpl);
        end
    end

    // redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr(COUNTER,31786)
    // low=0, high=255, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_i <= $unsigned(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_i) + $unsigned(8'd1);
        end
    end
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_q = redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_i[7:0];

    // redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem(DUALMEM,31785)
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_ia = $unsigned(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_inputreg0_q);
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_aa = redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_wraddr_q;
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_ab = redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_rdcnt_q[7:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(16),
        .widthad_a(8),
        .numwords_a(256),
        .width_b(16),
        .widthad_b(8),
        .numwords_b(256),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_aa),
        .data_a(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_ab),
        .q_b(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_q = redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_iq[15:0];

    // redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_outputreg0(DELAY,31784)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_outputreg0_q <= $unsigned(redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_mem_q);
        end
    end

    // valid_fanout_reg2(REG,13297)@321 + 1
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            valid_fanout_reg2_q <= $unsigned(redist886_sync_together4364_aunroll_x_in_i_valid_253_q);
        end
    end

    // i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_67273_c_compmm_m3(BLACKBOX,8799)@322
    c_compMM_m_i_llvm_fpga_ffwd_dest_i16_mem0000ue_67273_c_compmm_m0 thei_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_67273_c_compmm_m3 (
        .in_intel_reserved_ffwd_255_0(in_intel_reserved_ffwd_255_0),
        .in_stall_in(GND_q),
        .in_valid_in(valid_fanout_reg2_q),
        .out_dest_data_out_255_0(i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_67273_c_compmm_m3_out_dest_data_out_255_0),
        .out_stall_out(),
        .out_valid_out(),
        .clock(clock),
        .resetn(resetn)
    );

    // i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma(CHAINMULTADD,28998)@322 + 5
    // out q@328
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2 = i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_67273_c_compmm_m3_out_dest_data_out_255_0;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1] <= redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0] <= redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_outputreg0_q;
            i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_67274_c_compmm_m2_out_dest_data_out_256_0;
        end
    end

    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[0]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ah[1]);
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1 = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ch[1]);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena2, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena1, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .ay(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a1),
        .by(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_a0),
        .ax(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c1),
        .bx(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_c0),
        .resulta(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .negate(),
        .sub(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_delay ( .xin(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_s0), .xout(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q = $unsigned(i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835(ADD,8976)@328
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_a = $unsigned({{1{i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q[32]}}, i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_0_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vadd_vunroll_x_i_llvm_fpga_dot_product_i33_i33_v2i16_v2i16_dot_prod917_c_compmm_m0_dspb_native_dot_product_vmul_1_x_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_b = $unsigned({{5{i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_join_q[28]}}, i_shl_i_i_i_i_i_i_127_c_compmm_m3834_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_o[33:0];

    // rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x(MUX,23745)@328
    assign rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q or rightShiftStage0Idx1_uid23744_dupName_509_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q;
            1'b1 : rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23744_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x(MUX,23750)@328
    assign rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23749_dupName_509_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23746_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23749_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x(MUX,23755)@328
    assign rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23754_dupName_509_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23751_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23754_dupName_509_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3836_vt_select_20(BITSELECT,12543)@328
    assign i_unnamed_c_compmm_m3836_vt_select_20_b = rightShiftStage2_uid23756_dupName_509_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3836_vt_join(BITJOIN,12542)@328
    assign i_unnamed_c_compmm_m3836_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3836_vt_select_20_b};

    // i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x(BITSELECT,3734)@328
    assign i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x_b = i_unnamed_c_compmm_m3836_vt_join_q[15:0];

    // redist984_i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x_b_1(DELAY,30112)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist984_i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23765_dupName_510_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23764)@328
    assign rightShiftStage1Idx1Rng8_uid23765_dupName_510_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23767_dupName_510_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23766)@328
    assign rightShiftStage1Idx1_uid23767_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23765_dupName_510_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23760_dupName_510_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23759)@328
    assign rightShiftStage0Idx1Rng4_uid23760_dupName_510_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q[33:4];

    // rightShiftStage0Idx1_uid23762_dupName_510_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23761)@328
    assign rightShiftStage0Idx1_uid23762_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23760_dupName_510_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x(MUX,23763)@328
    assign rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q or rightShiftStage0Idx1_uid23762_dupName_510_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i_i_127_i_c_compmm_m3835_q;
            1'b1 : rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23762_dupName_510_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x(MUX,23768)@328
    assign rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23767_dupName_510_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23764_dupName_510_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23767_dupName_510_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3838_vt_select_21(BITSELECT,12546)@328
    assign i_unnamed_c_compmm_m3838_vt_select_21_b = rightShiftStage1_uid23769_dupName_510_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3838_vt_join(BITJOIN,12545)@328
    assign i_unnamed_c_compmm_m3838_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3838_vt_select_21_b};

    // i_unnamed_c_compmm_m3839_sel_x(BITSELECT,6215)@328
    assign i_unnamed_c_compmm_m3839_sel_x_b = i_unnamed_c_compmm_m3838_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3840_BitSelect_for_a(BITSELECT,28782)@328
    assign i_unnamed_c_compmm_m3840_BitSelect_for_a_b = i_unnamed_c_compmm_m3839_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3840_join(BITJOIN,28783)@328
    assign i_unnamed_c_compmm_m3840_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3840_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3840_vt_select_0(BITSELECT,12551)@328
    assign i_unnamed_c_compmm_m3840_vt_select_0_b = i_unnamed_c_compmm_m3840_join_q[0:0];

    // redist46_i_unnamed_c_compmm_m3840_vt_select_0_b_1(DELAY,29174)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist46_i_unnamed_c_compmm_m3840_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3840_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3840_vt_join(BITJOIN,12550)@329
    assign i_unnamed_c_compmm_m3840_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist46_i_unnamed_c_compmm_m3840_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i_i_127_c_compmm_m3841(ADD,7189)@329
    assign i_add_i_i_i_i_i_i_127_c_compmm_m3841_a = {1'b0, i_unnamed_c_compmm_m3840_vt_join_q};
    assign i_add_i_i_i_i_i_i_127_c_compmm_m3841_b = {1'b0, redist984_i_conv_i_i_i_i_i_127_c_compmm_m3837_sel_x_b_1_q};
    assign i_add_i_i_i_i_i_i_127_c_compmm_m3841_o = $unsigned(i_add_i_i_i_i_i_i_127_c_compmm_m3841_a) + $unsigned(i_add_i_i_i_i_i_i_127_c_compmm_m3841_b);
    assign i_add_i_i_i_i_i_i_127_c_compmm_m3841_q = i_add_i_i_i_i_i_i_127_c_compmm_m3841_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i_i_127_c_compmm_m3841_sel_x(BITSELECT,2203)@329
    assign bgTrunc_i_add_i_i_i_i_i_i_127_c_compmm_m3841_sel_x_b = i_add_i_i_i_i_i_i_127_c_compmm_m3841_q[15:0];

    // rightShiftStage2Idx1Rng8_uid23721_dupName_507_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23720)@328
    assign rightShiftStage2Idx1Rng8_uid23721_dupName_507_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23723_dupName_507_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23722)@328
    assign rightShiftStage2Idx1_uid23723_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23721_dupName_507_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23716_dupName_507_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23715)@328
    assign rightShiftStage1Idx1Rng4_uid23716_dupName_507_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23718_dupName_507_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23717)@328
    assign rightShiftStage1Idx1_uid23718_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23716_dupName_507_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23711_dupName_507_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23710)@328
    assign rightShiftStage0Idx1Rng1_uid23711_dupName_507_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q[33:1];

    // rightShiftStage0Idx1_uid23713_dupName_507_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23712)@328
    assign rightShiftStage0Idx1_uid23713_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23711_dupName_507_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24306_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(BITSELECT,24305)@327
    assign leftShiftStage2Idx1Rng8_uid24306_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in = leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24306_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24306_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24307_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(BITJOIN,24306)@327
    assign leftShiftStage2Idx1_uid24307_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24306_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24301_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(BITSELECT,24300)@327
    assign leftShiftStage1Idx1Rng4_uid24301_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in = leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24301_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24301_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24302_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(BITJOIN,24301)@327
    assign leftShiftStage1Idx1_uid24302_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24301_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24296_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(BITSELECT,24295)@327
    assign leftShiftStage0Idx1Rng1_uid24296_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24296_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24296_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24297_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(BITJOIN,24296)@327
    assign leftShiftStage0Idx1_uid24297_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24296_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23659_dupName_503_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23658)@326
    assign rightShiftStage2Idx1Rng8_uid23659_dupName_503_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23661_dupName_503_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23660)@326
    assign rightShiftStage2Idx1_uid23661_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23659_dupName_503_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23654_dupName_503_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23653)@326
    assign rightShiftStage1Idx1Rng4_uid23654_dupName_503_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23656_dupName_503_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23655)@326
    assign rightShiftStage1Idx1_uid23656_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23654_dupName_503_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23649_dupName_503_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23648)@326
    assign rightShiftStage0Idx1Rng1_uid23649_dupName_503_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q[33:1];

    // rightShiftStage0Idx1_uid23651_dupName_503_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23650)@326
    assign rightShiftStage0Idx1_uid23651_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23649_dupName_503_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24288_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(BITSELECT,24287)@325
    assign leftShiftStage2Idx1Rng8_uid24288_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in = leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24288_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24288_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24289_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(BITJOIN,24288)@325
    assign leftShiftStage2Idx1_uid24289_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24288_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24283_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(BITSELECT,24282)@325
    assign leftShiftStage1Idx1Rng4_uid24283_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in = leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24283_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24283_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24284_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(BITJOIN,24283)@325
    assign leftShiftStage1Idx1_uid24284_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24283_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24278_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(BITSELECT,24277)@325
    assign leftShiftStage0Idx1Rng1_uid24278_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24278_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24278_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24279_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(BITJOIN,24278)@325
    assign leftShiftStage0Idx1_uid24279_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24278_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23597_dupName_499_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23596)@324
    assign rightShiftStage2Idx1Rng8_uid23597_dupName_499_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23599_dupName_499_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23598)@324
    assign rightShiftStage2Idx1_uid23599_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23597_dupName_499_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23592_dupName_499_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23591)@324
    assign rightShiftStage1Idx1Rng4_uid23592_dupName_499_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23594_dupName_499_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23593)@324
    assign rightShiftStage1Idx1_uid23594_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23592_dupName_499_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23587_dupName_499_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23586)@324
    assign rightShiftStage0Idx1Rng1_uid23587_dupName_499_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q[33:1];

    // rightShiftStage0Idx1_uid23589_dupName_499_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23588)@324
    assign rightShiftStage0Idx1_uid23589_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23587_dupName_499_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24270_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(BITSELECT,24269)@323
    assign leftShiftStage2Idx1Rng8_uid24270_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in = leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24270_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24270_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24271_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(BITJOIN,24270)@323
    assign leftShiftStage2Idx1_uid24271_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24270_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24265_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(BITSELECT,24264)@323
    assign leftShiftStage1Idx1Rng4_uid24265_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in = leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24265_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24265_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24266_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(BITJOIN,24265)@323
    assign leftShiftStage1Idx1_uid24266_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24265_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24260_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(BITSELECT,24259)@323
    assign leftShiftStage0Idx1Rng1_uid24260_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24260_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24260_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24261_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(BITJOIN,24260)@323
    assign leftShiftStage0Idx1_uid24261_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24260_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23535_dupName_495_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23534)@322
    assign rightShiftStage2Idx1Rng8_uid23535_dupName_495_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23537_dupName_495_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23536)@322
    assign rightShiftStage2Idx1_uid23537_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23535_dupName_495_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23530_dupName_495_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23529)@322
    assign rightShiftStage1Idx1Rng4_uid23530_dupName_495_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23532_dupName_495_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23531)@322
    assign rightShiftStage1Idx1_uid23532_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23530_dupName_495_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23525_dupName_495_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23524)@322
    assign rightShiftStage0Idx1Rng1_uid23525_dupName_495_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q[33:1];

    // rightShiftStage0Idx1_uid23527_dupName_495_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23526)@322
    assign rightShiftStage0Idx1_uid23527_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23525_dupName_495_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24252_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(BITSELECT,24251)@321
    assign leftShiftStage2Idx1Rng8_uid24252_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in = leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24252_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24252_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24253_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(BITJOIN,24252)@321
    assign leftShiftStage2Idx1_uid24253_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24252_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24247_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(BITSELECT,24246)@321
    assign leftShiftStage1Idx1Rng4_uid24247_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in = leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24247_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24247_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24248_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(BITJOIN,24247)@321
    assign leftShiftStage1Idx1_uid24248_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24247_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24242_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(BITSELECT,24241)@321
    assign leftShiftStage0Idx1Rng1_uid24242_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24242_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24242_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24243_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(BITJOIN,24242)@321
    assign leftShiftStage0Idx1_uid24243_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24242_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23473_dupName_491_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23472)@320
    assign rightShiftStage2Idx1Rng8_uid23473_dupName_491_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23475_dupName_491_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23474)@320
    assign rightShiftStage2Idx1_uid23475_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23473_dupName_491_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23468_dupName_491_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23467)@320
    assign rightShiftStage1Idx1Rng4_uid23468_dupName_491_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23470_dupName_491_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23469)@320
    assign rightShiftStage1Idx1_uid23470_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23468_dupName_491_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23463_dupName_491_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23462)@320
    assign rightShiftStage0Idx1Rng1_uid23463_dupName_491_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q[33:1];

    // rightShiftStage0Idx1_uid23465_dupName_491_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23464)@320
    assign rightShiftStage0Idx1_uid23465_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23463_dupName_491_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24234_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(BITSELECT,24233)@319
    assign leftShiftStage2Idx1Rng8_uid24234_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in = leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24234_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24234_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24235_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(BITJOIN,24234)@319
    assign leftShiftStage2Idx1_uid24235_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24234_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24229_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(BITSELECT,24228)@319
    assign leftShiftStage1Idx1Rng4_uid24229_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in = leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24229_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24229_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24230_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(BITJOIN,24229)@319
    assign leftShiftStage1Idx1_uid24230_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24229_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24224_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(BITSELECT,24223)@319
    assign leftShiftStage0Idx1Rng1_uid24224_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24224_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24224_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24225_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(BITJOIN,24224)@319
    assign leftShiftStage0Idx1_uid24225_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24224_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23411_dupName_487_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23410)@318
    assign rightShiftStage2Idx1Rng8_uid23411_dupName_487_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23413_dupName_487_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23412)@318
    assign rightShiftStage2Idx1_uid23413_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23411_dupName_487_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23406_dupName_487_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23405)@318
    assign rightShiftStage1Idx1Rng4_uid23406_dupName_487_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23408_dupName_487_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23407)@318
    assign rightShiftStage1Idx1_uid23408_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23406_dupName_487_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23401_dupName_487_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23400)@318
    assign rightShiftStage0Idx1Rng1_uid23401_dupName_487_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q[33:1];

    // rightShiftStage0Idx1_uid23403_dupName_487_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23402)@318
    assign rightShiftStage0Idx1_uid23403_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23401_dupName_487_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24216_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(BITSELECT,24215)@317
    assign leftShiftStage2Idx1Rng8_uid24216_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in = leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24216_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24216_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24217_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(BITJOIN,24216)@317
    assign leftShiftStage2Idx1_uid24217_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24216_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24211_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(BITSELECT,24210)@317
    assign leftShiftStage1Idx1Rng4_uid24211_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in = leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24211_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24211_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24212_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(BITJOIN,24211)@317
    assign leftShiftStage1Idx1_uid24212_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24211_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24206_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(BITSELECT,24205)@317
    assign leftShiftStage0Idx1Rng1_uid24206_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24206_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24206_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24207_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(BITJOIN,24206)@317
    assign leftShiftStage0Idx1_uid24207_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24206_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23349_dupName_483_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23348)@316
    assign rightShiftStage2Idx1Rng8_uid23349_dupName_483_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23351_dupName_483_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23350)@316
    assign rightShiftStage2Idx1_uid23351_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23349_dupName_483_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23344_dupName_483_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23343)@316
    assign rightShiftStage1Idx1Rng4_uid23344_dupName_483_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23346_dupName_483_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23345)@316
    assign rightShiftStage1Idx1_uid23346_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23344_dupName_483_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23339_dupName_483_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23338)@316
    assign rightShiftStage0Idx1Rng1_uid23339_dupName_483_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q[33:1];

    // rightShiftStage0Idx1_uid23341_dupName_483_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23340)@316
    assign rightShiftStage0Idx1_uid23341_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23339_dupName_483_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24198_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(BITSELECT,24197)@315
    assign leftShiftStage2Idx1Rng8_uid24198_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in = leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24198_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24198_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24199_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(BITJOIN,24198)@315
    assign leftShiftStage2Idx1_uid24199_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24198_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24193_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(BITSELECT,24192)@315
    assign leftShiftStage1Idx1Rng4_uid24193_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in = leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24193_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24193_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24194_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(BITJOIN,24193)@315
    assign leftShiftStage1Idx1_uid24194_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24193_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24188_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(BITSELECT,24187)@315
    assign leftShiftStage0Idx1Rng1_uid24188_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24188_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24188_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24189_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(BITJOIN,24188)@315
    assign leftShiftStage0Idx1_uid24189_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24188_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23287_dupName_479_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23286)@314
    assign rightShiftStage2Idx1Rng8_uid23287_dupName_479_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23289_dupName_479_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23288)@314
    assign rightShiftStage2Idx1_uid23289_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23287_dupName_479_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23282_dupName_479_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23281)@314
    assign rightShiftStage1Idx1Rng4_uid23282_dupName_479_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23284_dupName_479_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23283)@314
    assign rightShiftStage1Idx1_uid23284_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23282_dupName_479_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23277_dupName_479_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23276)@314
    assign rightShiftStage0Idx1Rng1_uid23277_dupName_479_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q[33:1];

    // rightShiftStage0Idx1_uid23279_dupName_479_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23278)@314
    assign rightShiftStage0Idx1_uid23279_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23277_dupName_479_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24180_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(BITSELECT,24179)@313
    assign leftShiftStage2Idx1Rng8_uid24180_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in = leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24180_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24180_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24181_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(BITJOIN,24180)@313
    assign leftShiftStage2Idx1_uid24181_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24180_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24175_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(BITSELECT,24174)@313
    assign leftShiftStage1Idx1Rng4_uid24175_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in = leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24175_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24175_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24176_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(BITJOIN,24175)@313
    assign leftShiftStage1Idx1_uid24176_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24175_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24170_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(BITSELECT,24169)@313
    assign leftShiftStage0Idx1Rng1_uid24170_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24170_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24170_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24171_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(BITJOIN,24170)@313
    assign leftShiftStage0Idx1_uid24171_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24170_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23225_dupName_475_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23224)@312
    assign rightShiftStage2Idx1Rng8_uid23225_dupName_475_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23227_dupName_475_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23226)@312
    assign rightShiftStage2Idx1_uid23227_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23225_dupName_475_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23220_dupName_475_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23219)@312
    assign rightShiftStage1Idx1Rng4_uid23220_dupName_475_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23222_dupName_475_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23221)@312
    assign rightShiftStage1Idx1_uid23222_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23220_dupName_475_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23215_dupName_475_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23214)@312
    assign rightShiftStage0Idx1Rng1_uid23215_dupName_475_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q[33:1];

    // rightShiftStage0Idx1_uid23217_dupName_475_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23216)@312
    assign rightShiftStage0Idx1_uid23217_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23215_dupName_475_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24144_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(BITSELECT,24143)@311
    assign leftShiftStage2Idx1Rng8_uid24144_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in = leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24144_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24144_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24145_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(BITJOIN,24144)@311
    assign leftShiftStage2Idx1_uid24145_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24144_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24139_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(BITSELECT,24138)@311
    assign leftShiftStage1Idx1Rng4_uid24139_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in = leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24139_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24139_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24140_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(BITJOIN,24139)@311
    assign leftShiftStage1Idx1_uid24140_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24139_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24134_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(BITSELECT,24133)@311
    assign leftShiftStage0Idx1Rng1_uid24134_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24134_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24134_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24135_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(BITJOIN,24134)@311
    assign leftShiftStage0Idx1_uid24135_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24134_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23163_dupName_471_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23162)@310
    assign rightShiftStage2Idx1Rng8_uid23163_dupName_471_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23165_dupName_471_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23164)@310
    assign rightShiftStage2Idx1_uid23165_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23163_dupName_471_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23158_dupName_471_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23157)@310
    assign rightShiftStage1Idx1Rng4_uid23158_dupName_471_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23160_dupName_471_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23159)@310
    assign rightShiftStage1Idx1_uid23160_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23158_dupName_471_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23153_dupName_471_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23152)@310
    assign rightShiftStage0Idx1Rng1_uid23153_dupName_471_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q[33:1];

    // rightShiftStage0Idx1_uid23155_dupName_471_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23154)@310
    assign rightShiftStage0Idx1_uid23155_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23153_dupName_471_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24126_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(BITSELECT,24125)@309
    assign leftShiftStage2Idx1Rng8_uid24126_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in = leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24126_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24126_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24127_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(BITJOIN,24126)@309
    assign leftShiftStage2Idx1_uid24127_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24126_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24121_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(BITSELECT,24120)@309
    assign leftShiftStage1Idx1Rng4_uid24121_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in = leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24121_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24121_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24122_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(BITJOIN,24121)@309
    assign leftShiftStage1Idx1_uid24122_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24121_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24116_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(BITSELECT,24115)@309
    assign leftShiftStage0Idx1Rng1_uid24116_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24116_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24116_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24117_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(BITJOIN,24116)@309
    assign leftShiftStage0Idx1_uid24117_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24116_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23101_dupName_467_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23100)@308
    assign rightShiftStage2Idx1Rng8_uid23101_dupName_467_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23103_dupName_467_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23102)@308
    assign rightShiftStage2Idx1_uid23103_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23101_dupName_467_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23096_dupName_467_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23095)@308
    assign rightShiftStage1Idx1Rng4_uid23096_dupName_467_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23098_dupName_467_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23097)@308
    assign rightShiftStage1Idx1_uid23098_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23096_dupName_467_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23091_dupName_467_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23090)@308
    assign rightShiftStage0Idx1Rng1_uid23091_dupName_467_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q[33:1];

    // rightShiftStage0Idx1_uid23093_dupName_467_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23092)@308
    assign rightShiftStage0Idx1_uid23093_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23091_dupName_467_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24108_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(BITSELECT,24107)@307
    assign leftShiftStage2Idx1Rng8_uid24108_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in = leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24108_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24108_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24109_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(BITJOIN,24108)@307
    assign leftShiftStage2Idx1_uid24109_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24108_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24103_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(BITSELECT,24102)@307
    assign leftShiftStage1Idx1Rng4_uid24103_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in = leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24103_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24103_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24104_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(BITJOIN,24103)@307
    assign leftShiftStage1Idx1_uid24104_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24103_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24098_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(BITSELECT,24097)@307
    assign leftShiftStage0Idx1Rng1_uid24098_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24098_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24098_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24099_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(BITJOIN,24098)@307
    assign leftShiftStage0Idx1_uid24099_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24098_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid23039_dupName_463_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23038)@306
    assign rightShiftStage2Idx1Rng8_uid23039_dupName_463_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid23041_dupName_463_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23040)@306
    assign rightShiftStage2Idx1_uid23041_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid23039_dupName_463_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid23034_dupName_463_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23033)@306
    assign rightShiftStage1Idx1Rng4_uid23034_dupName_463_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid23036_dupName_463_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23035)@306
    assign rightShiftStage1Idx1_uid23036_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid23034_dupName_463_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid23029_dupName_463_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23028)@306
    assign rightShiftStage0Idx1Rng1_uid23029_dupName_463_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q[33:1];

    // rightShiftStage0Idx1_uid23031_dupName_463_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23030)@306
    assign rightShiftStage0Idx1_uid23031_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid23029_dupName_463_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24090_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(BITSELECT,24089)@305
    assign leftShiftStage2Idx1Rng8_uid24090_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in = leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24090_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24090_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24091_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(BITJOIN,24090)@305
    assign leftShiftStage2Idx1_uid24091_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24090_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24085_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(BITSELECT,24084)@305
    assign leftShiftStage1Idx1Rng4_uid24085_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in = leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24085_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24085_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24086_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(BITJOIN,24085)@305
    assign leftShiftStage1Idx1_uid24086_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24085_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24080_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(BITSELECT,24079)@305
    assign leftShiftStage0Idx1Rng1_uid24080_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24080_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24080_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24081_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(BITJOIN,24080)@305
    assign leftShiftStage0Idx1_uid24081_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24080_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22977_dupName_459_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22976)@304
    assign rightShiftStage2Idx1Rng8_uid22977_dupName_459_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22979_dupName_459_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22978)@304
    assign rightShiftStage2Idx1_uid22979_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22977_dupName_459_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22972_dupName_459_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22971)@304
    assign rightShiftStage1Idx1Rng4_uid22972_dupName_459_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22974_dupName_459_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22973)@304
    assign rightShiftStage1Idx1_uid22974_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22972_dupName_459_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22967_dupName_459_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22966)@304
    assign rightShiftStage0Idx1Rng1_uid22967_dupName_459_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q[33:1];

    // rightShiftStage0Idx1_uid22969_dupName_459_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22968)@304
    assign rightShiftStage0Idx1_uid22969_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22967_dupName_459_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24072_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(BITSELECT,24071)@303
    assign leftShiftStage2Idx1Rng8_uid24072_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in = leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24072_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24072_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24073_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(BITJOIN,24072)@303
    assign leftShiftStage2Idx1_uid24073_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24072_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24067_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(BITSELECT,24066)@303
    assign leftShiftStage1Idx1Rng4_uid24067_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in = leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24067_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24067_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24068_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(BITJOIN,24067)@303
    assign leftShiftStage1Idx1_uid24068_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24067_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24062_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(BITSELECT,24061)@303
    assign leftShiftStage0Idx1Rng1_uid24062_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24062_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24062_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24063_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(BITJOIN,24062)@303
    assign leftShiftStage0Idx1_uid24063_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24062_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22915_dupName_455_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22914)@302
    assign rightShiftStage2Idx1Rng8_uid22915_dupName_455_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22917_dupName_455_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22916)@302
    assign rightShiftStage2Idx1_uid22917_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22915_dupName_455_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22910_dupName_455_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22909)@302
    assign rightShiftStage1Idx1Rng4_uid22910_dupName_455_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22912_dupName_455_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22911)@302
    assign rightShiftStage1Idx1_uid22912_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22910_dupName_455_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22905_dupName_455_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22904)@302
    assign rightShiftStage0Idx1Rng1_uid22905_dupName_455_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q[33:1];

    // rightShiftStage0Idx1_uid22907_dupName_455_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22906)@302
    assign rightShiftStage0Idx1_uid22907_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22905_dupName_455_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24054_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(BITSELECT,24053)@301
    assign leftShiftStage2Idx1Rng8_uid24054_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in = leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24054_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24054_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24055_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(BITJOIN,24054)@301
    assign leftShiftStage2Idx1_uid24055_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24054_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24049_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(BITSELECT,24048)@301
    assign leftShiftStage1Idx1Rng4_uid24049_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in = leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24049_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24049_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24050_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(BITJOIN,24049)@301
    assign leftShiftStage1Idx1_uid24050_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24049_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24044_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(BITSELECT,24043)@301
    assign leftShiftStage0Idx1Rng1_uid24044_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24044_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24044_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24045_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(BITJOIN,24044)@301
    assign leftShiftStage0Idx1_uid24045_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24044_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22853_dupName_451_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22852)@300
    assign rightShiftStage2Idx1Rng8_uid22853_dupName_451_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22855_dupName_451_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22854)@300
    assign rightShiftStage2Idx1_uid22855_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22853_dupName_451_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22848_dupName_451_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22847)@300
    assign rightShiftStage1Idx1Rng4_uid22848_dupName_451_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22850_dupName_451_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22849)@300
    assign rightShiftStage1Idx1_uid22850_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22848_dupName_451_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22843_dupName_451_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22842)@300
    assign rightShiftStage0Idx1Rng1_uid22843_dupName_451_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q[33:1];

    // rightShiftStage0Idx1_uid22845_dupName_451_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22844)@300
    assign rightShiftStage0Idx1_uid22845_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22843_dupName_451_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24036_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(BITSELECT,24035)@299
    assign leftShiftStage2Idx1Rng8_uid24036_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in = leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24036_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24036_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24037_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(BITJOIN,24036)@299
    assign leftShiftStage2Idx1_uid24037_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24036_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24031_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(BITSELECT,24030)@299
    assign leftShiftStage1Idx1Rng4_uid24031_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in = leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24031_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24031_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24032_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(BITJOIN,24031)@299
    assign leftShiftStage1Idx1_uid24032_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24031_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24026_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(BITSELECT,24025)@299
    assign leftShiftStage0Idx1Rng1_uid24026_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24026_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24026_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24027_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(BITJOIN,24026)@299
    assign leftShiftStage0Idx1_uid24027_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24026_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22791_dupName_447_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22790)@298
    assign rightShiftStage2Idx1Rng8_uid22791_dupName_447_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22793_dupName_447_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22792)@298
    assign rightShiftStage2Idx1_uid22793_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22791_dupName_447_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22786_dupName_447_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22785)@298
    assign rightShiftStage1Idx1Rng4_uid22786_dupName_447_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22788_dupName_447_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22787)@298
    assign rightShiftStage1Idx1_uid22788_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22786_dupName_447_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22781_dupName_447_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22780)@298
    assign rightShiftStage0Idx1Rng1_uid22781_dupName_447_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q[33:1];

    // rightShiftStage0Idx1_uid22783_dupName_447_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22782)@298
    assign rightShiftStage0Idx1_uid22783_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22781_dupName_447_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24018_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(BITSELECT,24017)@297
    assign leftShiftStage2Idx1Rng8_uid24018_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in = leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24018_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24018_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24019_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(BITJOIN,24018)@297
    assign leftShiftStage2Idx1_uid24019_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24018_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24013_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(BITSELECT,24012)@297
    assign leftShiftStage1Idx1Rng4_uid24013_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in = leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24013_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24013_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24014_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(BITJOIN,24013)@297
    assign leftShiftStage1Idx1_uid24014_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24013_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24008_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(BITSELECT,24007)@297
    assign leftShiftStage0Idx1Rng1_uid24008_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24008_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24008_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24009_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(BITJOIN,24008)@297
    assign leftShiftStage0Idx1_uid24009_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24008_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22729_dupName_443_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22728)@296
    assign rightShiftStage2Idx1Rng8_uid22729_dupName_443_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22731_dupName_443_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22730)@296
    assign rightShiftStage2Idx1_uid22731_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22729_dupName_443_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22724_dupName_443_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22723)@296
    assign rightShiftStage1Idx1Rng4_uid22724_dupName_443_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22726_dupName_443_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22725)@296
    assign rightShiftStage1Idx1_uid22726_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22724_dupName_443_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22719_dupName_443_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22718)@296
    assign rightShiftStage0Idx1Rng1_uid22719_dupName_443_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q[33:1];

    // rightShiftStage0Idx1_uid22721_dupName_443_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22720)@296
    assign rightShiftStage0Idx1_uid22721_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22719_dupName_443_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24000_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(BITSELECT,23999)@295
    assign leftShiftStage2Idx1Rng8_uid24000_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in = leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24000_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24000_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24001_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(BITJOIN,24000)@295
    assign leftShiftStage2Idx1_uid24001_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24000_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23995_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(BITSELECT,23994)@295
    assign leftShiftStage1Idx1Rng4_uid23995_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in = leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23995_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23995_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23996_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(BITJOIN,23995)@295
    assign leftShiftStage1Idx1_uid23996_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23995_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23990_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(BITSELECT,23989)@295
    assign leftShiftStage0Idx1Rng1_uid23990_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23990_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23990_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23991_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(BITJOIN,23990)@295
    assign leftShiftStage0Idx1_uid23991_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23990_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22667_dupName_439_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22666)@294
    assign rightShiftStage2Idx1Rng8_uid22667_dupName_439_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22669_dupName_439_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22668)@294
    assign rightShiftStage2Idx1_uid22669_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22667_dupName_439_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22662_dupName_439_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22661)@294
    assign rightShiftStage1Idx1Rng4_uid22662_dupName_439_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22664_dupName_439_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22663)@294
    assign rightShiftStage1Idx1_uid22664_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22662_dupName_439_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22657_dupName_439_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22656)@294
    assign rightShiftStage0Idx1Rng1_uid22657_dupName_439_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q[33:1];

    // rightShiftStage0Idx1_uid22659_dupName_439_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22658)@294
    assign rightShiftStage0Idx1_uid22659_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22657_dupName_439_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23982_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(BITSELECT,23981)@293
    assign leftShiftStage2Idx1Rng8_uid23982_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in = leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23982_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23982_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23983_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(BITJOIN,23982)@293
    assign leftShiftStage2Idx1_uid23983_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23982_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23977_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(BITSELECT,23976)@293
    assign leftShiftStage1Idx1Rng4_uid23977_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in = leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23977_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23977_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23978_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(BITJOIN,23977)@293
    assign leftShiftStage1Idx1_uid23978_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23977_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23972_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(BITSELECT,23971)@293
    assign leftShiftStage0Idx1Rng1_uid23972_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23972_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23972_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23973_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(BITJOIN,23972)@293
    assign leftShiftStage0Idx1_uid23973_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23972_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22605_dupName_435_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22604)@292
    assign rightShiftStage2Idx1Rng8_uid22605_dupName_435_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22607_dupName_435_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22606)@292
    assign rightShiftStage2Idx1_uid22607_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22605_dupName_435_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22600_dupName_435_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22599)@292
    assign rightShiftStage1Idx1Rng4_uid22600_dupName_435_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22602_dupName_435_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22601)@292
    assign rightShiftStage1Idx1_uid22602_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22600_dupName_435_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22595_dupName_435_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22594)@292
    assign rightShiftStage0Idx1Rng1_uid22595_dupName_435_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q[33:1];

    // rightShiftStage0Idx1_uid22597_dupName_435_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22596)@292
    assign rightShiftStage0Idx1_uid22597_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22595_dupName_435_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23946_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(BITSELECT,23945)@291
    assign leftShiftStage2Idx1Rng8_uid23946_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in = leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23946_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23946_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23947_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(BITJOIN,23946)@291
    assign leftShiftStage2Idx1_uid23947_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23946_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23941_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(BITSELECT,23940)@291
    assign leftShiftStage1Idx1Rng4_uid23941_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in = leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23941_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23941_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23942_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(BITJOIN,23941)@291
    assign leftShiftStage1Idx1_uid23942_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23941_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23936_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(BITSELECT,23935)@291
    assign leftShiftStage0Idx1Rng1_uid23936_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23936_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23936_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23937_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(BITJOIN,23936)@291
    assign leftShiftStage0Idx1_uid23937_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23936_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22543_dupName_431_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22542)@290
    assign rightShiftStage2Idx1Rng8_uid22543_dupName_431_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22545_dupName_431_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22544)@290
    assign rightShiftStage2Idx1_uid22545_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22543_dupName_431_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22538_dupName_431_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22537)@290
    assign rightShiftStage1Idx1Rng4_uid22538_dupName_431_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22540_dupName_431_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22539)@290
    assign rightShiftStage1Idx1_uid22540_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22538_dupName_431_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22533_dupName_431_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22532)@290
    assign rightShiftStage0Idx1Rng1_uid22533_dupName_431_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q[33:1];

    // rightShiftStage0Idx1_uid22535_dupName_431_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22534)@290
    assign rightShiftStage0Idx1_uid22535_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22533_dupName_431_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23928_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(BITSELECT,23927)@289
    assign leftShiftStage2Idx1Rng8_uid23928_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in = leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23928_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23928_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23929_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(BITJOIN,23928)@289
    assign leftShiftStage2Idx1_uid23929_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23928_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23923_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(BITSELECT,23922)@289
    assign leftShiftStage1Idx1Rng4_uid23923_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in = leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23923_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23923_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23924_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(BITJOIN,23923)@289
    assign leftShiftStage1Idx1_uid23924_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23923_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23918_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(BITSELECT,23917)@289
    assign leftShiftStage0Idx1Rng1_uid23918_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23918_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23918_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23919_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(BITJOIN,23918)@289
    assign leftShiftStage0Idx1_uid23919_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23918_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22481_dupName_427_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22480)@288
    assign rightShiftStage2Idx1Rng8_uid22481_dupName_427_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22483_dupName_427_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22482)@288
    assign rightShiftStage2Idx1_uid22483_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22481_dupName_427_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22476_dupName_427_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22475)@288
    assign rightShiftStage1Idx1Rng4_uid22476_dupName_427_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22478_dupName_427_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22477)@288
    assign rightShiftStage1Idx1_uid22478_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22476_dupName_427_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22471_dupName_427_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22470)@288
    assign rightShiftStage0Idx1Rng1_uid22471_dupName_427_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q[33:1];

    // rightShiftStage0Idx1_uid22473_dupName_427_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22472)@288
    assign rightShiftStage0Idx1_uid22473_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22471_dupName_427_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23910_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(BITSELECT,23909)@287
    assign leftShiftStage2Idx1Rng8_uid23910_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in = leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23910_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23910_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23911_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(BITJOIN,23910)@287
    assign leftShiftStage2Idx1_uid23911_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23910_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23905_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(BITSELECT,23904)@287
    assign leftShiftStage1Idx1Rng4_uid23905_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in = leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23905_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23905_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23906_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(BITJOIN,23905)@287
    assign leftShiftStage1Idx1_uid23906_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23905_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23900_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(BITSELECT,23899)@287
    assign leftShiftStage0Idx1Rng1_uid23900_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23900_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23900_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23901_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(BITJOIN,23900)@287
    assign leftShiftStage0Idx1_uid23901_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23900_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22419_dupName_423_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22418)@286
    assign rightShiftStage2Idx1Rng8_uid22419_dupName_423_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22421_dupName_423_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22420)@286
    assign rightShiftStage2Idx1_uid22421_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22419_dupName_423_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22414_dupName_423_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22413)@286
    assign rightShiftStage1Idx1Rng4_uid22414_dupName_423_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22416_dupName_423_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22415)@286
    assign rightShiftStage1Idx1_uid22416_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22414_dupName_423_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22409_dupName_423_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22408)@286
    assign rightShiftStage0Idx1Rng1_uid22409_dupName_423_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q[33:1];

    // rightShiftStage0Idx1_uid22411_dupName_423_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22410)@286
    assign rightShiftStage0Idx1_uid22411_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22409_dupName_423_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23892_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(BITSELECT,23891)@285
    assign leftShiftStage2Idx1Rng8_uid23892_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in = leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23892_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23892_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23893_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(BITJOIN,23892)@285
    assign leftShiftStage2Idx1_uid23893_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23892_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23887_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(BITSELECT,23886)@285
    assign leftShiftStage1Idx1Rng4_uid23887_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in = leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23887_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23887_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23888_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(BITJOIN,23887)@285
    assign leftShiftStage1Idx1_uid23888_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23887_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23882_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(BITSELECT,23881)@285
    assign leftShiftStage0Idx1Rng1_uid23882_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23882_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23882_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23883_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(BITJOIN,23882)@285
    assign leftShiftStage0Idx1_uid23883_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23882_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22357_dupName_419_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22356)@284
    assign rightShiftStage2Idx1Rng8_uid22357_dupName_419_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22359_dupName_419_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22358)@284
    assign rightShiftStage2Idx1_uid22359_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22357_dupName_419_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22352_dupName_419_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22351)@284
    assign rightShiftStage1Idx1Rng4_uid22352_dupName_419_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22354_dupName_419_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22353)@284
    assign rightShiftStage1Idx1_uid22354_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22352_dupName_419_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22347_dupName_419_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22346)@284
    assign rightShiftStage0Idx1Rng1_uid22347_dupName_419_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q[33:1];

    // rightShiftStage0Idx1_uid22349_dupName_419_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22348)@284
    assign rightShiftStage0Idx1_uid22349_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22347_dupName_419_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23874_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(BITSELECT,23873)@283
    assign leftShiftStage2Idx1Rng8_uid23874_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in = leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23874_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23874_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23875_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(BITJOIN,23874)@283
    assign leftShiftStage2Idx1_uid23875_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23874_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23869_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(BITSELECT,23868)@283
    assign leftShiftStage1Idx1Rng4_uid23869_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in = leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23869_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23869_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23870_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(BITJOIN,23869)@283
    assign leftShiftStage1Idx1_uid23870_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23869_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23864_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(BITSELECT,23863)@283
    assign leftShiftStage0Idx1Rng1_uid23864_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23864_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23864_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23865_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(BITJOIN,23864)@283
    assign leftShiftStage0Idx1_uid23865_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23864_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22295_dupName_415_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22294)@282
    assign rightShiftStage2Idx1Rng8_uid22295_dupName_415_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22297_dupName_415_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22296)@282
    assign rightShiftStage2Idx1_uid22297_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22295_dupName_415_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22290_dupName_415_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22289)@282
    assign rightShiftStage1Idx1Rng4_uid22290_dupName_415_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22292_dupName_415_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22291)@282
    assign rightShiftStage1Idx1_uid22292_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22290_dupName_415_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22285_dupName_415_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22284)@282
    assign rightShiftStage0Idx1Rng1_uid22285_dupName_415_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q[33:1];

    // rightShiftStage0Idx1_uid22287_dupName_415_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22286)@282
    assign rightShiftStage0Idx1_uid22287_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22285_dupName_415_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23856_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(BITSELECT,23855)@281
    assign leftShiftStage2Idx1Rng8_uid23856_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in = leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23856_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23856_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23857_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(BITJOIN,23856)@281
    assign leftShiftStage2Idx1_uid23857_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23856_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23851_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(BITSELECT,23850)@281
    assign leftShiftStage1Idx1Rng4_uid23851_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in = leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23851_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23851_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23852_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(BITJOIN,23851)@281
    assign leftShiftStage1Idx1_uid23852_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23851_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23846_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(BITSELECT,23845)@281
    assign leftShiftStage0Idx1Rng1_uid23846_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23846_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23846_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23847_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(BITJOIN,23846)@281
    assign leftShiftStage0Idx1_uid23847_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23846_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22233_dupName_411_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22232)@280
    assign rightShiftStage2Idx1Rng8_uid22233_dupName_411_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22235_dupName_411_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22234)@280
    assign rightShiftStage2Idx1_uid22235_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22233_dupName_411_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22228_dupName_411_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22227)@280
    assign rightShiftStage1Idx1Rng4_uid22228_dupName_411_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22230_dupName_411_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22229)@280
    assign rightShiftStage1Idx1_uid22230_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22228_dupName_411_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22223_dupName_411_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22222)@280
    assign rightShiftStage0Idx1Rng1_uid22223_dupName_411_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q[33:1];

    // rightShiftStage0Idx1_uid22225_dupName_411_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22224)@280
    assign rightShiftStage0Idx1_uid22225_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22223_dupName_411_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23838_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(BITSELECT,23837)@279
    assign leftShiftStage2Idx1Rng8_uid23838_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in = leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23838_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23838_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23839_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(BITJOIN,23838)@279
    assign leftShiftStage2Idx1_uid23839_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23838_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23833_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(BITSELECT,23832)@279
    assign leftShiftStage1Idx1Rng4_uid23833_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in = leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23833_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23833_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23834_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(BITJOIN,23833)@279
    assign leftShiftStage1Idx1_uid23834_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23833_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23828_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(BITSELECT,23827)@279
    assign leftShiftStage0Idx1Rng1_uid23828_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23828_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23828_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23829_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(BITJOIN,23828)@279
    assign leftShiftStage0Idx1_uid23829_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23828_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22171_dupName_407_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22170)@278
    assign rightShiftStage2Idx1Rng8_uid22171_dupName_407_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22173_dupName_407_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22172)@278
    assign rightShiftStage2Idx1_uid22173_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22171_dupName_407_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22166_dupName_407_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22165)@278
    assign rightShiftStage1Idx1Rng4_uid22166_dupName_407_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22168_dupName_407_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22167)@278
    assign rightShiftStage1Idx1_uid22168_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22166_dupName_407_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22161_dupName_407_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22160)@278
    assign rightShiftStage0Idx1Rng1_uid22161_dupName_407_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q[33:1];

    // rightShiftStage0Idx1_uid22163_dupName_407_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22162)@278
    assign rightShiftStage0Idx1_uid22163_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22161_dupName_407_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23820_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(BITSELECT,23819)@277
    assign leftShiftStage2Idx1Rng8_uid23820_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in = leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23820_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23820_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23821_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(BITJOIN,23820)@277
    assign leftShiftStage2Idx1_uid23821_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23820_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23815_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(BITSELECT,23814)@277
    assign leftShiftStage1Idx1Rng4_uid23815_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in = leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23815_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23815_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23816_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(BITJOIN,23815)@277
    assign leftShiftStage1Idx1_uid23816_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23815_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23810_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(BITSELECT,23809)@277
    assign leftShiftStage0Idx1Rng1_uid23810_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23810_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23810_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23811_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(BITJOIN,23810)@277
    assign leftShiftStage0Idx1_uid23811_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23810_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22109_dupName_403_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22108)@276
    assign rightShiftStage2Idx1Rng8_uid22109_dupName_403_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22111_dupName_403_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22110)@276
    assign rightShiftStage2Idx1_uid22111_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22109_dupName_403_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22104_dupName_403_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22103)@276
    assign rightShiftStage1Idx1Rng4_uid22104_dupName_403_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22106_dupName_403_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22105)@276
    assign rightShiftStage1Idx1_uid22106_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22104_dupName_403_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22099_dupName_403_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22098)@276
    assign rightShiftStage0Idx1Rng1_uid22099_dupName_403_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q[33:1];

    // rightShiftStage0Idx1_uid22101_dupName_403_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22100)@276
    assign rightShiftStage0Idx1_uid22101_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22099_dupName_403_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23802_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(BITSELECT,23801)@275
    assign leftShiftStage2Idx1Rng8_uid23802_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in = leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23802_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23802_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23803_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(BITJOIN,23802)@275
    assign leftShiftStage2Idx1_uid23803_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23802_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23797_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(BITSELECT,23796)@275
    assign leftShiftStage1Idx1Rng4_uid23797_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in = leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23797_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23797_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23798_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(BITJOIN,23797)@275
    assign leftShiftStage1Idx1_uid23798_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23797_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23792_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(BITSELECT,23791)@275
    assign leftShiftStage0Idx1Rng1_uid23792_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23792_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23792_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23793_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(BITJOIN,23792)@275
    assign leftShiftStage0Idx1_uid23793_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23792_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid22047_dupName_399_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22046)@274
    assign rightShiftStage2Idx1Rng8_uid22047_dupName_399_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid22049_dupName_399_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22048)@274
    assign rightShiftStage2Idx1_uid22049_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid22047_dupName_399_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid22042_dupName_399_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22041)@274
    assign rightShiftStage1Idx1Rng4_uid22042_dupName_399_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid22044_dupName_399_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22043)@274
    assign rightShiftStage1Idx1_uid22044_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid22042_dupName_399_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid22037_dupName_399_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22036)@274
    assign rightShiftStage0Idx1Rng1_uid22037_dupName_399_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q[33:1];

    // rightShiftStage0Idx1_uid22039_dupName_399_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22038)@274
    assign rightShiftStage0Idx1_uid22039_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid22037_dupName_399_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23784_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(BITSELECT,23783)@273
    assign leftShiftStage2Idx1Rng8_uid23784_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in = leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23784_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23784_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23785_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(BITJOIN,23784)@273
    assign leftShiftStage2Idx1_uid23785_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23784_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23779_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(BITSELECT,23778)@273
    assign leftShiftStage1Idx1Rng4_uid23779_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in = leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23779_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23779_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23780_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(BITJOIN,23779)@273
    assign leftShiftStage1Idx1_uid23780_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23779_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23774_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(BITSELECT,23773)@273
    assign leftShiftStage0Idx1Rng1_uid23774_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23774_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23774_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23775_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(BITJOIN,23774)@273
    assign leftShiftStage0Idx1_uid23775_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23774_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21985_dupName_395_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21984)@272
    assign rightShiftStage2Idx1Rng8_uid21985_dupName_395_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21987_dupName_395_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21986)@272
    assign rightShiftStage2Idx1_uid21987_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21985_dupName_395_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21980_dupName_395_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21979)@272
    assign rightShiftStage1Idx1Rng4_uid21980_dupName_395_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21982_dupName_395_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21981)@272
    assign rightShiftStage1Idx1_uid21982_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21980_dupName_395_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21975_dupName_395_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21974)@272
    assign rightShiftStage0Idx1Rng1_uid21975_dupName_395_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q[33:1];

    // rightShiftStage0Idx1_uid21977_dupName_395_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21976)@272
    assign rightShiftStage0Idx1_uid21977_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21975_dupName_395_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26034_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(BITSELECT,26033)@271
    assign leftShiftStage2Idx1Rng8_uid26034_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in = leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26034_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26034_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26035_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(BITJOIN,26034)@271
    assign leftShiftStage2Idx1_uid26035_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26034_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26029_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(BITSELECT,26028)@271
    assign leftShiftStage1Idx1Rng4_uid26029_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in = leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26029_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26029_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26030_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(BITJOIN,26029)@271
    assign leftShiftStage1Idx1_uid26030_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26029_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26024_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(BITSELECT,26023)@271
    assign leftShiftStage0Idx1Rng1_uid26024_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26024_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26024_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26025_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(BITJOIN,26024)@271
    assign leftShiftStage0Idx1_uid26025_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26024_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21923_dupName_391_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21922)@270
    assign rightShiftStage2Idx1Rng8_uid21923_dupName_391_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21925_dupName_391_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21924)@270
    assign rightShiftStage2Idx1_uid21925_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21923_dupName_391_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21918_dupName_391_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21917)@270
    assign rightShiftStage1Idx1Rng4_uid21918_dupName_391_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21920_dupName_391_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21919)@270
    assign rightShiftStage1Idx1_uid21920_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21918_dupName_391_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21913_dupName_391_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21912)@270
    assign rightShiftStage0Idx1Rng1_uid21913_dupName_391_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q[33:1];

    // rightShiftStage0Idx1_uid21915_dupName_391_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21914)@270
    assign rightShiftStage0Idx1_uid21915_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21913_dupName_391_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26016_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(BITSELECT,26015)@269
    assign leftShiftStage2Idx1Rng8_uid26016_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in = leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26016_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26016_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26017_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(BITJOIN,26016)@269
    assign leftShiftStage2Idx1_uid26017_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26016_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26011_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(BITSELECT,26010)@269
    assign leftShiftStage1Idx1Rng4_uid26011_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in = leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26011_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26011_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26012_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(BITJOIN,26011)@269
    assign leftShiftStage1Idx1_uid26012_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26011_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26006_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(BITSELECT,26005)@269
    assign leftShiftStage0Idx1Rng1_uid26006_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26006_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26006_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26007_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(BITJOIN,26006)@269
    assign leftShiftStage0Idx1_uid26007_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26006_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21861_dupName_387_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21860)@268
    assign rightShiftStage2Idx1Rng8_uid21861_dupName_387_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21863_dupName_387_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21862)@268
    assign rightShiftStage2Idx1_uid21863_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21861_dupName_387_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21856_dupName_387_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21855)@268
    assign rightShiftStage1Idx1Rng4_uid21856_dupName_387_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21858_dupName_387_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21857)@268
    assign rightShiftStage1Idx1_uid21858_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21856_dupName_387_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21851_dupName_387_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21850)@268
    assign rightShiftStage0Idx1Rng1_uid21851_dupName_387_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q[33:1];

    // rightShiftStage0Idx1_uid21853_dupName_387_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21852)@268
    assign rightShiftStage0Idx1_uid21853_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21851_dupName_387_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25998_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(BITSELECT,25997)@267
    assign leftShiftStage2Idx1Rng8_uid25998_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in = leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25998_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25998_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25999_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(BITJOIN,25998)@267
    assign leftShiftStage2Idx1_uid25999_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25998_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25993_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(BITSELECT,25992)@267
    assign leftShiftStage1Idx1Rng4_uid25993_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in = leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25993_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25993_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25994_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(BITJOIN,25993)@267
    assign leftShiftStage1Idx1_uid25994_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25993_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25988_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(BITSELECT,25987)@267
    assign leftShiftStage0Idx1Rng1_uid25988_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25988_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25988_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25989_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(BITJOIN,25988)@267
    assign leftShiftStage0Idx1_uid25989_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25988_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21799_dupName_383_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21798)@266
    assign rightShiftStage2Idx1Rng8_uid21799_dupName_383_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21801_dupName_383_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21800)@266
    assign rightShiftStage2Idx1_uid21801_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21799_dupName_383_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21794_dupName_383_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21793)@266
    assign rightShiftStage1Idx1Rng4_uid21794_dupName_383_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21796_dupName_383_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21795)@266
    assign rightShiftStage1Idx1_uid21796_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21794_dupName_383_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21789_dupName_383_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21788)@266
    assign rightShiftStage0Idx1Rng1_uid21789_dupName_383_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q[33:1];

    // rightShiftStage0Idx1_uid21791_dupName_383_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21790)@266
    assign rightShiftStage0Idx1_uid21791_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21789_dupName_383_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25980_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(BITSELECT,25979)@265
    assign leftShiftStage2Idx1Rng8_uid25980_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in = leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25980_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25980_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25981_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(BITJOIN,25980)@265
    assign leftShiftStage2Idx1_uid25981_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25980_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25975_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(BITSELECT,25974)@265
    assign leftShiftStage1Idx1Rng4_uid25975_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in = leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25975_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25975_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25976_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(BITJOIN,25975)@265
    assign leftShiftStage1Idx1_uid25976_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25975_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25970_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(BITSELECT,25969)@265
    assign leftShiftStage0Idx1Rng1_uid25970_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25970_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25970_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25971_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(BITJOIN,25970)@265
    assign leftShiftStage0Idx1_uid25971_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25970_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21737_dupName_379_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21736)@264
    assign rightShiftStage2Idx1Rng8_uid21737_dupName_379_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21739_dupName_379_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21738)@264
    assign rightShiftStage2Idx1_uid21739_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21737_dupName_379_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21732_dupName_379_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21731)@264
    assign rightShiftStage1Idx1Rng4_uid21732_dupName_379_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21734_dupName_379_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21733)@264
    assign rightShiftStage1Idx1_uid21734_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21732_dupName_379_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21727_dupName_379_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21726)@264
    assign rightShiftStage0Idx1Rng1_uid21727_dupName_379_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q[33:1];

    // rightShiftStage0Idx1_uid21729_dupName_379_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21728)@264
    assign rightShiftStage0Idx1_uid21729_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21727_dupName_379_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25962_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(BITSELECT,25961)@263
    assign leftShiftStage2Idx1Rng8_uid25962_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in = leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25962_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25962_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25963_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(BITJOIN,25962)@263
    assign leftShiftStage2Idx1_uid25963_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25962_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25957_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(BITSELECT,25956)@263
    assign leftShiftStage1Idx1Rng4_uid25957_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in = leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25957_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25957_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25958_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(BITJOIN,25957)@263
    assign leftShiftStage1Idx1_uid25958_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25957_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25952_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(BITSELECT,25951)@263
    assign leftShiftStage0Idx1Rng1_uid25952_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25952_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25952_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25953_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(BITJOIN,25952)@263
    assign leftShiftStage0Idx1_uid25953_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25952_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21675_dupName_375_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21674)@262
    assign rightShiftStage2Idx1Rng8_uid21675_dupName_375_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21677_dupName_375_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21676)@262
    assign rightShiftStage2Idx1_uid21677_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21675_dupName_375_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21670_dupName_375_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21669)@262
    assign rightShiftStage1Idx1Rng4_uid21670_dupName_375_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21672_dupName_375_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21671)@262
    assign rightShiftStage1Idx1_uid21672_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21670_dupName_375_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21665_dupName_375_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21664)@262
    assign rightShiftStage0Idx1Rng1_uid21665_dupName_375_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q[33:1];

    // rightShiftStage0Idx1_uid21667_dupName_375_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21666)@262
    assign rightShiftStage0Idx1_uid21667_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21665_dupName_375_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25944_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(BITSELECT,25943)@261
    assign leftShiftStage2Idx1Rng8_uid25944_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in = leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25944_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25944_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25945_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(BITJOIN,25944)@261
    assign leftShiftStage2Idx1_uid25945_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25944_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25939_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(BITSELECT,25938)@261
    assign leftShiftStage1Idx1Rng4_uid25939_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in = leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25939_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25939_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25940_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(BITJOIN,25939)@261
    assign leftShiftStage1Idx1_uid25940_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25939_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25934_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(BITSELECT,25933)@261
    assign leftShiftStage0Idx1Rng1_uid25934_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25934_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25934_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25935_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(BITJOIN,25934)@261
    assign leftShiftStage0Idx1_uid25935_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25934_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21613_dupName_371_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21612)@260
    assign rightShiftStage2Idx1Rng8_uid21613_dupName_371_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21615_dupName_371_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21614)@260
    assign rightShiftStage2Idx1_uid21615_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21613_dupName_371_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21608_dupName_371_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21607)@260
    assign rightShiftStage1Idx1Rng4_uid21608_dupName_371_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21610_dupName_371_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21609)@260
    assign rightShiftStage1Idx1_uid21610_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21608_dupName_371_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21603_dupName_371_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21602)@260
    assign rightShiftStage0Idx1Rng1_uid21603_dupName_371_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q[33:1];

    // rightShiftStage0Idx1_uid21605_dupName_371_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21604)@260
    assign rightShiftStage0Idx1_uid21605_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21603_dupName_371_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25926_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(BITSELECT,25925)@259
    assign leftShiftStage2Idx1Rng8_uid25926_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in = leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25926_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25926_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25927_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(BITJOIN,25926)@259
    assign leftShiftStage2Idx1_uid25927_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25926_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25921_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(BITSELECT,25920)@259
    assign leftShiftStage1Idx1Rng4_uid25921_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in = leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25921_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25921_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25922_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(BITJOIN,25921)@259
    assign leftShiftStage1Idx1_uid25922_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25921_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25916_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(BITSELECT,25915)@259
    assign leftShiftStage0Idx1Rng1_uid25916_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25916_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25916_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25917_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(BITJOIN,25916)@259
    assign leftShiftStage0Idx1_uid25917_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25916_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21551_dupName_367_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21550)@258
    assign rightShiftStage2Idx1Rng8_uid21551_dupName_367_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21553_dupName_367_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21552)@258
    assign rightShiftStage2Idx1_uid21553_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21551_dupName_367_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21546_dupName_367_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21545)@258
    assign rightShiftStage1Idx1Rng4_uid21546_dupName_367_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21548_dupName_367_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21547)@258
    assign rightShiftStage1Idx1_uid21548_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21546_dupName_367_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21541_dupName_367_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21540)@258
    assign rightShiftStage0Idx1Rng1_uid21541_dupName_367_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q[33:1];

    // rightShiftStage0Idx1_uid21543_dupName_367_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21542)@258
    assign rightShiftStage0Idx1_uid21543_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21541_dupName_367_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25908_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(BITSELECT,25907)@257
    assign leftShiftStage2Idx1Rng8_uid25908_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in = leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25908_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25908_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25909_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(BITJOIN,25908)@257
    assign leftShiftStage2Idx1_uid25909_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25908_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25903_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(BITSELECT,25902)@257
    assign leftShiftStage1Idx1Rng4_uid25903_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in = leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25903_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25903_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25904_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(BITJOIN,25903)@257
    assign leftShiftStage1Idx1_uid25904_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25903_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25898_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(BITSELECT,25897)@257
    assign leftShiftStage0Idx1Rng1_uid25898_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25898_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25898_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25899_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(BITJOIN,25898)@257
    assign leftShiftStage0Idx1_uid25899_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25898_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21489_dupName_363_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21488)@256
    assign rightShiftStage2Idx1Rng8_uid21489_dupName_363_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21491_dupName_363_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21490)@256
    assign rightShiftStage2Idx1_uid21491_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21489_dupName_363_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21484_dupName_363_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21483)@256
    assign rightShiftStage1Idx1Rng4_uid21484_dupName_363_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21486_dupName_363_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21485)@256
    assign rightShiftStage1Idx1_uid21486_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21484_dupName_363_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21479_dupName_363_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21478)@256
    assign rightShiftStage0Idx1Rng1_uid21479_dupName_363_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q[33:1];

    // rightShiftStage0Idx1_uid21481_dupName_363_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21480)@256
    assign rightShiftStage0Idx1_uid21481_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21479_dupName_363_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25890_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(BITSELECT,25889)@255
    assign leftShiftStage2Idx1Rng8_uid25890_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in = leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25890_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25890_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25891_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(BITJOIN,25890)@255
    assign leftShiftStage2Idx1_uid25891_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25890_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25885_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(BITSELECT,25884)@255
    assign leftShiftStage1Idx1Rng4_uid25885_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in = leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25885_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25885_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25886_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(BITJOIN,25885)@255
    assign leftShiftStage1Idx1_uid25886_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25885_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25880_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(BITSELECT,25879)@255
    assign leftShiftStage0Idx1Rng1_uid25880_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25880_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25880_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25881_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(BITJOIN,25880)@255
    assign leftShiftStage0Idx1_uid25881_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25880_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21427_dupName_359_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21426)@254
    assign rightShiftStage2Idx1Rng8_uid21427_dupName_359_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21429_dupName_359_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21428)@254
    assign rightShiftStage2Idx1_uid21429_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21427_dupName_359_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21422_dupName_359_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21421)@254
    assign rightShiftStage1Idx1Rng4_uid21422_dupName_359_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21424_dupName_359_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21423)@254
    assign rightShiftStage1Idx1_uid21424_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21422_dupName_359_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21417_dupName_359_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21416)@254
    assign rightShiftStage0Idx1Rng1_uid21417_dupName_359_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q[33:1];

    // rightShiftStage0Idx1_uid21419_dupName_359_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21418)@254
    assign rightShiftStage0Idx1_uid21419_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21417_dupName_359_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25872_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(BITSELECT,25871)@253
    assign leftShiftStage2Idx1Rng8_uid25872_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in = leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25872_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25872_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25873_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(BITJOIN,25872)@253
    assign leftShiftStage2Idx1_uid25873_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25872_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25867_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(BITSELECT,25866)@253
    assign leftShiftStage1Idx1Rng4_uid25867_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in = leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25867_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25867_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25868_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(BITJOIN,25867)@253
    assign leftShiftStage1Idx1_uid25868_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25867_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25862_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(BITSELECT,25861)@253
    assign leftShiftStage0Idx1Rng1_uid25862_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25862_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25862_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25863_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(BITJOIN,25862)@253
    assign leftShiftStage0Idx1_uid25863_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25862_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21365_dupName_355_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21364)@252
    assign rightShiftStage2Idx1Rng8_uid21365_dupName_355_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21367_dupName_355_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21366)@252
    assign rightShiftStage2Idx1_uid21367_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21365_dupName_355_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21360_dupName_355_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21359)@252
    assign rightShiftStage1Idx1Rng4_uid21360_dupName_355_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21362_dupName_355_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21361)@252
    assign rightShiftStage1Idx1_uid21362_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21360_dupName_355_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21355_dupName_355_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21354)@252
    assign rightShiftStage0Idx1Rng1_uid21355_dupName_355_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q[33:1];

    // rightShiftStage0Idx1_uid21357_dupName_355_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21356)@252
    assign rightShiftStage0Idx1_uid21357_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21355_dupName_355_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25836_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(BITSELECT,25835)@251
    assign leftShiftStage2Idx1Rng8_uid25836_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in = leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25836_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25836_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25837_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(BITJOIN,25836)@251
    assign leftShiftStage2Idx1_uid25837_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25836_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25831_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(BITSELECT,25830)@251
    assign leftShiftStage1Idx1Rng4_uid25831_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in = leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25831_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25831_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25832_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(BITJOIN,25831)@251
    assign leftShiftStage1Idx1_uid25832_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25831_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25826_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(BITSELECT,25825)@251
    assign leftShiftStage0Idx1Rng1_uid25826_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25826_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25826_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25827_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(BITJOIN,25826)@251
    assign leftShiftStage0Idx1_uid25827_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25826_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21303_dupName_351_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21302)@250
    assign rightShiftStage2Idx1Rng8_uid21303_dupName_351_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21305_dupName_351_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21304)@250
    assign rightShiftStage2Idx1_uid21305_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21303_dupName_351_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21298_dupName_351_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21297)@250
    assign rightShiftStage1Idx1Rng4_uid21298_dupName_351_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21300_dupName_351_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21299)@250
    assign rightShiftStage1Idx1_uid21300_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21298_dupName_351_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21293_dupName_351_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21292)@250
    assign rightShiftStage0Idx1Rng1_uid21293_dupName_351_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q[33:1];

    // rightShiftStage0Idx1_uid21295_dupName_351_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21294)@250
    assign rightShiftStage0Idx1_uid21295_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21293_dupName_351_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25818_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(BITSELECT,25817)@249
    assign leftShiftStage2Idx1Rng8_uid25818_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in = leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25818_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25818_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25819_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(BITJOIN,25818)@249
    assign leftShiftStage2Idx1_uid25819_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25818_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25813_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(BITSELECT,25812)@249
    assign leftShiftStage1Idx1Rng4_uid25813_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in = leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25813_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25813_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25814_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(BITJOIN,25813)@249
    assign leftShiftStage1Idx1_uid25814_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25813_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25808_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(BITSELECT,25807)@249
    assign leftShiftStage0Idx1Rng1_uid25808_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25808_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25808_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25809_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(BITJOIN,25808)@249
    assign leftShiftStage0Idx1_uid25809_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25808_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21241_dupName_347_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21240)@248
    assign rightShiftStage2Idx1Rng8_uid21241_dupName_347_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21243_dupName_347_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21242)@248
    assign rightShiftStage2Idx1_uid21243_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21241_dupName_347_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21236_dupName_347_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21235)@248
    assign rightShiftStage1Idx1Rng4_uid21236_dupName_347_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21238_dupName_347_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21237)@248
    assign rightShiftStage1Idx1_uid21238_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21236_dupName_347_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21231_dupName_347_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21230)@248
    assign rightShiftStage0Idx1Rng1_uid21231_dupName_347_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q[33:1];

    // rightShiftStage0Idx1_uid21233_dupName_347_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21232)@248
    assign rightShiftStage0Idx1_uid21233_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21231_dupName_347_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25800_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(BITSELECT,25799)@247
    assign leftShiftStage2Idx1Rng8_uid25800_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in = leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25800_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25800_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25801_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(BITJOIN,25800)@247
    assign leftShiftStage2Idx1_uid25801_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25800_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25795_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(BITSELECT,25794)@247
    assign leftShiftStage1Idx1Rng4_uid25795_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in = leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25795_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25795_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25796_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(BITJOIN,25795)@247
    assign leftShiftStage1Idx1_uid25796_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25795_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25790_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(BITSELECT,25789)@247
    assign leftShiftStage0Idx1Rng1_uid25790_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25790_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25790_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25791_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(BITJOIN,25790)@247
    assign leftShiftStage0Idx1_uid25791_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25790_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21179_dupName_343_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21178)@246
    assign rightShiftStage2Idx1Rng8_uid21179_dupName_343_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21181_dupName_343_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21180)@246
    assign rightShiftStage2Idx1_uid21181_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21179_dupName_343_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21174_dupName_343_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21173)@246
    assign rightShiftStage1Idx1Rng4_uid21174_dupName_343_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21176_dupName_343_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21175)@246
    assign rightShiftStage1Idx1_uid21176_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21174_dupName_343_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21169_dupName_343_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21168)@246
    assign rightShiftStage0Idx1Rng1_uid21169_dupName_343_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q[33:1];

    // rightShiftStage0Idx1_uid21171_dupName_343_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21170)@246
    assign rightShiftStage0Idx1_uid21171_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21169_dupName_343_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25782_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(BITSELECT,25781)@245
    assign leftShiftStage2Idx1Rng8_uid25782_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in = leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25782_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25782_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25783_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(BITJOIN,25782)@245
    assign leftShiftStage2Idx1_uid25783_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25782_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25777_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(BITSELECT,25776)@245
    assign leftShiftStage1Idx1Rng4_uid25777_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in = leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25777_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25777_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25778_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(BITJOIN,25777)@245
    assign leftShiftStage1Idx1_uid25778_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25777_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25772_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(BITSELECT,25771)@245
    assign leftShiftStage0Idx1Rng1_uid25772_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25772_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25772_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25773_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(BITJOIN,25772)@245
    assign leftShiftStage0Idx1_uid25773_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25772_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21117_dupName_339_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21116)@244
    assign rightShiftStage2Idx1Rng8_uid21117_dupName_339_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21119_dupName_339_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21118)@244
    assign rightShiftStage2Idx1_uid21119_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21117_dupName_339_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21112_dupName_339_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21111)@244
    assign rightShiftStage1Idx1Rng4_uid21112_dupName_339_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21114_dupName_339_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21113)@244
    assign rightShiftStage1Idx1_uid21114_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21112_dupName_339_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21107_dupName_339_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21106)@244
    assign rightShiftStage0Idx1Rng1_uid21107_dupName_339_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q[33:1];

    // rightShiftStage0Idx1_uid21109_dupName_339_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21108)@244
    assign rightShiftStage0Idx1_uid21109_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21107_dupName_339_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25764_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(BITSELECT,25763)@243
    assign leftShiftStage2Idx1Rng8_uid25764_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in = leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25764_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25764_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25765_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(BITJOIN,25764)@243
    assign leftShiftStage2Idx1_uid25765_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25764_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25759_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(BITSELECT,25758)@243
    assign leftShiftStage1Idx1Rng4_uid25759_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in = leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25759_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25759_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25760_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(BITJOIN,25759)@243
    assign leftShiftStage1Idx1_uid25760_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25759_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25754_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(BITSELECT,25753)@243
    assign leftShiftStage0Idx1Rng1_uid25754_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25754_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25754_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25755_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(BITJOIN,25754)@243
    assign leftShiftStage0Idx1_uid25755_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25754_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid21055_dupName_335_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21054)@242
    assign rightShiftStage2Idx1Rng8_uid21055_dupName_335_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid21057_dupName_335_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21056)@242
    assign rightShiftStage2Idx1_uid21057_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid21055_dupName_335_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid21050_dupName_335_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21049)@242
    assign rightShiftStage1Idx1Rng4_uid21050_dupName_335_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid21052_dupName_335_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21051)@242
    assign rightShiftStage1Idx1_uid21052_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid21050_dupName_335_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid21045_dupName_335_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21044)@242
    assign rightShiftStage0Idx1Rng1_uid21045_dupName_335_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q[33:1];

    // rightShiftStage0Idx1_uid21047_dupName_335_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21046)@242
    assign rightShiftStage0Idx1_uid21047_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid21045_dupName_335_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25746_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(BITSELECT,25745)@241
    assign leftShiftStage2Idx1Rng8_uid25746_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in = leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25746_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25746_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25747_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(BITJOIN,25746)@241
    assign leftShiftStage2Idx1_uid25747_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25746_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25741_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(BITSELECT,25740)@241
    assign leftShiftStage1Idx1Rng4_uid25741_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in = leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25741_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25741_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25742_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(BITJOIN,25741)@241
    assign leftShiftStage1Idx1_uid25742_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25741_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25736_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(BITSELECT,25735)@241
    assign leftShiftStage0Idx1Rng1_uid25736_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25736_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25736_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25737_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(BITJOIN,25736)@241
    assign leftShiftStage0Idx1_uid25737_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25736_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20993_dupName_331_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20992)@240
    assign rightShiftStage2Idx1Rng8_uid20993_dupName_331_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20995_dupName_331_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20994)@240
    assign rightShiftStage2Idx1_uid20995_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20993_dupName_331_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20988_dupName_331_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20987)@240
    assign rightShiftStage1Idx1Rng4_uid20988_dupName_331_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20990_dupName_331_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20989)@240
    assign rightShiftStage1Idx1_uid20990_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20988_dupName_331_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20983_dupName_331_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20982)@240
    assign rightShiftStage0Idx1Rng1_uid20983_dupName_331_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q[33:1];

    // rightShiftStage0Idx1_uid20985_dupName_331_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20984)@240
    assign rightShiftStage0Idx1_uid20985_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20983_dupName_331_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25728_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(BITSELECT,25727)@239
    assign leftShiftStage2Idx1Rng8_uid25728_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in = leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25728_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25728_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25729_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(BITJOIN,25728)@239
    assign leftShiftStage2Idx1_uid25729_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25728_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25723_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(BITSELECT,25722)@239
    assign leftShiftStage1Idx1Rng4_uid25723_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in = leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25723_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25723_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25724_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(BITJOIN,25723)@239
    assign leftShiftStage1Idx1_uid25724_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25723_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25718_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(BITSELECT,25717)@239
    assign leftShiftStage0Idx1Rng1_uid25718_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25718_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25718_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25719_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(BITJOIN,25718)@239
    assign leftShiftStage0Idx1_uid25719_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25718_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20931_dupName_327_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20930)@238
    assign rightShiftStage2Idx1Rng8_uid20931_dupName_327_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20933_dupName_327_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20932)@238
    assign rightShiftStage2Idx1_uid20933_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20931_dupName_327_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20926_dupName_327_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20925)@238
    assign rightShiftStage1Idx1Rng4_uid20926_dupName_327_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20928_dupName_327_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20927)@238
    assign rightShiftStage1Idx1_uid20928_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20926_dupName_327_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20921_dupName_327_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20920)@238
    assign rightShiftStage0Idx1Rng1_uid20921_dupName_327_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q[33:1];

    // rightShiftStage0Idx1_uid20923_dupName_327_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20922)@238
    assign rightShiftStage0Idx1_uid20923_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20921_dupName_327_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25710_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(BITSELECT,25709)@237
    assign leftShiftStage2Idx1Rng8_uid25710_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in = leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25710_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25710_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25711_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(BITJOIN,25710)@237
    assign leftShiftStage2Idx1_uid25711_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25710_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25705_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(BITSELECT,25704)@237
    assign leftShiftStage1Idx1Rng4_uid25705_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in = leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25705_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25705_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25706_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(BITJOIN,25705)@237
    assign leftShiftStage1Idx1_uid25706_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25705_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25700_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(BITSELECT,25699)@237
    assign leftShiftStage0Idx1Rng1_uid25700_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25700_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25700_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25701_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(BITJOIN,25700)@237
    assign leftShiftStage0Idx1_uid25701_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25700_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20869_dupName_323_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20868)@236
    assign rightShiftStage2Idx1Rng8_uid20869_dupName_323_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20871_dupName_323_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20870)@236
    assign rightShiftStage2Idx1_uid20871_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20869_dupName_323_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20864_dupName_323_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20863)@236
    assign rightShiftStage1Idx1Rng4_uid20864_dupName_323_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20866_dupName_323_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20865)@236
    assign rightShiftStage1Idx1_uid20866_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20864_dupName_323_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20859_dupName_323_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20858)@236
    assign rightShiftStage0Idx1Rng1_uid20859_dupName_323_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q[33:1];

    // rightShiftStage0Idx1_uid20861_dupName_323_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20860)@236
    assign rightShiftStage0Idx1_uid20861_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20859_dupName_323_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25692_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(BITSELECT,25691)@235
    assign leftShiftStage2Idx1Rng8_uid25692_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in = leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25692_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25692_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25693_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(BITJOIN,25692)@235
    assign leftShiftStage2Idx1_uid25693_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25692_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25687_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(BITSELECT,25686)@235
    assign leftShiftStage1Idx1Rng4_uid25687_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in = leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25687_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25687_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25688_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(BITJOIN,25687)@235
    assign leftShiftStage1Idx1_uid25688_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25687_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25682_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(BITSELECT,25681)@235
    assign leftShiftStage0Idx1Rng1_uid25682_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25682_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25682_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25683_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(BITJOIN,25682)@235
    assign leftShiftStage0Idx1_uid25683_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25682_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20807_dupName_319_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20806)@234
    assign rightShiftStage2Idx1Rng8_uid20807_dupName_319_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20809_dupName_319_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20808)@234
    assign rightShiftStage2Idx1_uid20809_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20807_dupName_319_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20802_dupName_319_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20801)@234
    assign rightShiftStage1Idx1Rng4_uid20802_dupName_319_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20804_dupName_319_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20803)@234
    assign rightShiftStage1Idx1_uid20804_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20802_dupName_319_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20797_dupName_319_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20796)@234
    assign rightShiftStage0Idx1Rng1_uid20797_dupName_319_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q[33:1];

    // rightShiftStage0Idx1_uid20799_dupName_319_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20798)@234
    assign rightShiftStage0Idx1_uid20799_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20797_dupName_319_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25674_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(BITSELECT,25673)@233
    assign leftShiftStage2Idx1Rng8_uid25674_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in = leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25674_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25674_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25675_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(BITJOIN,25674)@233
    assign leftShiftStage2Idx1_uid25675_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25674_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25669_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(BITSELECT,25668)@233
    assign leftShiftStage1Idx1Rng4_uid25669_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in = leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25669_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25669_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25670_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(BITJOIN,25669)@233
    assign leftShiftStage1Idx1_uid25670_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25669_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25664_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(BITSELECT,25663)@233
    assign leftShiftStage0Idx1Rng1_uid25664_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25664_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25664_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25665_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(BITJOIN,25664)@233
    assign leftShiftStage0Idx1_uid25665_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25664_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20745_dupName_315_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20744)@232
    assign rightShiftStage2Idx1Rng8_uid20745_dupName_315_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20747_dupName_315_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20746)@232
    assign rightShiftStage2Idx1_uid20747_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20745_dupName_315_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20740_dupName_315_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20739)@232
    assign rightShiftStage1Idx1Rng4_uid20740_dupName_315_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20742_dupName_315_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20741)@232
    assign rightShiftStage1Idx1_uid20742_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20740_dupName_315_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20735_dupName_315_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20734)@232
    assign rightShiftStage0Idx1Rng1_uid20735_dupName_315_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q[33:1];

    // rightShiftStage0Idx1_uid20737_dupName_315_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20736)@232
    assign rightShiftStage0Idx1_uid20737_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20735_dupName_315_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25638_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(BITSELECT,25637)@231
    assign leftShiftStage2Idx1Rng8_uid25638_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in = leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25638_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25638_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25639_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(BITJOIN,25638)@231
    assign leftShiftStage2Idx1_uid25639_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25638_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25633_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(BITSELECT,25632)@231
    assign leftShiftStage1Idx1Rng4_uid25633_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in = leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25633_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25633_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25634_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(BITJOIN,25633)@231
    assign leftShiftStage1Idx1_uid25634_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25633_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25628_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(BITSELECT,25627)@231
    assign leftShiftStage0Idx1Rng1_uid25628_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25628_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25628_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25629_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(BITJOIN,25628)@231
    assign leftShiftStage0Idx1_uid25629_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25628_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20683_dupName_311_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20682)@230
    assign rightShiftStage2Idx1Rng8_uid20683_dupName_311_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20685_dupName_311_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20684)@230
    assign rightShiftStage2Idx1_uid20685_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20683_dupName_311_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20678_dupName_311_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20677)@230
    assign rightShiftStage1Idx1Rng4_uid20678_dupName_311_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20680_dupName_311_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20679)@230
    assign rightShiftStage1Idx1_uid20680_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20678_dupName_311_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20673_dupName_311_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20672)@230
    assign rightShiftStage0Idx1Rng1_uid20673_dupName_311_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q[33:1];

    // rightShiftStage0Idx1_uid20675_dupName_311_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20674)@230
    assign rightShiftStage0Idx1_uid20675_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20673_dupName_311_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25620_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(BITSELECT,25619)@229
    assign leftShiftStage2Idx1Rng8_uid25620_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in = leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25620_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25620_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25621_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(BITJOIN,25620)@229
    assign leftShiftStage2Idx1_uid25621_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25620_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25615_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(BITSELECT,25614)@229
    assign leftShiftStage1Idx1Rng4_uid25615_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in = leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25615_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25615_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25616_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(BITJOIN,25615)@229
    assign leftShiftStage1Idx1_uid25616_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25615_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25610_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(BITSELECT,25609)@229
    assign leftShiftStage0Idx1Rng1_uid25610_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25610_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25610_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25611_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(BITJOIN,25610)@229
    assign leftShiftStage0Idx1_uid25611_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25610_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20621_dupName_307_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20620)@228
    assign rightShiftStage2Idx1Rng8_uid20621_dupName_307_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20623_dupName_307_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20622)@228
    assign rightShiftStage2Idx1_uid20623_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20621_dupName_307_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20616_dupName_307_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20615)@228
    assign rightShiftStage1Idx1Rng4_uid20616_dupName_307_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20618_dupName_307_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20617)@228
    assign rightShiftStage1Idx1_uid20618_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20616_dupName_307_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20611_dupName_307_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20610)@228
    assign rightShiftStage0Idx1Rng1_uid20611_dupName_307_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q[33:1];

    // rightShiftStage0Idx1_uid20613_dupName_307_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20612)@228
    assign rightShiftStage0Idx1_uid20613_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20611_dupName_307_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25602_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(BITSELECT,25601)@227
    assign leftShiftStage2Idx1Rng8_uid25602_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in = leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25602_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25602_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25603_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(BITJOIN,25602)@227
    assign leftShiftStage2Idx1_uid25603_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25602_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25597_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(BITSELECT,25596)@227
    assign leftShiftStage1Idx1Rng4_uid25597_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in = leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25597_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25597_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25598_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(BITJOIN,25597)@227
    assign leftShiftStage1Idx1_uid25598_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25597_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25592_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(BITSELECT,25591)@227
    assign leftShiftStage0Idx1Rng1_uid25592_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25592_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25592_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25593_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(BITJOIN,25592)@227
    assign leftShiftStage0Idx1_uid25593_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25592_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20559_dupName_303_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20558)@226
    assign rightShiftStage2Idx1Rng8_uid20559_dupName_303_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20561_dupName_303_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20560)@226
    assign rightShiftStage2Idx1_uid20561_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20559_dupName_303_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20554_dupName_303_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20553)@226
    assign rightShiftStage1Idx1Rng4_uid20554_dupName_303_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20556_dupName_303_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20555)@226
    assign rightShiftStage1Idx1_uid20556_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20554_dupName_303_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20549_dupName_303_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20548)@226
    assign rightShiftStage0Idx1Rng1_uid20549_dupName_303_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q[33:1];

    // rightShiftStage0Idx1_uid20551_dupName_303_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20550)@226
    assign rightShiftStage0Idx1_uid20551_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20549_dupName_303_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25584_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(BITSELECT,25583)@225
    assign leftShiftStage2Idx1Rng8_uid25584_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in = leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25584_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25584_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25585_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(BITJOIN,25584)@225
    assign leftShiftStage2Idx1_uid25585_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25584_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25579_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(BITSELECT,25578)@225
    assign leftShiftStage1Idx1Rng4_uid25579_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in = leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25579_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25579_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25580_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(BITJOIN,25579)@225
    assign leftShiftStage1Idx1_uid25580_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25579_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25574_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(BITSELECT,25573)@225
    assign leftShiftStage0Idx1Rng1_uid25574_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25574_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25574_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25575_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(BITJOIN,25574)@225
    assign leftShiftStage0Idx1_uid25575_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25574_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20497_dupName_299_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20496)@224
    assign rightShiftStage2Idx1Rng8_uid20497_dupName_299_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20499_dupName_299_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20498)@224
    assign rightShiftStage2Idx1_uid20499_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20497_dupName_299_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20492_dupName_299_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20491)@224
    assign rightShiftStage1Idx1Rng4_uid20492_dupName_299_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20494_dupName_299_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20493)@224
    assign rightShiftStage1Idx1_uid20494_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20492_dupName_299_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20487_dupName_299_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20486)@224
    assign rightShiftStage0Idx1Rng1_uid20487_dupName_299_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q[33:1];

    // rightShiftStage0Idx1_uid20489_dupName_299_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20488)@224
    assign rightShiftStage0Idx1_uid20489_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20487_dupName_299_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25566_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(BITSELECT,25565)@223
    assign leftShiftStage2Idx1Rng8_uid25566_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in = leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25566_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25566_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25567_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(BITJOIN,25566)@223
    assign leftShiftStage2Idx1_uid25567_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25566_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25561_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(BITSELECT,25560)@223
    assign leftShiftStage1Idx1Rng4_uid25561_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in = leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25561_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25561_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25562_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(BITJOIN,25561)@223
    assign leftShiftStage1Idx1_uid25562_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25561_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25556_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(BITSELECT,25555)@223
    assign leftShiftStage0Idx1Rng1_uid25556_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25556_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25556_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25557_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(BITJOIN,25556)@223
    assign leftShiftStage0Idx1_uid25557_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25556_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20435_dupName_295_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20434)@222
    assign rightShiftStage2Idx1Rng8_uid20435_dupName_295_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20437_dupName_295_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20436)@222
    assign rightShiftStage2Idx1_uid20437_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20435_dupName_295_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20430_dupName_295_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20429)@222
    assign rightShiftStage1Idx1Rng4_uid20430_dupName_295_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20432_dupName_295_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20431)@222
    assign rightShiftStage1Idx1_uid20432_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20430_dupName_295_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20425_dupName_295_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20424)@222
    assign rightShiftStage0Idx1Rng1_uid20425_dupName_295_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q[33:1];

    // rightShiftStage0Idx1_uid20427_dupName_295_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20426)@222
    assign rightShiftStage0Idx1_uid20427_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20425_dupName_295_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25548_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(BITSELECT,25547)@221
    assign leftShiftStage2Idx1Rng8_uid25548_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in = leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25548_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25548_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25549_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(BITJOIN,25548)@221
    assign leftShiftStage2Idx1_uid25549_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25548_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25543_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(BITSELECT,25542)@221
    assign leftShiftStage1Idx1Rng4_uid25543_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in = leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25543_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25543_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25544_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(BITJOIN,25543)@221
    assign leftShiftStage1Idx1_uid25544_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25543_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25538_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(BITSELECT,25537)@221
    assign leftShiftStage0Idx1Rng1_uid25538_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25538_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25538_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25539_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(BITJOIN,25538)@221
    assign leftShiftStage0Idx1_uid25539_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25538_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20373_dupName_291_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20372)@220
    assign rightShiftStage2Idx1Rng8_uid20373_dupName_291_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20375_dupName_291_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20374)@220
    assign rightShiftStage2Idx1_uid20375_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20373_dupName_291_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20368_dupName_291_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20367)@220
    assign rightShiftStage1Idx1Rng4_uid20368_dupName_291_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20370_dupName_291_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20369)@220
    assign rightShiftStage1Idx1_uid20370_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20368_dupName_291_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20363_dupName_291_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20362)@220
    assign rightShiftStage0Idx1Rng1_uid20363_dupName_291_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q[33:1];

    // rightShiftStage0Idx1_uid20365_dupName_291_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20364)@220
    assign rightShiftStage0Idx1_uid20365_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20363_dupName_291_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25530_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(BITSELECT,25529)@219
    assign leftShiftStage2Idx1Rng8_uid25530_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in = leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25530_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25530_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25531_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(BITJOIN,25530)@219
    assign leftShiftStage2Idx1_uid25531_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25530_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25525_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(BITSELECT,25524)@219
    assign leftShiftStage1Idx1Rng4_uid25525_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in = leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25525_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25525_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25526_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(BITJOIN,25525)@219
    assign leftShiftStage1Idx1_uid25526_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25525_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25520_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(BITSELECT,25519)@219
    assign leftShiftStage0Idx1Rng1_uid25520_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25520_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25520_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25521_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(BITJOIN,25520)@219
    assign leftShiftStage0Idx1_uid25521_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25520_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20311_dupName_287_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20310)@218
    assign rightShiftStage2Idx1Rng8_uid20311_dupName_287_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20313_dupName_287_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20312)@218
    assign rightShiftStage2Idx1_uid20313_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20311_dupName_287_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20306_dupName_287_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20305)@218
    assign rightShiftStage1Idx1Rng4_uid20306_dupName_287_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20308_dupName_287_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20307)@218
    assign rightShiftStage1Idx1_uid20308_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20306_dupName_287_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20301_dupName_287_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20300)@218
    assign rightShiftStage0Idx1Rng1_uid20301_dupName_287_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q[33:1];

    // rightShiftStage0Idx1_uid20303_dupName_287_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20302)@218
    assign rightShiftStage0Idx1_uid20303_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20301_dupName_287_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25512_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(BITSELECT,25511)@217
    assign leftShiftStage2Idx1Rng8_uid25512_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in = leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25512_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25512_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25513_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(BITJOIN,25512)@217
    assign leftShiftStage2Idx1_uid25513_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25512_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25507_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(BITSELECT,25506)@217
    assign leftShiftStage1Idx1Rng4_uid25507_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in = leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25507_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25507_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25508_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(BITJOIN,25507)@217
    assign leftShiftStage1Idx1_uid25508_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25507_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25502_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(BITSELECT,25501)@217
    assign leftShiftStage0Idx1Rng1_uid25502_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25502_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25502_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25503_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(BITJOIN,25502)@217
    assign leftShiftStage0Idx1_uid25503_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25502_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20249_dupName_283_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20248)@216
    assign rightShiftStage2Idx1Rng8_uid20249_dupName_283_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20251_dupName_283_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20250)@216
    assign rightShiftStage2Idx1_uid20251_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20249_dupName_283_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20244_dupName_283_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20243)@216
    assign rightShiftStage1Idx1Rng4_uid20244_dupName_283_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20246_dupName_283_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20245)@216
    assign rightShiftStage1Idx1_uid20246_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20244_dupName_283_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20239_dupName_283_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20238)@216
    assign rightShiftStage0Idx1Rng1_uid20239_dupName_283_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q[33:1];

    // rightShiftStage0Idx1_uid20241_dupName_283_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20240)@216
    assign rightShiftStage0Idx1_uid20241_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20239_dupName_283_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25494_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(BITSELECT,25493)@215
    assign leftShiftStage2Idx1Rng8_uid25494_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in = leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25494_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25494_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25495_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(BITJOIN,25494)@215
    assign leftShiftStage2Idx1_uid25495_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25494_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25489_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(BITSELECT,25488)@215
    assign leftShiftStage1Idx1Rng4_uid25489_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in = leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25489_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25489_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25490_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(BITJOIN,25489)@215
    assign leftShiftStage1Idx1_uid25490_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25489_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25484_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(BITSELECT,25483)@215
    assign leftShiftStage0Idx1Rng1_uid25484_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25484_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25484_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25485_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(BITJOIN,25484)@215
    assign leftShiftStage0Idx1_uid25485_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25484_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20187_dupName_279_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20186)@214
    assign rightShiftStage2Idx1Rng8_uid20187_dupName_279_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20189_dupName_279_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20188)@214
    assign rightShiftStage2Idx1_uid20189_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20187_dupName_279_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20182_dupName_279_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20181)@214
    assign rightShiftStage1Idx1Rng4_uid20182_dupName_279_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20184_dupName_279_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20183)@214
    assign rightShiftStage1Idx1_uid20184_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20182_dupName_279_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20177_dupName_279_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20176)@214
    assign rightShiftStage0Idx1Rng1_uid20177_dupName_279_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q[33:1];

    // rightShiftStage0Idx1_uid20179_dupName_279_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20178)@214
    assign rightShiftStage0Idx1_uid20179_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20177_dupName_279_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25476_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(BITSELECT,25475)@213
    assign leftShiftStage2Idx1Rng8_uid25476_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in = leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25476_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25476_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25477_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(BITJOIN,25476)@213
    assign leftShiftStage2Idx1_uid25477_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25476_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25471_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(BITSELECT,25470)@213
    assign leftShiftStage1Idx1Rng4_uid25471_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in = leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25471_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25471_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25472_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(BITJOIN,25471)@213
    assign leftShiftStage1Idx1_uid25472_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25471_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25466_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(BITSELECT,25465)@213
    assign leftShiftStage0Idx1Rng1_uid25466_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25466_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25466_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25467_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(BITJOIN,25466)@213
    assign leftShiftStage0Idx1_uid25467_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25466_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20125_dupName_275_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20124)@212
    assign rightShiftStage2Idx1Rng8_uid20125_dupName_275_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20127_dupName_275_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20126)@212
    assign rightShiftStage2Idx1_uid20127_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20125_dupName_275_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20120_dupName_275_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20119)@212
    assign rightShiftStage1Idx1Rng4_uid20120_dupName_275_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20122_dupName_275_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20121)@212
    assign rightShiftStage1Idx1_uid20122_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20120_dupName_275_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20115_dupName_275_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20114)@212
    assign rightShiftStage0Idx1Rng1_uid20115_dupName_275_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q[33:1];

    // rightShiftStage0Idx1_uid20117_dupName_275_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20116)@212
    assign rightShiftStage0Idx1_uid20117_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20115_dupName_275_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25440_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(BITSELECT,25439)@211
    assign leftShiftStage2Idx1Rng8_uid25440_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in = leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25440_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25440_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25441_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(BITJOIN,25440)@211
    assign leftShiftStage2Idx1_uid25441_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25440_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25435_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(BITSELECT,25434)@211
    assign leftShiftStage1Idx1Rng4_uid25435_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in = leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25435_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25435_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25436_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(BITJOIN,25435)@211
    assign leftShiftStage1Idx1_uid25436_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25435_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25430_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(BITSELECT,25429)@211
    assign leftShiftStage0Idx1Rng1_uid25430_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25430_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25430_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25431_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(BITJOIN,25430)@211
    assign leftShiftStage0Idx1_uid25431_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25430_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20063_dupName_271_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20062)@210
    assign rightShiftStage2Idx1Rng8_uid20063_dupName_271_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20065_dupName_271_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20064)@210
    assign rightShiftStage2Idx1_uid20065_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20063_dupName_271_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid20058_dupName_271_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20057)@210
    assign rightShiftStage1Idx1Rng4_uid20058_dupName_271_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid20060_dupName_271_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20059)@210
    assign rightShiftStage1Idx1_uid20060_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid20058_dupName_271_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid20053_dupName_271_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20052)@210
    assign rightShiftStage0Idx1Rng1_uid20053_dupName_271_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q[33:1];

    // rightShiftStage0Idx1_uid20055_dupName_271_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20054)@210
    assign rightShiftStage0Idx1_uid20055_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid20053_dupName_271_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25422_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(BITSELECT,25421)@209
    assign leftShiftStage2Idx1Rng8_uid25422_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in = leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25422_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25422_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25423_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(BITJOIN,25422)@209
    assign leftShiftStage2Idx1_uid25423_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25422_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25417_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(BITSELECT,25416)@209
    assign leftShiftStage1Idx1Rng4_uid25417_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in = leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25417_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25417_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25418_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(BITJOIN,25417)@209
    assign leftShiftStage1Idx1_uid25418_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25417_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25412_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(BITSELECT,25411)@209
    assign leftShiftStage0Idx1Rng1_uid25412_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25412_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25412_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25413_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(BITJOIN,25412)@209
    assign leftShiftStage0Idx1_uid25413_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25412_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid20001_dupName_267_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20000)@208
    assign rightShiftStage2Idx1Rng8_uid20001_dupName_267_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid20003_dupName_267_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20002)@208
    assign rightShiftStage2Idx1_uid20003_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid20001_dupName_267_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19996_dupName_267_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19995)@208
    assign rightShiftStage1Idx1Rng4_uid19996_dupName_267_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19998_dupName_267_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19997)@208
    assign rightShiftStage1Idx1_uid19998_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19996_dupName_267_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19991_dupName_267_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19990)@208
    assign rightShiftStage0Idx1Rng1_uid19991_dupName_267_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q[33:1];

    // rightShiftStage0Idx1_uid19993_dupName_267_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19992)@208
    assign rightShiftStage0Idx1_uid19993_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19991_dupName_267_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25404_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(BITSELECT,25403)@207
    assign leftShiftStage2Idx1Rng8_uid25404_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in = leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25404_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25404_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25405_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(BITJOIN,25404)@207
    assign leftShiftStage2Idx1_uid25405_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25404_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25399_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(BITSELECT,25398)@207
    assign leftShiftStage1Idx1Rng4_uid25399_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in = leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25399_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25399_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25400_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(BITJOIN,25399)@207
    assign leftShiftStage1Idx1_uid25400_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25399_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25394_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(BITSELECT,25393)@207
    assign leftShiftStage0Idx1Rng1_uid25394_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25394_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25394_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25395_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(BITJOIN,25394)@207
    assign leftShiftStage0Idx1_uid25395_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25394_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19939_dupName_263_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19938)@206
    assign rightShiftStage2Idx1Rng8_uid19939_dupName_263_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19941_dupName_263_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19940)@206
    assign rightShiftStage2Idx1_uid19941_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19939_dupName_263_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19934_dupName_263_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19933)@206
    assign rightShiftStage1Idx1Rng4_uid19934_dupName_263_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19936_dupName_263_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19935)@206
    assign rightShiftStage1Idx1_uid19936_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19934_dupName_263_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19929_dupName_263_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19928)@206
    assign rightShiftStage0Idx1Rng1_uid19929_dupName_263_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q[33:1];

    // rightShiftStage0Idx1_uid19931_dupName_263_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19930)@206
    assign rightShiftStage0Idx1_uid19931_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19929_dupName_263_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25386_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(BITSELECT,25385)@205
    assign leftShiftStage2Idx1Rng8_uid25386_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in = leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25386_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25386_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25387_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(BITJOIN,25386)@205
    assign leftShiftStage2Idx1_uid25387_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25386_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25381_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(BITSELECT,25380)@205
    assign leftShiftStage1Idx1Rng4_uid25381_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in = leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25381_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25381_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25382_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(BITJOIN,25381)@205
    assign leftShiftStage1Idx1_uid25382_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25381_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25376_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(BITSELECT,25375)@205
    assign leftShiftStage0Idx1Rng1_uid25376_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25376_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25376_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25377_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(BITJOIN,25376)@205
    assign leftShiftStage0Idx1_uid25377_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25376_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19877_dupName_259_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19876)@204
    assign rightShiftStage2Idx1Rng8_uid19877_dupName_259_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19879_dupName_259_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19878)@204
    assign rightShiftStage2Idx1_uid19879_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19877_dupName_259_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19872_dupName_259_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19871)@204
    assign rightShiftStage1Idx1Rng4_uid19872_dupName_259_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19874_dupName_259_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19873)@204
    assign rightShiftStage1Idx1_uid19874_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19872_dupName_259_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19867_dupName_259_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19866)@204
    assign rightShiftStage0Idx1Rng1_uid19867_dupName_259_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q[33:1];

    // rightShiftStage0Idx1_uid19869_dupName_259_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19868)@204
    assign rightShiftStage0Idx1_uid19869_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19867_dupName_259_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25368_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(BITSELECT,25367)@203
    assign leftShiftStage2Idx1Rng8_uid25368_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in = leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25368_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25368_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25369_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(BITJOIN,25368)@203
    assign leftShiftStage2Idx1_uid25369_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25368_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25363_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(BITSELECT,25362)@203
    assign leftShiftStage1Idx1Rng4_uid25363_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in = leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25363_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25363_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25364_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(BITJOIN,25363)@203
    assign leftShiftStage1Idx1_uid25364_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25363_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25358_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(BITSELECT,25357)@203
    assign leftShiftStage0Idx1Rng1_uid25358_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25358_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25358_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25359_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(BITJOIN,25358)@203
    assign leftShiftStage0Idx1_uid25359_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25358_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19815_dupName_255_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19814)@202
    assign rightShiftStage2Idx1Rng8_uid19815_dupName_255_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19817_dupName_255_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19816)@202
    assign rightShiftStage2Idx1_uid19817_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19815_dupName_255_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19810_dupName_255_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19809)@202
    assign rightShiftStage1Idx1Rng4_uid19810_dupName_255_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19812_dupName_255_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19811)@202
    assign rightShiftStage1Idx1_uid19812_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19810_dupName_255_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19805_dupName_255_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19804)@202
    assign rightShiftStage0Idx1Rng1_uid19805_dupName_255_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q[33:1];

    // rightShiftStage0Idx1_uid19807_dupName_255_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19806)@202
    assign rightShiftStage0Idx1_uid19807_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19805_dupName_255_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25350_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(BITSELECT,25349)@201
    assign leftShiftStage2Idx1Rng8_uid25350_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in = leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25350_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25350_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25351_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(BITJOIN,25350)@201
    assign leftShiftStage2Idx1_uid25351_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25350_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25345_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(BITSELECT,25344)@201
    assign leftShiftStage1Idx1Rng4_uid25345_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in = leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25345_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25345_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25346_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(BITJOIN,25345)@201
    assign leftShiftStage1Idx1_uid25346_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25345_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25340_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(BITSELECT,25339)@201
    assign leftShiftStage0Idx1Rng1_uid25340_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25340_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25340_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25341_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(BITJOIN,25340)@201
    assign leftShiftStage0Idx1_uid25341_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25340_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19753_dupName_251_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19752)@200
    assign rightShiftStage2Idx1Rng8_uid19753_dupName_251_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19755_dupName_251_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19754)@200
    assign rightShiftStage2Idx1_uid19755_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19753_dupName_251_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19748_dupName_251_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19747)@200
    assign rightShiftStage1Idx1Rng4_uid19748_dupName_251_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19750_dupName_251_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19749)@200
    assign rightShiftStage1Idx1_uid19750_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19748_dupName_251_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19743_dupName_251_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19742)@200
    assign rightShiftStage0Idx1Rng1_uid19743_dupName_251_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q[33:1];

    // rightShiftStage0Idx1_uid19745_dupName_251_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19744)@200
    assign rightShiftStage0Idx1_uid19745_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19743_dupName_251_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25332_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(BITSELECT,25331)@199
    assign leftShiftStage2Idx1Rng8_uid25332_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in = leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25332_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25332_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25333_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(BITJOIN,25332)@199
    assign leftShiftStage2Idx1_uid25333_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25332_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25327_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(BITSELECT,25326)@199
    assign leftShiftStage1Idx1Rng4_uid25327_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in = leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25327_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25327_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25328_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(BITJOIN,25327)@199
    assign leftShiftStage1Idx1_uid25328_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25327_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25322_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(BITSELECT,25321)@199
    assign leftShiftStage0Idx1Rng1_uid25322_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25322_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25322_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25323_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(BITJOIN,25322)@199
    assign leftShiftStage0Idx1_uid25323_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25322_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19691_dupName_247_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19690)@198
    assign rightShiftStage2Idx1Rng8_uid19691_dupName_247_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19693_dupName_247_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19692)@198
    assign rightShiftStage2Idx1_uid19693_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19691_dupName_247_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19686_dupName_247_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19685)@198
    assign rightShiftStage1Idx1Rng4_uid19686_dupName_247_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19688_dupName_247_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19687)@198
    assign rightShiftStage1Idx1_uid19688_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19686_dupName_247_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19681_dupName_247_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19680)@198
    assign rightShiftStage0Idx1Rng1_uid19681_dupName_247_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q[33:1];

    // rightShiftStage0Idx1_uid19683_dupName_247_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19682)@198
    assign rightShiftStage0Idx1_uid19683_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19681_dupName_247_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25314_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(BITSELECT,25313)@197
    assign leftShiftStage2Idx1Rng8_uid25314_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in = leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25314_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25314_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25315_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(BITJOIN,25314)@197
    assign leftShiftStage2Idx1_uid25315_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25314_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25309_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(BITSELECT,25308)@197
    assign leftShiftStage1Idx1Rng4_uid25309_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in = leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25309_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25309_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25310_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(BITJOIN,25309)@197
    assign leftShiftStage1Idx1_uid25310_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25309_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25304_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(BITSELECT,25303)@197
    assign leftShiftStage0Idx1Rng1_uid25304_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25304_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25304_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25305_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(BITJOIN,25304)@197
    assign leftShiftStage0Idx1_uid25305_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25304_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19629_dupName_243_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19628)@196
    assign rightShiftStage2Idx1Rng8_uid19629_dupName_243_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19631_dupName_243_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19630)@196
    assign rightShiftStage2Idx1_uid19631_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19629_dupName_243_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19624_dupName_243_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19623)@196
    assign rightShiftStage1Idx1Rng4_uid19624_dupName_243_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19626_dupName_243_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19625)@196
    assign rightShiftStage1Idx1_uid19626_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19624_dupName_243_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19619_dupName_243_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19618)@196
    assign rightShiftStage0Idx1Rng1_uid19619_dupName_243_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q[33:1];

    // rightShiftStage0Idx1_uid19621_dupName_243_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19620)@196
    assign rightShiftStage0Idx1_uid19621_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19619_dupName_243_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25296_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(BITSELECT,25295)@195
    assign leftShiftStage2Idx1Rng8_uid25296_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in = leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25296_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25296_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25297_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(BITJOIN,25296)@195
    assign leftShiftStage2Idx1_uid25297_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25296_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25291_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(BITSELECT,25290)@195
    assign leftShiftStage1Idx1Rng4_uid25291_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in = leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25291_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25291_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25292_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(BITJOIN,25291)@195
    assign leftShiftStage1Idx1_uid25292_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25291_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25286_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(BITSELECT,25285)@195
    assign leftShiftStage0Idx1Rng1_uid25286_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25286_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25286_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25287_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(BITJOIN,25286)@195
    assign leftShiftStage0Idx1_uid25287_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25286_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19567_dupName_239_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19566)@194
    assign rightShiftStage2Idx1Rng8_uid19567_dupName_239_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19569_dupName_239_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19568)@194
    assign rightShiftStage2Idx1_uid19569_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19567_dupName_239_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19562_dupName_239_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19561)@194
    assign rightShiftStage1Idx1Rng4_uid19562_dupName_239_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19564_dupName_239_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19563)@194
    assign rightShiftStage1Idx1_uid19564_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19562_dupName_239_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19557_dupName_239_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19556)@194
    assign rightShiftStage0Idx1Rng1_uid19557_dupName_239_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q[33:1];

    // rightShiftStage0Idx1_uid19559_dupName_239_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19558)@194
    assign rightShiftStage0Idx1_uid19559_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19557_dupName_239_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25278_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(BITSELECT,25277)@193
    assign leftShiftStage2Idx1Rng8_uid25278_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in = leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25278_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25278_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25279_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(BITJOIN,25278)@193
    assign leftShiftStage2Idx1_uid25279_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25278_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25273_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(BITSELECT,25272)@193
    assign leftShiftStage1Idx1Rng4_uid25273_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in = leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25273_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25273_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25274_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(BITJOIN,25273)@193
    assign leftShiftStage1Idx1_uid25274_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25273_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25268_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(BITSELECT,25267)@193
    assign leftShiftStage0Idx1Rng1_uid25268_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25268_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25268_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25269_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(BITJOIN,25268)@193
    assign leftShiftStage0Idx1_uid25269_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25268_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19505_dupName_235_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19504)@192
    assign rightShiftStage2Idx1Rng8_uid19505_dupName_235_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19507_dupName_235_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19506)@192
    assign rightShiftStage2Idx1_uid19507_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19505_dupName_235_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19500_dupName_235_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19499)@192
    assign rightShiftStage1Idx1Rng4_uid19500_dupName_235_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19502_dupName_235_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19501)@192
    assign rightShiftStage1Idx1_uid19502_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19500_dupName_235_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19495_dupName_235_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19494)@192
    assign rightShiftStage0Idx1Rng1_uid19495_dupName_235_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q[33:1];

    // rightShiftStage0Idx1_uid19497_dupName_235_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19496)@192
    assign rightShiftStage0Idx1_uid19497_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19495_dupName_235_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25242_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(BITSELECT,25241)@191
    assign leftShiftStage2Idx1Rng8_uid25242_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in = leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25242_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25242_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25243_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(BITJOIN,25242)@191
    assign leftShiftStage2Idx1_uid25243_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25242_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25237_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(BITSELECT,25236)@191
    assign leftShiftStage1Idx1Rng4_uid25237_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in = leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25237_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25237_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25238_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(BITJOIN,25237)@191
    assign leftShiftStage1Idx1_uid25238_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25237_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25232_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(BITSELECT,25231)@191
    assign leftShiftStage0Idx1Rng1_uid25232_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25232_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25232_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25233_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(BITJOIN,25232)@191
    assign leftShiftStage0Idx1_uid25233_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25232_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19443_dupName_231_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19442)@190
    assign rightShiftStage2Idx1Rng8_uid19443_dupName_231_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19445_dupName_231_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19444)@190
    assign rightShiftStage2Idx1_uid19445_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19443_dupName_231_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19438_dupName_231_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19437)@190
    assign rightShiftStage1Idx1Rng4_uid19438_dupName_231_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19440_dupName_231_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19439)@190
    assign rightShiftStage1Idx1_uid19440_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19438_dupName_231_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19433_dupName_231_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19432)@190
    assign rightShiftStage0Idx1Rng1_uid19433_dupName_231_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q[33:1];

    // rightShiftStage0Idx1_uid19435_dupName_231_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19434)@190
    assign rightShiftStage0Idx1_uid19435_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19433_dupName_231_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25224_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(BITSELECT,25223)@189
    assign leftShiftStage2Idx1Rng8_uid25224_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in = leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25224_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25224_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25225_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(BITJOIN,25224)@189
    assign leftShiftStage2Idx1_uid25225_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25224_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25219_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(BITSELECT,25218)@189
    assign leftShiftStage1Idx1Rng4_uid25219_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in = leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25219_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25219_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25220_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(BITJOIN,25219)@189
    assign leftShiftStage1Idx1_uid25220_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25219_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25214_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(BITSELECT,25213)@189
    assign leftShiftStage0Idx1Rng1_uid25214_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25214_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25214_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25215_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(BITJOIN,25214)@189
    assign leftShiftStage0Idx1_uid25215_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25214_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19381_dupName_227_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19380)@188
    assign rightShiftStage2Idx1Rng8_uid19381_dupName_227_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19383_dupName_227_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19382)@188
    assign rightShiftStage2Idx1_uid19383_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19381_dupName_227_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19376_dupName_227_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19375)@188
    assign rightShiftStage1Idx1Rng4_uid19376_dupName_227_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19378_dupName_227_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19377)@188
    assign rightShiftStage1Idx1_uid19378_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19376_dupName_227_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19371_dupName_227_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19370)@188
    assign rightShiftStage0Idx1Rng1_uid19371_dupName_227_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q[33:1];

    // rightShiftStage0Idx1_uid19373_dupName_227_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19372)@188
    assign rightShiftStage0Idx1_uid19373_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19371_dupName_227_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25206_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(BITSELECT,25205)@187
    assign leftShiftStage2Idx1Rng8_uid25206_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in = leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25206_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25206_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25207_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(BITJOIN,25206)@187
    assign leftShiftStage2Idx1_uid25207_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25206_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25201_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(BITSELECT,25200)@187
    assign leftShiftStage1Idx1Rng4_uid25201_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in = leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25201_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25201_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25202_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(BITJOIN,25201)@187
    assign leftShiftStage1Idx1_uid25202_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25201_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25196_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(BITSELECT,25195)@187
    assign leftShiftStage0Idx1Rng1_uid25196_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25196_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25196_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25197_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(BITJOIN,25196)@187
    assign leftShiftStage0Idx1_uid25197_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25196_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19319_dupName_223_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19318)@186
    assign rightShiftStage2Idx1Rng8_uid19319_dupName_223_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19321_dupName_223_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19320)@186
    assign rightShiftStage2Idx1_uid19321_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19319_dupName_223_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19314_dupName_223_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19313)@186
    assign rightShiftStage1Idx1Rng4_uid19314_dupName_223_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19316_dupName_223_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19315)@186
    assign rightShiftStage1Idx1_uid19316_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19314_dupName_223_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19309_dupName_223_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19308)@186
    assign rightShiftStage0Idx1Rng1_uid19309_dupName_223_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q[33:1];

    // rightShiftStage0Idx1_uid19311_dupName_223_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19310)@186
    assign rightShiftStage0Idx1_uid19311_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19309_dupName_223_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25188_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(BITSELECT,25187)@185
    assign leftShiftStage2Idx1Rng8_uid25188_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in = leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25188_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25188_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25189_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(BITJOIN,25188)@185
    assign leftShiftStage2Idx1_uid25189_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25188_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25183_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(BITSELECT,25182)@185
    assign leftShiftStage1Idx1Rng4_uid25183_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in = leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25183_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25183_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25184_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(BITJOIN,25183)@185
    assign leftShiftStage1Idx1_uid25184_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25183_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25178_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(BITSELECT,25177)@185
    assign leftShiftStage0Idx1Rng1_uid25178_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25178_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25178_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25179_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(BITJOIN,25178)@185
    assign leftShiftStage0Idx1_uid25179_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25178_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19257_dupName_219_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19256)@184
    assign rightShiftStage2Idx1Rng8_uid19257_dupName_219_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19259_dupName_219_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19258)@184
    assign rightShiftStage2Idx1_uid19259_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19257_dupName_219_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19252_dupName_219_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19251)@184
    assign rightShiftStage1Idx1Rng4_uid19252_dupName_219_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19254_dupName_219_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19253)@184
    assign rightShiftStage1Idx1_uid19254_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19252_dupName_219_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19247_dupName_219_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19246)@184
    assign rightShiftStage0Idx1Rng1_uid19247_dupName_219_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q[33:1];

    // rightShiftStage0Idx1_uid19249_dupName_219_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19248)@184
    assign rightShiftStage0Idx1_uid19249_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19247_dupName_219_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25170_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(BITSELECT,25169)@183
    assign leftShiftStage2Idx1Rng8_uid25170_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in = leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25170_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25170_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25171_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(BITJOIN,25170)@183
    assign leftShiftStage2Idx1_uid25171_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25170_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25165_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(BITSELECT,25164)@183
    assign leftShiftStage1Idx1Rng4_uid25165_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in = leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25165_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25165_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25166_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(BITJOIN,25165)@183
    assign leftShiftStage1Idx1_uid25166_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25165_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25160_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(BITSELECT,25159)@183
    assign leftShiftStage0Idx1Rng1_uid25160_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25160_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25160_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25161_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(BITJOIN,25160)@183
    assign leftShiftStage0Idx1_uid25161_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25160_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19195_dupName_215_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19194)@182
    assign rightShiftStage2Idx1Rng8_uid19195_dupName_215_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19197_dupName_215_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19196)@182
    assign rightShiftStage2Idx1_uid19197_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19195_dupName_215_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19190_dupName_215_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19189)@182
    assign rightShiftStage1Idx1Rng4_uid19190_dupName_215_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19192_dupName_215_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19191)@182
    assign rightShiftStage1Idx1_uid19192_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19190_dupName_215_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19185_dupName_215_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19184)@182
    assign rightShiftStage0Idx1Rng1_uid19185_dupName_215_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q[33:1];

    // rightShiftStage0Idx1_uid19187_dupName_215_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19186)@182
    assign rightShiftStage0Idx1_uid19187_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19185_dupName_215_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25152_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(BITSELECT,25151)@181
    assign leftShiftStage2Idx1Rng8_uid25152_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in = leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25152_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25152_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25153_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(BITJOIN,25152)@181
    assign leftShiftStage2Idx1_uid25153_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25152_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25147_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(BITSELECT,25146)@181
    assign leftShiftStage1Idx1Rng4_uid25147_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in = leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25147_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25147_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25148_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(BITJOIN,25147)@181
    assign leftShiftStage1Idx1_uid25148_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25147_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25142_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(BITSELECT,25141)@181
    assign leftShiftStage0Idx1Rng1_uid25142_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25142_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25142_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25143_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(BITJOIN,25142)@181
    assign leftShiftStage0Idx1_uid25143_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25142_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19133_dupName_211_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19132)@180
    assign rightShiftStage2Idx1Rng8_uid19133_dupName_211_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19135_dupName_211_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19134)@180
    assign rightShiftStage2Idx1_uid19135_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19133_dupName_211_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19128_dupName_211_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19127)@180
    assign rightShiftStage1Idx1Rng4_uid19128_dupName_211_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19130_dupName_211_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19129)@180
    assign rightShiftStage1Idx1_uid19130_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19128_dupName_211_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19123_dupName_211_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19122)@180
    assign rightShiftStage0Idx1Rng1_uid19123_dupName_211_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q[33:1];

    // rightShiftStage0Idx1_uid19125_dupName_211_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19124)@180
    assign rightShiftStage0Idx1_uid19125_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19123_dupName_211_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25134_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(BITSELECT,25133)@179
    assign leftShiftStage2Idx1Rng8_uid25134_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in = leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25134_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25134_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25135_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(BITJOIN,25134)@179
    assign leftShiftStage2Idx1_uid25135_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25134_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25129_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(BITSELECT,25128)@179
    assign leftShiftStage1Idx1Rng4_uid25129_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in = leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25129_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25129_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25130_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(BITJOIN,25129)@179
    assign leftShiftStage1Idx1_uid25130_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25129_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25124_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(BITSELECT,25123)@179
    assign leftShiftStage0Idx1Rng1_uid25124_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25124_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25124_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25125_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(BITJOIN,25124)@179
    assign leftShiftStage0Idx1_uid25125_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25124_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19071_dupName_207_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19070)@178
    assign rightShiftStage2Idx1Rng8_uid19071_dupName_207_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19073_dupName_207_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19072)@178
    assign rightShiftStage2Idx1_uid19073_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19071_dupName_207_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19066_dupName_207_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19065)@178
    assign rightShiftStage1Idx1Rng4_uid19066_dupName_207_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19068_dupName_207_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19067)@178
    assign rightShiftStage1Idx1_uid19068_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19066_dupName_207_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid19061_dupName_207_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19060)@178
    assign rightShiftStage0Idx1Rng1_uid19061_dupName_207_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q[33:1];

    // rightShiftStage0Idx1_uid19063_dupName_207_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19062)@178
    assign rightShiftStage0Idx1_uid19063_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid19061_dupName_207_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25116_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(BITSELECT,25115)@177
    assign leftShiftStage2Idx1Rng8_uid25116_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in = leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25116_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25116_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25117_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(BITJOIN,25116)@177
    assign leftShiftStage2Idx1_uid25117_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25116_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25111_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(BITSELECT,25110)@177
    assign leftShiftStage1Idx1Rng4_uid25111_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in = leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25111_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25111_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25112_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(BITJOIN,25111)@177
    assign leftShiftStage1Idx1_uid25112_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25111_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25106_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(BITSELECT,25105)@177
    assign leftShiftStage0Idx1Rng1_uid25106_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25106_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25106_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25107_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(BITJOIN,25106)@177
    assign leftShiftStage0Idx1_uid25107_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25106_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid19009_dupName_203_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19008)@176
    assign rightShiftStage2Idx1Rng8_uid19009_dupName_203_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid19011_dupName_203_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19010)@176
    assign rightShiftStage2Idx1_uid19011_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid19009_dupName_203_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid19004_dupName_203_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19003)@176
    assign rightShiftStage1Idx1Rng4_uid19004_dupName_203_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid19006_dupName_203_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19005)@176
    assign rightShiftStage1Idx1_uid19006_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid19004_dupName_203_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18999_dupName_203_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18998)@176
    assign rightShiftStage0Idx1Rng1_uid18999_dupName_203_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q[33:1];

    // rightShiftStage0Idx1_uid19001_dupName_203_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19000)@176
    assign rightShiftStage0Idx1_uid19001_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18999_dupName_203_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25098_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(BITSELECT,25097)@175
    assign leftShiftStage2Idx1Rng8_uid25098_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in = leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25098_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25098_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25099_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(BITJOIN,25098)@175
    assign leftShiftStage2Idx1_uid25099_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25098_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25093_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(BITSELECT,25092)@175
    assign leftShiftStage1Idx1Rng4_uid25093_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in = leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25093_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25093_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25094_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(BITJOIN,25093)@175
    assign leftShiftStage1Idx1_uid25094_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25093_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25088_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(BITSELECT,25087)@175
    assign leftShiftStage0Idx1Rng1_uid25088_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25088_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25088_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25089_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(BITJOIN,25088)@175
    assign leftShiftStage0Idx1_uid25089_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25088_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18947_dupName_199_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18946)@174
    assign rightShiftStage2Idx1Rng8_uid18947_dupName_199_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18949_dupName_199_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18948)@174
    assign rightShiftStage2Idx1_uid18949_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18947_dupName_199_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18942_dupName_199_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18941)@174
    assign rightShiftStage1Idx1Rng4_uid18942_dupName_199_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18944_dupName_199_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18943)@174
    assign rightShiftStage1Idx1_uid18944_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18942_dupName_199_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18937_dupName_199_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18936)@174
    assign rightShiftStage0Idx1Rng1_uid18937_dupName_199_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q[33:1];

    // rightShiftStage0Idx1_uid18939_dupName_199_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18938)@174
    assign rightShiftStage0Idx1_uid18939_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18937_dupName_199_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25080_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(BITSELECT,25079)@173
    assign leftShiftStage2Idx1Rng8_uid25080_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in = leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25080_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25080_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25081_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(BITJOIN,25080)@173
    assign leftShiftStage2Idx1_uid25081_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25080_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25075_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(BITSELECT,25074)@173
    assign leftShiftStage1Idx1Rng4_uid25075_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in = leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25075_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25075_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25076_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(BITJOIN,25075)@173
    assign leftShiftStage1Idx1_uid25076_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25075_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25070_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(BITSELECT,25069)@173
    assign leftShiftStage0Idx1Rng1_uid25070_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25070_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25070_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25071_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(BITJOIN,25070)@173
    assign leftShiftStage0Idx1_uid25071_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25070_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18885_dupName_195_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18884)@172
    assign rightShiftStage2Idx1Rng8_uid18885_dupName_195_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18887_dupName_195_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18886)@172
    assign rightShiftStage2Idx1_uid18887_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18885_dupName_195_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18880_dupName_195_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18879)@172
    assign rightShiftStage1Idx1Rng4_uid18880_dupName_195_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18882_dupName_195_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18881)@172
    assign rightShiftStage1Idx1_uid18882_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18880_dupName_195_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18875_dupName_195_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18874)@172
    assign rightShiftStage0Idx1Rng1_uid18875_dupName_195_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q[33:1];

    // rightShiftStage0Idx1_uid18877_dupName_195_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18876)@172
    assign rightShiftStage0Idx1_uid18877_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18875_dupName_195_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25044_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(BITSELECT,25043)@171
    assign leftShiftStage2Idx1Rng8_uid25044_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in = leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25044_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25044_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25045_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(BITJOIN,25044)@171
    assign leftShiftStage2Idx1_uid25045_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25044_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25039_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(BITSELECT,25038)@171
    assign leftShiftStage1Idx1Rng4_uid25039_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in = leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25039_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25039_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25040_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(BITJOIN,25039)@171
    assign leftShiftStage1Idx1_uid25040_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25039_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25034_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(BITSELECT,25033)@171
    assign leftShiftStage0Idx1Rng1_uid25034_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25034_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25034_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25035_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(BITJOIN,25034)@171
    assign leftShiftStage0Idx1_uid25035_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25034_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18823_dupName_191_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18822)@170
    assign rightShiftStage2Idx1Rng8_uid18823_dupName_191_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18825_dupName_191_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18824)@170
    assign rightShiftStage2Idx1_uid18825_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18823_dupName_191_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18818_dupName_191_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18817)@170
    assign rightShiftStage1Idx1Rng4_uid18818_dupName_191_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18820_dupName_191_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18819)@170
    assign rightShiftStage1Idx1_uid18820_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18818_dupName_191_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18813_dupName_191_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18812)@170
    assign rightShiftStage0Idx1Rng1_uid18813_dupName_191_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q[33:1];

    // rightShiftStage0Idx1_uid18815_dupName_191_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18814)@170
    assign rightShiftStage0Idx1_uid18815_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18813_dupName_191_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25026_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(BITSELECT,25025)@169
    assign leftShiftStage2Idx1Rng8_uid25026_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in = leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25026_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25026_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25027_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(BITJOIN,25026)@169
    assign leftShiftStage2Idx1_uid25027_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25026_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25021_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(BITSELECT,25020)@169
    assign leftShiftStage1Idx1Rng4_uid25021_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in = leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25021_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25021_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25022_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(BITJOIN,25021)@169
    assign leftShiftStage1Idx1_uid25022_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25021_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25016_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(BITSELECT,25015)@169
    assign leftShiftStage0Idx1Rng1_uid25016_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25016_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25016_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25017_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(BITJOIN,25016)@169
    assign leftShiftStage0Idx1_uid25017_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25016_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18761_dupName_187_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18760)@168
    assign rightShiftStage2Idx1Rng8_uid18761_dupName_187_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18763_dupName_187_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18762)@168
    assign rightShiftStage2Idx1_uid18763_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18761_dupName_187_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18756_dupName_187_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18755)@168
    assign rightShiftStage1Idx1Rng4_uid18756_dupName_187_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18758_dupName_187_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18757)@168
    assign rightShiftStage1Idx1_uid18758_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18756_dupName_187_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18751_dupName_187_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18750)@168
    assign rightShiftStage0Idx1Rng1_uid18751_dupName_187_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q[33:1];

    // rightShiftStage0Idx1_uid18753_dupName_187_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18752)@168
    assign rightShiftStage0Idx1_uid18753_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18751_dupName_187_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25008_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(BITSELECT,25007)@167
    assign leftShiftStage2Idx1Rng8_uid25008_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in = leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25008_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25008_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25009_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(BITJOIN,25008)@167
    assign leftShiftStage2Idx1_uid25009_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25008_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25003_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(BITSELECT,25002)@167
    assign leftShiftStage1Idx1Rng4_uid25003_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in = leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25003_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25003_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25004_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(BITJOIN,25003)@167
    assign leftShiftStage1Idx1_uid25004_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25003_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24998_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(BITSELECT,24997)@167
    assign leftShiftStage0Idx1Rng1_uid24998_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24998_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24998_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24999_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(BITJOIN,24998)@167
    assign leftShiftStage0Idx1_uid24999_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24998_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18699_dupName_183_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18698)@166
    assign rightShiftStage2Idx1Rng8_uid18699_dupName_183_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18701_dupName_183_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18700)@166
    assign rightShiftStage2Idx1_uid18701_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18699_dupName_183_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18694_dupName_183_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18693)@166
    assign rightShiftStage1Idx1Rng4_uid18694_dupName_183_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18696_dupName_183_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18695)@166
    assign rightShiftStage1Idx1_uid18696_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18694_dupName_183_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18689_dupName_183_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18688)@166
    assign rightShiftStage0Idx1Rng1_uid18689_dupName_183_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q[33:1];

    // rightShiftStage0Idx1_uid18691_dupName_183_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18690)@166
    assign rightShiftStage0Idx1_uid18691_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18689_dupName_183_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24990_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(BITSELECT,24989)@165
    assign leftShiftStage2Idx1Rng8_uid24990_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in = leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24990_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24990_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24991_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(BITJOIN,24990)@165
    assign leftShiftStage2Idx1_uid24991_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24990_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24985_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(BITSELECT,24984)@165
    assign leftShiftStage1Idx1Rng4_uid24985_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in = leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24985_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24985_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24986_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(BITJOIN,24985)@165
    assign leftShiftStage1Idx1_uid24986_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24985_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24980_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(BITSELECT,24979)@165
    assign leftShiftStage0Idx1Rng1_uid24980_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24980_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24980_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24981_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(BITJOIN,24980)@165
    assign leftShiftStage0Idx1_uid24981_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24980_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18637_dupName_179_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18636)@164
    assign rightShiftStage2Idx1Rng8_uid18637_dupName_179_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18639_dupName_179_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18638)@164
    assign rightShiftStage2Idx1_uid18639_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18637_dupName_179_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18632_dupName_179_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18631)@164
    assign rightShiftStage1Idx1Rng4_uid18632_dupName_179_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18634_dupName_179_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18633)@164
    assign rightShiftStage1Idx1_uid18634_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18632_dupName_179_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18627_dupName_179_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18626)@164
    assign rightShiftStage0Idx1Rng1_uid18627_dupName_179_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q[33:1];

    // rightShiftStage0Idx1_uid18629_dupName_179_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18628)@164
    assign rightShiftStage0Idx1_uid18629_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18627_dupName_179_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24972_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(BITSELECT,24971)@163
    assign leftShiftStage2Idx1Rng8_uid24972_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in = leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24972_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24972_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24973_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(BITJOIN,24972)@163
    assign leftShiftStage2Idx1_uid24973_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24972_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24967_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(BITSELECT,24966)@163
    assign leftShiftStage1Idx1Rng4_uid24967_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in = leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24967_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24967_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24968_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(BITJOIN,24967)@163
    assign leftShiftStage1Idx1_uid24968_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24967_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24962_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(BITSELECT,24961)@163
    assign leftShiftStage0Idx1Rng1_uid24962_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24962_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24962_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24963_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(BITJOIN,24962)@163
    assign leftShiftStage0Idx1_uid24963_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24962_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18575_dupName_175_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18574)@162
    assign rightShiftStage2Idx1Rng8_uid18575_dupName_175_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18577_dupName_175_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18576)@162
    assign rightShiftStage2Idx1_uid18577_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18575_dupName_175_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18570_dupName_175_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18569)@162
    assign rightShiftStage1Idx1Rng4_uid18570_dupName_175_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18572_dupName_175_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18571)@162
    assign rightShiftStage1Idx1_uid18572_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18570_dupName_175_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18565_dupName_175_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18564)@162
    assign rightShiftStage0Idx1Rng1_uid18565_dupName_175_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q[33:1];

    // rightShiftStage0Idx1_uid18567_dupName_175_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18566)@162
    assign rightShiftStage0Idx1_uid18567_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18565_dupName_175_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24954_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(BITSELECT,24953)@161
    assign leftShiftStage2Idx1Rng8_uid24954_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in = leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24954_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24954_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24955_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(BITJOIN,24954)@161
    assign leftShiftStage2Idx1_uid24955_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24954_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24949_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(BITSELECT,24948)@161
    assign leftShiftStage1Idx1Rng4_uid24949_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in = leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24949_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24949_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24950_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(BITJOIN,24949)@161
    assign leftShiftStage1Idx1_uid24950_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24949_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24944_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(BITSELECT,24943)@161
    assign leftShiftStage0Idx1Rng1_uid24944_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24944_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24944_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24945_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(BITJOIN,24944)@161
    assign leftShiftStage0Idx1_uid24945_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24944_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18513_dupName_171_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18512)@160
    assign rightShiftStage2Idx1Rng8_uid18513_dupName_171_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18515_dupName_171_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18514)@160
    assign rightShiftStage2Idx1_uid18515_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18513_dupName_171_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18508_dupName_171_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18507)@160
    assign rightShiftStage1Idx1Rng4_uid18508_dupName_171_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18510_dupName_171_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18509)@160
    assign rightShiftStage1Idx1_uid18510_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18508_dupName_171_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18503_dupName_171_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18502)@160
    assign rightShiftStage0Idx1Rng1_uid18503_dupName_171_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q[33:1];

    // rightShiftStage0Idx1_uid18505_dupName_171_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18504)@160
    assign rightShiftStage0Idx1_uid18505_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18503_dupName_171_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24936_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(BITSELECT,24935)@159
    assign leftShiftStage2Idx1Rng8_uid24936_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in = leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24936_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24936_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24937_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(BITJOIN,24936)@159
    assign leftShiftStage2Idx1_uid24937_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24936_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24931_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(BITSELECT,24930)@159
    assign leftShiftStage1Idx1Rng4_uid24931_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in = leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24931_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24931_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24932_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(BITJOIN,24931)@159
    assign leftShiftStage1Idx1_uid24932_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24931_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24926_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(BITSELECT,24925)@159
    assign leftShiftStage0Idx1Rng1_uid24926_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24926_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24926_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24927_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(BITJOIN,24926)@159
    assign leftShiftStage0Idx1_uid24927_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24926_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18451_dupName_167_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18450)@158
    assign rightShiftStage2Idx1Rng8_uid18451_dupName_167_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18453_dupName_167_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18452)@158
    assign rightShiftStage2Idx1_uid18453_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18451_dupName_167_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18446_dupName_167_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18445)@158
    assign rightShiftStage1Idx1Rng4_uid18446_dupName_167_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18448_dupName_167_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18447)@158
    assign rightShiftStage1Idx1_uid18448_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18446_dupName_167_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18441_dupName_167_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18440)@158
    assign rightShiftStage0Idx1Rng1_uid18441_dupName_167_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q[33:1];

    // rightShiftStage0Idx1_uid18443_dupName_167_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18442)@158
    assign rightShiftStage0Idx1_uid18443_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18441_dupName_167_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24918_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(BITSELECT,24917)@157
    assign leftShiftStage2Idx1Rng8_uid24918_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in = leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24918_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24918_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24919_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(BITJOIN,24918)@157
    assign leftShiftStage2Idx1_uid24919_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24918_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24913_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(BITSELECT,24912)@157
    assign leftShiftStage1Idx1Rng4_uid24913_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in = leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24913_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24913_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24914_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(BITJOIN,24913)@157
    assign leftShiftStage1Idx1_uid24914_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24913_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24908_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(BITSELECT,24907)@157
    assign leftShiftStage0Idx1Rng1_uid24908_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24908_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24908_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24909_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(BITJOIN,24908)@157
    assign leftShiftStage0Idx1_uid24909_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24908_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18389_dupName_163_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18388)@156
    assign rightShiftStage2Idx1Rng8_uid18389_dupName_163_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18391_dupName_163_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18390)@156
    assign rightShiftStage2Idx1_uid18391_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18389_dupName_163_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18384_dupName_163_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18383)@156
    assign rightShiftStage1Idx1Rng4_uid18384_dupName_163_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18386_dupName_163_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18385)@156
    assign rightShiftStage1Idx1_uid18386_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18384_dupName_163_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18379_dupName_163_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18378)@156
    assign rightShiftStage0Idx1Rng1_uid18379_dupName_163_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q[33:1];

    // rightShiftStage0Idx1_uid18381_dupName_163_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18380)@156
    assign rightShiftStage0Idx1_uid18381_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18379_dupName_163_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24900_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(BITSELECT,24899)@155
    assign leftShiftStage2Idx1Rng8_uid24900_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in = leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24900_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24900_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24901_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(BITJOIN,24900)@155
    assign leftShiftStage2Idx1_uid24901_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24900_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24895_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(BITSELECT,24894)@155
    assign leftShiftStage1Idx1Rng4_uid24895_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in = leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24895_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24895_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24896_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(BITJOIN,24895)@155
    assign leftShiftStage1Idx1_uid24896_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24895_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24890_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(BITSELECT,24889)@155
    assign leftShiftStage0Idx1Rng1_uid24890_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24890_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24890_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24891_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(BITJOIN,24890)@155
    assign leftShiftStage0Idx1_uid24891_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24890_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18327_dupName_159_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18326)@154
    assign rightShiftStage2Idx1Rng8_uid18327_dupName_159_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18329_dupName_159_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18328)@154
    assign rightShiftStage2Idx1_uid18329_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18327_dupName_159_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18322_dupName_159_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18321)@154
    assign rightShiftStage1Idx1Rng4_uid18322_dupName_159_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18324_dupName_159_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18323)@154
    assign rightShiftStage1Idx1_uid18324_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18322_dupName_159_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18317_dupName_159_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18316)@154
    assign rightShiftStage0Idx1Rng1_uid18317_dupName_159_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q[33:1];

    // rightShiftStage0Idx1_uid18319_dupName_159_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18318)@154
    assign rightShiftStage0Idx1_uid18319_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18317_dupName_159_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24882_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(BITSELECT,24881)@153
    assign leftShiftStage2Idx1Rng8_uid24882_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in = leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24882_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24882_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24883_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(BITJOIN,24882)@153
    assign leftShiftStage2Idx1_uid24883_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24882_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24877_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(BITSELECT,24876)@153
    assign leftShiftStage1Idx1Rng4_uid24877_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in = leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24877_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24877_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24878_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(BITJOIN,24877)@153
    assign leftShiftStage1Idx1_uid24878_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24877_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24872_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(BITSELECT,24871)@153
    assign leftShiftStage0Idx1Rng1_uid24872_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24872_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24872_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24873_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(BITJOIN,24872)@153
    assign leftShiftStage0Idx1_uid24873_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24872_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18265_dupName_155_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18264)@152
    assign rightShiftStage2Idx1Rng8_uid18265_dupName_155_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18267_dupName_155_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18266)@152
    assign rightShiftStage2Idx1_uid18267_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18265_dupName_155_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18260_dupName_155_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18259)@152
    assign rightShiftStage1Idx1Rng4_uid18260_dupName_155_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18262_dupName_155_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18261)@152
    assign rightShiftStage1Idx1_uid18262_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18260_dupName_155_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18255_dupName_155_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18254)@152
    assign rightShiftStage0Idx1Rng1_uid18255_dupName_155_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q[33:1];

    // rightShiftStage0Idx1_uid18257_dupName_155_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18256)@152
    assign rightShiftStage0Idx1_uid18257_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18255_dupName_155_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24846_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(BITSELECT,24845)@151
    assign leftShiftStage2Idx1Rng8_uid24846_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in = leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24846_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24846_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24847_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(BITJOIN,24846)@151
    assign leftShiftStage2Idx1_uid24847_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24846_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24841_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(BITSELECT,24840)@151
    assign leftShiftStage1Idx1Rng4_uid24841_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in = leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24841_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24841_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24842_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(BITJOIN,24841)@151
    assign leftShiftStage1Idx1_uid24842_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24841_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24836_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(BITSELECT,24835)@151
    assign leftShiftStage0Idx1Rng1_uid24836_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24836_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24836_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24837_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(BITJOIN,24836)@151
    assign leftShiftStage0Idx1_uid24837_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24836_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18203_dupName_151_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18202)@150
    assign rightShiftStage2Idx1Rng8_uid18203_dupName_151_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18205_dupName_151_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18204)@150
    assign rightShiftStage2Idx1_uid18205_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18203_dupName_151_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18198_dupName_151_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18197)@150
    assign rightShiftStage1Idx1Rng4_uid18198_dupName_151_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18200_dupName_151_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18199)@150
    assign rightShiftStage1Idx1_uid18200_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18198_dupName_151_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18193_dupName_151_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18192)@150
    assign rightShiftStage0Idx1Rng1_uid18193_dupName_151_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q[33:1];

    // rightShiftStage0Idx1_uid18195_dupName_151_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18194)@150
    assign rightShiftStage0Idx1_uid18195_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18193_dupName_151_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24828_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(BITSELECT,24827)@149
    assign leftShiftStage2Idx1Rng8_uid24828_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in = leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24828_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24828_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24829_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(BITJOIN,24828)@149
    assign leftShiftStage2Idx1_uid24829_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24828_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24823_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(BITSELECT,24822)@149
    assign leftShiftStage1Idx1Rng4_uid24823_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in = leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24823_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24823_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24824_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(BITJOIN,24823)@149
    assign leftShiftStage1Idx1_uid24824_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24823_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24818_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(BITSELECT,24817)@149
    assign leftShiftStage0Idx1Rng1_uid24818_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24818_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24818_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24819_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(BITJOIN,24818)@149
    assign leftShiftStage0Idx1_uid24819_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24818_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18141_dupName_147_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18140)@148
    assign rightShiftStage2Idx1Rng8_uid18141_dupName_147_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18143_dupName_147_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18142)@148
    assign rightShiftStage2Idx1_uid18143_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18141_dupName_147_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18136_dupName_147_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18135)@148
    assign rightShiftStage1Idx1Rng4_uid18136_dupName_147_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18138_dupName_147_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18137)@148
    assign rightShiftStage1Idx1_uid18138_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18136_dupName_147_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18131_dupName_147_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18130)@148
    assign rightShiftStage0Idx1Rng1_uid18131_dupName_147_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q[33:1];

    // rightShiftStage0Idx1_uid18133_dupName_147_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18132)@148
    assign rightShiftStage0Idx1_uid18133_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18131_dupName_147_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24810_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(BITSELECT,24809)@147
    assign leftShiftStage2Idx1Rng8_uid24810_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in = leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24810_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24810_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24811_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(BITJOIN,24810)@147
    assign leftShiftStage2Idx1_uid24811_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24810_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24805_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(BITSELECT,24804)@147
    assign leftShiftStage1Idx1Rng4_uid24805_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in = leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24805_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24805_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24806_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(BITJOIN,24805)@147
    assign leftShiftStage1Idx1_uid24806_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24805_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24800_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(BITSELECT,24799)@147
    assign leftShiftStage0Idx1Rng1_uid24800_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24800_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24800_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24801_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(BITJOIN,24800)@147
    assign leftShiftStage0Idx1_uid24801_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24800_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18079_dupName_143_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18078)@146
    assign rightShiftStage2Idx1Rng8_uid18079_dupName_143_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18081_dupName_143_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18080)@146
    assign rightShiftStage2Idx1_uid18081_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18079_dupName_143_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18074_dupName_143_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18073)@146
    assign rightShiftStage1Idx1Rng4_uid18074_dupName_143_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18076_dupName_143_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18075)@146
    assign rightShiftStage1Idx1_uid18076_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18074_dupName_143_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18069_dupName_143_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18068)@146
    assign rightShiftStage0Idx1Rng1_uid18069_dupName_143_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q[33:1];

    // rightShiftStage0Idx1_uid18071_dupName_143_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18070)@146
    assign rightShiftStage0Idx1_uid18071_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18069_dupName_143_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24792_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(BITSELECT,24791)@145
    assign leftShiftStage2Idx1Rng8_uid24792_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in = leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24792_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24792_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24793_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(BITJOIN,24792)@145
    assign leftShiftStage2Idx1_uid24793_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24792_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24787_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(BITSELECT,24786)@145
    assign leftShiftStage1Idx1Rng4_uid24787_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in = leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24787_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24787_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24788_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(BITJOIN,24787)@145
    assign leftShiftStage1Idx1_uid24788_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24787_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24782_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(BITSELECT,24781)@145
    assign leftShiftStage0Idx1Rng1_uid24782_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24782_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24782_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24783_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(BITJOIN,24782)@145
    assign leftShiftStage0Idx1_uid24783_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24782_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid18017_dupName_139_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18016)@144
    assign rightShiftStage2Idx1Rng8_uid18017_dupName_139_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid18019_dupName_139_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18018)@144
    assign rightShiftStage2Idx1_uid18019_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid18017_dupName_139_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid18012_dupName_139_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18011)@144
    assign rightShiftStage1Idx1Rng4_uid18012_dupName_139_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid18014_dupName_139_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18013)@144
    assign rightShiftStage1Idx1_uid18014_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid18012_dupName_139_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid18007_dupName_139_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18006)@144
    assign rightShiftStage0Idx1Rng1_uid18007_dupName_139_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q[33:1];

    // rightShiftStage0Idx1_uid18009_dupName_139_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18008)@144
    assign rightShiftStage0Idx1_uid18009_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid18007_dupName_139_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24774_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(BITSELECT,24773)@143
    assign leftShiftStage2Idx1Rng8_uid24774_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in = leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24774_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24774_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24775_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(BITJOIN,24774)@143
    assign leftShiftStage2Idx1_uid24775_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24774_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24769_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(BITSELECT,24768)@143
    assign leftShiftStage1Idx1Rng4_uid24769_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in = leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24769_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24769_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24770_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(BITJOIN,24769)@143
    assign leftShiftStage1Idx1_uid24770_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24769_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24764_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(BITSELECT,24763)@143
    assign leftShiftStage0Idx1Rng1_uid24764_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24764_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24764_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24765_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(BITJOIN,24764)@143
    assign leftShiftStage0Idx1_uid24765_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24764_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17955_dupName_135_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17954)@142
    assign rightShiftStage2Idx1Rng8_uid17955_dupName_135_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17957_dupName_135_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17956)@142
    assign rightShiftStage2Idx1_uid17957_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17955_dupName_135_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17950_dupName_135_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17949)@142
    assign rightShiftStage1Idx1Rng4_uid17950_dupName_135_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17952_dupName_135_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17951)@142
    assign rightShiftStage1Idx1_uid17952_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17950_dupName_135_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17945_dupName_135_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17944)@142
    assign rightShiftStage0Idx1Rng1_uid17945_dupName_135_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q[33:1];

    // rightShiftStage0Idx1_uid17947_dupName_135_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17946)@142
    assign rightShiftStage0Idx1_uid17947_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17945_dupName_135_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24756_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(BITSELECT,24755)@141
    assign leftShiftStage2Idx1Rng8_uid24756_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in = leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24756_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24756_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24757_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(BITJOIN,24756)@141
    assign leftShiftStage2Idx1_uid24757_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24756_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24751_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(BITSELECT,24750)@141
    assign leftShiftStage1Idx1Rng4_uid24751_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in = leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24751_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24751_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24752_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(BITJOIN,24751)@141
    assign leftShiftStage1Idx1_uid24752_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24751_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24746_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(BITSELECT,24745)@141
    assign leftShiftStage0Idx1Rng1_uid24746_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24746_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24746_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24747_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(BITJOIN,24746)@141
    assign leftShiftStage0Idx1_uid24747_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24746_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17893_dupName_131_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17892)@140
    assign rightShiftStage2Idx1Rng8_uid17893_dupName_131_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17895_dupName_131_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17894)@140
    assign rightShiftStage2Idx1_uid17895_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17893_dupName_131_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17888_dupName_131_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17887)@140
    assign rightShiftStage1Idx1Rng4_uid17888_dupName_131_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17890_dupName_131_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17889)@140
    assign rightShiftStage1Idx1_uid17890_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17888_dupName_131_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17883_dupName_131_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17882)@140
    assign rightShiftStage0Idx1Rng1_uid17883_dupName_131_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q[33:1];

    // rightShiftStage0Idx1_uid17885_dupName_131_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17884)@140
    assign rightShiftStage0Idx1_uid17885_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17883_dupName_131_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24738_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(BITSELECT,24737)@139
    assign leftShiftStage2Idx1Rng8_uid24738_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in = leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24738_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24738_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24739_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(BITJOIN,24738)@139
    assign leftShiftStage2Idx1_uid24739_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24738_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24733_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(BITSELECT,24732)@139
    assign leftShiftStage1Idx1Rng4_uid24733_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in = leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24733_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24733_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24734_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(BITJOIN,24733)@139
    assign leftShiftStage1Idx1_uid24734_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24733_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24728_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(BITSELECT,24727)@139
    assign leftShiftStage0Idx1Rng1_uid24728_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24728_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24728_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24729_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(BITJOIN,24728)@139
    assign leftShiftStage0Idx1_uid24729_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24728_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17831_dupName_127_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17830)@138
    assign rightShiftStage2Idx1Rng8_uid17831_dupName_127_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17833_dupName_127_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17832)@138
    assign rightShiftStage2Idx1_uid17833_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17831_dupName_127_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17826_dupName_127_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17825)@138
    assign rightShiftStage1Idx1Rng4_uid17826_dupName_127_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17828_dupName_127_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17827)@138
    assign rightShiftStage1Idx1_uid17828_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17826_dupName_127_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17821_dupName_127_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17820)@138
    assign rightShiftStage0Idx1Rng1_uid17821_dupName_127_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q[33:1];

    // rightShiftStage0Idx1_uid17823_dupName_127_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17822)@138
    assign rightShiftStage0Idx1_uid17823_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17821_dupName_127_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24720_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(BITSELECT,24719)@137
    assign leftShiftStage2Idx1Rng8_uid24720_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in = leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24720_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24720_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24721_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(BITJOIN,24720)@137
    assign leftShiftStage2Idx1_uid24721_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24720_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24715_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(BITSELECT,24714)@137
    assign leftShiftStage1Idx1Rng4_uid24715_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in = leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24715_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24715_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24716_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(BITJOIN,24715)@137
    assign leftShiftStage1Idx1_uid24716_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24715_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24710_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(BITSELECT,24709)@137
    assign leftShiftStage0Idx1Rng1_uid24710_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24710_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24710_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24711_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(BITJOIN,24710)@137
    assign leftShiftStage0Idx1_uid24711_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24710_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17769_dupName_123_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17768)@136
    assign rightShiftStage2Idx1Rng8_uid17769_dupName_123_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17771_dupName_123_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17770)@136
    assign rightShiftStage2Idx1_uid17771_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17769_dupName_123_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17764_dupName_123_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17763)@136
    assign rightShiftStage1Idx1Rng4_uid17764_dupName_123_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17766_dupName_123_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17765)@136
    assign rightShiftStage1Idx1_uid17766_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17764_dupName_123_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17759_dupName_123_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17758)@136
    assign rightShiftStage0Idx1Rng1_uid17759_dupName_123_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q[33:1];

    // rightShiftStage0Idx1_uid17761_dupName_123_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17760)@136
    assign rightShiftStage0Idx1_uid17761_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17759_dupName_123_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24702_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(BITSELECT,24701)@135
    assign leftShiftStage2Idx1Rng8_uid24702_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in = leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24702_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24702_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24703_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(BITJOIN,24702)@135
    assign leftShiftStage2Idx1_uid24703_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24702_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24697_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(BITSELECT,24696)@135
    assign leftShiftStage1Idx1Rng4_uid24697_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in = leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24697_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24697_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24698_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(BITJOIN,24697)@135
    assign leftShiftStage1Idx1_uid24698_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24697_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24692_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(BITSELECT,24691)@135
    assign leftShiftStage0Idx1Rng1_uid24692_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24692_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24692_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24693_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(BITJOIN,24692)@135
    assign leftShiftStage0Idx1_uid24693_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24692_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17707_dupName_119_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17706)@134
    assign rightShiftStage2Idx1Rng8_uid17707_dupName_119_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17709_dupName_119_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17708)@134
    assign rightShiftStage2Idx1_uid17709_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17707_dupName_119_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17702_dupName_119_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17701)@134
    assign rightShiftStage1Idx1Rng4_uid17702_dupName_119_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17704_dupName_119_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17703)@134
    assign rightShiftStage1Idx1_uid17704_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17702_dupName_119_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17697_dupName_119_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17696)@134
    assign rightShiftStage0Idx1Rng1_uid17697_dupName_119_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q[33:1];

    // rightShiftStage0Idx1_uid17699_dupName_119_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17698)@134
    assign rightShiftStage0Idx1_uid17699_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17697_dupName_119_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24684_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(BITSELECT,24683)@133
    assign leftShiftStage2Idx1Rng8_uid24684_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in = leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24684_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24684_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24685_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(BITJOIN,24684)@133
    assign leftShiftStage2Idx1_uid24685_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24684_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24679_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(BITSELECT,24678)@133
    assign leftShiftStage1Idx1Rng4_uid24679_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in = leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24679_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24679_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24680_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(BITJOIN,24679)@133
    assign leftShiftStage1Idx1_uid24680_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24679_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24674_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(BITSELECT,24673)@133
    assign leftShiftStage0Idx1Rng1_uid24674_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24674_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24674_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24675_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(BITJOIN,24674)@133
    assign leftShiftStage0Idx1_uid24675_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24674_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17645_dupName_115_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17644)@132
    assign rightShiftStage2Idx1Rng8_uid17645_dupName_115_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17647_dupName_115_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17646)@132
    assign rightShiftStage2Idx1_uid17647_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17645_dupName_115_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17640_dupName_115_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17639)@132
    assign rightShiftStage1Idx1Rng4_uid17640_dupName_115_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17642_dupName_115_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17641)@132
    assign rightShiftStage1Idx1_uid17642_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17640_dupName_115_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17635_dupName_115_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17634)@132
    assign rightShiftStage0Idx1Rng1_uid17635_dupName_115_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q[33:1];

    // rightShiftStage0Idx1_uid17637_dupName_115_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17636)@132
    assign rightShiftStage0Idx1_uid17637_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17635_dupName_115_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24648_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(BITSELECT,24647)@131
    assign leftShiftStage2Idx1Rng8_uid24648_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in = leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24648_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24648_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24649_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(BITJOIN,24648)@131
    assign leftShiftStage2Idx1_uid24649_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24648_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24643_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(BITSELECT,24642)@131
    assign leftShiftStage1Idx1Rng4_uid24643_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in = leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24643_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24643_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24644_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(BITJOIN,24643)@131
    assign leftShiftStage1Idx1_uid24644_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24643_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24638_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(BITSELECT,24637)@131
    assign leftShiftStage0Idx1Rng1_uid24638_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24638_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24638_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24639_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(BITJOIN,24638)@131
    assign leftShiftStage0Idx1_uid24639_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24638_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17583_dupName_111_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17582)@130
    assign rightShiftStage2Idx1Rng8_uid17583_dupName_111_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17585_dupName_111_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17584)@130
    assign rightShiftStage2Idx1_uid17585_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17583_dupName_111_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17578_dupName_111_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17577)@130
    assign rightShiftStage1Idx1Rng4_uid17578_dupName_111_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17580_dupName_111_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17579)@130
    assign rightShiftStage1Idx1_uid17580_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17578_dupName_111_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17573_dupName_111_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17572)@130
    assign rightShiftStage0Idx1Rng1_uid17573_dupName_111_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q[33:1];

    // rightShiftStage0Idx1_uid17575_dupName_111_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17574)@130
    assign rightShiftStage0Idx1_uid17575_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17573_dupName_111_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24630_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(BITSELECT,24629)@129
    assign leftShiftStage2Idx1Rng8_uid24630_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in = leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24630_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24630_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24631_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(BITJOIN,24630)@129
    assign leftShiftStage2Idx1_uid24631_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24630_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24625_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(BITSELECT,24624)@129
    assign leftShiftStage1Idx1Rng4_uid24625_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in = leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24625_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24625_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24626_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(BITJOIN,24625)@129
    assign leftShiftStage1Idx1_uid24626_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24625_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24620_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(BITSELECT,24619)@129
    assign leftShiftStage0Idx1Rng1_uid24620_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24620_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24620_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24621_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(BITJOIN,24620)@129
    assign leftShiftStage0Idx1_uid24621_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24620_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17521_dupName_107_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17520)@128
    assign rightShiftStage2Idx1Rng8_uid17521_dupName_107_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17523_dupName_107_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17522)@128
    assign rightShiftStage2Idx1_uid17523_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17521_dupName_107_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17516_dupName_107_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17515)@128
    assign rightShiftStage1Idx1Rng4_uid17516_dupName_107_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17518_dupName_107_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17517)@128
    assign rightShiftStage1Idx1_uid17518_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17516_dupName_107_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17511_dupName_107_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17510)@128
    assign rightShiftStage0Idx1Rng1_uid17511_dupName_107_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q[33:1];

    // rightShiftStage0Idx1_uid17513_dupName_107_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17512)@128
    assign rightShiftStage0Idx1_uid17513_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17511_dupName_107_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24612_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(BITSELECT,24611)@127
    assign leftShiftStage2Idx1Rng8_uid24612_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in = leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24612_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24612_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24613_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(BITJOIN,24612)@127
    assign leftShiftStage2Idx1_uid24613_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24612_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24607_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(BITSELECT,24606)@127
    assign leftShiftStage1Idx1Rng4_uid24607_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in = leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24607_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24607_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24608_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(BITJOIN,24607)@127
    assign leftShiftStage1Idx1_uid24608_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24607_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24602_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(BITSELECT,24601)@127
    assign leftShiftStage0Idx1Rng1_uid24602_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24602_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24602_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24603_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(BITJOIN,24602)@127
    assign leftShiftStage0Idx1_uid24603_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24602_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17459_dupName_103_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17458)@126
    assign rightShiftStage2Idx1Rng8_uid17459_dupName_103_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17461_dupName_103_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17460)@126
    assign rightShiftStage2Idx1_uid17461_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17459_dupName_103_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17454_dupName_103_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17453)@126
    assign rightShiftStage1Idx1Rng4_uid17454_dupName_103_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17456_dupName_103_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17455)@126
    assign rightShiftStage1Idx1_uid17456_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17454_dupName_103_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17449_dupName_103_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17448)@126
    assign rightShiftStage0Idx1Rng1_uid17449_dupName_103_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q[33:1];

    // rightShiftStage0Idx1_uid17451_dupName_103_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17450)@126
    assign rightShiftStage0Idx1_uid17451_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17449_dupName_103_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24594_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(BITSELECT,24593)@125
    assign leftShiftStage2Idx1Rng8_uid24594_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in = leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24594_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24594_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24595_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(BITJOIN,24594)@125
    assign leftShiftStage2Idx1_uid24595_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24594_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24589_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(BITSELECT,24588)@125
    assign leftShiftStage1Idx1Rng4_uid24589_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in = leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24589_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24589_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24590_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(BITJOIN,24589)@125
    assign leftShiftStage1Idx1_uid24590_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24589_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24584_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(BITSELECT,24583)@125
    assign leftShiftStage0Idx1Rng1_uid24584_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24584_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24584_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24585_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(BITJOIN,24584)@125
    assign leftShiftStage0Idx1_uid24585_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24584_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17397_dupName_99_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17396)@124
    assign rightShiftStage2Idx1Rng8_uid17397_dupName_99_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17399_dupName_99_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17398)@124
    assign rightShiftStage2Idx1_uid17399_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17397_dupName_99_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17392_dupName_99_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17391)@124
    assign rightShiftStage1Idx1Rng4_uid17392_dupName_99_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17394_dupName_99_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17393)@124
    assign rightShiftStage1Idx1_uid17394_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17392_dupName_99_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17387_dupName_99_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17386)@124
    assign rightShiftStage0Idx1Rng1_uid17387_dupName_99_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q[33:1];

    // rightShiftStage0Idx1_uid17389_dupName_99_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17388)@124
    assign rightShiftStage0Idx1_uid17389_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17387_dupName_99_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24576_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(BITSELECT,24575)@123
    assign leftShiftStage2Idx1Rng8_uid24576_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in = leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24576_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24576_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24577_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(BITJOIN,24576)@123
    assign leftShiftStage2Idx1_uid24577_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24576_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24571_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(BITSELECT,24570)@123
    assign leftShiftStage1Idx1Rng4_uid24571_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in = leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24571_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24571_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24572_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(BITJOIN,24571)@123
    assign leftShiftStage1Idx1_uid24572_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24571_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24566_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(BITSELECT,24565)@123
    assign leftShiftStage0Idx1Rng1_uid24566_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24566_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24566_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24567_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(BITJOIN,24566)@123
    assign leftShiftStage0Idx1_uid24567_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24566_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17335_dupName_95_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17334)@122
    assign rightShiftStage2Idx1Rng8_uid17335_dupName_95_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17337_dupName_95_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17336)@122
    assign rightShiftStage2Idx1_uid17337_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17335_dupName_95_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17330_dupName_95_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17329)@122
    assign rightShiftStage1Idx1Rng4_uid17330_dupName_95_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17332_dupName_95_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17331)@122
    assign rightShiftStage1Idx1_uid17332_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17330_dupName_95_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17325_dupName_95_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17324)@122
    assign rightShiftStage0Idx1Rng1_uid17325_dupName_95_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q[33:1];

    // rightShiftStage0Idx1_uid17327_dupName_95_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17326)@122
    assign rightShiftStage0Idx1_uid17327_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17325_dupName_95_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24558_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(BITSELECT,24557)@121
    assign leftShiftStage2Idx1Rng8_uid24558_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in = leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24558_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24558_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24559_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(BITJOIN,24558)@121
    assign leftShiftStage2Idx1_uid24559_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24558_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24553_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(BITSELECT,24552)@121
    assign leftShiftStage1Idx1Rng4_uid24553_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in = leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24553_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24553_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24554_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(BITJOIN,24553)@121
    assign leftShiftStage1Idx1_uid24554_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24553_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24548_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(BITSELECT,24547)@121
    assign leftShiftStage0Idx1Rng1_uid24548_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24548_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24548_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24549_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(BITJOIN,24548)@121
    assign leftShiftStage0Idx1_uid24549_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24548_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17273_dupName_91_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17272)@120
    assign rightShiftStage2Idx1Rng8_uid17273_dupName_91_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17275_dupName_91_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17274)@120
    assign rightShiftStage2Idx1_uid17275_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17273_dupName_91_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17268_dupName_91_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17267)@120
    assign rightShiftStage1Idx1Rng4_uid17268_dupName_91_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17270_dupName_91_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17269)@120
    assign rightShiftStage1Idx1_uid17270_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17268_dupName_91_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17263_dupName_91_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17262)@120
    assign rightShiftStage0Idx1Rng1_uid17263_dupName_91_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q[33:1];

    // rightShiftStage0Idx1_uid17265_dupName_91_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17264)@120
    assign rightShiftStage0Idx1_uid17265_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17263_dupName_91_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24540_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(BITSELECT,24539)@119
    assign leftShiftStage2Idx1Rng8_uid24540_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in = leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24540_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24540_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24541_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(BITJOIN,24540)@119
    assign leftShiftStage2Idx1_uid24541_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24540_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24535_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(BITSELECT,24534)@119
    assign leftShiftStage1Idx1Rng4_uid24535_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in = leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24535_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24535_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24536_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(BITJOIN,24535)@119
    assign leftShiftStage1Idx1_uid24536_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24535_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24530_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(BITSELECT,24529)@119
    assign leftShiftStage0Idx1Rng1_uid24530_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24530_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24530_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24531_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(BITJOIN,24530)@119
    assign leftShiftStage0Idx1_uid24531_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24530_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17211_dupName_87_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17210)@118
    assign rightShiftStage2Idx1Rng8_uid17211_dupName_87_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17213_dupName_87_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17212)@118
    assign rightShiftStage2Idx1_uid17213_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17211_dupName_87_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17206_dupName_87_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17205)@118
    assign rightShiftStage1Idx1Rng4_uid17206_dupName_87_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17208_dupName_87_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17207)@118
    assign rightShiftStage1Idx1_uid17208_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17206_dupName_87_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17201_dupName_87_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17200)@118
    assign rightShiftStage0Idx1Rng1_uid17201_dupName_87_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q[33:1];

    // rightShiftStage0Idx1_uid17203_dupName_87_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17202)@118
    assign rightShiftStage0Idx1_uid17203_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17201_dupName_87_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24522_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(BITSELECT,24521)@117
    assign leftShiftStage2Idx1Rng8_uid24522_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in = leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24522_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24522_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24523_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(BITJOIN,24522)@117
    assign leftShiftStage2Idx1_uid24523_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24522_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24517_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(BITSELECT,24516)@117
    assign leftShiftStage1Idx1Rng4_uid24517_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in = leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24517_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24517_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24518_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(BITJOIN,24517)@117
    assign leftShiftStage1Idx1_uid24518_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24517_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24512_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(BITSELECT,24511)@117
    assign leftShiftStage0Idx1Rng1_uid24512_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24512_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24512_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24513_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(BITJOIN,24512)@117
    assign leftShiftStage0Idx1_uid24513_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24512_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17149_dupName_83_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17148)@116
    assign rightShiftStage2Idx1Rng8_uid17149_dupName_83_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17151_dupName_83_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17150)@116
    assign rightShiftStage2Idx1_uid17151_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17149_dupName_83_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17144_dupName_83_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17143)@116
    assign rightShiftStage1Idx1Rng4_uid17144_dupName_83_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17146_dupName_83_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17145)@116
    assign rightShiftStage1Idx1_uid17146_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17144_dupName_83_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17139_dupName_83_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17138)@116
    assign rightShiftStage0Idx1Rng1_uid17139_dupName_83_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q[33:1];

    // rightShiftStage0Idx1_uid17141_dupName_83_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17140)@116
    assign rightShiftStage0Idx1_uid17141_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17139_dupName_83_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24504_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(BITSELECT,24503)@115
    assign leftShiftStage2Idx1Rng8_uid24504_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in = leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24504_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24504_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24505_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(BITJOIN,24504)@115
    assign leftShiftStage2Idx1_uid24505_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24504_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24499_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(BITSELECT,24498)@115
    assign leftShiftStage1Idx1Rng4_uid24499_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in = leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24499_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24499_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24500_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(BITJOIN,24499)@115
    assign leftShiftStage1Idx1_uid24500_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24499_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24494_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(BITSELECT,24493)@115
    assign leftShiftStage0Idx1Rng1_uid24494_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24494_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24494_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24495_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(BITJOIN,24494)@115
    assign leftShiftStage0Idx1_uid24495_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24494_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17087_dupName_79_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17086)@114
    assign rightShiftStage2Idx1Rng8_uid17087_dupName_79_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17089_dupName_79_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17088)@114
    assign rightShiftStage2Idx1_uid17089_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17087_dupName_79_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17082_dupName_79_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17081)@114
    assign rightShiftStage1Idx1Rng4_uid17082_dupName_79_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17084_dupName_79_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17083)@114
    assign rightShiftStage1Idx1_uid17084_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17082_dupName_79_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17077_dupName_79_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17076)@114
    assign rightShiftStage0Idx1Rng1_uid17077_dupName_79_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q[33:1];

    // rightShiftStage0Idx1_uid17079_dupName_79_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17078)@114
    assign rightShiftStage0Idx1_uid17079_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17077_dupName_79_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24486_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(BITSELECT,24485)@113
    assign leftShiftStage2Idx1Rng8_uid24486_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in = leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24486_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24486_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24487_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(BITJOIN,24486)@113
    assign leftShiftStage2Idx1_uid24487_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24486_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24481_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(BITSELECT,24480)@113
    assign leftShiftStage1Idx1Rng4_uid24481_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in = leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24481_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24481_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24482_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(BITJOIN,24481)@113
    assign leftShiftStage1Idx1_uid24482_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24481_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24476_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(BITSELECT,24475)@113
    assign leftShiftStage0Idx1Rng1_uid24476_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24476_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24476_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24477_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(BITJOIN,24476)@113
    assign leftShiftStage0Idx1_uid24477_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24476_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid17025_dupName_75_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17024)@112
    assign rightShiftStage2Idx1Rng8_uid17025_dupName_75_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid17027_dupName_75_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17026)@112
    assign rightShiftStage2Idx1_uid17027_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid17025_dupName_75_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid17020_dupName_75_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17019)@112
    assign rightShiftStage1Idx1Rng4_uid17020_dupName_75_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid17022_dupName_75_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17021)@112
    assign rightShiftStage1Idx1_uid17022_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid17020_dupName_75_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid17015_dupName_75_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17014)@112
    assign rightShiftStage0Idx1Rng1_uid17015_dupName_75_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q[33:1];

    // rightShiftStage0Idx1_uid17017_dupName_75_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17016)@112
    assign rightShiftStage0Idx1_uid17017_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid17015_dupName_75_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24450_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(BITSELECT,24449)@111
    assign leftShiftStage2Idx1Rng8_uid24450_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in = leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24450_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24450_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24451_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(BITJOIN,24450)@111
    assign leftShiftStage2Idx1_uid24451_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24450_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24445_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(BITSELECT,24444)@111
    assign leftShiftStage1Idx1Rng4_uid24445_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in = leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24445_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24445_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24446_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(BITJOIN,24445)@111
    assign leftShiftStage1Idx1_uid24446_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24445_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24440_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(BITSELECT,24439)@111
    assign leftShiftStage0Idx1Rng1_uid24440_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24440_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24440_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24441_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(BITJOIN,24440)@111
    assign leftShiftStage0Idx1_uid24441_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24440_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16963_dupName_71_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16962)@110
    assign rightShiftStage2Idx1Rng8_uid16963_dupName_71_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16965_dupName_71_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16964)@110
    assign rightShiftStage2Idx1_uid16965_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16963_dupName_71_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16958_dupName_71_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16957)@110
    assign rightShiftStage1Idx1Rng4_uid16958_dupName_71_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16960_dupName_71_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16959)@110
    assign rightShiftStage1Idx1_uid16960_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16958_dupName_71_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16953_dupName_71_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16952)@110
    assign rightShiftStage0Idx1Rng1_uid16953_dupName_71_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q[33:1];

    // rightShiftStage0Idx1_uid16955_dupName_71_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16954)@110
    assign rightShiftStage0Idx1_uid16955_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16953_dupName_71_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24432_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(BITSELECT,24431)@109
    assign leftShiftStage2Idx1Rng8_uid24432_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in = leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24432_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24432_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24433_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(BITJOIN,24432)@109
    assign leftShiftStage2Idx1_uid24433_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24432_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24427_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(BITSELECT,24426)@109
    assign leftShiftStage1Idx1Rng4_uid24427_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in = leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24427_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24427_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24428_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(BITJOIN,24427)@109
    assign leftShiftStage1Idx1_uid24428_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24427_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24422_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(BITSELECT,24421)@109
    assign leftShiftStage0Idx1Rng1_uid24422_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24422_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24422_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24423_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(BITJOIN,24422)@109
    assign leftShiftStage0Idx1_uid24423_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24422_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16901_dupName_67_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16900)@108
    assign rightShiftStage2Idx1Rng8_uid16901_dupName_67_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16903_dupName_67_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16902)@108
    assign rightShiftStage2Idx1_uid16903_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16901_dupName_67_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16896_dupName_67_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16895)@108
    assign rightShiftStage1Idx1Rng4_uid16896_dupName_67_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16898_dupName_67_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16897)@108
    assign rightShiftStage1Idx1_uid16898_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16896_dupName_67_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16891_dupName_67_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16890)@108
    assign rightShiftStage0Idx1Rng1_uid16891_dupName_67_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q[33:1];

    // rightShiftStage0Idx1_uid16893_dupName_67_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16892)@108
    assign rightShiftStage0Idx1_uid16893_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16891_dupName_67_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24414_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(BITSELECT,24413)@107
    assign leftShiftStage2Idx1Rng8_uid24414_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in = leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24414_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24414_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24415_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(BITJOIN,24414)@107
    assign leftShiftStage2Idx1_uid24415_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24414_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24409_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(BITSELECT,24408)@107
    assign leftShiftStage1Idx1Rng4_uid24409_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in = leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24409_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24409_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24410_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(BITJOIN,24409)@107
    assign leftShiftStage1Idx1_uid24410_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24409_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24404_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(BITSELECT,24403)@107
    assign leftShiftStage0Idx1Rng1_uid24404_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24404_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24404_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24405_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(BITJOIN,24404)@107
    assign leftShiftStage0Idx1_uid24405_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24404_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16839_dupName_63_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16838)@106
    assign rightShiftStage2Idx1Rng8_uid16839_dupName_63_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16841_dupName_63_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16840)@106
    assign rightShiftStage2Idx1_uid16841_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16839_dupName_63_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16834_dupName_63_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16833)@106
    assign rightShiftStage1Idx1Rng4_uid16834_dupName_63_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16836_dupName_63_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16835)@106
    assign rightShiftStage1Idx1_uid16836_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16834_dupName_63_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16829_dupName_63_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16828)@106
    assign rightShiftStage0Idx1Rng1_uid16829_dupName_63_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q[33:1];

    // rightShiftStage0Idx1_uid16831_dupName_63_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16830)@106
    assign rightShiftStage0Idx1_uid16831_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16829_dupName_63_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24396_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(BITSELECT,24395)@105
    assign leftShiftStage2Idx1Rng8_uid24396_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in = leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24396_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24396_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24397_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(BITJOIN,24396)@105
    assign leftShiftStage2Idx1_uid24397_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24396_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24391_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(BITSELECT,24390)@105
    assign leftShiftStage1Idx1Rng4_uid24391_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in = leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24391_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24391_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24392_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(BITJOIN,24391)@105
    assign leftShiftStage1Idx1_uid24392_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24391_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24386_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(BITSELECT,24385)@105
    assign leftShiftStage0Idx1Rng1_uid24386_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24386_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24386_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24387_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(BITJOIN,24386)@105
    assign leftShiftStage0Idx1_uid24387_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24386_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16777_dupName_59_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16776)@104
    assign rightShiftStage2Idx1Rng8_uid16777_dupName_59_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16779_dupName_59_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16778)@104
    assign rightShiftStage2Idx1_uid16779_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16777_dupName_59_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16772_dupName_59_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16771)@104
    assign rightShiftStage1Idx1Rng4_uid16772_dupName_59_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16774_dupName_59_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16773)@104
    assign rightShiftStage1Idx1_uid16774_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16772_dupName_59_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16767_dupName_59_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16766)@104
    assign rightShiftStage0Idx1Rng1_uid16767_dupName_59_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q[33:1];

    // rightShiftStage0Idx1_uid16769_dupName_59_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16768)@104
    assign rightShiftStage0Idx1_uid16769_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16767_dupName_59_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24378_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(BITSELECT,24377)@103
    assign leftShiftStage2Idx1Rng8_uid24378_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in = leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24378_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24378_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24379_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(BITJOIN,24378)@103
    assign leftShiftStage2Idx1_uid24379_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24378_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24373_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(BITSELECT,24372)@103
    assign leftShiftStage1Idx1Rng4_uid24373_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in = leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24373_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24373_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24374_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(BITJOIN,24373)@103
    assign leftShiftStage1Idx1_uid24374_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24373_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24368_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(BITSELECT,24367)@103
    assign leftShiftStage0Idx1Rng1_uid24368_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24368_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24368_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24369_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(BITJOIN,24368)@103
    assign leftShiftStage0Idx1_uid24369_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24368_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16715_dupName_55_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16714)@102
    assign rightShiftStage2Idx1Rng8_uid16715_dupName_55_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16717_dupName_55_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16716)@102
    assign rightShiftStage2Idx1_uid16717_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16715_dupName_55_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16710_dupName_55_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16709)@102
    assign rightShiftStage1Idx1Rng4_uid16710_dupName_55_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16712_dupName_55_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16711)@102
    assign rightShiftStage1Idx1_uid16712_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16710_dupName_55_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16705_dupName_55_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16704)@102
    assign rightShiftStage0Idx1Rng1_uid16705_dupName_55_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q[33:1];

    // rightShiftStage0Idx1_uid16707_dupName_55_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16706)@102
    assign rightShiftStage0Idx1_uid16707_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16705_dupName_55_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24360_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(BITSELECT,24359)@101
    assign leftShiftStage2Idx1Rng8_uid24360_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in = leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24360_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24360_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24361_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(BITJOIN,24360)@101
    assign leftShiftStage2Idx1_uid24361_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24360_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24355_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(BITSELECT,24354)@101
    assign leftShiftStage1Idx1Rng4_uid24355_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in = leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24355_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24355_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24356_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(BITJOIN,24355)@101
    assign leftShiftStage1Idx1_uid24356_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24355_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24350_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(BITSELECT,24349)@101
    assign leftShiftStage0Idx1Rng1_uid24350_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24350_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24350_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24351_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(BITJOIN,24350)@101
    assign leftShiftStage0Idx1_uid24351_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24350_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16653_dupName_51_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16652)@100
    assign rightShiftStage2Idx1Rng8_uid16653_dupName_51_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16655_dupName_51_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16654)@100
    assign rightShiftStage2Idx1_uid16655_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16653_dupName_51_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16648_dupName_51_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16647)@100
    assign rightShiftStage1Idx1Rng4_uid16648_dupName_51_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16650_dupName_51_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16649)@100
    assign rightShiftStage1Idx1_uid16650_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16648_dupName_51_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16643_dupName_51_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16642)@100
    assign rightShiftStage0Idx1Rng1_uid16643_dupName_51_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q[33:1];

    // rightShiftStage0Idx1_uid16645_dupName_51_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16644)@100
    assign rightShiftStage0Idx1_uid16645_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16643_dupName_51_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24342_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(BITSELECT,24341)@99
    assign leftShiftStage2Idx1Rng8_uid24342_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in = leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24342_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24342_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24343_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(BITJOIN,24342)@99
    assign leftShiftStage2Idx1_uid24343_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24342_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24337_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(BITSELECT,24336)@99
    assign leftShiftStage1Idx1Rng4_uid24337_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in = leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24337_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24337_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24338_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(BITJOIN,24337)@99
    assign leftShiftStage1Idx1_uid24338_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24337_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24332_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(BITSELECT,24331)@99
    assign leftShiftStage0Idx1Rng1_uid24332_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24332_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24332_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24333_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(BITJOIN,24332)@99
    assign leftShiftStage0Idx1_uid24333_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24332_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16591_dupName_47_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16590)@98
    assign rightShiftStage2Idx1Rng8_uid16591_dupName_47_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16593_dupName_47_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16592)@98
    assign rightShiftStage2Idx1_uid16593_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16591_dupName_47_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16586_dupName_47_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16585)@98
    assign rightShiftStage1Idx1Rng4_uid16586_dupName_47_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16588_dupName_47_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16587)@98
    assign rightShiftStage1Idx1_uid16588_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16586_dupName_47_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16581_dupName_47_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16580)@98
    assign rightShiftStage0Idx1Rng1_uid16581_dupName_47_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q[33:1];

    // rightShiftStage0Idx1_uid16583_dupName_47_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16582)@98
    assign rightShiftStage0Idx1_uid16583_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16581_dupName_47_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24324_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(BITSELECT,24323)@97
    assign leftShiftStage2Idx1Rng8_uid24324_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in = leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24324_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24324_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24325_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(BITJOIN,24324)@97
    assign leftShiftStage2Idx1_uid24325_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24324_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24319_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(BITSELECT,24318)@97
    assign leftShiftStage1Idx1Rng4_uid24319_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in = leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24319_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24319_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24320_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(BITJOIN,24319)@97
    assign leftShiftStage1Idx1_uid24320_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24319_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24314_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(BITSELECT,24313)@97
    assign leftShiftStage0Idx1Rng1_uid24314_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24314_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24314_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24315_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(BITJOIN,24314)@97
    assign leftShiftStage0Idx1_uid24315_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24314_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16529_dupName_43_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16528)@96
    assign rightShiftStage2Idx1Rng8_uid16529_dupName_43_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16531_dupName_43_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16530)@96
    assign rightShiftStage2Idx1_uid16531_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16529_dupName_43_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16524_dupName_43_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16523)@96
    assign rightShiftStage1Idx1Rng4_uid16524_dupName_43_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16526_dupName_43_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16525)@96
    assign rightShiftStage1Idx1_uid16526_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16524_dupName_43_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16519_dupName_43_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16518)@96
    assign rightShiftStage0Idx1Rng1_uid16519_dupName_43_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q[33:1];

    // rightShiftStage0Idx1_uid16521_dupName_43_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16520)@96
    assign rightShiftStage0Idx1_uid16521_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16519_dupName_43_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24162_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(BITSELECT,24161)@95
    assign leftShiftStage2Idx1Rng8_uid24162_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in = leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24162_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24162_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24163_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(BITJOIN,24162)@95
    assign leftShiftStage2Idx1_uid24163_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24162_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24157_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(BITSELECT,24156)@95
    assign leftShiftStage1Idx1Rng4_uid24157_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in = leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24157_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24157_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24158_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(BITJOIN,24157)@95
    assign leftShiftStage1Idx1_uid24158_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24157_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24152_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(BITSELECT,24151)@95
    assign leftShiftStage0Idx1Rng1_uid24152_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24152_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24152_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24153_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(BITJOIN,24152)@95
    assign leftShiftStage0Idx1_uid24153_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24152_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16467_dupName_39_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16466)@94
    assign rightShiftStage2Idx1Rng8_uid16467_dupName_39_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16469_dupName_39_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16468)@94
    assign rightShiftStage2Idx1_uid16469_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16467_dupName_39_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16462_dupName_39_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16461)@94
    assign rightShiftStage1Idx1Rng4_uid16462_dupName_39_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16464_dupName_39_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16463)@94
    assign rightShiftStage1Idx1_uid16464_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16462_dupName_39_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16457_dupName_39_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16456)@94
    assign rightShiftStage0Idx1Rng1_uid16457_dupName_39_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q[33:1];

    // rightShiftStage0Idx1_uid16459_dupName_39_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16458)@94
    assign rightShiftStage0Idx1_uid16459_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16457_dupName_39_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid23964_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(BITSELECT,23963)@93
    assign leftShiftStage2Idx1Rng8_uid23964_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in = leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid23964_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid23964_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid23965_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(BITJOIN,23964)@93
    assign leftShiftStage2Idx1_uid23965_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid23964_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid23959_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(BITSELECT,23958)@93
    assign leftShiftStage1Idx1Rng4_uid23959_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in = leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid23959_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid23959_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid23960_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(BITJOIN,23959)@93
    assign leftShiftStage1Idx1_uid23960_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid23959_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid23954_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(BITSELECT,23953)@93
    assign leftShiftStage0Idx1Rng1_uid23954_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid23954_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid23954_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid23955_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(BITJOIN,23954)@93
    assign leftShiftStage0Idx1_uid23955_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid23954_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16405_dupName_35_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16404)@92
    assign rightShiftStage2Idx1Rng8_uid16405_dupName_35_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16407_dupName_35_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16406)@92
    assign rightShiftStage2Idx1_uid16407_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16405_dupName_35_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16400_dupName_35_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16399)@92
    assign rightShiftStage1Idx1Rng4_uid16400_dupName_35_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16402_dupName_35_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16401)@92
    assign rightShiftStage1Idx1_uid16402_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16400_dupName_35_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16395_dupName_35_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16394)@92
    assign rightShiftStage0Idx1Rng1_uid16395_dupName_35_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q[33:1];

    // rightShiftStage0Idx1_uid16397_dupName_35_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16396)@92
    assign rightShiftStage0Idx1_uid16397_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16395_dupName_35_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid26052_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(BITSELECT,26051)@91
    assign leftShiftStage2Idx1Rng8_uid26052_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in = leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid26052_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid26052_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid26053_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(BITJOIN,26052)@91
    assign leftShiftStage2Idx1_uid26053_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid26052_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid26047_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(BITSELECT,26046)@91
    assign leftShiftStage1Idx1Rng4_uid26047_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in = leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid26047_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid26047_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid26048_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(BITJOIN,26047)@91
    assign leftShiftStage1Idx1_uid26048_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid26047_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid26042_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(BITSELECT,26041)@91
    assign leftShiftStage0Idx1Rng1_uid26042_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid26042_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid26042_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid26043_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(BITJOIN,26042)@91
    assign leftShiftStage0Idx1_uid26043_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid26042_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16343_dupName_31_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16342)@90
    assign rightShiftStage2Idx1Rng8_uid16343_dupName_31_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16345_dupName_31_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16344)@90
    assign rightShiftStage2Idx1_uid16345_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16343_dupName_31_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16338_dupName_31_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16337)@90
    assign rightShiftStage1Idx1Rng4_uid16338_dupName_31_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16340_dupName_31_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16339)@90
    assign rightShiftStage1Idx1_uid16340_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16338_dupName_31_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16333_dupName_31_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16332)@90
    assign rightShiftStage0Idx1Rng1_uid16333_dupName_31_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q[33:1];

    // rightShiftStage0Idx1_uid16335_dupName_31_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16334)@90
    assign rightShiftStage0Idx1_uid16335_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16333_dupName_31_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25854_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(BITSELECT,25853)@89
    assign leftShiftStage2Idx1Rng8_uid25854_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in = leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25854_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25854_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25855_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(BITJOIN,25854)@89
    assign leftShiftStage2Idx1_uid25855_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25854_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25849_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(BITSELECT,25848)@89
    assign leftShiftStage1Idx1Rng4_uid25849_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in = leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25849_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25849_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25850_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(BITJOIN,25849)@89
    assign leftShiftStage1Idx1_uid25850_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25849_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25844_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(BITSELECT,25843)@89
    assign leftShiftStage0Idx1Rng1_uid25844_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25844_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25844_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25845_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(BITJOIN,25844)@89
    assign leftShiftStage0Idx1_uid25845_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25844_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16281_dupName_27_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16280)@88
    assign rightShiftStage2Idx1Rng8_uid16281_dupName_27_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16283_dupName_27_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16282)@88
    assign rightShiftStage2Idx1_uid16283_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16281_dupName_27_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16276_dupName_27_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16275)@88
    assign rightShiftStage1Idx1Rng4_uid16276_dupName_27_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16278_dupName_27_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16277)@88
    assign rightShiftStage1Idx1_uid16278_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16276_dupName_27_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16271_dupName_27_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16270)@88
    assign rightShiftStage0Idx1Rng1_uid16271_dupName_27_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q[33:1];

    // rightShiftStage0Idx1_uid16273_dupName_27_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16272)@88
    assign rightShiftStage0Idx1_uid16273_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16271_dupName_27_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25656_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(BITSELECT,25655)@87
    assign leftShiftStage2Idx1Rng8_uid25656_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in = leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25656_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25656_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25657_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(BITJOIN,25656)@87
    assign leftShiftStage2Idx1_uid25657_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25656_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25651_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(BITSELECT,25650)@87
    assign leftShiftStage1Idx1Rng4_uid25651_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in = leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25651_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25651_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25652_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(BITJOIN,25651)@87
    assign leftShiftStage1Idx1_uid25652_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25651_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25646_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(BITSELECT,25645)@87
    assign leftShiftStage0Idx1Rng1_uid25646_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25646_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25646_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25647_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(BITJOIN,25646)@87
    assign leftShiftStage0Idx1_uid25647_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25646_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16219_dupName_23_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16218)@86
    assign rightShiftStage2Idx1Rng8_uid16219_dupName_23_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16221_dupName_23_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16220)@86
    assign rightShiftStage2Idx1_uid16221_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16219_dupName_23_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16214_dupName_23_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16213)@86
    assign rightShiftStage1Idx1Rng4_uid16214_dupName_23_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16216_dupName_23_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16215)@86
    assign rightShiftStage1Idx1_uid16216_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16214_dupName_23_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16209_dupName_23_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16208)@86
    assign rightShiftStage0Idx1Rng1_uid16209_dupName_23_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q[33:1];

    // rightShiftStage0Idx1_uid16211_dupName_23_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16210)@86
    assign rightShiftStage0Idx1_uid16211_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16209_dupName_23_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25458_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(BITSELECT,25457)@85
    assign leftShiftStage2Idx1Rng8_uid25458_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in = leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25458_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25458_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25459_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(BITJOIN,25458)@85
    assign leftShiftStage2Idx1_uid25459_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25458_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25453_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(BITSELECT,25452)@85
    assign leftShiftStage1Idx1Rng4_uid25453_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in = leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25453_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25453_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25454_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(BITJOIN,25453)@85
    assign leftShiftStage1Idx1_uid25454_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25453_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25448_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(BITSELECT,25447)@85
    assign leftShiftStage0Idx1Rng1_uid25448_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25448_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25448_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25449_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(BITJOIN,25448)@85
    assign leftShiftStage0Idx1_uid25449_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25448_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16157_dupName_19_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16156)@84
    assign rightShiftStage2Idx1Rng8_uid16157_dupName_19_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16159_dupName_19_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16158)@84
    assign rightShiftStage2Idx1_uid16159_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16157_dupName_19_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16152_dupName_19_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16151)@84
    assign rightShiftStage1Idx1Rng4_uid16152_dupName_19_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16154_dupName_19_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16153)@84
    assign rightShiftStage1Idx1_uid16154_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16152_dupName_19_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16147_dupName_19_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16146)@84
    assign rightShiftStage0Idx1Rng1_uid16147_dupName_19_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q[33:1];

    // rightShiftStage0Idx1_uid16149_dupName_19_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16148)@84
    assign rightShiftStage0Idx1_uid16149_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16147_dupName_19_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25260_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(BITSELECT,25259)@83
    assign leftShiftStage2Idx1Rng8_uid25260_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in = leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25260_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25260_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25261_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(BITJOIN,25260)@83
    assign leftShiftStage2Idx1_uid25261_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25260_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25255_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(BITSELECT,25254)@83
    assign leftShiftStage1Idx1Rng4_uid25255_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in = leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25255_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25255_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25256_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(BITJOIN,25255)@83
    assign leftShiftStage1Idx1_uid25256_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25255_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25250_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(BITSELECT,25249)@83
    assign leftShiftStage0Idx1Rng1_uid25250_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25250_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25250_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25251_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(BITJOIN,25250)@83
    assign leftShiftStage0Idx1_uid25251_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25250_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16095_dupName_15_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16094)@82
    assign rightShiftStage2Idx1Rng8_uid16095_dupName_15_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16097_dupName_15_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16096)@82
    assign rightShiftStage2Idx1_uid16097_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16095_dupName_15_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16090_dupName_15_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16089)@82
    assign rightShiftStage1Idx1Rng4_uid16090_dupName_15_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16092_dupName_15_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16091)@82
    assign rightShiftStage1Idx1_uid16092_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16090_dupName_15_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16085_dupName_15_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16084)@82
    assign rightShiftStage0Idx1Rng1_uid16085_dupName_15_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q[33:1];

    // rightShiftStage0Idx1_uid16087_dupName_15_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16086)@82
    assign rightShiftStage0Idx1_uid16087_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16085_dupName_15_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid25062_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(BITSELECT,25061)@81
    assign leftShiftStage2Idx1Rng8_uid25062_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in = leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid25062_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid25062_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid25063_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(BITJOIN,25062)@81
    assign leftShiftStage2Idx1_uid25063_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid25062_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid25057_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(BITSELECT,25056)@81
    assign leftShiftStage1Idx1Rng4_uid25057_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in = leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid25057_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid25057_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid25058_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(BITJOIN,25057)@81
    assign leftShiftStage1Idx1_uid25058_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid25057_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid25052_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(BITSELECT,25051)@81
    assign leftShiftStage0Idx1Rng1_uid25052_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid25052_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid25052_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid25053_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(BITJOIN,25052)@81
    assign leftShiftStage0Idx1_uid25053_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid25052_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid16033_dupName_11_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16032)@80
    assign rightShiftStage2Idx1Rng8_uid16033_dupName_11_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid16035_dupName_11_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16034)@80
    assign rightShiftStage2Idx1_uid16035_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid16033_dupName_11_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid16028_dupName_11_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16027)@80
    assign rightShiftStage1Idx1Rng4_uid16028_dupName_11_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid16030_dupName_11_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16029)@80
    assign rightShiftStage1Idx1_uid16030_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid16028_dupName_11_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid16023_dupName_11_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16022)@80
    assign rightShiftStage0Idx1Rng1_uid16023_dupName_11_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q[33:1];

    // rightShiftStage0Idx1_uid16025_dupName_11_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16024)@80
    assign rightShiftStage0Idx1_uid16025_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid16023_dupName_11_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24864_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(BITSELECT,24863)@79
    assign leftShiftStage2Idx1Rng8_uid24864_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in = leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24864_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24864_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24865_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(BITJOIN,24864)@79
    assign leftShiftStage2Idx1_uid24865_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24864_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24859_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(BITSELECT,24858)@79
    assign leftShiftStage1Idx1Rng4_uid24859_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in = leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24859_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24859_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24860_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(BITJOIN,24859)@79
    assign leftShiftStage1Idx1_uid24860_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24859_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24854_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(BITSELECT,24853)@79
    assign leftShiftStage0Idx1Rng1_uid24854_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24854_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24854_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24855_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(BITJOIN,24854)@79
    assign leftShiftStage0Idx1_uid24855_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24854_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15971_dupName_7_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15970)@78
    assign rightShiftStage2Idx1Rng8_uid15971_dupName_7_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15973_dupName_7_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15972)@78
    assign rightShiftStage2Idx1_uid15973_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid15971_dupName_7_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15966_dupName_7_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15965)@78
    assign rightShiftStage1Idx1Rng4_uid15966_dupName_7_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15968_dupName_7_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15967)@78
    assign rightShiftStage1Idx1_uid15968_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid15966_dupName_7_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15961_dupName_7_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15960)@78
    assign rightShiftStage0Idx1Rng1_uid15961_dupName_7_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q[33:1];

    // rightShiftStage0Idx1_uid15963_dupName_7_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15962)@78
    assign rightShiftStage0Idx1_uid15963_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15961_dupName_7_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24666_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(BITSELECT,24665)@77
    assign leftShiftStage2Idx1Rng8_uid24666_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in = leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24666_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24666_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24667_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(BITJOIN,24666)@77
    assign leftShiftStage2Idx1_uid24667_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24666_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24661_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(BITSELECT,24660)@77
    assign leftShiftStage1Idx1Rng4_uid24661_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in = leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24661_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24661_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24662_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(BITJOIN,24661)@77
    assign leftShiftStage1Idx1_uid24662_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24661_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24656_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(BITSELECT,24655)@77
    assign leftShiftStage0Idx1Rng1_uid24656_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24656_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24656_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24657_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(BITJOIN,24656)@77
    assign leftShiftStage0Idx1_uid24657_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24656_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid15909_dupName_3_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15908)@76
    assign rightShiftStage2Idx1Rng8_uid15909_dupName_3_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid15911_dupName_3_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15910)@76
    assign rightShiftStage2Idx1_uid15911_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid15909_dupName_3_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid15904_dupName_3_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15903)@76
    assign rightShiftStage1Idx1Rng4_uid15904_dupName_3_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid15906_dupName_3_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15905)@76
    assign rightShiftStage1Idx1_uid15906_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid15904_dupName_3_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid15899_dupName_3_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15898)@76
    assign rightShiftStage0Idx1Rng1_uid15899_dupName_3_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q[33:1];

    // rightShiftStage0Idx1_uid15901_dupName_3_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15900)@76
    assign rightShiftStage0Idx1_uid15901_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid15899_dupName_3_i_unnamed_c_compmm_m0_shift_x_b};

    // leftShiftStage2Idx1Rng8_uid24468_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(BITSELECT,24467)@75
    assign leftShiftStage2Idx1Rng8_uid24468_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in = leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q[20:0];
    assign leftShiftStage2Idx1Rng8_uid24468_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b = leftShiftStage2Idx1Rng8_uid24468_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in[20:0];

    // leftShiftStage2Idx1_uid24469_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(BITJOIN,24468)@75
    assign leftShiftStage2Idx1_uid24469_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = {leftShiftStage2Idx1Rng8_uid24468_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b, rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage1Idx1Rng4_uid24463_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(BITSELECT,24462)@75
    assign leftShiftStage1Idx1Rng4_uid24463_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in = leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q[24:0];
    assign leftShiftStage1Idx1Rng4_uid24463_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b = leftShiftStage1Idx1Rng4_uid24463_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in[24:0];

    // leftShiftStage1Idx1_uid24464_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(BITJOIN,24463)@75
    assign leftShiftStage1Idx1_uid24464_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = {leftShiftStage1Idx1Rng4_uid24463_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b, rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q};

    // leftShiftStage0Idx1Rng1_uid24458_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(BITSELECT,24457)@75
    assign leftShiftStage0Idx1Rng1_uid24458_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in = i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_join_q[27:0];
    assign leftShiftStage0Idx1Rng1_uid24458_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b = leftShiftStage0Idx1Rng1_uid24458_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_in[27:0];

    // leftShiftStage0Idx1_uid24459_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(BITJOIN,24458)@75
    assign leftShiftStage0Idx1_uid24459_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = {leftShiftStage0Idx1Rng1_uid24458_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_b, GND_q};

    // rightShiftStage2Idx1Rng8_uid28355_i_unnamed_c_compmm_m0_shift_x(BITSELECT,28354)@75
    assign rightShiftStage2Idx1Rng8_uid28355_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage2Idx1_uid28357_i_unnamed_c_compmm_m0_shift_x(BITJOIN,28356)@75
    assign rightShiftStage2Idx1_uid28357_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage2Idx1Rng8_uid28355_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage1Idx1Rng4_uid28350_i_unnamed_c_compmm_m0_shift_x(BITSELECT,28349)@75
    assign rightShiftStage1Idx1Rng4_uid28350_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_q[33:4];

    // rightShiftStage1Idx1_uid28352_i_unnamed_c_compmm_m0_shift_x(BITJOIN,28351)@75
    assign rightShiftStage1Idx1_uid28352_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng4_uid28350_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng1_uid28345_i_unnamed_c_compmm_m0_shift_x(BITSELECT,28344)@75
    assign rightShiftStage0Idx1Rng1_uid28345_i_unnamed_c_compmm_m0_shift_x_b = i_conv_i_i_i84_i_c_compmm_m262_sel_x_b[33:1];

    // rightShiftStage0Idx1_uid28347_i_unnamed_c_compmm_m0_shift_x(BITJOIN,28346)@75
    assign rightShiftStage0Idx1_uid28347_i_unnamed_c_compmm_m0_shift_x_q = {GND_q, rightShiftStage0Idx1Rng1_uid28345_i_unnamed_c_compmm_m0_shift_x_b};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma(CHAINMULTADD,29127)@69 + 5
    // out q@75
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6420_c_compmm_m256_out_dest_data_out_2_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6419_c_compmm_m257_out_dest_data_out_1_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ch[0] <= redist504_sync_together4364_aunroll_x_in_c1_eni5_2_tpl_1_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ch[1] <= redist503_sync_together4364_aunroll_x_in_c1_eni5_1_tpl_1_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_qq[32:0]);

    // i_conv_i_i_i84_i_c_compmm_m262_sel_x(BITSELECT,3448)@75
    assign i_conv_i_i_i84_i_c_compmm_m262_sel_x_b = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_i_c_compmm_m259_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_i_c_compmm_m261_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_i_c_compmm_m260_merged_cma_q[32:0]});

    // rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x(MUX,28348)@75
    assign rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_s or i_conv_i_i_i84_i_c_compmm_m262_sel_x_b or rightShiftStage0Idx1_uid28347_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_q = i_conv_i_i_i84_i_c_compmm_m262_sel_x_b;
            1'b1 : rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid28347_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x(MUX,28353)@75
    assign rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid28352_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid28349_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid28352_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x(MUX,28358)@75
    assign rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid28357_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid28354_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid28357_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m263_vt_select_20(BITSELECT,11509)@75
    assign i_unnamed_c_compmm_m263_vt_select_20_b = rightShiftStage2_uid28359_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m263_vt_join(BITJOIN,11508)@75
    assign i_unnamed_c_compmm_m263_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m263_vt_select_20_b};

    // i_conv_i_i_i_i97_i_c_compmm_m264_sel_x(BITSELECT,3576)@75
    assign i_conv_i_i_i_i97_i_c_compmm_m264_sel_x_b = i_unnamed_c_compmm_m263_vt_join_q[15:0];

    // rightShiftStage1Idx1Rng8_uid15860_dupName_0_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15859)@75
    assign rightShiftStage1Idx1Rng8_uid15860_dupName_0_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15862_dupName_0_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15861)@75
    assign rightShiftStage1Idx1_uid15862_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid15860_dupName_0_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15855_dupName_0_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15854)@75
    assign rightShiftStage0Idx1Rng4_uid15855_dupName_0_i_unnamed_c_compmm_m0_shift_x_b = i_conv_i_i_i84_i_c_compmm_m262_sel_x_b[33:4];

    // rightShiftStage0Idx1_uid15857_dupName_0_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15856)@75
    assign rightShiftStage0Idx1_uid15857_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid15855_dupName_0_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x(MUX,15858)@75
    assign rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_s or i_conv_i_i_i84_i_c_compmm_m262_sel_x_b or rightShiftStage0Idx1_uid15857_dupName_0_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = i_conv_i_i_i84_i_c_compmm_m262_sel_x_b;
            1'b1 : rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15857_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x(MUX,15863)@75
    assign rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15862_dupName_0_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15859_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15862_dupName_0_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m265_vt_select_21(BITSELECT,11526)@75
    assign i_unnamed_c_compmm_m265_vt_select_21_b = rightShiftStage1_uid15864_dupName_0_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m265_vt_join(BITJOIN,11525)@75
    assign i_unnamed_c_compmm_m265_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m265_vt_select_21_b};

    // i_unnamed_c_compmm_m266_sel_x(BITSELECT,6122)@75
    assign i_unnamed_c_compmm_m266_sel_x_b = i_unnamed_c_compmm_m265_vt_join_q[15:0];

    // i_unnamed_c_compmm_m267_BitSelect_for_a(BITSELECT,28598)@75
    assign i_unnamed_c_compmm_m267_BitSelect_for_a_b = i_unnamed_c_compmm_m266_sel_x_b[0:0];

    // i_unnamed_c_compmm_m267_join(BITJOIN,28599)@75
    assign i_unnamed_c_compmm_m267_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m267_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m267_vt_select_0(BITSELECT,11550)@75
    assign i_unnamed_c_compmm_m267_vt_select_0_b = i_unnamed_c_compmm_m267_join_q[0:0];

    // i_unnamed_c_compmm_m267_vt_join(BITJOIN,11549)@75
    assign i_unnamed_c_compmm_m267_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, i_unnamed_c_compmm_m267_vt_select_0_b};

    // i_add_i_i_i_i_i126_i_c_compmm_m268(ADD,7159)@75
    assign i_add_i_i_i_i_i126_i_c_compmm_m268_a = {1'b0, i_unnamed_c_compmm_m267_vt_join_q};
    assign i_add_i_i_i_i_i126_i_c_compmm_m268_b = {1'b0, i_conv_i_i_i_i97_i_c_compmm_m264_sel_x_b};
    assign i_add_i_i_i_i_i126_i_c_compmm_m268_o = $unsigned(i_add_i_i_i_i_i126_i_c_compmm_m268_a) + $unsigned(i_add_i_i_i_i_i126_i_c_compmm_m268_b);
    assign i_add_i_i_i_i_i126_i_c_compmm_m268_q = i_add_i_i_i_i_i126_i_c_compmm_m268_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_c_compmm_m268_sel_x(BITSELECT,2173)@75
    assign bgTrunc_i_add_i_i_i_i_i126_i_c_compmm_m268_sel_x_b = i_add_i_i_i_i_i126_i_c_compmm_m268_q[15:0];

    // i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_sel_x(BITSELECT,3616)@75
    assign i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_c_compmm_m268_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_select_15(BITSELECT,7575)@75
    assign i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_select_15_b = i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_join(BITJOIN,7574)@75
    assign i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_select_15_b};

    // leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(MUX,24460)@75
    assign leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_join_q or leftShiftStage0Idx1_uid24459_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_1_c_compmm_m286_vt_join_q;
            1'b1 : leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24459_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(MUX,24465)@75
    assign leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s or leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24464_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = leftShiftStage0_uid24461_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24464_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x(MUX,24470)@75
    assign leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s or leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24469_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = leftShiftStage1_uid24466_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24469_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28(BITSELECT,9574)@75
    assign i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28_b = leftShiftStage2_uid24471_i_shl_i_i_i_i_i77_i_1_c_compmm_m0_shift_x_q[28:13];

    // redist464_i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28_b_1(DELAY,29592)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist464_i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_join(BITJOIN,9573)@76
    assign i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_join_q = {redist464_i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma(CHAINMULTADD,29038)@70 + 5
    // out q@76
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6422_c_compmm_m254_out_dest_data_out_4_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6421_c_compmm_m255_out_dest_data_out_3_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ch[0] <= redist506_sync_together4364_aunroll_x_in_c1_eni5_4_tpl_2_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ch[1] <= redist505_sync_together4364_aunroll_x_in_c1_eni5_3_tpl_2_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288(ADD,8858)@76
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_1_i_c_compmm_m283_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_1_i_c_compmm_m285_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_1_i_c_compmm_m284_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_1_c_compmm_m287_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_o[33:0];

    // rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x(MUX,15902)@76
    assign rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q or rightShiftStage0Idx1_uid15901_dupName_3_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q;
            1'b1 : rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15901_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x(MUX,15907)@76
    assign rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15906_dupName_3_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15903_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15906_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x(MUX,15912)@76
    assign rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid15911_dupName_3_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid15908_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid15911_dupName_3_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m289_vt_select_20(BITSELECT,11740)@76
    assign i_unnamed_c_compmm_m289_vt_select_20_b = rightShiftStage2_uid15913_dupName_3_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m289_vt_join(BITJOIN,11739)@76
    assign i_unnamed_c_compmm_m289_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m289_vt_select_20_b};

    // i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x(BITSELECT,3487)@76
    assign i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x_b = i_unnamed_c_compmm_m289_vt_join_q[15:0];

    // redist1102_i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x_b_1(DELAY,30230)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1102_i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15922_dupName_4_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15921)@76
    assign rightShiftStage1Idx1Rng8_uid15922_dupName_4_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15924_dupName_4_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15923)@76
    assign rightShiftStage1Idx1_uid15924_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid15922_dupName_4_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15917_dupName_4_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15916)@76
    assign rightShiftStage0Idx1Rng4_uid15917_dupName_4_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q[33:4];

    // rightShiftStage0Idx1_uid15919_dupName_4_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15918)@76
    assign rightShiftStage0Idx1_uid15919_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid15917_dupName_4_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x(MUX,15920)@76
    assign rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q or rightShiftStage0Idx1_uid15919_dupName_4_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_1_i_c_compmm_m288_q;
            1'b1 : rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15919_dupName_4_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x(MUX,15925)@76
    assign rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15924_dupName_4_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15921_dupName_4_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15924_dupName_4_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m291_vt_select_21(BITSELECT,11754)@76
    assign i_unnamed_c_compmm_m291_vt_select_21_b = rightShiftStage1_uid15926_dupName_4_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m291_vt_join(BITJOIN,11753)@76
    assign i_unnamed_c_compmm_m291_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m291_vt_select_21_b};

    // i_unnamed_c_compmm_m292_sel_x(BITSELECT,6143)@76
    assign i_unnamed_c_compmm_m292_sel_x_b = i_unnamed_c_compmm_m291_vt_join_q[15:0];

    // i_unnamed_c_compmm_m293_BitSelect_for_a(BITSELECT,28640)@76
    assign i_unnamed_c_compmm_m293_BitSelect_for_a_b = i_unnamed_c_compmm_m292_sel_x_b[0:0];

    // i_unnamed_c_compmm_m293_join(BITJOIN,28641)@76
    assign i_unnamed_c_compmm_m293_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m293_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m293_vt_select_0(BITSELECT,11773)@76
    assign i_unnamed_c_compmm_m293_vt_select_0_b = i_unnamed_c_compmm_m293_join_q[0:0];

    // redist116_i_unnamed_c_compmm_m293_vt_select_0_b_1(DELAY,29244)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist116_i_unnamed_c_compmm_m293_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m293_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m293_vt_join(BITJOIN,11772)@77
    assign i_unnamed_c_compmm_m293_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist116_i_unnamed_c_compmm_m293_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_1_c_compmm_m294(ADD,7070)@77
    assign i_add_i_i_i_i_i126_i_1_c_compmm_m294_a = {1'b0, i_unnamed_c_compmm_m293_vt_join_q};
    assign i_add_i_i_i_i_i126_i_1_c_compmm_m294_b = {1'b0, redist1102_i_conv_i_i_i_i97_i_1_c_compmm_m290_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_1_c_compmm_m294_o = $unsigned(i_add_i_i_i_i_i126_i_1_c_compmm_m294_a) + $unsigned(i_add_i_i_i_i_i126_i_1_c_compmm_m294_b);
    assign i_add_i_i_i_i_i126_i_1_c_compmm_m294_q = i_add_i_i_i_i_i126_i_1_c_compmm_m294_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_1_c_compmm_m294_sel_x(BITSELECT,2084)@77
    assign bgTrunc_i_add_i_i_i_i_i126_i_1_c_compmm_m294_sel_x_b = i_add_i_i_i_i_i126_i_1_c_compmm_m294_q[15:0];

    // i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_sel_x(BITSELECT,3627)@77
    assign i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_1_c_compmm_m294_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_select_15(BITSELECT,7619)@77
    assign i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_select_15_b = i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_join(BITJOIN,7618)@77
    assign i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_select_15_b};

    // leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(MUX,24658)@77
    assign leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_join_q or leftShiftStage0Idx1_uid24657_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_2_c_compmm_m314_vt_join_q;
            1'b1 : leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24657_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(MUX,24663)@77
    assign leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s or leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24662_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = leftShiftStage0_uid24659_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24662_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x(MUX,24668)@77
    assign leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s or leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24667_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = leftShiftStage1_uid24664_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24667_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28(BITSELECT,9607)@77
    assign i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28_b = leftShiftStage2_uid24669_i_shl_i_i_i_i_i77_i_2_c_compmm_m0_shift_x_q[28:13];

    // redist453_i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28_b_1(DELAY,29581)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist453_i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_join(BITJOIN,9606)@78
    assign i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_join_q = {redist453_i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma(CHAINMULTADD,29049)@72 + 5
    // out q@78
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6424_c_compmm_m252_out_dest_data_out_6_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6423_c_compmm_m253_out_dest_data_out_5_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ch[0] <= redist508_sync_together4364_aunroll_x_in_c1_eni5_6_tpl_4_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ch[1] <= redist507_sync_together4364_aunroll_x_in_c1_eni5_5_tpl_4_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316(ADD,8869)@78
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_2_i_c_compmm_m311_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_2_i_c_compmm_m313_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_2_i_c_compmm_m312_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_2_c_compmm_m315_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_o[33:0];

    // rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x(MUX,15964)@78
    assign rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q or rightShiftStage0Idx1_uid15963_dupName_7_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q;
            1'b1 : rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15963_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x(MUX,15969)@78
    assign rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15968_dupName_7_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15965_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15968_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x(MUX,15974)@78
    assign rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid15973_dupName_7_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid15970_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid15973_dupName_7_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m317_vt_select_20(BITSELECT,11978)@78
    assign i_unnamed_c_compmm_m317_vt_select_20_b = rightShiftStage2_uid15975_dupName_7_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m317_vt_join(BITJOIN,11977)@78
    assign i_unnamed_c_compmm_m317_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m317_vt_select_20_b};

    // i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x(BITSELECT,3498)@78
    assign i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x_b = i_unnamed_c_compmm_m317_vt_join_q[15:0];

    // redist1091_i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x_b_1(DELAY,30219)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1091_i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid15984_dupName_8_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15983)@78
    assign rightShiftStage1Idx1Rng8_uid15984_dupName_8_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid15986_dupName_8_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15985)@78
    assign rightShiftStage1Idx1_uid15986_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid15984_dupName_8_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid15979_dupName_8_i_unnamed_c_compmm_m0_shift_x(BITSELECT,15978)@78
    assign rightShiftStage0Idx1Rng4_uid15979_dupName_8_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q[33:4];

    // rightShiftStage0Idx1_uid15981_dupName_8_i_unnamed_c_compmm_m0_shift_x(BITJOIN,15980)@78
    assign rightShiftStage0Idx1_uid15981_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid15979_dupName_8_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x(MUX,15982)@78
    assign rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q or rightShiftStage0Idx1_uid15981_dupName_8_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_2_i_c_compmm_m316_q;
            1'b1 : rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid15981_dupName_8_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x(MUX,15987)@78
    assign rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid15986_dupName_8_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid15983_dupName_8_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid15986_dupName_8_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m319_vt_select_21(BITSELECT,11996)@78
    assign i_unnamed_c_compmm_m319_vt_select_21_b = rightShiftStage1_uid15988_dupName_8_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m319_vt_join(BITJOIN,11995)@78
    assign i_unnamed_c_compmm_m319_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m319_vt_select_21_b};

    // i_unnamed_c_compmm_m320_sel_x(BITSELECT,6165)@78
    assign i_unnamed_c_compmm_m320_sel_x_b = i_unnamed_c_compmm_m319_vt_join_q[15:0];

    // i_unnamed_c_compmm_m321_BitSelect_for_a(BITSELECT,28684)@78
    assign i_unnamed_c_compmm_m321_BitSelect_for_a_b = i_unnamed_c_compmm_m320_sel_x_b[0:0];

    // i_unnamed_c_compmm_m321_join(BITJOIN,28685)@78
    assign i_unnamed_c_compmm_m321_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m321_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m321_vt_select_0(BITSELECT,12012)@78
    assign i_unnamed_c_compmm_m321_vt_select_0_b = i_unnamed_c_compmm_m321_join_q[0:0];

    // redist95_i_unnamed_c_compmm_m321_vt_select_0_b_1(DELAY,29223)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist95_i_unnamed_c_compmm_m321_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m321_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m321_vt_join(BITJOIN,12011)@79
    assign i_unnamed_c_compmm_m321_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist95_i_unnamed_c_compmm_m321_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_2_c_compmm_m322(ADD,7081)@79
    assign i_add_i_i_i_i_i126_i_2_c_compmm_m322_a = {1'b0, i_unnamed_c_compmm_m321_vt_join_q};
    assign i_add_i_i_i_i_i126_i_2_c_compmm_m322_b = {1'b0, redist1091_i_conv_i_i_i_i97_i_2_c_compmm_m318_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_2_c_compmm_m322_o = $unsigned(i_add_i_i_i_i_i126_i_2_c_compmm_m322_a) + $unsigned(i_add_i_i_i_i_i126_i_2_c_compmm_m322_b);
    assign i_add_i_i_i_i_i126_i_2_c_compmm_m322_q = i_add_i_i_i_i_i126_i_2_c_compmm_m322_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_2_c_compmm_m322_sel_x(BITSELECT,2095)@79
    assign bgTrunc_i_add_i_i_i_i_i126_i_2_c_compmm_m322_sel_x_b = i_add_i_i_i_i_i126_i_2_c_compmm_m322_q[15:0];

    // i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_sel_x(BITSELECT,3638)@79
    assign i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_2_c_compmm_m322_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_select_15(BITSELECT,7663)@79
    assign i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_select_15_b = i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_join(BITJOIN,7662)@79
    assign i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_select_15_b};

    // leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(MUX,24856)@79
    assign leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_join_q or leftShiftStage0Idx1_uid24855_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_3_c_compmm_m342_vt_join_q;
            1'b1 : leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24855_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(MUX,24861)@79
    assign leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s or leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24860_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = leftShiftStage0_uid24857_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24860_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x(MUX,24866)@79
    assign leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s or leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24865_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = leftShiftStage1_uid24862_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24865_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28(BITSELECT,9640)@79
    assign i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28_b = leftShiftStage2_uid24867_i_shl_i_i_i_i_i77_i_3_c_compmm_m0_shift_x_q[28:13];

    // redist442_i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28_b_1(DELAY,29570)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist442_i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_join(BITJOIN,9639)@80
    assign i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_join_q = {redist442_i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma(CHAINMULTADD,29060)@74 + 5
    // out q@80
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6426_c_compmm_m250_out_dest_data_out_8_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6425_c_compmm_m251_out_dest_data_out_7_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ch[0] <= redist510_sync_together4364_aunroll_x_in_c1_eni5_8_tpl_6_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ch[1] <= redist509_sync_together4364_aunroll_x_in_c1_eni5_7_tpl_6_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344(ADD,8880)@80
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_3_i_c_compmm_m339_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_3_i_c_compmm_m341_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_3_i_c_compmm_m340_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_3_c_compmm_m343_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_o[33:0];

    // rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x(MUX,16026)@80
    assign rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q or rightShiftStage0Idx1_uid16025_dupName_11_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q;
            1'b1 : rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16025_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x(MUX,16031)@80
    assign rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16030_dupName_11_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16027_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16030_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x(MUX,16036)@80
    assign rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16035_dupName_11_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16032_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16035_dupName_11_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m345_vt_select_20(BITSELECT,12220)@80
    assign i_unnamed_c_compmm_m345_vt_select_20_b = rightShiftStage2_uid16037_dupName_11_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m345_vt_join(BITJOIN,12219)@80
    assign i_unnamed_c_compmm_m345_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m345_vt_select_20_b};

    // i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x(BITSELECT,3509)@80
    assign i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x_b = i_unnamed_c_compmm_m345_vt_join_q[15:0];

    // redist1080_i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x_b_1(DELAY,30208)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1080_i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16046_dupName_12_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16045)@80
    assign rightShiftStage1Idx1Rng8_uid16046_dupName_12_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16048_dupName_12_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16047)@80
    assign rightShiftStage1Idx1_uid16048_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16046_dupName_12_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16041_dupName_12_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16040)@80
    assign rightShiftStage0Idx1Rng4_uid16041_dupName_12_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q[33:4];

    // rightShiftStage0Idx1_uid16043_dupName_12_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16042)@80
    assign rightShiftStage0Idx1_uid16043_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16041_dupName_12_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x(MUX,16044)@80
    assign rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q or rightShiftStage0Idx1_uid16043_dupName_12_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_3_i_c_compmm_m344_q;
            1'b1 : rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16043_dupName_12_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x(MUX,16049)@80
    assign rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16048_dupName_12_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16045_dupName_12_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16048_dupName_12_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m347_vt_select_21(BITSELECT,12238)@80
    assign i_unnamed_c_compmm_m347_vt_select_21_b = rightShiftStage1_uid16050_dupName_12_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m347_vt_join(BITJOIN,12237)@80
    assign i_unnamed_c_compmm_m347_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m347_vt_select_21_b};

    // i_unnamed_c_compmm_m348_sel_x(BITSELECT,6187)@80
    assign i_unnamed_c_compmm_m348_sel_x_b = i_unnamed_c_compmm_m347_vt_join_q[15:0];

    // i_unnamed_c_compmm_m349_BitSelect_for_a(BITSELECT,28728)@80
    assign i_unnamed_c_compmm_m349_BitSelect_for_a_b = i_unnamed_c_compmm_m348_sel_x_b[0:0];

    // i_unnamed_c_compmm_m349_join(BITJOIN,28729)@80
    assign i_unnamed_c_compmm_m349_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m349_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m349_vt_select_0(BITSELECT,12254)@80
    assign i_unnamed_c_compmm_m349_vt_select_0_b = i_unnamed_c_compmm_m349_join_q[0:0];

    // redist73_i_unnamed_c_compmm_m349_vt_select_0_b_1(DELAY,29201)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist73_i_unnamed_c_compmm_m349_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m349_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m349_vt_join(BITJOIN,12253)@81
    assign i_unnamed_c_compmm_m349_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist73_i_unnamed_c_compmm_m349_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_3_c_compmm_m350(ADD,7092)@81
    assign i_add_i_i_i_i_i126_i_3_c_compmm_m350_a = {1'b0, i_unnamed_c_compmm_m349_vt_join_q};
    assign i_add_i_i_i_i_i126_i_3_c_compmm_m350_b = {1'b0, redist1080_i_conv_i_i_i_i97_i_3_c_compmm_m346_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_3_c_compmm_m350_o = $unsigned(i_add_i_i_i_i_i126_i_3_c_compmm_m350_a) + $unsigned(i_add_i_i_i_i_i126_i_3_c_compmm_m350_b);
    assign i_add_i_i_i_i_i126_i_3_c_compmm_m350_q = i_add_i_i_i_i_i126_i_3_c_compmm_m350_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_3_c_compmm_m350_sel_x(BITSELECT,2106)@81
    assign bgTrunc_i_add_i_i_i_i_i126_i_3_c_compmm_m350_sel_x_b = i_add_i_i_i_i_i126_i_3_c_compmm_m350_q[15:0];

    // i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_sel_x(BITSELECT,3649)@81
    assign i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_3_c_compmm_m350_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_select_15(BITSELECT,7707)@81
    assign i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_select_15_b = i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_join(BITJOIN,7706)@81
    assign i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_select_15_b};

    // leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(MUX,25054)@81
    assign leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_join_q or leftShiftStage0Idx1_uid25053_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_4_c_compmm_m370_vt_join_q;
            1'b1 : leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25053_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(MUX,25059)@81
    assign leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s or leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25058_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = leftShiftStage0_uid25055_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25058_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x(MUX,25064)@81
    assign leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s or leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25063_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = leftShiftStage1_uid25060_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25063_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28(BITSELECT,9673)@81
    assign i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28_b = leftShiftStage2_uid25065_i_shl_i_i_i_i_i77_i_4_c_compmm_m0_shift_x_q[28:13];

    // redist431_i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28_b_1(DELAY,29559)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist431_i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_join(BITJOIN,9672)@82
    assign i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_join_q = {redist431_i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma(CHAINMULTADD,29071)@76 + 5
    // out q@82
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6428_c_compmm_m248_out_dest_data_out_10_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6427_c_compmm_m249_out_dest_data_out_9_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ch[0] <= redist512_sync_together4364_aunroll_x_in_c1_eni5_10_tpl_8_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ch[1] <= redist511_sync_together4364_aunroll_x_in_c1_eni5_9_tpl_8_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372(ADD,8891)@82
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_4_i_c_compmm_m367_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_4_i_c_compmm_m369_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_4_i_c_compmm_m368_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_4_c_compmm_m371_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_o[33:0];

    // rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x(MUX,16088)@82
    assign rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q or rightShiftStage0Idx1_uid16087_dupName_15_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q;
            1'b1 : rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16087_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x(MUX,16093)@82
    assign rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16092_dupName_15_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16089_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16092_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x(MUX,16098)@82
    assign rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16097_dupName_15_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16094_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16097_dupName_15_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m373_vt_select_20(BITSELECT,12462)@82
    assign i_unnamed_c_compmm_m373_vt_select_20_b = rightShiftStage2_uid16099_dupName_15_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m373_vt_join(BITJOIN,12461)@82
    assign i_unnamed_c_compmm_m373_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m373_vt_select_20_b};

    // i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x(BITSELECT,3520)@82
    assign i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x_b = i_unnamed_c_compmm_m373_vt_join_q[15:0];

    // redist1069_i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x_b_1(DELAY,30197)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1069_i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16108_dupName_16_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16107)@82
    assign rightShiftStage1Idx1Rng8_uid16108_dupName_16_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16110_dupName_16_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16109)@82
    assign rightShiftStage1Idx1_uid16110_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16108_dupName_16_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16103_dupName_16_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16102)@82
    assign rightShiftStage0Idx1Rng4_uid16103_dupName_16_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q[33:4];

    // rightShiftStage0Idx1_uid16105_dupName_16_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16104)@82
    assign rightShiftStage0Idx1_uid16105_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16103_dupName_16_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x(MUX,16106)@82
    assign rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q or rightShiftStage0Idx1_uid16105_dupName_16_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_4_i_c_compmm_m372_q;
            1'b1 : rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16105_dupName_16_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x(MUX,16111)@82
    assign rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16110_dupName_16_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16107_dupName_16_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16110_dupName_16_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m375_vt_select_21(BITSELECT,12480)@82
    assign i_unnamed_c_compmm_m375_vt_select_21_b = rightShiftStage1_uid16112_dupName_16_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m375_vt_join(BITJOIN,12479)@82
    assign i_unnamed_c_compmm_m375_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m375_vt_select_21_b};

    // i_unnamed_c_compmm_m376_sel_x(BITSELECT,6209)@82
    assign i_unnamed_c_compmm_m376_sel_x_b = i_unnamed_c_compmm_m375_vt_join_q[15:0];

    // i_unnamed_c_compmm_m377_BitSelect_for_a(BITSELECT,28772)@82
    assign i_unnamed_c_compmm_m377_BitSelect_for_a_b = i_unnamed_c_compmm_m376_sel_x_b[0:0];

    // i_unnamed_c_compmm_m377_join(BITJOIN,28773)@82
    assign i_unnamed_c_compmm_m377_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m377_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m377_vt_select_0(BITSELECT,12496)@82
    assign i_unnamed_c_compmm_m377_vt_select_0_b = i_unnamed_c_compmm_m377_join_q[0:0];

    // redist51_i_unnamed_c_compmm_m377_vt_select_0_b_1(DELAY,29179)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist51_i_unnamed_c_compmm_m377_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m377_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m377_vt_join(BITJOIN,12495)@83
    assign i_unnamed_c_compmm_m377_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist51_i_unnamed_c_compmm_m377_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_4_c_compmm_m378(ADD,7103)@83
    assign i_add_i_i_i_i_i126_i_4_c_compmm_m378_a = {1'b0, i_unnamed_c_compmm_m377_vt_join_q};
    assign i_add_i_i_i_i_i126_i_4_c_compmm_m378_b = {1'b0, redist1069_i_conv_i_i_i_i97_i_4_c_compmm_m374_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_4_c_compmm_m378_o = $unsigned(i_add_i_i_i_i_i126_i_4_c_compmm_m378_a) + $unsigned(i_add_i_i_i_i_i126_i_4_c_compmm_m378_b);
    assign i_add_i_i_i_i_i126_i_4_c_compmm_m378_q = i_add_i_i_i_i_i126_i_4_c_compmm_m378_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_4_c_compmm_m378_sel_x(BITSELECT,2117)@83
    assign bgTrunc_i_add_i_i_i_i_i126_i_4_c_compmm_m378_sel_x_b = i_add_i_i_i_i_i126_i_4_c_compmm_m378_q[15:0];

    // i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_sel_x(BITSELECT,3660)@83
    assign i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_4_c_compmm_m378_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_select_15(BITSELECT,7751)@83
    assign i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_select_15_b = i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_join(BITJOIN,7750)@83
    assign i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_select_15_b};

    // leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(MUX,25252)@83
    assign leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_join_q or leftShiftStage0Idx1_uid25251_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_5_c_compmm_m398_vt_join_q;
            1'b1 : leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25251_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(MUX,25257)@83
    assign leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s or leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25256_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = leftShiftStage0_uid25253_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25256_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x(MUX,25262)@83
    assign leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s or leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25261_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = leftShiftStage1_uid25258_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25261_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28(BITSELECT,9706)@83
    assign i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28_b = leftShiftStage2_uid25263_i_shl_i_i_i_i_i77_i_5_c_compmm_m0_shift_x_q[28:13];

    // redist420_i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28_b_1(DELAY,29548)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist420_i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_join(BITJOIN,9705)@84
    assign i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_join_q = {redist420_i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma(CHAINMULTADD,29082)@78 + 5
    // out q@84
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6430_c_compmm_m246_out_dest_data_out_12_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6429_c_compmm_m247_out_dest_data_out_11_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ch[0] <= redist514_sync_together4364_aunroll_x_in_c1_eni5_12_tpl_10_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ch[1] <= redist513_sync_together4364_aunroll_x_in_c1_eni5_11_tpl_10_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400(ADD,8902)@84
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_5_i_c_compmm_m395_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_5_i_c_compmm_m397_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_5_i_c_compmm_m396_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_5_c_compmm_m399_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_o[33:0];

    // rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x(MUX,16150)@84
    assign rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q or rightShiftStage0Idx1_uid16149_dupName_19_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q;
            1'b1 : rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16149_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x(MUX,16155)@84
    assign rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16154_dupName_19_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16151_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16154_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x(MUX,16160)@84
    assign rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16159_dupName_19_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16156_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16159_dupName_19_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m401_vt_select_20(BITSELECT,12565)@84
    assign i_unnamed_c_compmm_m401_vt_select_20_b = rightShiftStage2_uid16161_dupName_19_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m401_vt_join(BITJOIN,12564)@84
    assign i_unnamed_c_compmm_m401_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m401_vt_select_20_b};

    // i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x(BITSELECT,3531)@84
    assign i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x_b = i_unnamed_c_compmm_m401_vt_join_q[15:0];

    // redist1058_i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x_b_1(DELAY,30186)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1058_i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16170_dupName_20_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16169)@84
    assign rightShiftStage1Idx1Rng8_uid16170_dupName_20_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16172_dupName_20_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16171)@84
    assign rightShiftStage1Idx1_uid16172_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16170_dupName_20_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16165_dupName_20_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16164)@84
    assign rightShiftStage0Idx1Rng4_uid16165_dupName_20_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q[33:4];

    // rightShiftStage0Idx1_uid16167_dupName_20_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16166)@84
    assign rightShiftStage0Idx1_uid16167_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16165_dupName_20_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x(MUX,16168)@84
    assign rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q or rightShiftStage0Idx1_uid16167_dupName_20_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_5_i_c_compmm_m400_q;
            1'b1 : rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16167_dupName_20_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x(MUX,16173)@84
    assign rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16172_dupName_20_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16169_dupName_20_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16172_dupName_20_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m403_vt_select_21(BITSELECT,12568)@84
    assign i_unnamed_c_compmm_m403_vt_select_21_b = rightShiftStage1_uid16174_dupName_20_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m403_vt_join(BITJOIN,12567)@84
    assign i_unnamed_c_compmm_m403_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m403_vt_select_21_b};

    // i_unnamed_c_compmm_m404_sel_x(BITSELECT,6217)@84
    assign i_unnamed_c_compmm_m404_sel_x_b = i_unnamed_c_compmm_m403_vt_join_q[15:0];

    // i_unnamed_c_compmm_m405_BitSelect_for_a(BITSELECT,28786)@84
    assign i_unnamed_c_compmm_m405_BitSelect_for_a_b = i_unnamed_c_compmm_m404_sel_x_b[0:0];

    // i_unnamed_c_compmm_m405_join(BITJOIN,28787)@84
    assign i_unnamed_c_compmm_m405_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m405_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m405_vt_select_0(BITSELECT,12573)@84
    assign i_unnamed_c_compmm_m405_vt_select_0_b = i_unnamed_c_compmm_m405_join_q[0:0];

    // redist44_i_unnamed_c_compmm_m405_vt_select_0_b_1(DELAY,29172)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist44_i_unnamed_c_compmm_m405_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m405_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m405_vt_join(BITJOIN,12572)@85
    assign i_unnamed_c_compmm_m405_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist44_i_unnamed_c_compmm_m405_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_5_c_compmm_m406(ADD,7114)@85
    assign i_add_i_i_i_i_i126_i_5_c_compmm_m406_a = {1'b0, i_unnamed_c_compmm_m405_vt_join_q};
    assign i_add_i_i_i_i_i126_i_5_c_compmm_m406_b = {1'b0, redist1058_i_conv_i_i_i_i97_i_5_c_compmm_m402_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_5_c_compmm_m406_o = $unsigned(i_add_i_i_i_i_i126_i_5_c_compmm_m406_a) + $unsigned(i_add_i_i_i_i_i126_i_5_c_compmm_m406_b);
    assign i_add_i_i_i_i_i126_i_5_c_compmm_m406_q = i_add_i_i_i_i_i126_i_5_c_compmm_m406_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_5_c_compmm_m406_sel_x(BITSELECT,2128)@85
    assign bgTrunc_i_add_i_i_i_i_i126_i_5_c_compmm_m406_sel_x_b = i_add_i_i_i_i_i126_i_5_c_compmm_m406_q[15:0];

    // i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_sel_x(BITSELECT,3671)@85
    assign i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_5_c_compmm_m406_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_select_15(BITSELECT,7795)@85
    assign i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_select_15_b = i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_join(BITJOIN,7794)@85
    assign i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_select_15_b};

    // leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(MUX,25450)@85
    assign leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_join_q or leftShiftStage0Idx1_uid25449_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_6_c_compmm_m426_vt_join_q;
            1'b1 : leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25449_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(MUX,25455)@85
    assign leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s or leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25454_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = leftShiftStage0_uid25451_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25454_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x(MUX,25460)@85
    assign leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s or leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25459_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = leftShiftStage1_uid25456_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25459_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28(BITSELECT,9739)@85
    assign i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28_b = leftShiftStage2_uid25461_i_shl_i_i_i_i_i77_i_6_c_compmm_m0_shift_x_q[28:13];

    // redist409_i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28_b_1(DELAY,29537)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist409_i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_join(BITJOIN,9738)@86
    assign i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_join_q = {redist409_i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma(CHAINMULTADD,29093)@80 + 5
    // out q@86
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6432_c_compmm_m244_out_dest_data_out_14_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6431_c_compmm_m245_out_dest_data_out_13_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ch[0] <= redist516_sync_together4364_aunroll_x_in_c1_eni5_14_tpl_12_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ch[1] <= redist515_sync_together4364_aunroll_x_in_c1_eni5_13_tpl_12_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428(ADD,8913)@86
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_6_i_c_compmm_m423_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_6_i_c_compmm_m425_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_6_i_c_compmm_m424_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_6_c_compmm_m427_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_o[33:0];

    // rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x(MUX,16212)@86
    assign rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q or rightShiftStage0Idx1_uid16211_dupName_23_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q;
            1'b1 : rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16211_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x(MUX,16217)@86
    assign rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16216_dupName_23_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16213_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16216_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x(MUX,16222)@86
    assign rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16221_dupName_23_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16218_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16221_dupName_23_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m429_vt_select_20(BITSELECT,12587)@86
    assign i_unnamed_c_compmm_m429_vt_select_20_b = rightShiftStage2_uid16223_dupName_23_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m429_vt_join(BITJOIN,12586)@86
    assign i_unnamed_c_compmm_m429_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m429_vt_select_20_b};

    // i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x(BITSELECT,3542)@86
    assign i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x_b = i_unnamed_c_compmm_m429_vt_join_q[15:0];

    // redist1047_i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x_b_1(DELAY,30175)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1047_i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16232_dupName_24_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16231)@86
    assign rightShiftStage1Idx1Rng8_uid16232_dupName_24_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16234_dupName_24_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16233)@86
    assign rightShiftStage1Idx1_uid16234_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16232_dupName_24_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16227_dupName_24_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16226)@86
    assign rightShiftStage0Idx1Rng4_uid16227_dupName_24_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q[33:4];

    // rightShiftStage0Idx1_uid16229_dupName_24_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16228)@86
    assign rightShiftStage0Idx1_uid16229_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16227_dupName_24_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x(MUX,16230)@86
    assign rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q or rightShiftStage0Idx1_uid16229_dupName_24_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_6_i_c_compmm_m428_q;
            1'b1 : rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16229_dupName_24_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x(MUX,16235)@86
    assign rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16234_dupName_24_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16231_dupName_24_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16234_dupName_24_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m431_vt_select_21(BITSELECT,12590)@86
    assign i_unnamed_c_compmm_m431_vt_select_21_b = rightShiftStage1_uid16236_dupName_24_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m431_vt_join(BITJOIN,12589)@86
    assign i_unnamed_c_compmm_m431_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m431_vt_select_21_b};

    // i_unnamed_c_compmm_m432_sel_x(BITSELECT,6219)@86
    assign i_unnamed_c_compmm_m432_sel_x_b = i_unnamed_c_compmm_m431_vt_join_q[15:0];

    // i_unnamed_c_compmm_m433_BitSelect_for_a(BITSELECT,28790)@86
    assign i_unnamed_c_compmm_m433_BitSelect_for_a_b = i_unnamed_c_compmm_m432_sel_x_b[0:0];

    // i_unnamed_c_compmm_m433_join(BITJOIN,28791)@86
    assign i_unnamed_c_compmm_m433_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m433_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m433_vt_select_0(BITSELECT,12595)@86
    assign i_unnamed_c_compmm_m433_vt_select_0_b = i_unnamed_c_compmm_m433_join_q[0:0];

    // redist42_i_unnamed_c_compmm_m433_vt_select_0_b_1(DELAY,29170)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist42_i_unnamed_c_compmm_m433_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m433_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m433_vt_join(BITJOIN,12594)@87
    assign i_unnamed_c_compmm_m433_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist42_i_unnamed_c_compmm_m433_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_6_c_compmm_m434(ADD,7125)@87
    assign i_add_i_i_i_i_i126_i_6_c_compmm_m434_a = {1'b0, i_unnamed_c_compmm_m433_vt_join_q};
    assign i_add_i_i_i_i_i126_i_6_c_compmm_m434_b = {1'b0, redist1047_i_conv_i_i_i_i97_i_6_c_compmm_m430_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_6_c_compmm_m434_o = $unsigned(i_add_i_i_i_i_i126_i_6_c_compmm_m434_a) + $unsigned(i_add_i_i_i_i_i126_i_6_c_compmm_m434_b);
    assign i_add_i_i_i_i_i126_i_6_c_compmm_m434_q = i_add_i_i_i_i_i126_i_6_c_compmm_m434_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_6_c_compmm_m434_sel_x(BITSELECT,2139)@87
    assign bgTrunc_i_add_i_i_i_i_i126_i_6_c_compmm_m434_sel_x_b = i_add_i_i_i_i_i126_i_6_c_compmm_m434_q[15:0];

    // i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_sel_x(BITSELECT,3682)@87
    assign i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_6_c_compmm_m434_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_select_15(BITSELECT,7839)@87
    assign i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_select_15_b = i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_join(BITJOIN,7838)@87
    assign i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_select_15_b};

    // leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(MUX,25648)@87
    assign leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_join_q or leftShiftStage0Idx1_uid25647_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_7_c_compmm_m454_vt_join_q;
            1'b1 : leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25647_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(MUX,25653)@87
    assign leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s or leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25652_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = leftShiftStage0_uid25649_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25652_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x(MUX,25658)@87
    assign leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s or leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25657_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = leftShiftStage1_uid25654_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25657_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28(BITSELECT,9772)@87
    assign i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28_b = leftShiftStage2_uid25659_i_shl_i_i_i_i_i77_i_7_c_compmm_m0_shift_x_q[28:13];

    // redist398_i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28_b_1(DELAY,29526)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist398_i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_join(BITJOIN,9771)@88
    assign i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_join_q = {redist398_i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma(CHAINMULTADD,29104)@82 + 5
    // out q@88
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6434_c_compmm_m242_out_dest_data_out_16_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6433_c_compmm_m243_out_dest_data_out_15_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ch[0] <= redist518_sync_together4364_aunroll_x_in_c1_eni5_16_tpl_14_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ch[1] <= redist517_sync_together4364_aunroll_x_in_c1_eni5_15_tpl_14_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456(ADD,8924)@88
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_7_i_c_compmm_m451_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_7_i_c_compmm_m453_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_7_i_c_compmm_m452_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_7_c_compmm_m455_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_o[33:0];

    // rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x(MUX,16274)@88
    assign rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q or rightShiftStage0Idx1_uid16273_dupName_27_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q;
            1'b1 : rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16273_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x(MUX,16279)@88
    assign rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16278_dupName_27_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16275_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16278_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x(MUX,16284)@88
    assign rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16283_dupName_27_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16280_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16283_dupName_27_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m457_vt_select_20(BITSELECT,12609)@88
    assign i_unnamed_c_compmm_m457_vt_select_20_b = rightShiftStage2_uid16285_dupName_27_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m457_vt_join(BITJOIN,12608)@88
    assign i_unnamed_c_compmm_m457_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m457_vt_select_20_b};

    // i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x(BITSELECT,3553)@88
    assign i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x_b = i_unnamed_c_compmm_m457_vt_join_q[15:0];

    // redist1036_i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x_b_1(DELAY,30164)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1036_i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16294_dupName_28_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16293)@88
    assign rightShiftStage1Idx1Rng8_uid16294_dupName_28_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16296_dupName_28_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16295)@88
    assign rightShiftStage1Idx1_uid16296_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16294_dupName_28_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16289_dupName_28_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16288)@88
    assign rightShiftStage0Idx1Rng4_uid16289_dupName_28_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q[33:4];

    // rightShiftStage0Idx1_uid16291_dupName_28_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16290)@88
    assign rightShiftStage0Idx1_uid16291_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16289_dupName_28_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x(MUX,16292)@88
    assign rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q or rightShiftStage0Idx1_uid16291_dupName_28_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_7_i_c_compmm_m456_q;
            1'b1 : rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16291_dupName_28_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x(MUX,16297)@88
    assign rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16296_dupName_28_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16293_dupName_28_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16296_dupName_28_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m459_vt_select_21(BITSELECT,12612)@88
    assign i_unnamed_c_compmm_m459_vt_select_21_b = rightShiftStage1_uid16298_dupName_28_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m459_vt_join(BITJOIN,12611)@88
    assign i_unnamed_c_compmm_m459_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m459_vt_select_21_b};

    // i_unnamed_c_compmm_m460_sel_x(BITSELECT,6221)@88
    assign i_unnamed_c_compmm_m460_sel_x_b = i_unnamed_c_compmm_m459_vt_join_q[15:0];

    // i_unnamed_c_compmm_m461_BitSelect_for_a(BITSELECT,28794)@88
    assign i_unnamed_c_compmm_m461_BitSelect_for_a_b = i_unnamed_c_compmm_m460_sel_x_b[0:0];

    // i_unnamed_c_compmm_m461_join(BITJOIN,28795)@88
    assign i_unnamed_c_compmm_m461_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m461_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m461_vt_select_0(BITSELECT,12617)@88
    assign i_unnamed_c_compmm_m461_vt_select_0_b = i_unnamed_c_compmm_m461_join_q[0:0];

    // redist40_i_unnamed_c_compmm_m461_vt_select_0_b_1(DELAY,29168)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist40_i_unnamed_c_compmm_m461_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m461_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m461_vt_join(BITJOIN,12616)@89
    assign i_unnamed_c_compmm_m461_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist40_i_unnamed_c_compmm_m461_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_7_c_compmm_m462(ADD,7136)@89
    assign i_add_i_i_i_i_i126_i_7_c_compmm_m462_a = {1'b0, i_unnamed_c_compmm_m461_vt_join_q};
    assign i_add_i_i_i_i_i126_i_7_c_compmm_m462_b = {1'b0, redist1036_i_conv_i_i_i_i97_i_7_c_compmm_m458_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_7_c_compmm_m462_o = $unsigned(i_add_i_i_i_i_i126_i_7_c_compmm_m462_a) + $unsigned(i_add_i_i_i_i_i126_i_7_c_compmm_m462_b);
    assign i_add_i_i_i_i_i126_i_7_c_compmm_m462_q = i_add_i_i_i_i_i126_i_7_c_compmm_m462_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_7_c_compmm_m462_sel_x(BITSELECT,2150)@89
    assign bgTrunc_i_add_i_i_i_i_i126_i_7_c_compmm_m462_sel_x_b = i_add_i_i_i_i_i126_i_7_c_compmm_m462_q[15:0];

    // i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_sel_x(BITSELECT,3693)@89
    assign i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_7_c_compmm_m462_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_select_15(BITSELECT,7883)@89
    assign i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_select_15_b = i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_join(BITJOIN,7882)@89
    assign i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_select_15_b};

    // leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(MUX,25846)@89
    assign leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_join_q or leftShiftStage0Idx1_uid25845_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_8_c_compmm_m482_vt_join_q;
            1'b1 : leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25845_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(MUX,25851)@89
    assign leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s or leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25850_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = leftShiftStage0_uid25847_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25850_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x(MUX,25856)@89
    assign leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s or leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25855_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = leftShiftStage1_uid25852_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25855_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28(BITSELECT,9805)@89
    assign i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28_b = leftShiftStage2_uid25857_i_shl_i_i_i_i_i77_i_8_c_compmm_m0_shift_x_q[28:13];

    // redist387_i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28_b_1(DELAY,29515)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist387_i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_join(BITJOIN,9804)@90
    assign i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_join_q = {redist387_i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma(CHAINMULTADD,29115)@84 + 5
    // out q@90
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_6436_c_compmm_m240_out_dest_data_out_18_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6435_c_compmm_m241_out_dest_data_out_17_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ch[0] <= redist520_sync_together4364_aunroll_x_in_c1_eni5_18_tpl_16_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ch[1] <= redist519_sync_together4364_aunroll_x_in_c1_eni5_17_tpl_16_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484(ADD,8935)@90
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_8_i_c_compmm_m479_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_8_i_c_compmm_m481_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_8_i_c_compmm_m480_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_8_c_compmm_m483_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_o[33:0];

    // rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x(MUX,16336)@90
    assign rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q or rightShiftStage0Idx1_uid16335_dupName_31_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q;
            1'b1 : rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16335_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x(MUX,16341)@90
    assign rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16340_dupName_31_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16337_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16340_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x(MUX,16346)@90
    assign rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16345_dupName_31_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16342_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16345_dupName_31_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m485_vt_select_20(BITSELECT,12631)@90
    assign i_unnamed_c_compmm_m485_vt_select_20_b = rightShiftStage2_uid16347_dupName_31_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m485_vt_join(BITJOIN,12630)@90
    assign i_unnamed_c_compmm_m485_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m485_vt_select_20_b};

    // i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x(BITSELECT,3564)@90
    assign i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x_b = i_unnamed_c_compmm_m485_vt_join_q[15:0];

    // redist1025_i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x_b_1(DELAY,30153)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1025_i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16356_dupName_32_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16355)@90
    assign rightShiftStage1Idx1Rng8_uid16356_dupName_32_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16358_dupName_32_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16357)@90
    assign rightShiftStage1Idx1_uid16358_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16356_dupName_32_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16351_dupName_32_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16350)@90
    assign rightShiftStage0Idx1Rng4_uid16351_dupName_32_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q[33:4];

    // rightShiftStage0Idx1_uid16353_dupName_32_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16352)@90
    assign rightShiftStage0Idx1_uid16353_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16351_dupName_32_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x(MUX,16354)@90
    assign rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q or rightShiftStage0Idx1_uid16353_dupName_32_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_8_i_c_compmm_m484_q;
            1'b1 : rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16353_dupName_32_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x(MUX,16359)@90
    assign rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16358_dupName_32_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16355_dupName_32_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16358_dupName_32_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m487_vt_select_21(BITSELECT,12634)@90
    assign i_unnamed_c_compmm_m487_vt_select_21_b = rightShiftStage1_uid16360_dupName_32_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m487_vt_join(BITJOIN,12633)@90
    assign i_unnamed_c_compmm_m487_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m487_vt_select_21_b};

    // i_unnamed_c_compmm_m488_sel_x(BITSELECT,6223)@90
    assign i_unnamed_c_compmm_m488_sel_x_b = i_unnamed_c_compmm_m487_vt_join_q[15:0];

    // i_unnamed_c_compmm_m489_BitSelect_for_a(BITSELECT,28798)@90
    assign i_unnamed_c_compmm_m489_BitSelect_for_a_b = i_unnamed_c_compmm_m488_sel_x_b[0:0];

    // i_unnamed_c_compmm_m489_join(BITJOIN,28799)@90
    assign i_unnamed_c_compmm_m489_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m489_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m489_vt_select_0(BITSELECT,12639)@90
    assign i_unnamed_c_compmm_m489_vt_select_0_b = i_unnamed_c_compmm_m489_join_q[0:0];

    // redist38_i_unnamed_c_compmm_m489_vt_select_0_b_1(DELAY,29166)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist38_i_unnamed_c_compmm_m489_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m489_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m489_vt_join(BITJOIN,12638)@91
    assign i_unnamed_c_compmm_m489_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist38_i_unnamed_c_compmm_m489_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_8_c_compmm_m490(ADD,7147)@91
    assign i_add_i_i_i_i_i126_i_8_c_compmm_m490_a = {1'b0, i_unnamed_c_compmm_m489_vt_join_q};
    assign i_add_i_i_i_i_i126_i_8_c_compmm_m490_b = {1'b0, redist1025_i_conv_i_i_i_i97_i_8_c_compmm_m486_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_8_c_compmm_m490_o = $unsigned(i_add_i_i_i_i_i126_i_8_c_compmm_m490_a) + $unsigned(i_add_i_i_i_i_i126_i_8_c_compmm_m490_b);
    assign i_add_i_i_i_i_i126_i_8_c_compmm_m490_q = i_add_i_i_i_i_i126_i_8_c_compmm_m490_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_8_c_compmm_m490_sel_x(BITSELECT,2161)@91
    assign bgTrunc_i_add_i_i_i_i_i126_i_8_c_compmm_m490_sel_x_b = i_add_i_i_i_i_i126_i_8_c_compmm_m490_q[15:0];

    // i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_sel_x(BITSELECT,3704)@91
    assign i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_8_c_compmm_m490_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_select_15(BITSELECT,7927)@91
    assign i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_select_15_b = i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_join(BITJOIN,7926)@91
    assign i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_select_15_b};

    // leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(MUX,26044)@91
    assign leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_join_q or leftShiftStage0Idx1_uid26043_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_9_c_compmm_m510_vt_join_q;
            1'b1 : leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26043_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(MUX,26049)@91
    assign leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s or leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26048_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = leftShiftStage0_uid26045_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26048_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x(MUX,26054)@91
    assign leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s or leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26053_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = leftShiftStage1_uid26050_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26053_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28(BITSELECT,9838)@91
    assign i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28_b = leftShiftStage2_uid26055_i_shl_i_i_i_i_i77_i_9_c_compmm_m0_shift_x_q[28:13];

    // redist376_i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28_b_1(DELAY,29504)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist376_i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_join(BITJOIN,9837)@92
    assign i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_join_q = {redist376_i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma(CHAINMULTADD,29126)@86 + 5
    // out q@92
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_6438_c_compmm_m238_out_dest_data_out_20_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_6437_c_compmm_m239_out_dest_data_out_19_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ch[0] <= redist522_sync_together4364_aunroll_x_in_c1_eni5_20_tpl_18_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ch[1] <= redist521_sync_together4364_aunroll_x_in_c1_eni5_19_tpl_18_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512(ADD,8946)@92
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_9_i_c_compmm_m507_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_9_i_c_compmm_m509_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_9_i_c_compmm_m508_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_9_c_compmm_m511_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_o[33:0];

    // rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x(MUX,16398)@92
    assign rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q or rightShiftStage0Idx1_uid16397_dupName_35_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q;
            1'b1 : rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16397_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x(MUX,16403)@92
    assign rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16402_dupName_35_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16399_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16402_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x(MUX,16408)@92
    assign rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16407_dupName_35_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16404_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16407_dupName_35_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m513_vt_select_20(BITSELECT,12653)@92
    assign i_unnamed_c_compmm_m513_vt_select_20_b = rightShiftStage2_uid16409_dupName_35_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m513_vt_join(BITJOIN,12652)@92
    assign i_unnamed_c_compmm_m513_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m513_vt_select_20_b};

    // i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x(BITSELECT,3575)@92
    assign i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x_b = i_unnamed_c_compmm_m513_vt_join_q[15:0];

    // redist1014_i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x_b_1(DELAY,30142)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1014_i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16418_dupName_36_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16417)@92
    assign rightShiftStage1Idx1Rng8_uid16418_dupName_36_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16420_dupName_36_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16419)@92
    assign rightShiftStage1Idx1_uid16420_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16418_dupName_36_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16413_dupName_36_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16412)@92
    assign rightShiftStage0Idx1Rng4_uid16413_dupName_36_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q[33:4];

    // rightShiftStage0Idx1_uid16415_dupName_36_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16414)@92
    assign rightShiftStage0Idx1_uid16415_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16413_dupName_36_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x(MUX,16416)@92
    assign rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q or rightShiftStage0Idx1_uid16415_dupName_36_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_9_i_c_compmm_m512_q;
            1'b1 : rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16415_dupName_36_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x(MUX,16421)@92
    assign rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16420_dupName_36_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16417_dupName_36_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16420_dupName_36_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m515_vt_select_21(BITSELECT,12656)@92
    assign i_unnamed_c_compmm_m515_vt_select_21_b = rightShiftStage1_uid16422_dupName_36_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m515_vt_join(BITJOIN,12655)@92
    assign i_unnamed_c_compmm_m515_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m515_vt_select_21_b};

    // i_unnamed_c_compmm_m516_sel_x(BITSELECT,6225)@92
    assign i_unnamed_c_compmm_m516_sel_x_b = i_unnamed_c_compmm_m515_vt_join_q[15:0];

    // i_unnamed_c_compmm_m517_BitSelect_for_a(BITSELECT,28802)@92
    assign i_unnamed_c_compmm_m517_BitSelect_for_a_b = i_unnamed_c_compmm_m516_sel_x_b[0:0];

    // i_unnamed_c_compmm_m517_join(BITJOIN,28803)@92
    assign i_unnamed_c_compmm_m517_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m517_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m517_vt_select_0(BITSELECT,12661)@92
    assign i_unnamed_c_compmm_m517_vt_select_0_b = i_unnamed_c_compmm_m517_join_q[0:0];

    // redist36_i_unnamed_c_compmm_m517_vt_select_0_b_1(DELAY,29164)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist36_i_unnamed_c_compmm_m517_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m517_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m517_vt_join(BITJOIN,12660)@93
    assign i_unnamed_c_compmm_m517_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist36_i_unnamed_c_compmm_m517_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_9_c_compmm_m518(ADD,7158)@93
    assign i_add_i_i_i_i_i126_i_9_c_compmm_m518_a = {1'b0, i_unnamed_c_compmm_m517_vt_join_q};
    assign i_add_i_i_i_i_i126_i_9_c_compmm_m518_b = {1'b0, redist1014_i_conv_i_i_i_i97_i_9_c_compmm_m514_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_9_c_compmm_m518_o = $unsigned(i_add_i_i_i_i_i126_i_9_c_compmm_m518_a) + $unsigned(i_add_i_i_i_i_i126_i_9_c_compmm_m518_b);
    assign i_add_i_i_i_i_i126_i_9_c_compmm_m518_q = i_add_i_i_i_i_i126_i_9_c_compmm_m518_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_9_c_compmm_m518_sel_x(BITSELECT,2172)@93
    assign bgTrunc_i_add_i_i_i_i_i126_i_9_c_compmm_m518_sel_x_b = i_add_i_i_i_i_i126_i_9_c_compmm_m518_q[15:0];

    // i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_sel_x(BITSELECT,3588)@93
    assign i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_9_c_compmm_m518_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_select_15(BITSELECT,7463)@93
    assign i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_select_15_b = i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_join(BITJOIN,7462)@93
    assign i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_select_15_b};

    // leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(MUX,23956)@93
    assign leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_join_q or leftShiftStage0Idx1_uid23955_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_10_c_compmm_m538_vt_join_q;
            1'b1 : leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23955_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(MUX,23961)@93
    assign leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s or leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23960_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = leftShiftStage0_uid23957_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23960_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x(MUX,23966)@93
    assign leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s or leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23965_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = leftShiftStage1_uid23962_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23965_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28(BITSELECT,9490)@93
    assign i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28_b = leftShiftStage2_uid23967_i_shl_i_i_i_i_i77_i_10_c_compmm_m0_shift_x_q[28:13];

    // redist492_i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28_b_1(DELAY,29620)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist492_i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_join(BITJOIN,9489)@94
    assign i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_join_q = {redist492_i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma(CHAINMULTADD,29010)@88 + 5
    // out q@94
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_6440_c_compmm_m236_out_dest_data_out_22_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_6439_c_compmm_m237_out_dest_data_out_21_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ch[0] <= redist524_sync_together4364_aunroll_x_in_c1_eni5_22_tpl_20_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ch[1] <= redist523_sync_together4364_aunroll_x_in_c1_eni5_21_tpl_20_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540(ADD,8830)@94
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_10_i_c_compmm_m535_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_10_i_c_compmm_m537_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_10_i_c_compmm_m536_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_10_c_compmm_m539_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_o[33:0];

    // rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x(MUX,16460)@94
    assign rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q or rightShiftStage0Idx1_uid16459_dupName_39_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q;
            1'b1 : rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16459_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x(MUX,16465)@94
    assign rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16464_dupName_39_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16461_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16464_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x(MUX,16470)@94
    assign rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16469_dupName_39_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16466_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16469_dupName_39_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m541_vt_select_20(BITSELECT,12675)@94
    assign i_unnamed_c_compmm_m541_vt_select_20_b = rightShiftStage2_uid16471_dupName_39_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m541_vt_join(BITJOIN,12674)@94
    assign i_unnamed_c_compmm_m541_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m541_vt_select_20_b};

    // i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x(BITSELECT,3459)@94
    assign i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x_b = i_unnamed_c_compmm_m541_vt_join_q[15:0];

    // redist1130_i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x_b_1(DELAY,30258)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1130_i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16480_dupName_40_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16479)@94
    assign rightShiftStage1Idx1Rng8_uid16480_dupName_40_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16482_dupName_40_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16481)@94
    assign rightShiftStage1Idx1_uid16482_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16480_dupName_40_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16475_dupName_40_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16474)@94
    assign rightShiftStage0Idx1Rng4_uid16475_dupName_40_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q[33:4];

    // rightShiftStage0Idx1_uid16477_dupName_40_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16476)@94
    assign rightShiftStage0Idx1_uid16477_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16475_dupName_40_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x(MUX,16478)@94
    assign rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q or rightShiftStage0Idx1_uid16477_dupName_40_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_10_i_c_compmm_m540_q;
            1'b1 : rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16477_dupName_40_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x(MUX,16483)@94
    assign rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16482_dupName_40_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16479_dupName_40_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16482_dupName_40_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m543_vt_select_21(BITSELECT,12678)@94
    assign i_unnamed_c_compmm_m543_vt_select_21_b = rightShiftStage1_uid16484_dupName_40_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m543_vt_join(BITJOIN,12677)@94
    assign i_unnamed_c_compmm_m543_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m543_vt_select_21_b};

    // i_unnamed_c_compmm_m544_sel_x(BITSELECT,6227)@94
    assign i_unnamed_c_compmm_m544_sel_x_b = i_unnamed_c_compmm_m543_vt_join_q[15:0];

    // i_unnamed_c_compmm_m545_BitSelect_for_a(BITSELECT,28806)@94
    assign i_unnamed_c_compmm_m545_BitSelect_for_a_b = i_unnamed_c_compmm_m544_sel_x_b[0:0];

    // i_unnamed_c_compmm_m545_join(BITJOIN,28807)@94
    assign i_unnamed_c_compmm_m545_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m545_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m545_vt_select_0(BITSELECT,12683)@94
    assign i_unnamed_c_compmm_m545_vt_select_0_b = i_unnamed_c_compmm_m545_join_q[0:0];

    // redist34_i_unnamed_c_compmm_m545_vt_select_0_b_1(DELAY,29162)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist34_i_unnamed_c_compmm_m545_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m545_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m545_vt_join(BITJOIN,12682)@95
    assign i_unnamed_c_compmm_m545_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist34_i_unnamed_c_compmm_m545_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_10_c_compmm_m546(ADD,7042)@95
    assign i_add_i_i_i_i_i126_i_10_c_compmm_m546_a = {1'b0, i_unnamed_c_compmm_m545_vt_join_q};
    assign i_add_i_i_i_i_i126_i_10_c_compmm_m546_b = {1'b0, redist1130_i_conv_i_i_i_i97_i_10_c_compmm_m542_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_10_c_compmm_m546_o = $unsigned(i_add_i_i_i_i_i126_i_10_c_compmm_m546_a) + $unsigned(i_add_i_i_i_i_i126_i_10_c_compmm_m546_b);
    assign i_add_i_i_i_i_i126_i_10_c_compmm_m546_q = i_add_i_i_i_i_i126_i_10_c_compmm_m546_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_10_c_compmm_m546_sel_x(BITSELECT,2056)@95
    assign bgTrunc_i_add_i_i_i_i_i126_i_10_c_compmm_m546_sel_x_b = i_add_i_i_i_i_i126_i_10_c_compmm_m546_q[15:0];

    // i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_sel_x(BITSELECT,3599)@95
    assign i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_10_c_compmm_m546_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_select_15(BITSELECT,7507)@95
    assign i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_select_15_b = i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_join(BITJOIN,7506)@95
    assign i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_select_15_b};

    // leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(MUX,24154)@95
    assign leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_join_q or leftShiftStage0Idx1_uid24153_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_11_c_compmm_m566_vt_join_q;
            1'b1 : leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24153_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(MUX,24159)@95
    assign leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s or leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24158_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = leftShiftStage0_uid24155_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24158_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x(MUX,24164)@95
    assign leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s or leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24163_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = leftShiftStage1_uid24160_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24163_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28(BITSELECT,9523)@95
    assign i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28_b = leftShiftStage2_uid24165_i_shl_i_i_i_i_i77_i_11_c_compmm_m0_shift_x_q[28:13];

    // redist481_i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28_b_1(DELAY,29609)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist481_i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_join(BITJOIN,9522)@96
    assign i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_join_q = {redist481_i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma(CHAINMULTADD,29021)@90 + 5
    // out q@96
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_6442_c_compmm_m234_out_dest_data_out_24_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_6441_c_compmm_m235_out_dest_data_out_23_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ch[0] <= redist526_sync_together4364_aunroll_x_in_c1_eni5_24_tpl_22_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ch[1] <= redist525_sync_together4364_aunroll_x_in_c1_eni5_23_tpl_22_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568(ADD,8841)@96
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_11_i_c_compmm_m563_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_11_i_c_compmm_m565_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_11_i_c_compmm_m564_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_11_c_compmm_m567_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_o[33:0];

    // rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x(MUX,16522)@96
    assign rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q or rightShiftStage0Idx1_uid16521_dupName_43_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q;
            1'b1 : rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16521_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x(MUX,16527)@96
    assign rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16526_dupName_43_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16523_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16526_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x(MUX,16532)@96
    assign rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16531_dupName_43_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16528_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16531_dupName_43_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m569_vt_select_20(BITSELECT,12697)@96
    assign i_unnamed_c_compmm_m569_vt_select_20_b = rightShiftStage2_uid16533_dupName_43_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m569_vt_join(BITJOIN,12696)@96
    assign i_unnamed_c_compmm_m569_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m569_vt_select_20_b};

    // i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x(BITSELECT,3470)@96
    assign i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x_b = i_unnamed_c_compmm_m569_vt_join_q[15:0];

    // redist1119_i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x_b_1(DELAY,30247)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1119_i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16542_dupName_44_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16541)@96
    assign rightShiftStage1Idx1Rng8_uid16542_dupName_44_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16544_dupName_44_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16543)@96
    assign rightShiftStage1Idx1_uid16544_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16542_dupName_44_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16537_dupName_44_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16536)@96
    assign rightShiftStage0Idx1Rng4_uid16537_dupName_44_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q[33:4];

    // rightShiftStage0Idx1_uid16539_dupName_44_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16538)@96
    assign rightShiftStage0Idx1_uid16539_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16537_dupName_44_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x(MUX,16540)@96
    assign rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q or rightShiftStage0Idx1_uid16539_dupName_44_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_11_i_c_compmm_m568_q;
            1'b1 : rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16539_dupName_44_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x(MUX,16545)@96
    assign rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16544_dupName_44_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16541_dupName_44_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16544_dupName_44_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m571_vt_select_21(BITSELECT,12700)@96
    assign i_unnamed_c_compmm_m571_vt_select_21_b = rightShiftStage1_uid16546_dupName_44_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m571_vt_join(BITJOIN,12699)@96
    assign i_unnamed_c_compmm_m571_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m571_vt_select_21_b};

    // i_unnamed_c_compmm_m572_sel_x(BITSELECT,6229)@96
    assign i_unnamed_c_compmm_m572_sel_x_b = i_unnamed_c_compmm_m571_vt_join_q[15:0];

    // i_unnamed_c_compmm_m573_BitSelect_for_a(BITSELECT,28810)@96
    assign i_unnamed_c_compmm_m573_BitSelect_for_a_b = i_unnamed_c_compmm_m572_sel_x_b[0:0];

    // i_unnamed_c_compmm_m573_join(BITJOIN,28811)@96
    assign i_unnamed_c_compmm_m573_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m573_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m573_vt_select_0(BITSELECT,12705)@96
    assign i_unnamed_c_compmm_m573_vt_select_0_b = i_unnamed_c_compmm_m573_join_q[0:0];

    // redist32_i_unnamed_c_compmm_m573_vt_select_0_b_1(DELAY,29160)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist32_i_unnamed_c_compmm_m573_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m573_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m573_vt_join(BITJOIN,12704)@97
    assign i_unnamed_c_compmm_m573_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist32_i_unnamed_c_compmm_m573_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_11_c_compmm_m574(ADD,7053)@97
    assign i_add_i_i_i_i_i126_i_11_c_compmm_m574_a = {1'b0, i_unnamed_c_compmm_m573_vt_join_q};
    assign i_add_i_i_i_i_i126_i_11_c_compmm_m574_b = {1'b0, redist1119_i_conv_i_i_i_i97_i_11_c_compmm_m570_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_11_c_compmm_m574_o = $unsigned(i_add_i_i_i_i_i126_i_11_c_compmm_m574_a) + $unsigned(i_add_i_i_i_i_i126_i_11_c_compmm_m574_b);
    assign i_add_i_i_i_i_i126_i_11_c_compmm_m574_q = i_add_i_i_i_i_i126_i_11_c_compmm_m574_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_11_c_compmm_m574_sel_x(BITSELECT,2067)@97
    assign bgTrunc_i_add_i_i_i_i_i126_i_11_c_compmm_m574_sel_x_b = i_add_i_i_i_i_i126_i_11_c_compmm_m574_q[15:0];

    // i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_sel_x(BITSELECT,3608)@97
    assign i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_11_c_compmm_m574_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_select_15(BITSELECT,7543)@97
    assign i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_select_15_b = i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_join(BITJOIN,7542)@97
    assign i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_select_15_b};

    // leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(MUX,24316)@97
    assign leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_join_q or leftShiftStage0Idx1_uid24315_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_12_c_compmm_m594_vt_join_q;
            1'b1 : leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24315_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(MUX,24321)@97
    assign leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s or leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24320_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = leftShiftStage0_uid24317_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24320_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x(MUX,24326)@97
    assign leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s or leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24325_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = leftShiftStage1_uid24322_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24325_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28(BITSELECT,9550)@97
    assign i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28_b = leftShiftStage2_uid24327_i_shl_i_i_i_i_i77_i_12_c_compmm_m0_shift_x_q[28:13];

    // redist472_i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28_b_1(DELAY,29600)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist472_i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_join(BITJOIN,9549)@98
    assign i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_join_q = {redist472_i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma(CHAINMULTADD,29030)@92 + 5
    // out q@98
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_6444_c_compmm_m232_out_dest_data_out_26_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_6443_c_compmm_m233_out_dest_data_out_25_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ch[0] <= redist528_sync_together4364_aunroll_x_in_c1_eni5_26_tpl_24_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ch[1] <= redist527_sync_together4364_aunroll_x_in_c1_eni5_25_tpl_24_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596(ADD,8850)@98
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_12_i_c_compmm_m591_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_12_i_c_compmm_m593_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_12_i_c_compmm_m592_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_12_c_compmm_m595_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_o[33:0];

    // rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x(MUX,16584)@98
    assign rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q or rightShiftStage0Idx1_uid16583_dupName_47_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q;
            1'b1 : rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16583_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x(MUX,16589)@98
    assign rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16588_dupName_47_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16585_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16588_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x(MUX,16594)@98
    assign rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16593_dupName_47_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16590_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16593_dupName_47_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m597_vt_select_20(BITSELECT,12719)@98
    assign i_unnamed_c_compmm_m597_vt_select_20_b = rightShiftStage2_uid16595_dupName_47_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m597_vt_join(BITJOIN,12718)@98
    assign i_unnamed_c_compmm_m597_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m597_vt_select_20_b};

    // i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x(BITSELECT,3479)@98
    assign i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x_b = i_unnamed_c_compmm_m597_vt_join_q[15:0];

    // redist1110_i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x_b_1(DELAY,30238)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1110_i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16604_dupName_48_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16603)@98
    assign rightShiftStage1Idx1Rng8_uid16604_dupName_48_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16606_dupName_48_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16605)@98
    assign rightShiftStage1Idx1_uid16606_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16604_dupName_48_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16599_dupName_48_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16598)@98
    assign rightShiftStage0Idx1Rng4_uid16599_dupName_48_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q[33:4];

    // rightShiftStage0Idx1_uid16601_dupName_48_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16600)@98
    assign rightShiftStage0Idx1_uid16601_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16599_dupName_48_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x(MUX,16602)@98
    assign rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q or rightShiftStage0Idx1_uid16601_dupName_48_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_12_i_c_compmm_m596_q;
            1'b1 : rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16601_dupName_48_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x(MUX,16607)@98
    assign rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16606_dupName_48_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16603_dupName_48_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16606_dupName_48_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m599_vt_select_21(BITSELECT,12722)@98
    assign i_unnamed_c_compmm_m599_vt_select_21_b = rightShiftStage1_uid16608_dupName_48_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m599_vt_join(BITJOIN,12721)@98
    assign i_unnamed_c_compmm_m599_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m599_vt_select_21_b};

    // i_unnamed_c_compmm_m600_sel_x(BITSELECT,6231)@98
    assign i_unnamed_c_compmm_m600_sel_x_b = i_unnamed_c_compmm_m599_vt_join_q[15:0];

    // i_unnamed_c_compmm_m601_BitSelect_for_a(BITSELECT,28814)@98
    assign i_unnamed_c_compmm_m601_BitSelect_for_a_b = i_unnamed_c_compmm_m600_sel_x_b[0:0];

    // i_unnamed_c_compmm_m601_join(BITJOIN,28815)@98
    assign i_unnamed_c_compmm_m601_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m601_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m601_vt_select_0(BITSELECT,12727)@98
    assign i_unnamed_c_compmm_m601_vt_select_0_b = i_unnamed_c_compmm_m601_join_q[0:0];

    // redist30_i_unnamed_c_compmm_m601_vt_select_0_b_1(DELAY,29158)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist30_i_unnamed_c_compmm_m601_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m601_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m601_vt_join(BITJOIN,12726)@99
    assign i_unnamed_c_compmm_m601_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist30_i_unnamed_c_compmm_m601_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_12_c_compmm_m602(ADD,7062)@99
    assign i_add_i_i_i_i_i126_i_12_c_compmm_m602_a = {1'b0, i_unnamed_c_compmm_m601_vt_join_q};
    assign i_add_i_i_i_i_i126_i_12_c_compmm_m602_b = {1'b0, redist1110_i_conv_i_i_i_i97_i_12_c_compmm_m598_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_12_c_compmm_m602_o = $unsigned(i_add_i_i_i_i_i126_i_12_c_compmm_m602_a) + $unsigned(i_add_i_i_i_i_i126_i_12_c_compmm_m602_b);
    assign i_add_i_i_i_i_i126_i_12_c_compmm_m602_q = i_add_i_i_i_i_i126_i_12_c_compmm_m602_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_12_c_compmm_m602_sel_x(BITSELECT,2076)@99
    assign bgTrunc_i_add_i_i_i_i_i126_i_12_c_compmm_m602_sel_x_b = i_add_i_i_i_i_i126_i_12_c_compmm_m602_q[15:0];

    // i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_sel_x(BITSELECT,3609)@99
    assign i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_12_c_compmm_m602_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_select_15(BITSELECT,7547)@99
    assign i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_select_15_b = i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_join(BITJOIN,7546)@99
    assign i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_select_15_b};

    // leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(MUX,24334)@99
    assign leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_join_q or leftShiftStage0Idx1_uid24333_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_13_c_compmm_m622_vt_join_q;
            1'b1 : leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24333_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(MUX,24339)@99
    assign leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s or leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24338_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = leftShiftStage0_uid24335_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24338_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x(MUX,24344)@99
    assign leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s or leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24343_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = leftShiftStage1_uid24340_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24343_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28(BITSELECT,9553)@99
    assign i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28_b = leftShiftStage2_uid24345_i_shl_i_i_i_i_i77_i_13_c_compmm_m0_shift_x_q[28:13];

    // redist471_i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28_b_1(DELAY,29599)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist471_i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_join(BITJOIN,9552)@100
    assign i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_join_q = {redist471_i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma(CHAINMULTADD,29031)@94 + 5
    // out q@100
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_6446_c_compmm_m230_out_dest_data_out_28_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_6445_c_compmm_m231_out_dest_data_out_27_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ch[0] <= redist530_sync_together4364_aunroll_x_in_c1_eni5_28_tpl_26_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ch[1] <= redist529_sync_together4364_aunroll_x_in_c1_eni5_27_tpl_26_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624(ADD,8851)@100
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_13_i_c_compmm_m619_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_13_i_c_compmm_m621_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_13_i_c_compmm_m620_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_13_c_compmm_m623_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_o[33:0];

    // rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x(MUX,16646)@100
    assign rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q or rightShiftStage0Idx1_uid16645_dupName_51_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q;
            1'b1 : rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16645_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x(MUX,16651)@100
    assign rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16650_dupName_51_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16647_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16650_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x(MUX,16656)@100
    assign rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16655_dupName_51_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16652_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16655_dupName_51_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m625_vt_select_20(BITSELECT,12741)@100
    assign i_unnamed_c_compmm_m625_vt_select_20_b = rightShiftStage2_uid16657_dupName_51_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m625_vt_join(BITJOIN,12740)@100
    assign i_unnamed_c_compmm_m625_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m625_vt_select_20_b};

    // i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x(BITSELECT,3480)@100
    assign i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x_b = i_unnamed_c_compmm_m625_vt_join_q[15:0];

    // redist1109_i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x_b_1(DELAY,30237)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1109_i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16666_dupName_52_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16665)@100
    assign rightShiftStage1Idx1Rng8_uid16666_dupName_52_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16668_dupName_52_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16667)@100
    assign rightShiftStage1Idx1_uid16668_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16666_dupName_52_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16661_dupName_52_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16660)@100
    assign rightShiftStage0Idx1Rng4_uid16661_dupName_52_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q[33:4];

    // rightShiftStage0Idx1_uid16663_dupName_52_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16662)@100
    assign rightShiftStage0Idx1_uid16663_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16661_dupName_52_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x(MUX,16664)@100
    assign rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q or rightShiftStage0Idx1_uid16663_dupName_52_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_13_i_c_compmm_m624_q;
            1'b1 : rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16663_dupName_52_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x(MUX,16669)@100
    assign rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16668_dupName_52_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16665_dupName_52_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16668_dupName_52_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m627_vt_select_21(BITSELECT,12744)@100
    assign i_unnamed_c_compmm_m627_vt_select_21_b = rightShiftStage1_uid16670_dupName_52_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m627_vt_join(BITJOIN,12743)@100
    assign i_unnamed_c_compmm_m627_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m627_vt_select_21_b};

    // i_unnamed_c_compmm_m628_sel_x(BITSELECT,6233)@100
    assign i_unnamed_c_compmm_m628_sel_x_b = i_unnamed_c_compmm_m627_vt_join_q[15:0];

    // i_unnamed_c_compmm_m629_BitSelect_for_a(BITSELECT,28818)@100
    assign i_unnamed_c_compmm_m629_BitSelect_for_a_b = i_unnamed_c_compmm_m628_sel_x_b[0:0];

    // i_unnamed_c_compmm_m629_join(BITJOIN,28819)@100
    assign i_unnamed_c_compmm_m629_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m629_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m629_vt_select_0(BITSELECT,12749)@100
    assign i_unnamed_c_compmm_m629_vt_select_0_b = i_unnamed_c_compmm_m629_join_q[0:0];

    // redist28_i_unnamed_c_compmm_m629_vt_select_0_b_1(DELAY,29156)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist28_i_unnamed_c_compmm_m629_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m629_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m629_vt_join(BITJOIN,12748)@101
    assign i_unnamed_c_compmm_m629_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist28_i_unnamed_c_compmm_m629_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_13_c_compmm_m630(ADD,7063)@101
    assign i_add_i_i_i_i_i126_i_13_c_compmm_m630_a = {1'b0, i_unnamed_c_compmm_m629_vt_join_q};
    assign i_add_i_i_i_i_i126_i_13_c_compmm_m630_b = {1'b0, redist1109_i_conv_i_i_i_i97_i_13_c_compmm_m626_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_13_c_compmm_m630_o = $unsigned(i_add_i_i_i_i_i126_i_13_c_compmm_m630_a) + $unsigned(i_add_i_i_i_i_i126_i_13_c_compmm_m630_b);
    assign i_add_i_i_i_i_i126_i_13_c_compmm_m630_q = i_add_i_i_i_i_i126_i_13_c_compmm_m630_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_13_c_compmm_m630_sel_x(BITSELECT,2077)@101
    assign bgTrunc_i_add_i_i_i_i_i126_i_13_c_compmm_m630_sel_x_b = i_add_i_i_i_i_i126_i_13_c_compmm_m630_q[15:0];

    // i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_sel_x(BITSELECT,3610)@101
    assign i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_13_c_compmm_m630_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_select_15(BITSELECT,7551)@101
    assign i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_select_15_b = i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_join(BITJOIN,7550)@101
    assign i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_select_15_b};

    // leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(MUX,24352)@101
    assign leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_join_q or leftShiftStage0Idx1_uid24351_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_14_c_compmm_m650_vt_join_q;
            1'b1 : leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24351_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(MUX,24357)@101
    assign leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s or leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24356_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = leftShiftStage0_uid24353_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24356_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x(MUX,24362)@101
    assign leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s or leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24361_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = leftShiftStage1_uid24358_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24361_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28(BITSELECT,9556)@101
    assign i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28_b = leftShiftStage2_uid24363_i_shl_i_i_i_i_i77_i_14_c_compmm_m0_shift_x_q[28:13];

    // redist470_i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28_b_1(DELAY,29598)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist470_i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_join(BITJOIN,9555)@102
    assign i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_join_q = {redist470_i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma(CHAINMULTADD,29032)@96 + 5
    // out q@102
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_6448_c_compmm_m228_out_dest_data_out_30_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_6447_c_compmm_m229_out_dest_data_out_29_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ch[0] <= redist532_sync_together4364_aunroll_x_in_c1_eni5_30_tpl_28_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ch[1] <= redist531_sync_together4364_aunroll_x_in_c1_eni5_29_tpl_28_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652(ADD,8852)@102
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_14_i_c_compmm_m647_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_14_i_c_compmm_m649_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_14_i_c_compmm_m648_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_14_c_compmm_m651_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_o[33:0];

    // rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x(MUX,16708)@102
    assign rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q or rightShiftStage0Idx1_uid16707_dupName_55_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q;
            1'b1 : rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16707_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x(MUX,16713)@102
    assign rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16712_dupName_55_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16709_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16712_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x(MUX,16718)@102
    assign rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16717_dupName_55_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16714_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16717_dupName_55_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m653_vt_select_20(BITSELECT,12763)@102
    assign i_unnamed_c_compmm_m653_vt_select_20_b = rightShiftStage2_uid16719_dupName_55_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m653_vt_join(BITJOIN,12762)@102
    assign i_unnamed_c_compmm_m653_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m653_vt_select_20_b};

    // i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x(BITSELECT,3481)@102
    assign i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x_b = i_unnamed_c_compmm_m653_vt_join_q[15:0];

    // redist1108_i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x_b_1(DELAY,30236)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1108_i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16728_dupName_56_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16727)@102
    assign rightShiftStage1Idx1Rng8_uid16728_dupName_56_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16730_dupName_56_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16729)@102
    assign rightShiftStage1Idx1_uid16730_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16728_dupName_56_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16723_dupName_56_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16722)@102
    assign rightShiftStage0Idx1Rng4_uid16723_dupName_56_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q[33:4];

    // rightShiftStage0Idx1_uid16725_dupName_56_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16724)@102
    assign rightShiftStage0Idx1_uid16725_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16723_dupName_56_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x(MUX,16726)@102
    assign rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q or rightShiftStage0Idx1_uid16725_dupName_56_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_14_i_c_compmm_m652_q;
            1'b1 : rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16725_dupName_56_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x(MUX,16731)@102
    assign rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16730_dupName_56_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16727_dupName_56_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16730_dupName_56_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m655_vt_select_21(BITSELECT,12766)@102
    assign i_unnamed_c_compmm_m655_vt_select_21_b = rightShiftStage1_uid16732_dupName_56_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m655_vt_join(BITJOIN,12765)@102
    assign i_unnamed_c_compmm_m655_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m655_vt_select_21_b};

    // i_unnamed_c_compmm_m656_sel_x(BITSELECT,6235)@102
    assign i_unnamed_c_compmm_m656_sel_x_b = i_unnamed_c_compmm_m655_vt_join_q[15:0];

    // i_unnamed_c_compmm_m657_BitSelect_for_a(BITSELECT,28822)@102
    assign i_unnamed_c_compmm_m657_BitSelect_for_a_b = i_unnamed_c_compmm_m656_sel_x_b[0:0];

    // i_unnamed_c_compmm_m657_join(BITJOIN,28823)@102
    assign i_unnamed_c_compmm_m657_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m657_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m657_vt_select_0(BITSELECT,12771)@102
    assign i_unnamed_c_compmm_m657_vt_select_0_b = i_unnamed_c_compmm_m657_join_q[0:0];

    // redist26_i_unnamed_c_compmm_m657_vt_select_0_b_1(DELAY,29154)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist26_i_unnamed_c_compmm_m657_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m657_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m657_vt_join(BITJOIN,12770)@103
    assign i_unnamed_c_compmm_m657_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist26_i_unnamed_c_compmm_m657_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_14_c_compmm_m658(ADD,7064)@103
    assign i_add_i_i_i_i_i126_i_14_c_compmm_m658_a = {1'b0, i_unnamed_c_compmm_m657_vt_join_q};
    assign i_add_i_i_i_i_i126_i_14_c_compmm_m658_b = {1'b0, redist1108_i_conv_i_i_i_i97_i_14_c_compmm_m654_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_14_c_compmm_m658_o = $unsigned(i_add_i_i_i_i_i126_i_14_c_compmm_m658_a) + $unsigned(i_add_i_i_i_i_i126_i_14_c_compmm_m658_b);
    assign i_add_i_i_i_i_i126_i_14_c_compmm_m658_q = i_add_i_i_i_i_i126_i_14_c_compmm_m658_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_14_c_compmm_m658_sel_x(BITSELECT,2078)@103
    assign bgTrunc_i_add_i_i_i_i_i126_i_14_c_compmm_m658_sel_x_b = i_add_i_i_i_i_i126_i_14_c_compmm_m658_q[15:0];

    // i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_sel_x(BITSELECT,3611)@103
    assign i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_14_c_compmm_m658_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_select_15(BITSELECT,7555)@103
    assign i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_select_15_b = i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_join(BITJOIN,7554)@103
    assign i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_select_15_b};

    // leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(MUX,24370)@103
    assign leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_join_q or leftShiftStage0Idx1_uid24369_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_15_c_compmm_m678_vt_join_q;
            1'b1 : leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24369_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(MUX,24375)@103
    assign leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s or leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24374_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = leftShiftStage0_uid24371_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24374_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x(MUX,24380)@103
    assign leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s or leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24379_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = leftShiftStage1_uid24376_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24379_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28(BITSELECT,9559)@103
    assign i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28_b = leftShiftStage2_uid24381_i_shl_i_i_i_i_i77_i_15_c_compmm_m0_shift_x_q[28:13];

    // redist469_i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28_b_1(DELAY,29597)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist469_i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_join(BITJOIN,9558)@104
    assign i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_join_q = {redist469_i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma(CHAINMULTADD,29033)@98 + 5
    // out q@104
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_6450_c_compmm_m226_out_dest_data_out_32_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_6449_c_compmm_m227_out_dest_data_out_31_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ch[0] <= redist534_sync_together4364_aunroll_x_in_c1_eni5_32_tpl_30_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ch[1] <= redist533_sync_together4364_aunroll_x_in_c1_eni5_31_tpl_30_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680(ADD,8853)@104
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_15_i_c_compmm_m675_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_15_i_c_compmm_m677_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_15_i_c_compmm_m676_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_15_c_compmm_m679_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_o[33:0];

    // rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x(MUX,16770)@104
    assign rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q or rightShiftStage0Idx1_uid16769_dupName_59_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q;
            1'b1 : rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16769_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x(MUX,16775)@104
    assign rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16774_dupName_59_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16771_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16774_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x(MUX,16780)@104
    assign rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16779_dupName_59_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16776_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16779_dupName_59_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m681_vt_select_20(BITSELECT,12785)@104
    assign i_unnamed_c_compmm_m681_vt_select_20_b = rightShiftStage2_uid16781_dupName_59_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m681_vt_join(BITJOIN,12784)@104
    assign i_unnamed_c_compmm_m681_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m681_vt_select_20_b};

    // i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x(BITSELECT,3482)@104
    assign i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x_b = i_unnamed_c_compmm_m681_vt_join_q[15:0];

    // redist1107_i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x_b_1(DELAY,30235)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1107_i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16790_dupName_60_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16789)@104
    assign rightShiftStage1Idx1Rng8_uid16790_dupName_60_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16792_dupName_60_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16791)@104
    assign rightShiftStage1Idx1_uid16792_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16790_dupName_60_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16785_dupName_60_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16784)@104
    assign rightShiftStage0Idx1Rng4_uid16785_dupName_60_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q[33:4];

    // rightShiftStage0Idx1_uid16787_dupName_60_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16786)@104
    assign rightShiftStage0Idx1_uid16787_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16785_dupName_60_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x(MUX,16788)@104
    assign rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q or rightShiftStage0Idx1_uid16787_dupName_60_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_15_i_c_compmm_m680_q;
            1'b1 : rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16787_dupName_60_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x(MUX,16793)@104
    assign rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16792_dupName_60_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16789_dupName_60_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16792_dupName_60_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m683_vt_select_21(BITSELECT,12788)@104
    assign i_unnamed_c_compmm_m683_vt_select_21_b = rightShiftStage1_uid16794_dupName_60_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m683_vt_join(BITJOIN,12787)@104
    assign i_unnamed_c_compmm_m683_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m683_vt_select_21_b};

    // i_unnamed_c_compmm_m684_sel_x(BITSELECT,6237)@104
    assign i_unnamed_c_compmm_m684_sel_x_b = i_unnamed_c_compmm_m683_vt_join_q[15:0];

    // i_unnamed_c_compmm_m685_BitSelect_for_a(BITSELECT,28826)@104
    assign i_unnamed_c_compmm_m685_BitSelect_for_a_b = i_unnamed_c_compmm_m684_sel_x_b[0:0];

    // i_unnamed_c_compmm_m685_join(BITJOIN,28827)@104
    assign i_unnamed_c_compmm_m685_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m685_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m685_vt_select_0(BITSELECT,12793)@104
    assign i_unnamed_c_compmm_m685_vt_select_0_b = i_unnamed_c_compmm_m685_join_q[0:0];

    // redist24_i_unnamed_c_compmm_m685_vt_select_0_b_1(DELAY,29152)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist24_i_unnamed_c_compmm_m685_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m685_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m685_vt_join(BITJOIN,12792)@105
    assign i_unnamed_c_compmm_m685_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist24_i_unnamed_c_compmm_m685_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_15_c_compmm_m686(ADD,7065)@105
    assign i_add_i_i_i_i_i126_i_15_c_compmm_m686_a = {1'b0, i_unnamed_c_compmm_m685_vt_join_q};
    assign i_add_i_i_i_i_i126_i_15_c_compmm_m686_b = {1'b0, redist1107_i_conv_i_i_i_i97_i_15_c_compmm_m682_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_15_c_compmm_m686_o = $unsigned(i_add_i_i_i_i_i126_i_15_c_compmm_m686_a) + $unsigned(i_add_i_i_i_i_i126_i_15_c_compmm_m686_b);
    assign i_add_i_i_i_i_i126_i_15_c_compmm_m686_q = i_add_i_i_i_i_i126_i_15_c_compmm_m686_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_15_c_compmm_m686_sel_x(BITSELECT,2079)@105
    assign bgTrunc_i_add_i_i_i_i_i126_i_15_c_compmm_m686_sel_x_b = i_add_i_i_i_i_i126_i_15_c_compmm_m686_q[15:0];

    // i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_sel_x(BITSELECT,3612)@105
    assign i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_15_c_compmm_m686_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_select_15(BITSELECT,7559)@105
    assign i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_select_15_b = i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_join(BITJOIN,7558)@105
    assign i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_select_15_b};

    // leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(MUX,24388)@105
    assign leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_join_q or leftShiftStage0Idx1_uid24387_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_16_c_compmm_m706_vt_join_q;
            1'b1 : leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24387_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(MUX,24393)@105
    assign leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s or leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24392_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = leftShiftStage0_uid24389_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24392_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x(MUX,24398)@105
    assign leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s or leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24397_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = leftShiftStage1_uid24394_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24397_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28(BITSELECT,9562)@105
    assign i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28_b = leftShiftStage2_uid24399_i_shl_i_i_i_i_i77_i_16_c_compmm_m0_shift_x_q[28:13];

    // redist468_i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28_b_1(DELAY,29596)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist468_i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_join(BITJOIN,9561)@106
    assign i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_join_q = {redist468_i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma(CHAINMULTADD,29034)@100 + 5
    // out q@106
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_6452_c_compmm_m224_out_dest_data_out_34_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_6451_c_compmm_m225_out_dest_data_out_33_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ch[0] <= redist536_sync_together4364_aunroll_x_in_c1_eni5_34_tpl_32_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ch[1] <= redist535_sync_together4364_aunroll_x_in_c1_eni5_33_tpl_32_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708(ADD,8854)@106
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_16_i_c_compmm_m703_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_16_i_c_compmm_m705_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_16_i_c_compmm_m704_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_16_c_compmm_m707_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_o[33:0];

    // rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x(MUX,16832)@106
    assign rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q or rightShiftStage0Idx1_uid16831_dupName_63_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q;
            1'b1 : rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16831_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x(MUX,16837)@106
    assign rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16836_dupName_63_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16833_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16836_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x(MUX,16842)@106
    assign rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16841_dupName_63_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16838_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16841_dupName_63_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m709_vt_select_20(BITSELECT,12807)@106
    assign i_unnamed_c_compmm_m709_vt_select_20_b = rightShiftStage2_uid16843_dupName_63_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m709_vt_join(BITJOIN,12806)@106
    assign i_unnamed_c_compmm_m709_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m709_vt_select_20_b};

    // i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x(BITSELECT,3483)@106
    assign i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x_b = i_unnamed_c_compmm_m709_vt_join_q[15:0];

    // redist1106_i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x_b_1(DELAY,30234)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1106_i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16852_dupName_64_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16851)@106
    assign rightShiftStage1Idx1Rng8_uid16852_dupName_64_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16854_dupName_64_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16853)@106
    assign rightShiftStage1Idx1_uid16854_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16852_dupName_64_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16847_dupName_64_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16846)@106
    assign rightShiftStage0Idx1Rng4_uid16847_dupName_64_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q[33:4];

    // rightShiftStage0Idx1_uid16849_dupName_64_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16848)@106
    assign rightShiftStage0Idx1_uid16849_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16847_dupName_64_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x(MUX,16850)@106
    assign rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q or rightShiftStage0Idx1_uid16849_dupName_64_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_16_i_c_compmm_m708_q;
            1'b1 : rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16849_dupName_64_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x(MUX,16855)@106
    assign rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16854_dupName_64_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16851_dupName_64_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16854_dupName_64_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m711_vt_select_21(BITSELECT,12810)@106
    assign i_unnamed_c_compmm_m711_vt_select_21_b = rightShiftStage1_uid16856_dupName_64_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m711_vt_join(BITJOIN,12809)@106
    assign i_unnamed_c_compmm_m711_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m711_vt_select_21_b};

    // i_unnamed_c_compmm_m712_sel_x(BITSELECT,6239)@106
    assign i_unnamed_c_compmm_m712_sel_x_b = i_unnamed_c_compmm_m711_vt_join_q[15:0];

    // i_unnamed_c_compmm_m713_BitSelect_for_a(BITSELECT,28830)@106
    assign i_unnamed_c_compmm_m713_BitSelect_for_a_b = i_unnamed_c_compmm_m712_sel_x_b[0:0];

    // i_unnamed_c_compmm_m713_join(BITJOIN,28831)@106
    assign i_unnamed_c_compmm_m713_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m713_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m713_vt_select_0(BITSELECT,12815)@106
    assign i_unnamed_c_compmm_m713_vt_select_0_b = i_unnamed_c_compmm_m713_join_q[0:0];

    // redist22_i_unnamed_c_compmm_m713_vt_select_0_b_1(DELAY,29150)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist22_i_unnamed_c_compmm_m713_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m713_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m713_vt_join(BITJOIN,12814)@107
    assign i_unnamed_c_compmm_m713_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist22_i_unnamed_c_compmm_m713_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_16_c_compmm_m714(ADD,7066)@107
    assign i_add_i_i_i_i_i126_i_16_c_compmm_m714_a = {1'b0, i_unnamed_c_compmm_m713_vt_join_q};
    assign i_add_i_i_i_i_i126_i_16_c_compmm_m714_b = {1'b0, redist1106_i_conv_i_i_i_i97_i_16_c_compmm_m710_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_16_c_compmm_m714_o = $unsigned(i_add_i_i_i_i_i126_i_16_c_compmm_m714_a) + $unsigned(i_add_i_i_i_i_i126_i_16_c_compmm_m714_b);
    assign i_add_i_i_i_i_i126_i_16_c_compmm_m714_q = i_add_i_i_i_i_i126_i_16_c_compmm_m714_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_16_c_compmm_m714_sel_x(BITSELECT,2080)@107
    assign bgTrunc_i_add_i_i_i_i_i126_i_16_c_compmm_m714_sel_x_b = i_add_i_i_i_i_i126_i_16_c_compmm_m714_q[15:0];

    // i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_sel_x(BITSELECT,3613)@107
    assign i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_16_c_compmm_m714_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_select_15(BITSELECT,7563)@107
    assign i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_select_15_b = i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_join(BITJOIN,7562)@107
    assign i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_select_15_b};

    // leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(MUX,24406)@107
    assign leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_join_q or leftShiftStage0Idx1_uid24405_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_17_c_compmm_m734_vt_join_q;
            1'b1 : leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24405_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(MUX,24411)@107
    assign leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s or leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24410_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = leftShiftStage0_uid24407_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24410_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x(MUX,24416)@107
    assign leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s or leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24415_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = leftShiftStage1_uid24412_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24415_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28(BITSELECT,9565)@107
    assign i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28_b = leftShiftStage2_uid24417_i_shl_i_i_i_i_i77_i_17_c_compmm_m0_shift_x_q[28:13];

    // redist467_i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28_b_1(DELAY,29595)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist467_i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_join(BITJOIN,9564)@108
    assign i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_join_q = {redist467_i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma(CHAINMULTADD,29035)@102 + 5
    // out q@108
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_6454_c_compmm_m222_out_dest_data_out_36_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_6453_c_compmm_m223_out_dest_data_out_35_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ch[0] <= redist538_sync_together4364_aunroll_x_in_c1_eni5_36_tpl_34_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ch[1] <= redist537_sync_together4364_aunroll_x_in_c1_eni5_35_tpl_34_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736(ADD,8855)@108
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_17_i_c_compmm_m731_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_17_i_c_compmm_m733_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_17_i_c_compmm_m732_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_17_c_compmm_m735_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_o[33:0];

    // rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x(MUX,16894)@108
    assign rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q or rightShiftStage0Idx1_uid16893_dupName_67_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q;
            1'b1 : rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16893_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x(MUX,16899)@108
    assign rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16898_dupName_67_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16895_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16898_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x(MUX,16904)@108
    assign rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16903_dupName_67_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16900_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16903_dupName_67_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m737_vt_select_20(BITSELECT,12829)@108
    assign i_unnamed_c_compmm_m737_vt_select_20_b = rightShiftStage2_uid16905_dupName_67_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m737_vt_join(BITJOIN,12828)@108
    assign i_unnamed_c_compmm_m737_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m737_vt_select_20_b};

    // i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x(BITSELECT,3484)@108
    assign i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x_b = i_unnamed_c_compmm_m737_vt_join_q[15:0];

    // redist1105_i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x_b_1(DELAY,30233)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1105_i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16914_dupName_68_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16913)@108
    assign rightShiftStage1Idx1Rng8_uid16914_dupName_68_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16916_dupName_68_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16915)@108
    assign rightShiftStage1Idx1_uid16916_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16914_dupName_68_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16909_dupName_68_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16908)@108
    assign rightShiftStage0Idx1Rng4_uid16909_dupName_68_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q[33:4];

    // rightShiftStage0Idx1_uid16911_dupName_68_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16910)@108
    assign rightShiftStage0Idx1_uid16911_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16909_dupName_68_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x(MUX,16912)@108
    assign rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q or rightShiftStage0Idx1_uid16911_dupName_68_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_17_i_c_compmm_m736_q;
            1'b1 : rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16911_dupName_68_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x(MUX,16917)@108
    assign rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16916_dupName_68_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16913_dupName_68_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16916_dupName_68_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m739_vt_select_21(BITSELECT,12832)@108
    assign i_unnamed_c_compmm_m739_vt_select_21_b = rightShiftStage1_uid16918_dupName_68_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m739_vt_join(BITJOIN,12831)@108
    assign i_unnamed_c_compmm_m739_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m739_vt_select_21_b};

    // i_unnamed_c_compmm_m740_sel_x(BITSELECT,6241)@108
    assign i_unnamed_c_compmm_m740_sel_x_b = i_unnamed_c_compmm_m739_vt_join_q[15:0];

    // i_unnamed_c_compmm_m741_BitSelect_for_a(BITSELECT,28834)@108
    assign i_unnamed_c_compmm_m741_BitSelect_for_a_b = i_unnamed_c_compmm_m740_sel_x_b[0:0];

    // i_unnamed_c_compmm_m741_join(BITJOIN,28835)@108
    assign i_unnamed_c_compmm_m741_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m741_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m741_vt_select_0(BITSELECT,12837)@108
    assign i_unnamed_c_compmm_m741_vt_select_0_b = i_unnamed_c_compmm_m741_join_q[0:0];

    // redist20_i_unnamed_c_compmm_m741_vt_select_0_b_1(DELAY,29148)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist20_i_unnamed_c_compmm_m741_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m741_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m741_vt_join(BITJOIN,12836)@109
    assign i_unnamed_c_compmm_m741_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist20_i_unnamed_c_compmm_m741_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_17_c_compmm_m742(ADD,7067)@109
    assign i_add_i_i_i_i_i126_i_17_c_compmm_m742_a = {1'b0, i_unnamed_c_compmm_m741_vt_join_q};
    assign i_add_i_i_i_i_i126_i_17_c_compmm_m742_b = {1'b0, redist1105_i_conv_i_i_i_i97_i_17_c_compmm_m738_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_17_c_compmm_m742_o = $unsigned(i_add_i_i_i_i_i126_i_17_c_compmm_m742_a) + $unsigned(i_add_i_i_i_i_i126_i_17_c_compmm_m742_b);
    assign i_add_i_i_i_i_i126_i_17_c_compmm_m742_q = i_add_i_i_i_i_i126_i_17_c_compmm_m742_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_17_c_compmm_m742_sel_x(BITSELECT,2081)@109
    assign bgTrunc_i_add_i_i_i_i_i126_i_17_c_compmm_m742_sel_x_b = i_add_i_i_i_i_i126_i_17_c_compmm_m742_q[15:0];

    // i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_sel_x(BITSELECT,3614)@109
    assign i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_17_c_compmm_m742_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_select_15(BITSELECT,7567)@109
    assign i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_select_15_b = i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_join(BITJOIN,7566)@109
    assign i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_select_15_b};

    // leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(MUX,24424)@109
    assign leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_join_q or leftShiftStage0Idx1_uid24423_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_18_c_compmm_m762_vt_join_q;
            1'b1 : leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24423_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(MUX,24429)@109
    assign leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s or leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24428_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = leftShiftStage0_uid24425_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24428_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x(MUX,24434)@109
    assign leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s or leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24433_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = leftShiftStage1_uid24430_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24433_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28(BITSELECT,9568)@109
    assign i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28_b = leftShiftStage2_uid24435_i_shl_i_i_i_i_i77_i_18_c_compmm_m0_shift_x_q[28:13];

    // redist466_i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28_b_1(DELAY,29594)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist466_i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_join(BITJOIN,9567)@110
    assign i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_join_q = {redist466_i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma(CHAINMULTADD,29036)@104 + 5
    // out q@110
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_6456_c_compmm_m220_out_dest_data_out_38_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_6455_c_compmm_m221_out_dest_data_out_37_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ch[0] <= redist540_sync_together4364_aunroll_x_in_c1_eni5_38_tpl_36_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ch[1] <= redist539_sync_together4364_aunroll_x_in_c1_eni5_37_tpl_36_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764(ADD,8856)@110
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_18_i_c_compmm_m759_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_18_i_c_compmm_m761_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_18_i_c_compmm_m760_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_18_c_compmm_m763_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_o[33:0];

    // rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x(MUX,16956)@110
    assign rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q or rightShiftStage0Idx1_uid16955_dupName_71_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q;
            1'b1 : rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16955_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x(MUX,16961)@110
    assign rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16960_dupName_71_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16957_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16960_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x(MUX,16966)@110
    assign rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid16965_dupName_71_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid16962_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid16965_dupName_71_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m765_vt_select_20(BITSELECT,12851)@110
    assign i_unnamed_c_compmm_m765_vt_select_20_b = rightShiftStage2_uid16967_dupName_71_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m765_vt_join(BITJOIN,12850)@110
    assign i_unnamed_c_compmm_m765_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m765_vt_select_20_b};

    // i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x(BITSELECT,3485)@110
    assign i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x_b = i_unnamed_c_compmm_m765_vt_join_q[15:0];

    // redist1104_i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x_b_1(DELAY,30232)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1104_i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid16976_dupName_72_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16975)@110
    assign rightShiftStage1Idx1Rng8_uid16976_dupName_72_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid16978_dupName_72_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16977)@110
    assign rightShiftStage1Idx1_uid16978_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid16976_dupName_72_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid16971_dupName_72_i_unnamed_c_compmm_m0_shift_x(BITSELECT,16970)@110
    assign rightShiftStage0Idx1Rng4_uid16971_dupName_72_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q[33:4];

    // rightShiftStage0Idx1_uid16973_dupName_72_i_unnamed_c_compmm_m0_shift_x(BITJOIN,16972)@110
    assign rightShiftStage0Idx1_uid16973_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid16971_dupName_72_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x(MUX,16974)@110
    assign rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q or rightShiftStage0Idx1_uid16973_dupName_72_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_18_i_c_compmm_m764_q;
            1'b1 : rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid16973_dupName_72_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x(MUX,16979)@110
    assign rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid16978_dupName_72_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid16975_dupName_72_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid16978_dupName_72_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m767_vt_select_21(BITSELECT,12854)@110
    assign i_unnamed_c_compmm_m767_vt_select_21_b = rightShiftStage1_uid16980_dupName_72_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m767_vt_join(BITJOIN,12853)@110
    assign i_unnamed_c_compmm_m767_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m767_vt_select_21_b};

    // i_unnamed_c_compmm_m768_sel_x(BITSELECT,6243)@110
    assign i_unnamed_c_compmm_m768_sel_x_b = i_unnamed_c_compmm_m767_vt_join_q[15:0];

    // i_unnamed_c_compmm_m769_BitSelect_for_a(BITSELECT,28838)@110
    assign i_unnamed_c_compmm_m769_BitSelect_for_a_b = i_unnamed_c_compmm_m768_sel_x_b[0:0];

    // i_unnamed_c_compmm_m769_join(BITJOIN,28839)@110
    assign i_unnamed_c_compmm_m769_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m769_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m769_vt_select_0(BITSELECT,12859)@110
    assign i_unnamed_c_compmm_m769_vt_select_0_b = i_unnamed_c_compmm_m769_join_q[0:0];

    // redist18_i_unnamed_c_compmm_m769_vt_select_0_b_1(DELAY,29146)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist18_i_unnamed_c_compmm_m769_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m769_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m769_vt_join(BITJOIN,12858)@111
    assign i_unnamed_c_compmm_m769_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist18_i_unnamed_c_compmm_m769_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_18_c_compmm_m770(ADD,7068)@111
    assign i_add_i_i_i_i_i126_i_18_c_compmm_m770_a = {1'b0, i_unnamed_c_compmm_m769_vt_join_q};
    assign i_add_i_i_i_i_i126_i_18_c_compmm_m770_b = {1'b0, redist1104_i_conv_i_i_i_i97_i_18_c_compmm_m766_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_18_c_compmm_m770_o = $unsigned(i_add_i_i_i_i_i126_i_18_c_compmm_m770_a) + $unsigned(i_add_i_i_i_i_i126_i_18_c_compmm_m770_b);
    assign i_add_i_i_i_i_i126_i_18_c_compmm_m770_q = i_add_i_i_i_i_i126_i_18_c_compmm_m770_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_18_c_compmm_m770_sel_x(BITSELECT,2082)@111
    assign bgTrunc_i_add_i_i_i_i_i126_i_18_c_compmm_m770_sel_x_b = i_add_i_i_i_i_i126_i_18_c_compmm_m770_q[15:0];

    // i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_sel_x(BITSELECT,3615)@111
    assign i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_18_c_compmm_m770_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_select_15(BITSELECT,7571)@111
    assign i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_select_15_b = i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_join(BITJOIN,7570)@111
    assign i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_select_15_b};

    // leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(MUX,24442)@111
    assign leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_join_q or leftShiftStage0Idx1_uid24441_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_19_c_compmm_m790_vt_join_q;
            1'b1 : leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24441_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(MUX,24447)@111
    assign leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s or leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24446_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = leftShiftStage0_uid24443_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24446_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x(MUX,24452)@111
    assign leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s or leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24451_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = leftShiftStage1_uid24448_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24451_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28(BITSELECT,9571)@111
    assign i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28_b = leftShiftStage2_uid24453_i_shl_i_i_i_i_i77_i_19_c_compmm_m0_shift_x_q[28:13];

    // redist465_i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28_b_1(DELAY,29593)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist465_i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_join(BITJOIN,9570)@112
    assign i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_join_q = {redist465_i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma(CHAINMULTADD,29037)@106 + 5
    // out q@112
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_6458_c_compmm_m218_out_dest_data_out_40_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_6457_c_compmm_m219_out_dest_data_out_39_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ch[0] <= redist542_sync_together4364_aunroll_x_in_c1_eni5_40_tpl_38_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ch[1] <= redist541_sync_together4364_aunroll_x_in_c1_eni5_39_tpl_38_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792(ADD,8857)@112
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_19_i_c_compmm_m787_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_19_i_c_compmm_m789_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_19_i_c_compmm_m788_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_19_c_compmm_m791_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_o[33:0];

    // rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x(MUX,17018)@112
    assign rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q or rightShiftStage0Idx1_uid17017_dupName_75_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q;
            1'b1 : rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17017_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x(MUX,17023)@112
    assign rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17022_dupName_75_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17019_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17022_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x(MUX,17028)@112
    assign rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17027_dupName_75_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17024_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17027_dupName_75_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m793_vt_select_20(BITSELECT,12873)@112
    assign i_unnamed_c_compmm_m793_vt_select_20_b = rightShiftStage2_uid17029_dupName_75_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m793_vt_join(BITJOIN,12872)@112
    assign i_unnamed_c_compmm_m793_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m793_vt_select_20_b};

    // i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x(BITSELECT,3486)@112
    assign i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x_b = i_unnamed_c_compmm_m793_vt_join_q[15:0];

    // redist1103_i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x_b_1(DELAY,30231)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1103_i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17038_dupName_76_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17037)@112
    assign rightShiftStage1Idx1Rng8_uid17038_dupName_76_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17040_dupName_76_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17039)@112
    assign rightShiftStage1Idx1_uid17040_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17038_dupName_76_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17033_dupName_76_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17032)@112
    assign rightShiftStage0Idx1Rng4_uid17033_dupName_76_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q[33:4];

    // rightShiftStage0Idx1_uid17035_dupName_76_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17034)@112
    assign rightShiftStage0Idx1_uid17035_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17033_dupName_76_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x(MUX,17036)@112
    assign rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q or rightShiftStage0Idx1_uid17035_dupName_76_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_19_i_c_compmm_m792_q;
            1'b1 : rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17035_dupName_76_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x(MUX,17041)@112
    assign rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17040_dupName_76_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17037_dupName_76_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17040_dupName_76_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m795_vt_select_21(BITSELECT,12876)@112
    assign i_unnamed_c_compmm_m795_vt_select_21_b = rightShiftStage1_uid17042_dupName_76_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m795_vt_join(BITJOIN,12875)@112
    assign i_unnamed_c_compmm_m795_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m795_vt_select_21_b};

    // i_unnamed_c_compmm_m796_sel_x(BITSELECT,6245)@112
    assign i_unnamed_c_compmm_m796_sel_x_b = i_unnamed_c_compmm_m795_vt_join_q[15:0];

    // i_unnamed_c_compmm_m797_BitSelect_for_a(BITSELECT,28842)@112
    assign i_unnamed_c_compmm_m797_BitSelect_for_a_b = i_unnamed_c_compmm_m796_sel_x_b[0:0];

    // i_unnamed_c_compmm_m797_join(BITJOIN,28843)@112
    assign i_unnamed_c_compmm_m797_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m797_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m797_vt_select_0(BITSELECT,12881)@112
    assign i_unnamed_c_compmm_m797_vt_select_0_b = i_unnamed_c_compmm_m797_join_q[0:0];

    // redist16_i_unnamed_c_compmm_m797_vt_select_0_b_1(DELAY,29144)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist16_i_unnamed_c_compmm_m797_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m797_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m797_vt_join(BITJOIN,12880)@113
    assign i_unnamed_c_compmm_m797_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist16_i_unnamed_c_compmm_m797_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_19_c_compmm_m798(ADD,7069)@113
    assign i_add_i_i_i_i_i126_i_19_c_compmm_m798_a = {1'b0, i_unnamed_c_compmm_m797_vt_join_q};
    assign i_add_i_i_i_i_i126_i_19_c_compmm_m798_b = {1'b0, redist1103_i_conv_i_i_i_i97_i_19_c_compmm_m794_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_19_c_compmm_m798_o = $unsigned(i_add_i_i_i_i_i126_i_19_c_compmm_m798_a) + $unsigned(i_add_i_i_i_i_i126_i_19_c_compmm_m798_b);
    assign i_add_i_i_i_i_i126_i_19_c_compmm_m798_q = i_add_i_i_i_i_i126_i_19_c_compmm_m798_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_19_c_compmm_m798_sel_x(BITSELECT,2083)@113
    assign bgTrunc_i_add_i_i_i_i_i126_i_19_c_compmm_m798_sel_x_b = i_add_i_i_i_i_i126_i_19_c_compmm_m798_q[15:0];

    // i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_sel_x(BITSELECT,3617)@113
    assign i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_19_c_compmm_m798_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_select_15(BITSELECT,7579)@113
    assign i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_select_15_b = i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_join(BITJOIN,7578)@113
    assign i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_select_15_b};

    // leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(MUX,24478)@113
    assign leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_join_q or leftShiftStage0Idx1_uid24477_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_20_c_compmm_m818_vt_join_q;
            1'b1 : leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24477_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(MUX,24483)@113
    assign leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s or leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24482_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = leftShiftStage0_uid24479_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24482_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x(MUX,24488)@113
    assign leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s or leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24487_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = leftShiftStage1_uid24484_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24487_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28(BITSELECT,9577)@113
    assign i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28_b = leftShiftStage2_uid24489_i_shl_i_i_i_i_i77_i_20_c_compmm_m0_shift_x_q[28:13];

    // redist463_i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28_b_1(DELAY,29591)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist463_i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_join(BITJOIN,9576)@114
    assign i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_join_q = {redist463_i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma(CHAINMULTADD,29039)@108 + 5
    // out q@114
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_6460_c_compmm_m216_out_dest_data_out_42_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_6459_c_compmm_m217_out_dest_data_out_41_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ch[0] <= redist544_sync_together4364_aunroll_x_in_c1_eni5_42_tpl_40_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ch[1] <= redist543_sync_together4364_aunroll_x_in_c1_eni5_41_tpl_40_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820(ADD,8859)@114
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_20_i_c_compmm_m815_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_20_i_c_compmm_m817_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_20_i_c_compmm_m816_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_20_c_compmm_m819_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_o[33:0];

    // rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x(MUX,17080)@114
    assign rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q or rightShiftStage0Idx1_uid17079_dupName_79_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q;
            1'b1 : rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17079_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x(MUX,17085)@114
    assign rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17084_dupName_79_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17081_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17084_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x(MUX,17090)@114
    assign rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17089_dupName_79_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17086_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17089_dupName_79_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m821_vt_select_20(BITSELECT,12895)@114
    assign i_unnamed_c_compmm_m821_vt_select_20_b = rightShiftStage2_uid17091_dupName_79_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m821_vt_join(BITJOIN,12894)@114
    assign i_unnamed_c_compmm_m821_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m821_vt_select_20_b};

    // i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x(BITSELECT,3488)@114
    assign i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x_b = i_unnamed_c_compmm_m821_vt_join_q[15:0];

    // redist1101_i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x_b_1(DELAY,30229)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1101_i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17100_dupName_80_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17099)@114
    assign rightShiftStage1Idx1Rng8_uid17100_dupName_80_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17102_dupName_80_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17101)@114
    assign rightShiftStage1Idx1_uid17102_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17100_dupName_80_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17095_dupName_80_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17094)@114
    assign rightShiftStage0Idx1Rng4_uid17095_dupName_80_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q[33:4];

    // rightShiftStage0Idx1_uid17097_dupName_80_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17096)@114
    assign rightShiftStage0Idx1_uid17097_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17095_dupName_80_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x(MUX,17098)@114
    assign rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q or rightShiftStage0Idx1_uid17097_dupName_80_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_20_i_c_compmm_m820_q;
            1'b1 : rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17097_dupName_80_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x(MUX,17103)@114
    assign rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17102_dupName_80_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17099_dupName_80_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17102_dupName_80_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m823_vt_select_21(BITSELECT,12898)@114
    assign i_unnamed_c_compmm_m823_vt_select_21_b = rightShiftStage1_uid17104_dupName_80_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m823_vt_join(BITJOIN,12897)@114
    assign i_unnamed_c_compmm_m823_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m823_vt_select_21_b};

    // i_unnamed_c_compmm_m824_sel_x(BITSELECT,6247)@114
    assign i_unnamed_c_compmm_m824_sel_x_b = i_unnamed_c_compmm_m823_vt_join_q[15:0];

    // i_unnamed_c_compmm_m825_BitSelect_for_a(BITSELECT,28846)@114
    assign i_unnamed_c_compmm_m825_BitSelect_for_a_b = i_unnamed_c_compmm_m824_sel_x_b[0:0];

    // i_unnamed_c_compmm_m825_join(BITJOIN,28847)@114
    assign i_unnamed_c_compmm_m825_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m825_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m825_vt_select_0(BITSELECT,12903)@114
    assign i_unnamed_c_compmm_m825_vt_select_0_b = i_unnamed_c_compmm_m825_join_q[0:0];

    // redist14_i_unnamed_c_compmm_m825_vt_select_0_b_1(DELAY,29142)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist14_i_unnamed_c_compmm_m825_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m825_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m825_vt_join(BITJOIN,12902)@115
    assign i_unnamed_c_compmm_m825_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist14_i_unnamed_c_compmm_m825_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_20_c_compmm_m826(ADD,7071)@115
    assign i_add_i_i_i_i_i126_i_20_c_compmm_m826_a = {1'b0, i_unnamed_c_compmm_m825_vt_join_q};
    assign i_add_i_i_i_i_i126_i_20_c_compmm_m826_b = {1'b0, redist1101_i_conv_i_i_i_i97_i_20_c_compmm_m822_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_20_c_compmm_m826_o = $unsigned(i_add_i_i_i_i_i126_i_20_c_compmm_m826_a) + $unsigned(i_add_i_i_i_i_i126_i_20_c_compmm_m826_b);
    assign i_add_i_i_i_i_i126_i_20_c_compmm_m826_q = i_add_i_i_i_i_i126_i_20_c_compmm_m826_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_20_c_compmm_m826_sel_x(BITSELECT,2085)@115
    assign bgTrunc_i_add_i_i_i_i_i126_i_20_c_compmm_m826_sel_x_b = i_add_i_i_i_i_i126_i_20_c_compmm_m826_q[15:0];

    // i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_sel_x(BITSELECT,3618)@115
    assign i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_20_c_compmm_m826_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_select_15(BITSELECT,7583)@115
    assign i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_select_15_b = i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_join(BITJOIN,7582)@115
    assign i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_select_15_b};

    // leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(MUX,24496)@115
    assign leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_join_q or leftShiftStage0Idx1_uid24495_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_21_c_compmm_m846_vt_join_q;
            1'b1 : leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24495_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(MUX,24501)@115
    assign leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s or leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24500_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = leftShiftStage0_uid24497_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24500_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x(MUX,24506)@115
    assign leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s or leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24505_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = leftShiftStage1_uid24502_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24505_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28(BITSELECT,9580)@115
    assign i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28_b = leftShiftStage2_uid24507_i_shl_i_i_i_i_i77_i_21_c_compmm_m0_shift_x_q[28:13];

    // redist462_i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28_b_1(DELAY,29590)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist462_i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_join(BITJOIN,9579)@116
    assign i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_join_q = {redist462_i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma(CHAINMULTADD,29040)@110 + 5
    // out q@116
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_6462_c_compmm_m214_out_dest_data_out_44_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_6461_c_compmm_m215_out_dest_data_out_43_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ch[0] <= redist546_sync_together4364_aunroll_x_in_c1_eni5_44_tpl_42_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ch[1] <= redist545_sync_together4364_aunroll_x_in_c1_eni5_43_tpl_42_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848(ADD,8860)@116
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_21_i_c_compmm_m843_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_21_i_c_compmm_m845_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_21_i_c_compmm_m844_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_21_c_compmm_m847_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_o[33:0];

    // rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x(MUX,17142)@116
    assign rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q or rightShiftStage0Idx1_uid17141_dupName_83_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q;
            1'b1 : rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17141_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x(MUX,17147)@116
    assign rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17146_dupName_83_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17143_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17146_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x(MUX,17152)@116
    assign rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17151_dupName_83_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17148_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17151_dupName_83_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m849_vt_select_20(BITSELECT,12917)@116
    assign i_unnamed_c_compmm_m849_vt_select_20_b = rightShiftStage2_uid17153_dupName_83_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m849_vt_join(BITJOIN,12916)@116
    assign i_unnamed_c_compmm_m849_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m849_vt_select_20_b};

    // i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x(BITSELECT,3489)@116
    assign i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x_b = i_unnamed_c_compmm_m849_vt_join_q[15:0];

    // redist1100_i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x_b_1(DELAY,30228)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1100_i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17162_dupName_84_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17161)@116
    assign rightShiftStage1Idx1Rng8_uid17162_dupName_84_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17164_dupName_84_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17163)@116
    assign rightShiftStage1Idx1_uid17164_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17162_dupName_84_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17157_dupName_84_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17156)@116
    assign rightShiftStage0Idx1Rng4_uid17157_dupName_84_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q[33:4];

    // rightShiftStage0Idx1_uid17159_dupName_84_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17158)@116
    assign rightShiftStage0Idx1_uid17159_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17157_dupName_84_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x(MUX,17160)@116
    assign rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q or rightShiftStage0Idx1_uid17159_dupName_84_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_21_i_c_compmm_m848_q;
            1'b1 : rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17159_dupName_84_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x(MUX,17165)@116
    assign rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17164_dupName_84_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17161_dupName_84_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17164_dupName_84_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m851_vt_select_21(BITSELECT,12920)@116
    assign i_unnamed_c_compmm_m851_vt_select_21_b = rightShiftStage1_uid17166_dupName_84_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m851_vt_join(BITJOIN,12919)@116
    assign i_unnamed_c_compmm_m851_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m851_vt_select_21_b};

    // i_unnamed_c_compmm_m852_sel_x(BITSELECT,6249)@116
    assign i_unnamed_c_compmm_m852_sel_x_b = i_unnamed_c_compmm_m851_vt_join_q[15:0];

    // i_unnamed_c_compmm_m853_BitSelect_for_a(BITSELECT,28850)@116
    assign i_unnamed_c_compmm_m853_BitSelect_for_a_b = i_unnamed_c_compmm_m852_sel_x_b[0:0];

    // i_unnamed_c_compmm_m853_join(BITJOIN,28851)@116
    assign i_unnamed_c_compmm_m853_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m853_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m853_vt_select_0(BITSELECT,12925)@116
    assign i_unnamed_c_compmm_m853_vt_select_0_b = i_unnamed_c_compmm_m853_join_q[0:0];

    // redist12_i_unnamed_c_compmm_m853_vt_select_0_b_1(DELAY,29140)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist12_i_unnamed_c_compmm_m853_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m853_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m853_vt_join(BITJOIN,12924)@117
    assign i_unnamed_c_compmm_m853_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist12_i_unnamed_c_compmm_m853_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_21_c_compmm_m854(ADD,7072)@117
    assign i_add_i_i_i_i_i126_i_21_c_compmm_m854_a = {1'b0, i_unnamed_c_compmm_m853_vt_join_q};
    assign i_add_i_i_i_i_i126_i_21_c_compmm_m854_b = {1'b0, redist1100_i_conv_i_i_i_i97_i_21_c_compmm_m850_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_21_c_compmm_m854_o = $unsigned(i_add_i_i_i_i_i126_i_21_c_compmm_m854_a) + $unsigned(i_add_i_i_i_i_i126_i_21_c_compmm_m854_b);
    assign i_add_i_i_i_i_i126_i_21_c_compmm_m854_q = i_add_i_i_i_i_i126_i_21_c_compmm_m854_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_21_c_compmm_m854_sel_x(BITSELECT,2086)@117
    assign bgTrunc_i_add_i_i_i_i_i126_i_21_c_compmm_m854_sel_x_b = i_add_i_i_i_i_i126_i_21_c_compmm_m854_q[15:0];

    // i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_sel_x(BITSELECT,3619)@117
    assign i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_21_c_compmm_m854_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_select_15(BITSELECT,7587)@117
    assign i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_select_15_b = i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_join(BITJOIN,7586)@117
    assign i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_select_15_b};

    // leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(MUX,24514)@117
    assign leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_join_q or leftShiftStage0Idx1_uid24513_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_22_c_compmm_m874_vt_join_q;
            1'b1 : leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24513_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(MUX,24519)@117
    assign leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s or leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24518_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = leftShiftStage0_uid24515_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24518_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x(MUX,24524)@117
    assign leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s or leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24523_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = leftShiftStage1_uid24520_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24523_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28(BITSELECT,9583)@117
    assign i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28_b = leftShiftStage2_uid24525_i_shl_i_i_i_i_i77_i_22_c_compmm_m0_shift_x_q[28:13];

    // redist461_i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28_b_1(DELAY,29589)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist461_i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_join(BITJOIN,9582)@118
    assign i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_join_q = {redist461_i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma(CHAINMULTADD,29041)@112 + 5
    // out q@118
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_6464_c_compmm_m212_out_dest_data_out_46_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_6463_c_compmm_m213_out_dest_data_out_45_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ch[0] <= redist548_sync_together4364_aunroll_x_in_c1_eni5_46_tpl_44_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ch[1] <= redist547_sync_together4364_aunroll_x_in_c1_eni5_45_tpl_44_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876(ADD,8861)@118
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_22_i_c_compmm_m871_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_22_i_c_compmm_m873_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_22_i_c_compmm_m872_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_22_c_compmm_m875_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_o[33:0];

    // rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x(MUX,17204)@118
    assign rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q or rightShiftStage0Idx1_uid17203_dupName_87_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q;
            1'b1 : rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17203_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x(MUX,17209)@118
    assign rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17208_dupName_87_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17205_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17208_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x(MUX,17214)@118
    assign rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17213_dupName_87_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17210_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17213_dupName_87_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m877_vt_select_20(BITSELECT,12939)@118
    assign i_unnamed_c_compmm_m877_vt_select_20_b = rightShiftStage2_uid17215_dupName_87_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m877_vt_join(BITJOIN,12938)@118
    assign i_unnamed_c_compmm_m877_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m877_vt_select_20_b};

    // i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x(BITSELECT,3490)@118
    assign i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x_b = i_unnamed_c_compmm_m877_vt_join_q[15:0];

    // redist1099_i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x_b_1(DELAY,30227)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1099_i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17224_dupName_88_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17223)@118
    assign rightShiftStage1Idx1Rng8_uid17224_dupName_88_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17226_dupName_88_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17225)@118
    assign rightShiftStage1Idx1_uid17226_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17224_dupName_88_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17219_dupName_88_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17218)@118
    assign rightShiftStage0Idx1Rng4_uid17219_dupName_88_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q[33:4];

    // rightShiftStage0Idx1_uid17221_dupName_88_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17220)@118
    assign rightShiftStage0Idx1_uid17221_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17219_dupName_88_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x(MUX,17222)@118
    assign rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q or rightShiftStage0Idx1_uid17221_dupName_88_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_22_i_c_compmm_m876_q;
            1'b1 : rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17221_dupName_88_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x(MUX,17227)@118
    assign rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17226_dupName_88_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17223_dupName_88_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17226_dupName_88_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m879_vt_select_21(BITSELECT,12942)@118
    assign i_unnamed_c_compmm_m879_vt_select_21_b = rightShiftStage1_uid17228_dupName_88_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m879_vt_join(BITJOIN,12941)@118
    assign i_unnamed_c_compmm_m879_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m879_vt_select_21_b};

    // i_unnamed_c_compmm_m880_sel_x(BITSELECT,6251)@118
    assign i_unnamed_c_compmm_m880_sel_x_b = i_unnamed_c_compmm_m879_vt_join_q[15:0];

    // i_unnamed_c_compmm_m881_BitSelect_for_a(BITSELECT,28854)@118
    assign i_unnamed_c_compmm_m881_BitSelect_for_a_b = i_unnamed_c_compmm_m880_sel_x_b[0:0];

    // i_unnamed_c_compmm_m881_join(BITJOIN,28855)@118
    assign i_unnamed_c_compmm_m881_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m881_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m881_vt_select_0(BITSELECT,12947)@118
    assign i_unnamed_c_compmm_m881_vt_select_0_b = i_unnamed_c_compmm_m881_join_q[0:0];

    // redist10_i_unnamed_c_compmm_m881_vt_select_0_b_1(DELAY,29138)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist10_i_unnamed_c_compmm_m881_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m881_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m881_vt_join(BITJOIN,12946)@119
    assign i_unnamed_c_compmm_m881_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist10_i_unnamed_c_compmm_m881_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_22_c_compmm_m882(ADD,7073)@119
    assign i_add_i_i_i_i_i126_i_22_c_compmm_m882_a = {1'b0, i_unnamed_c_compmm_m881_vt_join_q};
    assign i_add_i_i_i_i_i126_i_22_c_compmm_m882_b = {1'b0, redist1099_i_conv_i_i_i_i97_i_22_c_compmm_m878_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_22_c_compmm_m882_o = $unsigned(i_add_i_i_i_i_i126_i_22_c_compmm_m882_a) + $unsigned(i_add_i_i_i_i_i126_i_22_c_compmm_m882_b);
    assign i_add_i_i_i_i_i126_i_22_c_compmm_m882_q = i_add_i_i_i_i_i126_i_22_c_compmm_m882_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_22_c_compmm_m882_sel_x(BITSELECT,2087)@119
    assign bgTrunc_i_add_i_i_i_i_i126_i_22_c_compmm_m882_sel_x_b = i_add_i_i_i_i_i126_i_22_c_compmm_m882_q[15:0];

    // i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_sel_x(BITSELECT,3620)@119
    assign i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_22_c_compmm_m882_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_select_15(BITSELECT,7591)@119
    assign i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_select_15_b = i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_join(BITJOIN,7590)@119
    assign i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_select_15_b};

    // leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(MUX,24532)@119
    assign leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_join_q or leftShiftStage0Idx1_uid24531_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_23_c_compmm_m902_vt_join_q;
            1'b1 : leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24531_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(MUX,24537)@119
    assign leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s or leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24536_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = leftShiftStage0_uid24533_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24536_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x(MUX,24542)@119
    assign leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s or leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24541_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = leftShiftStage1_uid24538_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24541_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28(BITSELECT,9586)@119
    assign i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28_b = leftShiftStage2_uid24543_i_shl_i_i_i_i_i77_i_23_c_compmm_m0_shift_x_q[28:13];

    // redist460_i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28_b_1(DELAY,29588)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist460_i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_join(BITJOIN,9585)@120
    assign i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_join_q = {redist460_i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma(CHAINMULTADD,29042)@114 + 5
    // out q@120
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_6466_c_compmm_m210_out_dest_data_out_48_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_6465_c_compmm_m211_out_dest_data_out_47_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ch[0] <= redist550_sync_together4364_aunroll_x_in_c1_eni5_48_tpl_46_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ch[1] <= redist549_sync_together4364_aunroll_x_in_c1_eni5_47_tpl_46_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904(ADD,8862)@120
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_23_i_c_compmm_m899_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_23_i_c_compmm_m901_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_23_i_c_compmm_m900_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_23_c_compmm_m903_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_o[33:0];

    // rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x(MUX,17266)@120
    assign rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q or rightShiftStage0Idx1_uid17265_dupName_91_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q;
            1'b1 : rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17265_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x(MUX,17271)@120
    assign rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17270_dupName_91_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17267_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17270_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x(MUX,17276)@120
    assign rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17275_dupName_91_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17272_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17275_dupName_91_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m905_vt_select_20(BITSELECT,12961)@120
    assign i_unnamed_c_compmm_m905_vt_select_20_b = rightShiftStage2_uid17277_dupName_91_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m905_vt_join(BITJOIN,12960)@120
    assign i_unnamed_c_compmm_m905_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m905_vt_select_20_b};

    // i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x(BITSELECT,3491)@120
    assign i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x_b = i_unnamed_c_compmm_m905_vt_join_q[15:0];

    // redist1098_i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x_b_1(DELAY,30226)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1098_i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17286_dupName_92_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17285)@120
    assign rightShiftStage1Idx1Rng8_uid17286_dupName_92_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17288_dupName_92_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17287)@120
    assign rightShiftStage1Idx1_uid17288_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17286_dupName_92_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17281_dupName_92_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17280)@120
    assign rightShiftStage0Idx1Rng4_uid17281_dupName_92_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q[33:4];

    // rightShiftStage0Idx1_uid17283_dupName_92_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17282)@120
    assign rightShiftStage0Idx1_uid17283_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17281_dupName_92_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x(MUX,17284)@120
    assign rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q or rightShiftStage0Idx1_uid17283_dupName_92_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_23_i_c_compmm_m904_q;
            1'b1 : rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17283_dupName_92_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x(MUX,17289)@120
    assign rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17288_dupName_92_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17285_dupName_92_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17288_dupName_92_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m907_vt_select_21(BITSELECT,12964)@120
    assign i_unnamed_c_compmm_m907_vt_select_21_b = rightShiftStage1_uid17290_dupName_92_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m907_vt_join(BITJOIN,12963)@120
    assign i_unnamed_c_compmm_m907_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m907_vt_select_21_b};

    // i_unnamed_c_compmm_m908_sel_x(BITSELECT,6253)@120
    assign i_unnamed_c_compmm_m908_sel_x_b = i_unnamed_c_compmm_m907_vt_join_q[15:0];

    // i_unnamed_c_compmm_m909_BitSelect_for_a(BITSELECT,28858)@120
    assign i_unnamed_c_compmm_m909_BitSelect_for_a_b = i_unnamed_c_compmm_m908_sel_x_b[0:0];

    // i_unnamed_c_compmm_m909_join(BITJOIN,28859)@120
    assign i_unnamed_c_compmm_m909_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m909_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m909_vt_select_0(BITSELECT,12969)@120
    assign i_unnamed_c_compmm_m909_vt_select_0_b = i_unnamed_c_compmm_m909_join_q[0:0];

    // redist8_i_unnamed_c_compmm_m909_vt_select_0_b_1(DELAY,29136)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist8_i_unnamed_c_compmm_m909_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m909_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m909_vt_join(BITJOIN,12968)@121
    assign i_unnamed_c_compmm_m909_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist8_i_unnamed_c_compmm_m909_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_23_c_compmm_m910(ADD,7074)@121
    assign i_add_i_i_i_i_i126_i_23_c_compmm_m910_a = {1'b0, i_unnamed_c_compmm_m909_vt_join_q};
    assign i_add_i_i_i_i_i126_i_23_c_compmm_m910_b = {1'b0, redist1098_i_conv_i_i_i_i97_i_23_c_compmm_m906_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_23_c_compmm_m910_o = $unsigned(i_add_i_i_i_i_i126_i_23_c_compmm_m910_a) + $unsigned(i_add_i_i_i_i_i126_i_23_c_compmm_m910_b);
    assign i_add_i_i_i_i_i126_i_23_c_compmm_m910_q = i_add_i_i_i_i_i126_i_23_c_compmm_m910_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_23_c_compmm_m910_sel_x(BITSELECT,2088)@121
    assign bgTrunc_i_add_i_i_i_i_i126_i_23_c_compmm_m910_sel_x_b = i_add_i_i_i_i_i126_i_23_c_compmm_m910_q[15:0];

    // i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_sel_x(BITSELECT,3621)@121
    assign i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_23_c_compmm_m910_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_select_15(BITSELECT,7595)@121
    assign i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_select_15_b = i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_join(BITJOIN,7594)@121
    assign i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_select_15_b};

    // leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(MUX,24550)@121
    assign leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_join_q or leftShiftStage0Idx1_uid24549_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_24_c_compmm_m930_vt_join_q;
            1'b1 : leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24549_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(MUX,24555)@121
    assign leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s or leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24554_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = leftShiftStage0_uid24551_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24554_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x(MUX,24560)@121
    assign leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s or leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24559_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = leftShiftStage1_uid24556_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24559_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28(BITSELECT,9589)@121
    assign i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28_b = leftShiftStage2_uid24561_i_shl_i_i_i_i_i77_i_24_c_compmm_m0_shift_x_q[28:13];

    // redist459_i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28_b_1(DELAY,29587)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist459_i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_join(BITJOIN,9588)@122
    assign i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_join_q = {redist459_i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma(CHAINMULTADD,29043)@116 + 5
    // out q@122
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_6468_c_compmm_m208_out_dest_data_out_50_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_6467_c_compmm_m209_out_dest_data_out_49_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ch[0] <= redist552_sync_together4364_aunroll_x_in_c1_eni5_50_tpl_48_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ch[1] <= redist551_sync_together4364_aunroll_x_in_c1_eni5_49_tpl_48_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932(ADD,8863)@122
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_24_i_c_compmm_m927_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_24_i_c_compmm_m929_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_24_i_c_compmm_m928_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_24_c_compmm_m931_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_o[33:0];

    // rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x(MUX,17328)@122
    assign rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q or rightShiftStage0Idx1_uid17327_dupName_95_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q;
            1'b1 : rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17327_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x(MUX,17333)@122
    assign rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17332_dupName_95_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17329_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17332_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x(MUX,17338)@122
    assign rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17337_dupName_95_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17334_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17337_dupName_95_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m933_vt_select_20(BITSELECT,12983)@122
    assign i_unnamed_c_compmm_m933_vt_select_20_b = rightShiftStage2_uid17339_dupName_95_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m933_vt_join(BITJOIN,12982)@122
    assign i_unnamed_c_compmm_m933_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m933_vt_select_20_b};

    // i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x(BITSELECT,3492)@122
    assign i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x_b = i_unnamed_c_compmm_m933_vt_join_q[15:0];

    // redist1097_i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x_b_1(DELAY,30225)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1097_i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17348_dupName_96_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17347)@122
    assign rightShiftStage1Idx1Rng8_uid17348_dupName_96_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17350_dupName_96_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17349)@122
    assign rightShiftStage1Idx1_uid17350_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17348_dupName_96_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17343_dupName_96_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17342)@122
    assign rightShiftStage0Idx1Rng4_uid17343_dupName_96_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q[33:4];

    // rightShiftStage0Idx1_uid17345_dupName_96_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17344)@122
    assign rightShiftStage0Idx1_uid17345_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17343_dupName_96_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x(MUX,17346)@122
    assign rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q or rightShiftStage0Idx1_uid17345_dupName_96_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_24_i_c_compmm_m932_q;
            1'b1 : rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17345_dupName_96_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x(MUX,17351)@122
    assign rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17350_dupName_96_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17347_dupName_96_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17350_dupName_96_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m935_vt_select_21(BITSELECT,12986)@122
    assign i_unnamed_c_compmm_m935_vt_select_21_b = rightShiftStage1_uid17352_dupName_96_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m935_vt_join(BITJOIN,12985)@122
    assign i_unnamed_c_compmm_m935_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m935_vt_select_21_b};

    // i_unnamed_c_compmm_m936_sel_x(BITSELECT,6255)@122
    assign i_unnamed_c_compmm_m936_sel_x_b = i_unnamed_c_compmm_m935_vt_join_q[15:0];

    // i_unnamed_c_compmm_m937_BitSelect_for_a(BITSELECT,28862)@122
    assign i_unnamed_c_compmm_m937_BitSelect_for_a_b = i_unnamed_c_compmm_m936_sel_x_b[0:0];

    // i_unnamed_c_compmm_m937_join(BITJOIN,28863)@122
    assign i_unnamed_c_compmm_m937_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m937_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m937_vt_select_0(BITSELECT,12991)@122
    assign i_unnamed_c_compmm_m937_vt_select_0_b = i_unnamed_c_compmm_m937_join_q[0:0];

    // redist6_i_unnamed_c_compmm_m937_vt_select_0_b_1(DELAY,29134)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist6_i_unnamed_c_compmm_m937_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m937_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m937_vt_join(BITJOIN,12990)@123
    assign i_unnamed_c_compmm_m937_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist6_i_unnamed_c_compmm_m937_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_24_c_compmm_m938(ADD,7075)@123
    assign i_add_i_i_i_i_i126_i_24_c_compmm_m938_a = {1'b0, i_unnamed_c_compmm_m937_vt_join_q};
    assign i_add_i_i_i_i_i126_i_24_c_compmm_m938_b = {1'b0, redist1097_i_conv_i_i_i_i97_i_24_c_compmm_m934_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_24_c_compmm_m938_o = $unsigned(i_add_i_i_i_i_i126_i_24_c_compmm_m938_a) + $unsigned(i_add_i_i_i_i_i126_i_24_c_compmm_m938_b);
    assign i_add_i_i_i_i_i126_i_24_c_compmm_m938_q = i_add_i_i_i_i_i126_i_24_c_compmm_m938_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_24_c_compmm_m938_sel_x(BITSELECT,2089)@123
    assign bgTrunc_i_add_i_i_i_i_i126_i_24_c_compmm_m938_sel_x_b = i_add_i_i_i_i_i126_i_24_c_compmm_m938_q[15:0];

    // i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_sel_x(BITSELECT,3622)@123
    assign i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_24_c_compmm_m938_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_select_15(BITSELECT,7599)@123
    assign i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_select_15_b = i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_join(BITJOIN,7598)@123
    assign i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_select_15_b};

    // leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(MUX,24568)@123
    assign leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_join_q or leftShiftStage0Idx1_uid24567_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_25_c_compmm_m958_vt_join_q;
            1'b1 : leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24567_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(MUX,24573)@123
    assign leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s or leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24572_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = leftShiftStage0_uid24569_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24572_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x(MUX,24578)@123
    assign leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s or leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24577_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = leftShiftStage1_uid24574_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24577_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28(BITSELECT,9592)@123
    assign i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28_b = leftShiftStage2_uid24579_i_shl_i_i_i_i_i77_i_25_c_compmm_m0_shift_x_q[28:13];

    // redist458_i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28_b_1(DELAY,29586)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist458_i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_join(BITJOIN,9591)@124
    assign i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_join_q = {redist458_i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma(CHAINMULTADD,29044)@118 + 5
    // out q@124
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_6470_c_compmm_m206_out_dest_data_out_52_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_6469_c_compmm_m207_out_dest_data_out_51_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ch[0] <= redist554_sync_together4364_aunroll_x_in_c1_eni5_52_tpl_50_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ch[1] <= redist553_sync_together4364_aunroll_x_in_c1_eni5_51_tpl_50_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960(ADD,8864)@124
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_25_i_c_compmm_m955_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_25_i_c_compmm_m957_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_25_i_c_compmm_m956_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_25_c_compmm_m959_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_o[33:0];

    // rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x(MUX,17390)@124
    assign rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q or rightShiftStage0Idx1_uid17389_dupName_99_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q;
            1'b1 : rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17389_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x(MUX,17395)@124
    assign rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17394_dupName_99_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17391_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17394_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x(MUX,17400)@124
    assign rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17399_dupName_99_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17396_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17399_dupName_99_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m961_vt_select_20(BITSELECT,13005)@124
    assign i_unnamed_c_compmm_m961_vt_select_20_b = rightShiftStage2_uid17401_dupName_99_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m961_vt_join(BITJOIN,13004)@124
    assign i_unnamed_c_compmm_m961_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m961_vt_select_20_b};

    // i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x(BITSELECT,3493)@124
    assign i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x_b = i_unnamed_c_compmm_m961_vt_join_q[15:0];

    // redist1096_i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x_b_1(DELAY,30224)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1096_i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17410_dupName_100_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17409)@124
    assign rightShiftStage1Idx1Rng8_uid17410_dupName_100_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17412_dupName_100_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17411)@124
    assign rightShiftStage1Idx1_uid17412_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17410_dupName_100_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17405_dupName_100_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17404)@124
    assign rightShiftStage0Idx1Rng4_uid17405_dupName_100_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q[33:4];

    // rightShiftStage0Idx1_uid17407_dupName_100_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17406)@124
    assign rightShiftStage0Idx1_uid17407_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17405_dupName_100_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x(MUX,17408)@124
    assign rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q or rightShiftStage0Idx1_uid17407_dupName_100_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_25_i_c_compmm_m960_q;
            1'b1 : rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17407_dupName_100_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x(MUX,17413)@124
    assign rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17412_dupName_100_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17409_dupName_100_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17412_dupName_100_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m963_vt_select_21(BITSELECT,13008)@124
    assign i_unnamed_c_compmm_m963_vt_select_21_b = rightShiftStage1_uid17414_dupName_100_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m963_vt_join(BITJOIN,13007)@124
    assign i_unnamed_c_compmm_m963_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m963_vt_select_21_b};

    // i_unnamed_c_compmm_m964_sel_x(BITSELECT,6257)@124
    assign i_unnamed_c_compmm_m964_sel_x_b = i_unnamed_c_compmm_m963_vt_join_q[15:0];

    // i_unnamed_c_compmm_m965_BitSelect_for_a(BITSELECT,28866)@124
    assign i_unnamed_c_compmm_m965_BitSelect_for_a_b = i_unnamed_c_compmm_m964_sel_x_b[0:0];

    // i_unnamed_c_compmm_m965_join(BITJOIN,28867)@124
    assign i_unnamed_c_compmm_m965_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m965_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m965_vt_select_0(BITSELECT,13013)@124
    assign i_unnamed_c_compmm_m965_vt_select_0_b = i_unnamed_c_compmm_m965_join_q[0:0];

    // redist4_i_unnamed_c_compmm_m965_vt_select_0_b_1(DELAY,29132)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist4_i_unnamed_c_compmm_m965_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m965_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m965_vt_join(BITJOIN,13012)@125
    assign i_unnamed_c_compmm_m965_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist4_i_unnamed_c_compmm_m965_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_25_c_compmm_m966(ADD,7076)@125
    assign i_add_i_i_i_i_i126_i_25_c_compmm_m966_a = {1'b0, i_unnamed_c_compmm_m965_vt_join_q};
    assign i_add_i_i_i_i_i126_i_25_c_compmm_m966_b = {1'b0, redist1096_i_conv_i_i_i_i97_i_25_c_compmm_m962_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_25_c_compmm_m966_o = $unsigned(i_add_i_i_i_i_i126_i_25_c_compmm_m966_a) + $unsigned(i_add_i_i_i_i_i126_i_25_c_compmm_m966_b);
    assign i_add_i_i_i_i_i126_i_25_c_compmm_m966_q = i_add_i_i_i_i_i126_i_25_c_compmm_m966_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_25_c_compmm_m966_sel_x(BITSELECT,2090)@125
    assign bgTrunc_i_add_i_i_i_i_i126_i_25_c_compmm_m966_sel_x_b = i_add_i_i_i_i_i126_i_25_c_compmm_m966_q[15:0];

    // i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_sel_x(BITSELECT,3623)@125
    assign i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_25_c_compmm_m966_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_select_15(BITSELECT,7603)@125
    assign i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_select_15_b = i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_join(BITJOIN,7602)@125
    assign i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_select_15_b};

    // leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(MUX,24586)@125
    assign leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_join_q or leftShiftStage0Idx1_uid24585_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_26_c_compmm_m986_vt_join_q;
            1'b1 : leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24585_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(MUX,24591)@125
    assign leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s or leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24590_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = leftShiftStage0_uid24587_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24590_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x(MUX,24596)@125
    assign leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s or leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24595_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = leftShiftStage1_uid24592_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24595_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28(BITSELECT,9595)@125
    assign i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28_b = leftShiftStage2_uid24597_i_shl_i_i_i_i_i77_i_26_c_compmm_m0_shift_x_q[28:13];

    // redist457_i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28_b_1(DELAY,29585)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist457_i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_join(BITJOIN,9594)@126
    assign i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_join_q = {redist457_i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma(CHAINMULTADD,29045)@120 + 5
    // out q@126
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_6472_c_compmm_m204_out_dest_data_out_54_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_6471_c_compmm_m205_out_dest_data_out_53_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ch[0] <= redist556_sync_together4364_aunroll_x_in_c1_eni5_54_tpl_52_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ch[1] <= redist555_sync_together4364_aunroll_x_in_c1_eni5_53_tpl_52_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988(ADD,8865)@126
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_26_i_c_compmm_m983_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_26_i_c_compmm_m985_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_26_i_c_compmm_m984_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_26_c_compmm_m987_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_o[33:0];

    // rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x(MUX,17452)@126
    assign rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q or rightShiftStage0Idx1_uid17451_dupName_103_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q;
            1'b1 : rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17451_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x(MUX,17457)@126
    assign rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17456_dupName_103_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17453_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17456_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x(MUX,17462)@126
    assign rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17461_dupName_103_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17458_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17461_dupName_103_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m989_vt_select_20(BITSELECT,13027)@126
    assign i_unnamed_c_compmm_m989_vt_select_20_b = rightShiftStage2_uid17463_dupName_103_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m989_vt_join(BITJOIN,13026)@126
    assign i_unnamed_c_compmm_m989_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m989_vt_select_20_b};

    // i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x(BITSELECT,3494)@126
    assign i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x_b = i_unnamed_c_compmm_m989_vt_join_q[15:0];

    // redist1095_i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x_b_1(DELAY,30223)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1095_i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17472_dupName_104_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17471)@126
    assign rightShiftStage1Idx1Rng8_uid17472_dupName_104_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17474_dupName_104_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17473)@126
    assign rightShiftStage1Idx1_uid17474_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17472_dupName_104_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17467_dupName_104_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17466)@126
    assign rightShiftStage0Idx1Rng4_uid17467_dupName_104_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q[33:4];

    // rightShiftStage0Idx1_uid17469_dupName_104_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17468)@126
    assign rightShiftStage0Idx1_uid17469_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17467_dupName_104_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x(MUX,17470)@126
    assign rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q or rightShiftStage0Idx1_uid17469_dupName_104_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_26_i_c_compmm_m988_q;
            1'b1 : rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17469_dupName_104_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x(MUX,17475)@126
    assign rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17474_dupName_104_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17471_dupName_104_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17474_dupName_104_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m991_vt_select_21(BITSELECT,13030)@126
    assign i_unnamed_c_compmm_m991_vt_select_21_b = rightShiftStage1_uid17476_dupName_104_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m991_vt_join(BITJOIN,13029)@126
    assign i_unnamed_c_compmm_m991_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m991_vt_select_21_b};

    // i_unnamed_c_compmm_m992_sel_x(BITSELECT,6259)@126
    assign i_unnamed_c_compmm_m992_sel_x_b = i_unnamed_c_compmm_m991_vt_join_q[15:0];

    // i_unnamed_c_compmm_m993_BitSelect_for_a(BITSELECT,28870)@126
    assign i_unnamed_c_compmm_m993_BitSelect_for_a_b = i_unnamed_c_compmm_m992_sel_x_b[0:0];

    // i_unnamed_c_compmm_m993_join(BITJOIN,28871)@126
    assign i_unnamed_c_compmm_m993_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m993_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m993_vt_select_0(BITSELECT,13035)@126
    assign i_unnamed_c_compmm_m993_vt_select_0_b = i_unnamed_c_compmm_m993_join_q[0:0];

    // redist2_i_unnamed_c_compmm_m993_vt_select_0_b_1(DELAY,29130)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist2_i_unnamed_c_compmm_m993_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m993_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m993_vt_join(BITJOIN,13034)@127
    assign i_unnamed_c_compmm_m993_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist2_i_unnamed_c_compmm_m993_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_26_c_compmm_m994(ADD,7077)@127
    assign i_add_i_i_i_i_i126_i_26_c_compmm_m994_a = {1'b0, i_unnamed_c_compmm_m993_vt_join_q};
    assign i_add_i_i_i_i_i126_i_26_c_compmm_m994_b = {1'b0, redist1095_i_conv_i_i_i_i97_i_26_c_compmm_m990_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_26_c_compmm_m994_o = $unsigned(i_add_i_i_i_i_i126_i_26_c_compmm_m994_a) + $unsigned(i_add_i_i_i_i_i126_i_26_c_compmm_m994_b);
    assign i_add_i_i_i_i_i126_i_26_c_compmm_m994_q = i_add_i_i_i_i_i126_i_26_c_compmm_m994_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_26_c_compmm_m994_sel_x(BITSELECT,2091)@127
    assign bgTrunc_i_add_i_i_i_i_i126_i_26_c_compmm_m994_sel_x_b = i_add_i_i_i_i_i126_i_26_c_compmm_m994_q[15:0];

    // i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_sel_x(BITSELECT,3624)@127
    assign i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_26_c_compmm_m994_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_select_15(BITSELECT,7607)@127
    assign i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_select_15_b = i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_join(BITJOIN,7606)@127
    assign i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_select_15_b};

    // leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(MUX,24604)@127
    assign leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_join_q or leftShiftStage0Idx1_uid24603_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_27_c_compmm_m1014_vt_join_q;
            1'b1 : leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24603_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(MUX,24609)@127
    assign leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s or leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24608_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = leftShiftStage0_uid24605_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24608_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x(MUX,24614)@127
    assign leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s or leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24613_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = leftShiftStage1_uid24610_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24613_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28(BITSELECT,9598)@127
    assign i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28_b = leftShiftStage2_uid24615_i_shl_i_i_i_i_i77_i_27_c_compmm_m0_shift_x_q[28:13];

    // redist456_i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28_b_1(DELAY,29584)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist456_i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_join(BITJOIN,9597)@128
    assign i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_join_q = {redist456_i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma(CHAINMULTADD,29046)@122 + 5
    // out q@128
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_6474_c_compmm_m202_out_dest_data_out_56_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_6473_c_compmm_m203_out_dest_data_out_55_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ch[0] <= redist558_sync_together4364_aunroll_x_in_c1_eni5_56_tpl_54_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ch[1] <= redist557_sync_together4364_aunroll_x_in_c1_eni5_55_tpl_54_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016(ADD,8866)@128
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_27_i_c_compmm_m1011_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_27_i_c_compmm_m1013_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_27_i_c_compmm_m1012_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_27_c_compmm_m1015_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_o[33:0];

    // rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x(MUX,17514)@128
    assign rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q or rightShiftStage0Idx1_uid17513_dupName_107_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q;
            1'b1 : rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17513_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x(MUX,17519)@128
    assign rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17518_dupName_107_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17515_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17518_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x(MUX,17524)@128
    assign rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17523_dupName_107_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17520_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17523_dupName_107_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1017_vt_select_20(BITSELECT,10233)@128
    assign i_unnamed_c_compmm_m1017_vt_select_20_b = rightShiftStage2_uid17525_dupName_107_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1017_vt_join(BITJOIN,10232)@128
    assign i_unnamed_c_compmm_m1017_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1017_vt_select_20_b};

    // i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x(BITSELECT,3495)@128
    assign i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x_b = i_unnamed_c_compmm_m1017_vt_join_q[15:0];

    // redist1094_i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x_b_1(DELAY,30222)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1094_i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17534_dupName_108_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17533)@128
    assign rightShiftStage1Idx1Rng8_uid17534_dupName_108_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17536_dupName_108_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17535)@128
    assign rightShiftStage1Idx1_uid17536_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17534_dupName_108_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17529_dupName_108_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17528)@128
    assign rightShiftStage0Idx1Rng4_uid17529_dupName_108_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q[33:4];

    // rightShiftStage0Idx1_uid17531_dupName_108_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17530)@128
    assign rightShiftStage0Idx1_uid17531_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17529_dupName_108_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x(MUX,17532)@128
    assign rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q or rightShiftStage0Idx1_uid17531_dupName_108_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_27_i_c_compmm_m1016_q;
            1'b1 : rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17531_dupName_108_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x(MUX,17537)@128
    assign rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17536_dupName_108_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17533_dupName_108_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17536_dupName_108_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1019_vt_select_21(BITSELECT,10236)@128
    assign i_unnamed_c_compmm_m1019_vt_select_21_b = rightShiftStage1_uid17538_dupName_108_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1019_vt_join(BITJOIN,10235)@128
    assign i_unnamed_c_compmm_m1019_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1019_vt_select_21_b};

    // i_unnamed_c_compmm_m1020_sel_x(BITSELECT,6005)@128
    assign i_unnamed_c_compmm_m1020_sel_x_b = i_unnamed_c_compmm_m1019_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1021_BitSelect_for_a(BITSELECT,28362)@128
    assign i_unnamed_c_compmm_m1021_BitSelect_for_a_b = i_unnamed_c_compmm_m1020_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1021_join(BITJOIN,28363)@128
    assign i_unnamed_c_compmm_m1021_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1021_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1021_vt_select_0(BITSELECT,10241)@128
    assign i_unnamed_c_compmm_m1021_vt_select_0_b = i_unnamed_c_compmm_m1021_join_q[0:0];

    // redist253_i_unnamed_c_compmm_m1021_vt_select_0_b_1(DELAY,29381)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist253_i_unnamed_c_compmm_m1021_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1021_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1021_vt_join(BITJOIN,10240)@129
    assign i_unnamed_c_compmm_m1021_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist253_i_unnamed_c_compmm_m1021_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_27_c_compmm_m1022(ADD,7078)@129
    assign i_add_i_i_i_i_i126_i_27_c_compmm_m1022_a = {1'b0, i_unnamed_c_compmm_m1021_vt_join_q};
    assign i_add_i_i_i_i_i126_i_27_c_compmm_m1022_b = {1'b0, redist1094_i_conv_i_i_i_i97_i_27_c_compmm_m1018_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_27_c_compmm_m1022_o = $unsigned(i_add_i_i_i_i_i126_i_27_c_compmm_m1022_a) + $unsigned(i_add_i_i_i_i_i126_i_27_c_compmm_m1022_b);
    assign i_add_i_i_i_i_i126_i_27_c_compmm_m1022_q = i_add_i_i_i_i_i126_i_27_c_compmm_m1022_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_27_c_compmm_m1022_sel_x(BITSELECT,2092)@129
    assign bgTrunc_i_add_i_i_i_i_i126_i_27_c_compmm_m1022_sel_x_b = i_add_i_i_i_i_i126_i_27_c_compmm_m1022_q[15:0];

    // i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_sel_x(BITSELECT,3625)@129
    assign i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_27_c_compmm_m1022_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_select_15(BITSELECT,7611)@129
    assign i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_select_15_b = i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_join(BITJOIN,7610)@129
    assign i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_select_15_b};

    // leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(MUX,24622)@129
    assign leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_join_q or leftShiftStage0Idx1_uid24621_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_28_c_compmm_m1042_vt_join_q;
            1'b1 : leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24621_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(MUX,24627)@129
    assign leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s or leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24626_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = leftShiftStage0_uid24623_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24626_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x(MUX,24632)@129
    assign leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s or leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24631_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = leftShiftStage1_uid24628_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24631_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28(BITSELECT,9601)@129
    assign i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28_b = leftShiftStage2_uid24633_i_shl_i_i_i_i_i77_i_28_c_compmm_m0_shift_x_q[28:13];

    // redist455_i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28_b_1(DELAY,29583)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist455_i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_join(BITJOIN,9600)@130
    assign i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_join_q = {redist455_i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma(CHAINMULTADD,29047)@124 + 5
    // out q@130
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_6476_c_compmm_m200_out_dest_data_out_58_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_6475_c_compmm_m201_out_dest_data_out_57_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ch[0] <= redist560_sync_together4364_aunroll_x_in_c1_eni5_58_tpl_56_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ch[1] <= redist559_sync_together4364_aunroll_x_in_c1_eni5_57_tpl_56_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044(ADD,8867)@130
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_28_i_c_compmm_m1039_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_28_i_c_compmm_m1041_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_28_i_c_compmm_m1040_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_28_c_compmm_m1043_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_o[33:0];

    // rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x(MUX,17576)@130
    assign rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q or rightShiftStage0Idx1_uid17575_dupName_111_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q;
            1'b1 : rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17575_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x(MUX,17581)@130
    assign rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17580_dupName_111_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17577_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17580_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x(MUX,17586)@130
    assign rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17585_dupName_111_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17582_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17585_dupName_111_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1045_vt_select_20(BITSELECT,10255)@130
    assign i_unnamed_c_compmm_m1045_vt_select_20_b = rightShiftStage2_uid17587_dupName_111_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1045_vt_join(BITJOIN,10254)@130
    assign i_unnamed_c_compmm_m1045_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1045_vt_select_20_b};

    // i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x(BITSELECT,3496)@130
    assign i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x_b = i_unnamed_c_compmm_m1045_vt_join_q[15:0];

    // redist1093_i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x_b_1(DELAY,30221)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1093_i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17596_dupName_112_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17595)@130
    assign rightShiftStage1Idx1Rng8_uid17596_dupName_112_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17598_dupName_112_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17597)@130
    assign rightShiftStage1Idx1_uid17598_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17596_dupName_112_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17591_dupName_112_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17590)@130
    assign rightShiftStage0Idx1Rng4_uid17591_dupName_112_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q[33:4];

    // rightShiftStage0Idx1_uid17593_dupName_112_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17592)@130
    assign rightShiftStage0Idx1_uid17593_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17591_dupName_112_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x(MUX,17594)@130
    assign rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q or rightShiftStage0Idx1_uid17593_dupName_112_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_28_i_c_compmm_m1044_q;
            1'b1 : rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17593_dupName_112_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x(MUX,17599)@130
    assign rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17598_dupName_112_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17595_dupName_112_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17598_dupName_112_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1047_vt_select_21(BITSELECT,10258)@130
    assign i_unnamed_c_compmm_m1047_vt_select_21_b = rightShiftStage1_uid17600_dupName_112_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1047_vt_join(BITJOIN,10257)@130
    assign i_unnamed_c_compmm_m1047_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1047_vt_select_21_b};

    // i_unnamed_c_compmm_m1048_sel_x(BITSELECT,6007)@130
    assign i_unnamed_c_compmm_m1048_sel_x_b = i_unnamed_c_compmm_m1047_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1049_BitSelect_for_a(BITSELECT,28366)@130
    assign i_unnamed_c_compmm_m1049_BitSelect_for_a_b = i_unnamed_c_compmm_m1048_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1049_join(BITJOIN,28367)@130
    assign i_unnamed_c_compmm_m1049_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1049_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1049_vt_select_0(BITSELECT,10263)@130
    assign i_unnamed_c_compmm_m1049_vt_select_0_b = i_unnamed_c_compmm_m1049_join_q[0:0];

    // redist251_i_unnamed_c_compmm_m1049_vt_select_0_b_1(DELAY,29379)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist251_i_unnamed_c_compmm_m1049_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1049_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1049_vt_join(BITJOIN,10262)@131
    assign i_unnamed_c_compmm_m1049_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist251_i_unnamed_c_compmm_m1049_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_28_c_compmm_m1050(ADD,7079)@131
    assign i_add_i_i_i_i_i126_i_28_c_compmm_m1050_a = {1'b0, i_unnamed_c_compmm_m1049_vt_join_q};
    assign i_add_i_i_i_i_i126_i_28_c_compmm_m1050_b = {1'b0, redist1093_i_conv_i_i_i_i97_i_28_c_compmm_m1046_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_28_c_compmm_m1050_o = $unsigned(i_add_i_i_i_i_i126_i_28_c_compmm_m1050_a) + $unsigned(i_add_i_i_i_i_i126_i_28_c_compmm_m1050_b);
    assign i_add_i_i_i_i_i126_i_28_c_compmm_m1050_q = i_add_i_i_i_i_i126_i_28_c_compmm_m1050_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_28_c_compmm_m1050_sel_x(BITSELECT,2093)@131
    assign bgTrunc_i_add_i_i_i_i_i126_i_28_c_compmm_m1050_sel_x_b = i_add_i_i_i_i_i126_i_28_c_compmm_m1050_q[15:0];

    // i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_sel_x(BITSELECT,3626)@131
    assign i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_28_c_compmm_m1050_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_select_15(BITSELECT,7615)@131
    assign i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_select_15_b = i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_join(BITJOIN,7614)@131
    assign i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_select_15_b};

    // leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(MUX,24640)@131
    assign leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_join_q or leftShiftStage0Idx1_uid24639_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_29_c_compmm_m1070_vt_join_q;
            1'b1 : leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24639_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(MUX,24645)@131
    assign leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s or leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24644_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = leftShiftStage0_uid24641_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24644_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x(MUX,24650)@131
    assign leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s or leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24649_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = leftShiftStage1_uid24646_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24649_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28(BITSELECT,9604)@131
    assign i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28_b = leftShiftStage2_uid24651_i_shl_i_i_i_i_i77_i_29_c_compmm_m0_shift_x_q[28:13];

    // redist454_i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28_b_1(DELAY,29582)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist454_i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_join(BITJOIN,9603)@132
    assign i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_join_q = {redist454_i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma(CHAINMULTADD,29048)@126 + 5
    // out q@132
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_6478_c_compmm_m198_out_dest_data_out_60_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_6477_c_compmm_m199_out_dest_data_out_59_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ch[0] <= redist562_sync_together4364_aunroll_x_in_c1_eni5_60_tpl_58_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ch[1] <= redist561_sync_together4364_aunroll_x_in_c1_eni5_59_tpl_58_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072(ADD,8868)@132
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_29_i_c_compmm_m1067_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_29_i_c_compmm_m1069_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_29_i_c_compmm_m1068_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_29_c_compmm_m1071_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_o[33:0];

    // rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x(MUX,17638)@132
    assign rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q or rightShiftStage0Idx1_uid17637_dupName_115_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q;
            1'b1 : rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17637_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x(MUX,17643)@132
    assign rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17642_dupName_115_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17639_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17642_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x(MUX,17648)@132
    assign rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17647_dupName_115_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17644_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17647_dupName_115_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1073_vt_select_20(BITSELECT,10277)@132
    assign i_unnamed_c_compmm_m1073_vt_select_20_b = rightShiftStage2_uid17649_dupName_115_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1073_vt_join(BITJOIN,10276)@132
    assign i_unnamed_c_compmm_m1073_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1073_vt_select_20_b};

    // i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x(BITSELECT,3497)@132
    assign i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x_b = i_unnamed_c_compmm_m1073_vt_join_q[15:0];

    // redist1092_i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x_b_1(DELAY,30220)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1092_i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17658_dupName_116_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17657)@132
    assign rightShiftStage1Idx1Rng8_uid17658_dupName_116_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17660_dupName_116_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17659)@132
    assign rightShiftStage1Idx1_uid17660_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17658_dupName_116_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17653_dupName_116_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17652)@132
    assign rightShiftStage0Idx1Rng4_uid17653_dupName_116_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q[33:4];

    // rightShiftStage0Idx1_uid17655_dupName_116_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17654)@132
    assign rightShiftStage0Idx1_uid17655_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17653_dupName_116_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x(MUX,17656)@132
    assign rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q or rightShiftStage0Idx1_uid17655_dupName_116_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_29_i_c_compmm_m1072_q;
            1'b1 : rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17655_dupName_116_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x(MUX,17661)@132
    assign rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17660_dupName_116_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17657_dupName_116_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17660_dupName_116_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1075_vt_select_21(BITSELECT,10280)@132
    assign i_unnamed_c_compmm_m1075_vt_select_21_b = rightShiftStage1_uid17662_dupName_116_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1075_vt_join(BITJOIN,10279)@132
    assign i_unnamed_c_compmm_m1075_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1075_vt_select_21_b};

    // i_unnamed_c_compmm_m1076_sel_x(BITSELECT,6009)@132
    assign i_unnamed_c_compmm_m1076_sel_x_b = i_unnamed_c_compmm_m1075_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1077_BitSelect_for_a(BITSELECT,28370)@132
    assign i_unnamed_c_compmm_m1077_BitSelect_for_a_b = i_unnamed_c_compmm_m1076_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1077_join(BITJOIN,28371)@132
    assign i_unnamed_c_compmm_m1077_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1077_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1077_vt_select_0(BITSELECT,10285)@132
    assign i_unnamed_c_compmm_m1077_vt_select_0_b = i_unnamed_c_compmm_m1077_join_q[0:0];

    // redist249_i_unnamed_c_compmm_m1077_vt_select_0_b_1(DELAY,29377)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist249_i_unnamed_c_compmm_m1077_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1077_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1077_vt_join(BITJOIN,10284)@133
    assign i_unnamed_c_compmm_m1077_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist249_i_unnamed_c_compmm_m1077_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_29_c_compmm_m1078(ADD,7080)@133
    assign i_add_i_i_i_i_i126_i_29_c_compmm_m1078_a = {1'b0, i_unnamed_c_compmm_m1077_vt_join_q};
    assign i_add_i_i_i_i_i126_i_29_c_compmm_m1078_b = {1'b0, redist1092_i_conv_i_i_i_i97_i_29_c_compmm_m1074_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_29_c_compmm_m1078_o = $unsigned(i_add_i_i_i_i_i126_i_29_c_compmm_m1078_a) + $unsigned(i_add_i_i_i_i_i126_i_29_c_compmm_m1078_b);
    assign i_add_i_i_i_i_i126_i_29_c_compmm_m1078_q = i_add_i_i_i_i_i126_i_29_c_compmm_m1078_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_29_c_compmm_m1078_sel_x(BITSELECT,2094)@133
    assign bgTrunc_i_add_i_i_i_i_i126_i_29_c_compmm_m1078_sel_x_b = i_add_i_i_i_i_i126_i_29_c_compmm_m1078_q[15:0];

    // i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_sel_x(BITSELECT,3628)@133
    assign i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_29_c_compmm_m1078_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_select_15(BITSELECT,7623)@133
    assign i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_select_15_b = i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_join(BITJOIN,7622)@133
    assign i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_select_15_b};

    // leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(MUX,24676)@133
    assign leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_join_q or leftShiftStage0Idx1_uid24675_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_30_c_compmm_m1098_vt_join_q;
            1'b1 : leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24675_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(MUX,24681)@133
    assign leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s or leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24680_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = leftShiftStage0_uid24677_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24680_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x(MUX,24686)@133
    assign leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s or leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24685_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = leftShiftStage1_uid24682_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24685_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28(BITSELECT,9610)@133
    assign i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28_b = leftShiftStage2_uid24687_i_shl_i_i_i_i_i77_i_30_c_compmm_m0_shift_x_q[28:13];

    // redist452_i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28_b_1(DELAY,29580)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist452_i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_join(BITJOIN,9609)@134
    assign i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_join_q = {redist452_i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma(CHAINMULTADD,29050)@128 + 5
    // out q@134
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_6480_c_compmm_m196_out_dest_data_out_62_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_6479_c_compmm_m197_out_dest_data_out_61_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ch[0] <= redist564_sync_together4364_aunroll_x_in_c1_eni5_62_tpl_60_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ch[1] <= redist563_sync_together4364_aunroll_x_in_c1_eni5_61_tpl_60_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100(ADD,8870)@134
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_30_i_c_compmm_m1095_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_30_i_c_compmm_m1097_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_30_i_c_compmm_m1096_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_30_c_compmm_m1099_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_o[33:0];

    // rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x(MUX,17700)@134
    assign rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q or rightShiftStage0Idx1_uid17699_dupName_119_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q;
            1'b1 : rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17699_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x(MUX,17705)@134
    assign rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17704_dupName_119_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17701_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17704_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x(MUX,17710)@134
    assign rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17709_dupName_119_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17706_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17709_dupName_119_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1101_vt_select_20(BITSELECT,10299)@134
    assign i_unnamed_c_compmm_m1101_vt_select_20_b = rightShiftStage2_uid17711_dupName_119_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1101_vt_join(BITJOIN,10298)@134
    assign i_unnamed_c_compmm_m1101_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1101_vt_select_20_b};

    // i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x(BITSELECT,3499)@134
    assign i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x_b = i_unnamed_c_compmm_m1101_vt_join_q[15:0];

    // redist1090_i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x_b_1(DELAY,30218)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1090_i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17720_dupName_120_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17719)@134
    assign rightShiftStage1Idx1Rng8_uid17720_dupName_120_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17722_dupName_120_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17721)@134
    assign rightShiftStage1Idx1_uid17722_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17720_dupName_120_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17715_dupName_120_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17714)@134
    assign rightShiftStage0Idx1Rng4_uid17715_dupName_120_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q[33:4];

    // rightShiftStage0Idx1_uid17717_dupName_120_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17716)@134
    assign rightShiftStage0Idx1_uid17717_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17715_dupName_120_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x(MUX,17718)@134
    assign rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q or rightShiftStage0Idx1_uid17717_dupName_120_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_30_i_c_compmm_m1100_q;
            1'b1 : rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17717_dupName_120_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x(MUX,17723)@134
    assign rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17722_dupName_120_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17719_dupName_120_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17722_dupName_120_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1103_vt_select_21(BITSELECT,10302)@134
    assign i_unnamed_c_compmm_m1103_vt_select_21_b = rightShiftStage1_uid17724_dupName_120_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1103_vt_join(BITJOIN,10301)@134
    assign i_unnamed_c_compmm_m1103_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1103_vt_select_21_b};

    // i_unnamed_c_compmm_m1104_sel_x(BITSELECT,6011)@134
    assign i_unnamed_c_compmm_m1104_sel_x_b = i_unnamed_c_compmm_m1103_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1105_BitSelect_for_a(BITSELECT,28374)@134
    assign i_unnamed_c_compmm_m1105_BitSelect_for_a_b = i_unnamed_c_compmm_m1104_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1105_join(BITJOIN,28375)@134
    assign i_unnamed_c_compmm_m1105_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1105_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1105_vt_select_0(BITSELECT,10307)@134
    assign i_unnamed_c_compmm_m1105_vt_select_0_b = i_unnamed_c_compmm_m1105_join_q[0:0];

    // redist247_i_unnamed_c_compmm_m1105_vt_select_0_b_1(DELAY,29375)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist247_i_unnamed_c_compmm_m1105_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1105_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1105_vt_join(BITJOIN,10306)@135
    assign i_unnamed_c_compmm_m1105_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist247_i_unnamed_c_compmm_m1105_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_30_c_compmm_m1106(ADD,7082)@135
    assign i_add_i_i_i_i_i126_i_30_c_compmm_m1106_a = {1'b0, i_unnamed_c_compmm_m1105_vt_join_q};
    assign i_add_i_i_i_i_i126_i_30_c_compmm_m1106_b = {1'b0, redist1090_i_conv_i_i_i_i97_i_30_c_compmm_m1102_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_30_c_compmm_m1106_o = $unsigned(i_add_i_i_i_i_i126_i_30_c_compmm_m1106_a) + $unsigned(i_add_i_i_i_i_i126_i_30_c_compmm_m1106_b);
    assign i_add_i_i_i_i_i126_i_30_c_compmm_m1106_q = i_add_i_i_i_i_i126_i_30_c_compmm_m1106_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_30_c_compmm_m1106_sel_x(BITSELECT,2096)@135
    assign bgTrunc_i_add_i_i_i_i_i126_i_30_c_compmm_m1106_sel_x_b = i_add_i_i_i_i_i126_i_30_c_compmm_m1106_q[15:0];

    // i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_sel_x(BITSELECT,3629)@135
    assign i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_30_c_compmm_m1106_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_select_15(BITSELECT,7627)@135
    assign i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_select_15_b = i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_join(BITJOIN,7626)@135
    assign i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_select_15_b};

    // leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(MUX,24694)@135
    assign leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_join_q or leftShiftStage0Idx1_uid24693_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_31_c_compmm_m1126_vt_join_q;
            1'b1 : leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24693_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(MUX,24699)@135
    assign leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s or leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24698_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = leftShiftStage0_uid24695_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24698_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x(MUX,24704)@135
    assign leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s or leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24703_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = leftShiftStage1_uid24700_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24703_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28(BITSELECT,9613)@135
    assign i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28_b = leftShiftStage2_uid24705_i_shl_i_i_i_i_i77_i_31_c_compmm_m0_shift_x_q[28:13];

    // redist451_i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28_b_1(DELAY,29579)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist451_i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_join(BITJOIN,9612)@136
    assign i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_join_q = {redist451_i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma(CHAINMULTADD,29051)@130 + 5
    // out q@136
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_6482_c_compmm_m194_out_dest_data_out_64_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_6481_c_compmm_m195_out_dest_data_out_63_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ch[0] <= redist566_sync_together4364_aunroll_x_in_c1_eni5_64_tpl_62_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ch[1] <= redist565_sync_together4364_aunroll_x_in_c1_eni5_63_tpl_62_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128(ADD,8871)@136
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_31_i_c_compmm_m1123_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_31_i_c_compmm_m1125_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_31_i_c_compmm_m1124_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_31_c_compmm_m1127_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_o[33:0];

    // rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x(MUX,17762)@136
    assign rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q or rightShiftStage0Idx1_uid17761_dupName_123_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q;
            1'b1 : rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17761_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x(MUX,17767)@136
    assign rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17766_dupName_123_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17763_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17766_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x(MUX,17772)@136
    assign rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17771_dupName_123_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17768_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17771_dupName_123_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1129_vt_select_20(BITSELECT,10321)@136
    assign i_unnamed_c_compmm_m1129_vt_select_20_b = rightShiftStage2_uid17773_dupName_123_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1129_vt_join(BITJOIN,10320)@136
    assign i_unnamed_c_compmm_m1129_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1129_vt_select_20_b};

    // i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x(BITSELECT,3500)@136
    assign i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x_b = i_unnamed_c_compmm_m1129_vt_join_q[15:0];

    // redist1089_i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x_b_1(DELAY,30217)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1089_i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17782_dupName_124_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17781)@136
    assign rightShiftStage1Idx1Rng8_uid17782_dupName_124_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17784_dupName_124_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17783)@136
    assign rightShiftStage1Idx1_uid17784_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17782_dupName_124_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17777_dupName_124_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17776)@136
    assign rightShiftStage0Idx1Rng4_uid17777_dupName_124_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q[33:4];

    // rightShiftStage0Idx1_uid17779_dupName_124_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17778)@136
    assign rightShiftStage0Idx1_uid17779_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17777_dupName_124_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x(MUX,17780)@136
    assign rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q or rightShiftStage0Idx1_uid17779_dupName_124_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_31_i_c_compmm_m1128_q;
            1'b1 : rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17779_dupName_124_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x(MUX,17785)@136
    assign rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17784_dupName_124_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17781_dupName_124_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17784_dupName_124_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1131_vt_select_21(BITSELECT,10324)@136
    assign i_unnamed_c_compmm_m1131_vt_select_21_b = rightShiftStage1_uid17786_dupName_124_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1131_vt_join(BITJOIN,10323)@136
    assign i_unnamed_c_compmm_m1131_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1131_vt_select_21_b};

    // i_unnamed_c_compmm_m1132_sel_x(BITSELECT,6013)@136
    assign i_unnamed_c_compmm_m1132_sel_x_b = i_unnamed_c_compmm_m1131_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1133_BitSelect_for_a(BITSELECT,28378)@136
    assign i_unnamed_c_compmm_m1133_BitSelect_for_a_b = i_unnamed_c_compmm_m1132_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1133_join(BITJOIN,28379)@136
    assign i_unnamed_c_compmm_m1133_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1133_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1133_vt_select_0(BITSELECT,10329)@136
    assign i_unnamed_c_compmm_m1133_vt_select_0_b = i_unnamed_c_compmm_m1133_join_q[0:0];

    // redist245_i_unnamed_c_compmm_m1133_vt_select_0_b_1(DELAY,29373)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist245_i_unnamed_c_compmm_m1133_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1133_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1133_vt_join(BITJOIN,10328)@137
    assign i_unnamed_c_compmm_m1133_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist245_i_unnamed_c_compmm_m1133_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_31_c_compmm_m1134(ADD,7083)@137
    assign i_add_i_i_i_i_i126_i_31_c_compmm_m1134_a = {1'b0, i_unnamed_c_compmm_m1133_vt_join_q};
    assign i_add_i_i_i_i_i126_i_31_c_compmm_m1134_b = {1'b0, redist1089_i_conv_i_i_i_i97_i_31_c_compmm_m1130_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_31_c_compmm_m1134_o = $unsigned(i_add_i_i_i_i_i126_i_31_c_compmm_m1134_a) + $unsigned(i_add_i_i_i_i_i126_i_31_c_compmm_m1134_b);
    assign i_add_i_i_i_i_i126_i_31_c_compmm_m1134_q = i_add_i_i_i_i_i126_i_31_c_compmm_m1134_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_31_c_compmm_m1134_sel_x(BITSELECT,2097)@137
    assign bgTrunc_i_add_i_i_i_i_i126_i_31_c_compmm_m1134_sel_x_b = i_add_i_i_i_i_i126_i_31_c_compmm_m1134_q[15:0];

    // i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_sel_x(BITSELECT,3630)@137
    assign i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_31_c_compmm_m1134_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_select_15(BITSELECT,7631)@137
    assign i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_select_15_b = i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_join(BITJOIN,7630)@137
    assign i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_select_15_b};

    // leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(MUX,24712)@137
    assign leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_join_q or leftShiftStage0Idx1_uid24711_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_32_c_compmm_m1155_vt_join_q;
            1'b1 : leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24711_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(MUX,24717)@137
    assign leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s or leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24716_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = leftShiftStage0_uid24713_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24716_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x(MUX,24722)@137
    assign leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s or leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24721_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = leftShiftStage1_uid24718_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24721_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28(BITSELECT,9616)@137
    assign i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28_b = leftShiftStage2_uid24723_i_shl_i_i_i_i_i77_i_32_c_compmm_m0_shift_x_q[28:13];

    // redist450_i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28_b_1(DELAY,29578)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist450_i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_join(BITJOIN,9615)@138
    assign i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_join_q = {redist450_i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma(CHAINMULTADD,29052)@132 + 5
    // out q@138
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_6584_c_compmm_m192_out_dest_data_out_66_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_6583_c_compmm_m193_out_dest_data_out_65_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ch[0] <= redist568_sync_together4364_aunroll_x_in_c1_eni5_66_tpl_64_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ch[1] <= redist567_sync_together4364_aunroll_x_in_c1_eni5_65_tpl_64_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157(ADD,8872)@138
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_32_i_c_compmm_m1152_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_32_i_c_compmm_m1154_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_32_i_c_compmm_m1153_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_32_c_compmm_m1156_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_o[33:0];

    // rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x(MUX,17824)@138
    assign rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q or rightShiftStage0Idx1_uid17823_dupName_127_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q;
            1'b1 : rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17823_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x(MUX,17829)@138
    assign rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17828_dupName_127_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17825_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17828_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x(MUX,17834)@138
    assign rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17833_dupName_127_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17830_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17833_dupName_127_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1158_vt_select_20(BITSELECT,10343)@138
    assign i_unnamed_c_compmm_m1158_vt_select_20_b = rightShiftStage2_uid17835_dupName_127_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1158_vt_join(BITJOIN,10342)@138
    assign i_unnamed_c_compmm_m1158_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1158_vt_select_20_b};

    // i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x(BITSELECT,3501)@138
    assign i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x_b = i_unnamed_c_compmm_m1158_vt_join_q[15:0];

    // redist1088_i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x_b_1(DELAY,30216)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1088_i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17844_dupName_128_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17843)@138
    assign rightShiftStage1Idx1Rng8_uid17844_dupName_128_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17846_dupName_128_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17845)@138
    assign rightShiftStage1Idx1_uid17846_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17844_dupName_128_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17839_dupName_128_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17838)@138
    assign rightShiftStage0Idx1Rng4_uid17839_dupName_128_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q[33:4];

    // rightShiftStage0Idx1_uid17841_dupName_128_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17840)@138
    assign rightShiftStage0Idx1_uid17841_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17839_dupName_128_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x(MUX,17842)@138
    assign rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q or rightShiftStage0Idx1_uid17841_dupName_128_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_32_i_c_compmm_m1157_q;
            1'b1 : rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17841_dupName_128_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x(MUX,17847)@138
    assign rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17846_dupName_128_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17843_dupName_128_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17846_dupName_128_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1160_vt_select_21(BITSELECT,10346)@138
    assign i_unnamed_c_compmm_m1160_vt_select_21_b = rightShiftStage1_uid17848_dupName_128_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1160_vt_join(BITJOIN,10345)@138
    assign i_unnamed_c_compmm_m1160_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1160_vt_select_21_b};

    // i_unnamed_c_compmm_m1161_sel_x(BITSELECT,6015)@138
    assign i_unnamed_c_compmm_m1161_sel_x_b = i_unnamed_c_compmm_m1160_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1162_BitSelect_for_a(BITSELECT,28382)@138
    assign i_unnamed_c_compmm_m1162_BitSelect_for_a_b = i_unnamed_c_compmm_m1161_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1162_join(BITJOIN,28383)@138
    assign i_unnamed_c_compmm_m1162_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1162_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1162_vt_select_0(BITSELECT,10351)@138
    assign i_unnamed_c_compmm_m1162_vt_select_0_b = i_unnamed_c_compmm_m1162_join_q[0:0];

    // redist243_i_unnamed_c_compmm_m1162_vt_select_0_b_1(DELAY,29371)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist243_i_unnamed_c_compmm_m1162_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1162_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1162_vt_join(BITJOIN,10350)@139
    assign i_unnamed_c_compmm_m1162_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist243_i_unnamed_c_compmm_m1162_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_32_c_compmm_m1163(ADD,7084)@139
    assign i_add_i_i_i_i_i126_i_32_c_compmm_m1163_a = {1'b0, i_unnamed_c_compmm_m1162_vt_join_q};
    assign i_add_i_i_i_i_i126_i_32_c_compmm_m1163_b = {1'b0, redist1088_i_conv_i_i_i_i97_i_32_c_compmm_m1159_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_32_c_compmm_m1163_o = $unsigned(i_add_i_i_i_i_i126_i_32_c_compmm_m1163_a) + $unsigned(i_add_i_i_i_i_i126_i_32_c_compmm_m1163_b);
    assign i_add_i_i_i_i_i126_i_32_c_compmm_m1163_q = i_add_i_i_i_i_i126_i_32_c_compmm_m1163_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_32_c_compmm_m1163_sel_x(BITSELECT,2098)@139
    assign bgTrunc_i_add_i_i_i_i_i126_i_32_c_compmm_m1163_sel_x_b = i_add_i_i_i_i_i126_i_32_c_compmm_m1163_q[15:0];

    // i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_sel_x(BITSELECT,3631)@139
    assign i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_32_c_compmm_m1163_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_select_15(BITSELECT,7635)@139
    assign i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_select_15_b = i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_join(BITJOIN,7634)@139
    assign i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_select_15_b};

    // leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(MUX,24730)@139
    assign leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_join_q or leftShiftStage0Idx1_uid24729_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_33_c_compmm_m1183_vt_join_q;
            1'b1 : leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24729_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(MUX,24735)@139
    assign leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s or leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24734_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = leftShiftStage0_uid24731_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24734_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x(MUX,24740)@139
    assign leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s or leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24739_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = leftShiftStage1_uid24736_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24739_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28(BITSELECT,9619)@139
    assign i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28_b = leftShiftStage2_uid24741_i_shl_i_i_i_i_i77_i_33_c_compmm_m0_shift_x_q[28:13];

    // redist449_i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28_b_1(DELAY,29577)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist449_i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_join(BITJOIN,9618)@140
    assign i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_join_q = {redist449_i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma(CHAINMULTADD,29053)@134 + 5
    // out q@140
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_6586_c_compmm_m190_out_dest_data_out_68_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_6585_c_compmm_m191_out_dest_data_out_67_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ch[0] <= redist570_sync_together4364_aunroll_x_in_c1_eni5_68_tpl_66_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ch[1] <= redist569_sync_together4364_aunroll_x_in_c1_eni5_67_tpl_66_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185(ADD,8873)@140
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_33_i_c_compmm_m1180_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_33_i_c_compmm_m1182_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_33_i_c_compmm_m1181_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_33_c_compmm_m1184_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_o[33:0];

    // rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x(MUX,17886)@140
    assign rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q or rightShiftStage0Idx1_uid17885_dupName_131_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q;
            1'b1 : rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17885_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x(MUX,17891)@140
    assign rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17890_dupName_131_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17887_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17890_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x(MUX,17896)@140
    assign rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17895_dupName_131_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17892_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17895_dupName_131_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1186_vt_select_20(BITSELECT,10365)@140
    assign i_unnamed_c_compmm_m1186_vt_select_20_b = rightShiftStage2_uid17897_dupName_131_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1186_vt_join(BITJOIN,10364)@140
    assign i_unnamed_c_compmm_m1186_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1186_vt_select_20_b};

    // i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x(BITSELECT,3502)@140
    assign i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x_b = i_unnamed_c_compmm_m1186_vt_join_q[15:0];

    // redist1087_i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x_b_1(DELAY,30215)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1087_i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17906_dupName_132_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17905)@140
    assign rightShiftStage1Idx1Rng8_uid17906_dupName_132_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17908_dupName_132_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17907)@140
    assign rightShiftStage1Idx1_uid17908_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17906_dupName_132_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17901_dupName_132_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17900)@140
    assign rightShiftStage0Idx1Rng4_uid17901_dupName_132_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q[33:4];

    // rightShiftStage0Idx1_uid17903_dupName_132_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17902)@140
    assign rightShiftStage0Idx1_uid17903_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17901_dupName_132_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x(MUX,17904)@140
    assign rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q or rightShiftStage0Idx1_uid17903_dupName_132_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_33_i_c_compmm_m1185_q;
            1'b1 : rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17903_dupName_132_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x(MUX,17909)@140
    assign rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17908_dupName_132_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17905_dupName_132_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17908_dupName_132_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1188_vt_select_21(BITSELECT,10368)@140
    assign i_unnamed_c_compmm_m1188_vt_select_21_b = rightShiftStage1_uid17910_dupName_132_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1188_vt_join(BITJOIN,10367)@140
    assign i_unnamed_c_compmm_m1188_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1188_vt_select_21_b};

    // i_unnamed_c_compmm_m1189_sel_x(BITSELECT,6017)@140
    assign i_unnamed_c_compmm_m1189_sel_x_b = i_unnamed_c_compmm_m1188_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1190_BitSelect_for_a(BITSELECT,28386)@140
    assign i_unnamed_c_compmm_m1190_BitSelect_for_a_b = i_unnamed_c_compmm_m1189_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1190_join(BITJOIN,28387)@140
    assign i_unnamed_c_compmm_m1190_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1190_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1190_vt_select_0(BITSELECT,10373)@140
    assign i_unnamed_c_compmm_m1190_vt_select_0_b = i_unnamed_c_compmm_m1190_join_q[0:0];

    // redist241_i_unnamed_c_compmm_m1190_vt_select_0_b_1(DELAY,29369)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist241_i_unnamed_c_compmm_m1190_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1190_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1190_vt_join(BITJOIN,10372)@141
    assign i_unnamed_c_compmm_m1190_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist241_i_unnamed_c_compmm_m1190_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_33_c_compmm_m1191(ADD,7085)@141
    assign i_add_i_i_i_i_i126_i_33_c_compmm_m1191_a = {1'b0, i_unnamed_c_compmm_m1190_vt_join_q};
    assign i_add_i_i_i_i_i126_i_33_c_compmm_m1191_b = {1'b0, redist1087_i_conv_i_i_i_i97_i_33_c_compmm_m1187_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_33_c_compmm_m1191_o = $unsigned(i_add_i_i_i_i_i126_i_33_c_compmm_m1191_a) + $unsigned(i_add_i_i_i_i_i126_i_33_c_compmm_m1191_b);
    assign i_add_i_i_i_i_i126_i_33_c_compmm_m1191_q = i_add_i_i_i_i_i126_i_33_c_compmm_m1191_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_33_c_compmm_m1191_sel_x(BITSELECT,2099)@141
    assign bgTrunc_i_add_i_i_i_i_i126_i_33_c_compmm_m1191_sel_x_b = i_add_i_i_i_i_i126_i_33_c_compmm_m1191_q[15:0];

    // i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_sel_x(BITSELECT,3632)@141
    assign i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_33_c_compmm_m1191_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_select_15(BITSELECT,7639)@141
    assign i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_select_15_b = i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_join(BITJOIN,7638)@141
    assign i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_select_15_b};

    // leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(MUX,24748)@141
    assign leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_join_q or leftShiftStage0Idx1_uid24747_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_34_c_compmm_m1211_vt_join_q;
            1'b1 : leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24747_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(MUX,24753)@141
    assign leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s or leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24752_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = leftShiftStage0_uid24749_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24752_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x(MUX,24758)@141
    assign leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s or leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24757_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = leftShiftStage1_uid24754_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24757_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28(BITSELECT,9622)@141
    assign i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28_b = leftShiftStage2_uid24759_i_shl_i_i_i_i_i77_i_34_c_compmm_m0_shift_x_q[28:13];

    // redist448_i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28_b_1(DELAY,29576)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist448_i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_join(BITJOIN,9621)@142
    assign i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_join_q = {redist448_i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma(CHAINMULTADD,29054)@136 + 5
    // out q@142
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_6588_c_compmm_m188_out_dest_data_out_70_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_6587_c_compmm_m189_out_dest_data_out_69_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ch[0] <= redist572_sync_together4364_aunroll_x_in_c1_eni5_70_tpl_68_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ch[1] <= redist571_sync_together4364_aunroll_x_in_c1_eni5_69_tpl_68_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213(ADD,8874)@142
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_34_i_c_compmm_m1208_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_34_i_c_compmm_m1210_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_34_i_c_compmm_m1209_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_34_c_compmm_m1212_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_o[33:0];

    // rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x(MUX,17948)@142
    assign rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q or rightShiftStage0Idx1_uid17947_dupName_135_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q;
            1'b1 : rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17947_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x(MUX,17953)@142
    assign rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17952_dupName_135_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17949_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17952_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x(MUX,17958)@142
    assign rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid17957_dupName_135_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid17954_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid17957_dupName_135_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1214_vt_select_20(BITSELECT,10387)@142
    assign i_unnamed_c_compmm_m1214_vt_select_20_b = rightShiftStage2_uid17959_dupName_135_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1214_vt_join(BITJOIN,10386)@142
    assign i_unnamed_c_compmm_m1214_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1214_vt_select_20_b};

    // i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x(BITSELECT,3503)@142
    assign i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x_b = i_unnamed_c_compmm_m1214_vt_join_q[15:0];

    // redist1086_i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x_b_1(DELAY,30214)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1086_i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid17968_dupName_136_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17967)@142
    assign rightShiftStage1Idx1Rng8_uid17968_dupName_136_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid17970_dupName_136_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17969)@142
    assign rightShiftStage1Idx1_uid17970_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid17968_dupName_136_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid17963_dupName_136_i_unnamed_c_compmm_m0_shift_x(BITSELECT,17962)@142
    assign rightShiftStage0Idx1Rng4_uid17963_dupName_136_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q[33:4];

    // rightShiftStage0Idx1_uid17965_dupName_136_i_unnamed_c_compmm_m0_shift_x(BITJOIN,17964)@142
    assign rightShiftStage0Idx1_uid17965_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid17963_dupName_136_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x(MUX,17966)@142
    assign rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q or rightShiftStage0Idx1_uid17965_dupName_136_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_34_i_c_compmm_m1213_q;
            1'b1 : rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid17965_dupName_136_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x(MUX,17971)@142
    assign rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid17970_dupName_136_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid17967_dupName_136_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid17970_dupName_136_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1216_vt_select_21(BITSELECT,10390)@142
    assign i_unnamed_c_compmm_m1216_vt_select_21_b = rightShiftStage1_uid17972_dupName_136_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1216_vt_join(BITJOIN,10389)@142
    assign i_unnamed_c_compmm_m1216_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1216_vt_select_21_b};

    // i_unnamed_c_compmm_m1217_sel_x(BITSELECT,6019)@142
    assign i_unnamed_c_compmm_m1217_sel_x_b = i_unnamed_c_compmm_m1216_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1218_BitSelect_for_a(BITSELECT,28390)@142
    assign i_unnamed_c_compmm_m1218_BitSelect_for_a_b = i_unnamed_c_compmm_m1217_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1218_join(BITJOIN,28391)@142
    assign i_unnamed_c_compmm_m1218_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1218_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1218_vt_select_0(BITSELECT,10395)@142
    assign i_unnamed_c_compmm_m1218_vt_select_0_b = i_unnamed_c_compmm_m1218_join_q[0:0];

    // redist239_i_unnamed_c_compmm_m1218_vt_select_0_b_1(DELAY,29367)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist239_i_unnamed_c_compmm_m1218_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1218_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1218_vt_join(BITJOIN,10394)@143
    assign i_unnamed_c_compmm_m1218_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist239_i_unnamed_c_compmm_m1218_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_34_c_compmm_m1219(ADD,7086)@143
    assign i_add_i_i_i_i_i126_i_34_c_compmm_m1219_a = {1'b0, i_unnamed_c_compmm_m1218_vt_join_q};
    assign i_add_i_i_i_i_i126_i_34_c_compmm_m1219_b = {1'b0, redist1086_i_conv_i_i_i_i97_i_34_c_compmm_m1215_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_34_c_compmm_m1219_o = $unsigned(i_add_i_i_i_i_i126_i_34_c_compmm_m1219_a) + $unsigned(i_add_i_i_i_i_i126_i_34_c_compmm_m1219_b);
    assign i_add_i_i_i_i_i126_i_34_c_compmm_m1219_q = i_add_i_i_i_i_i126_i_34_c_compmm_m1219_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_34_c_compmm_m1219_sel_x(BITSELECT,2100)@143
    assign bgTrunc_i_add_i_i_i_i_i126_i_34_c_compmm_m1219_sel_x_b = i_add_i_i_i_i_i126_i_34_c_compmm_m1219_q[15:0];

    // i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_sel_x(BITSELECT,3633)@143
    assign i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_34_c_compmm_m1219_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_select_15(BITSELECT,7643)@143
    assign i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_select_15_b = i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_join(BITJOIN,7642)@143
    assign i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_select_15_b};

    // leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(MUX,24766)@143
    assign leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_join_q or leftShiftStage0Idx1_uid24765_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_35_c_compmm_m1239_vt_join_q;
            1'b1 : leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24765_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(MUX,24771)@143
    assign leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s or leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24770_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = leftShiftStage0_uid24767_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24770_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x(MUX,24776)@143
    assign leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s or leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24775_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = leftShiftStage1_uid24772_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24775_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28(BITSELECT,9625)@143
    assign i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28_b = leftShiftStage2_uid24777_i_shl_i_i_i_i_i77_i_35_c_compmm_m0_shift_x_q[28:13];

    // redist447_i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28_b_1(DELAY,29575)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist447_i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_join(BITJOIN,9624)@144
    assign i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_join_q = {redist447_i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma(CHAINMULTADD,29055)@138 + 5
    // out q@144
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_6590_c_compmm_m186_out_dest_data_out_72_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_6589_c_compmm_m187_out_dest_data_out_71_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ch[0] <= redist574_sync_together4364_aunroll_x_in_c1_eni5_72_tpl_70_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ch[1] <= redist573_sync_together4364_aunroll_x_in_c1_eni5_71_tpl_70_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241(ADD,8875)@144
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_35_i_c_compmm_m1236_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_35_i_c_compmm_m1238_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_35_i_c_compmm_m1237_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_35_c_compmm_m1240_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_o[33:0];

    // rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x(MUX,18010)@144
    assign rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q or rightShiftStage0Idx1_uid18009_dupName_139_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q;
            1'b1 : rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18009_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x(MUX,18015)@144
    assign rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18014_dupName_139_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18011_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18014_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x(MUX,18020)@144
    assign rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18019_dupName_139_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18016_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18019_dupName_139_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1242_vt_select_20(BITSELECT,10409)@144
    assign i_unnamed_c_compmm_m1242_vt_select_20_b = rightShiftStage2_uid18021_dupName_139_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1242_vt_join(BITJOIN,10408)@144
    assign i_unnamed_c_compmm_m1242_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1242_vt_select_20_b};

    // i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x(BITSELECT,3504)@144
    assign i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x_b = i_unnamed_c_compmm_m1242_vt_join_q[15:0];

    // redist1085_i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x_b_1(DELAY,30213)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1085_i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18030_dupName_140_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18029)@144
    assign rightShiftStage1Idx1Rng8_uid18030_dupName_140_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18032_dupName_140_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18031)@144
    assign rightShiftStage1Idx1_uid18032_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18030_dupName_140_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18025_dupName_140_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18024)@144
    assign rightShiftStage0Idx1Rng4_uid18025_dupName_140_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q[33:4];

    // rightShiftStage0Idx1_uid18027_dupName_140_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18026)@144
    assign rightShiftStage0Idx1_uid18027_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18025_dupName_140_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x(MUX,18028)@144
    assign rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q or rightShiftStage0Idx1_uid18027_dupName_140_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_35_i_c_compmm_m1241_q;
            1'b1 : rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18027_dupName_140_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x(MUX,18033)@144
    assign rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18032_dupName_140_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18029_dupName_140_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18032_dupName_140_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1244_vt_select_21(BITSELECT,10412)@144
    assign i_unnamed_c_compmm_m1244_vt_select_21_b = rightShiftStage1_uid18034_dupName_140_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1244_vt_join(BITJOIN,10411)@144
    assign i_unnamed_c_compmm_m1244_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1244_vt_select_21_b};

    // i_unnamed_c_compmm_m1245_sel_x(BITSELECT,6021)@144
    assign i_unnamed_c_compmm_m1245_sel_x_b = i_unnamed_c_compmm_m1244_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1246_BitSelect_for_a(BITSELECT,28394)@144
    assign i_unnamed_c_compmm_m1246_BitSelect_for_a_b = i_unnamed_c_compmm_m1245_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1246_join(BITJOIN,28395)@144
    assign i_unnamed_c_compmm_m1246_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1246_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1246_vt_select_0(BITSELECT,10417)@144
    assign i_unnamed_c_compmm_m1246_vt_select_0_b = i_unnamed_c_compmm_m1246_join_q[0:0];

    // redist237_i_unnamed_c_compmm_m1246_vt_select_0_b_1(DELAY,29365)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist237_i_unnamed_c_compmm_m1246_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1246_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1246_vt_join(BITJOIN,10416)@145
    assign i_unnamed_c_compmm_m1246_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist237_i_unnamed_c_compmm_m1246_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_35_c_compmm_m1247(ADD,7087)@145
    assign i_add_i_i_i_i_i126_i_35_c_compmm_m1247_a = {1'b0, i_unnamed_c_compmm_m1246_vt_join_q};
    assign i_add_i_i_i_i_i126_i_35_c_compmm_m1247_b = {1'b0, redist1085_i_conv_i_i_i_i97_i_35_c_compmm_m1243_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_35_c_compmm_m1247_o = $unsigned(i_add_i_i_i_i_i126_i_35_c_compmm_m1247_a) + $unsigned(i_add_i_i_i_i_i126_i_35_c_compmm_m1247_b);
    assign i_add_i_i_i_i_i126_i_35_c_compmm_m1247_q = i_add_i_i_i_i_i126_i_35_c_compmm_m1247_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_35_c_compmm_m1247_sel_x(BITSELECT,2101)@145
    assign bgTrunc_i_add_i_i_i_i_i126_i_35_c_compmm_m1247_sel_x_b = i_add_i_i_i_i_i126_i_35_c_compmm_m1247_q[15:0];

    // i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_sel_x(BITSELECT,3634)@145
    assign i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_35_c_compmm_m1247_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_select_15(BITSELECT,7647)@145
    assign i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_select_15_b = i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_join(BITJOIN,7646)@145
    assign i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_select_15_b};

    // leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(MUX,24784)@145
    assign leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_join_q or leftShiftStage0Idx1_uid24783_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_36_c_compmm_m1267_vt_join_q;
            1'b1 : leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24783_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(MUX,24789)@145
    assign leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s or leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24788_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = leftShiftStage0_uid24785_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24788_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x(MUX,24794)@145
    assign leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s or leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24793_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = leftShiftStage1_uid24790_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24793_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28(BITSELECT,9628)@145
    assign i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28_b = leftShiftStage2_uid24795_i_shl_i_i_i_i_i77_i_36_c_compmm_m0_shift_x_q[28:13];

    // redist446_i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28_b_1(DELAY,29574)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist446_i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_join(BITJOIN,9627)@146
    assign i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_join_q = {redist446_i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma(CHAINMULTADD,29056)@140 + 5
    // out q@146
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_6592_c_compmm_m184_out_dest_data_out_74_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_6591_c_compmm_m185_out_dest_data_out_73_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ch[0] <= redist576_sync_together4364_aunroll_x_in_c1_eni5_74_tpl_72_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ch[1] <= redist575_sync_together4364_aunroll_x_in_c1_eni5_73_tpl_72_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269(ADD,8876)@146
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_36_i_c_compmm_m1264_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_36_i_c_compmm_m1266_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_36_i_c_compmm_m1265_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_36_c_compmm_m1268_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_o[33:0];

    // rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x(MUX,18072)@146
    assign rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q or rightShiftStage0Idx1_uid18071_dupName_143_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q;
            1'b1 : rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18071_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x(MUX,18077)@146
    assign rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18076_dupName_143_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18073_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18076_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x(MUX,18082)@146
    assign rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18081_dupName_143_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18078_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18081_dupName_143_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1270_vt_select_20(BITSELECT,10431)@146
    assign i_unnamed_c_compmm_m1270_vt_select_20_b = rightShiftStage2_uid18083_dupName_143_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1270_vt_join(BITJOIN,10430)@146
    assign i_unnamed_c_compmm_m1270_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1270_vt_select_20_b};

    // i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x(BITSELECT,3505)@146
    assign i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x_b = i_unnamed_c_compmm_m1270_vt_join_q[15:0];

    // redist1084_i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x_b_1(DELAY,30212)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1084_i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18092_dupName_144_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18091)@146
    assign rightShiftStage1Idx1Rng8_uid18092_dupName_144_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18094_dupName_144_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18093)@146
    assign rightShiftStage1Idx1_uid18094_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18092_dupName_144_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18087_dupName_144_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18086)@146
    assign rightShiftStage0Idx1Rng4_uid18087_dupName_144_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q[33:4];

    // rightShiftStage0Idx1_uid18089_dupName_144_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18088)@146
    assign rightShiftStage0Idx1_uid18089_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18087_dupName_144_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x(MUX,18090)@146
    assign rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q or rightShiftStage0Idx1_uid18089_dupName_144_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_36_i_c_compmm_m1269_q;
            1'b1 : rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18089_dupName_144_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x(MUX,18095)@146
    assign rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18094_dupName_144_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18091_dupName_144_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18094_dupName_144_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1272_vt_select_21(BITSELECT,10434)@146
    assign i_unnamed_c_compmm_m1272_vt_select_21_b = rightShiftStage1_uid18096_dupName_144_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1272_vt_join(BITJOIN,10433)@146
    assign i_unnamed_c_compmm_m1272_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1272_vt_select_21_b};

    // i_unnamed_c_compmm_m1273_sel_x(BITSELECT,6023)@146
    assign i_unnamed_c_compmm_m1273_sel_x_b = i_unnamed_c_compmm_m1272_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1274_BitSelect_for_a(BITSELECT,28398)@146
    assign i_unnamed_c_compmm_m1274_BitSelect_for_a_b = i_unnamed_c_compmm_m1273_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1274_join(BITJOIN,28399)@146
    assign i_unnamed_c_compmm_m1274_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1274_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1274_vt_select_0(BITSELECT,10439)@146
    assign i_unnamed_c_compmm_m1274_vt_select_0_b = i_unnamed_c_compmm_m1274_join_q[0:0];

    // redist235_i_unnamed_c_compmm_m1274_vt_select_0_b_1(DELAY,29363)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist235_i_unnamed_c_compmm_m1274_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1274_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1274_vt_join(BITJOIN,10438)@147
    assign i_unnamed_c_compmm_m1274_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist235_i_unnamed_c_compmm_m1274_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_36_c_compmm_m1275(ADD,7088)@147
    assign i_add_i_i_i_i_i126_i_36_c_compmm_m1275_a = {1'b0, i_unnamed_c_compmm_m1274_vt_join_q};
    assign i_add_i_i_i_i_i126_i_36_c_compmm_m1275_b = {1'b0, redist1084_i_conv_i_i_i_i97_i_36_c_compmm_m1271_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_36_c_compmm_m1275_o = $unsigned(i_add_i_i_i_i_i126_i_36_c_compmm_m1275_a) + $unsigned(i_add_i_i_i_i_i126_i_36_c_compmm_m1275_b);
    assign i_add_i_i_i_i_i126_i_36_c_compmm_m1275_q = i_add_i_i_i_i_i126_i_36_c_compmm_m1275_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_36_c_compmm_m1275_sel_x(BITSELECT,2102)@147
    assign bgTrunc_i_add_i_i_i_i_i126_i_36_c_compmm_m1275_sel_x_b = i_add_i_i_i_i_i126_i_36_c_compmm_m1275_q[15:0];

    // i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_sel_x(BITSELECT,3635)@147
    assign i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_36_c_compmm_m1275_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_select_15(BITSELECT,7651)@147
    assign i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_select_15_b = i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_join(BITJOIN,7650)@147
    assign i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_select_15_b};

    // leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(MUX,24802)@147
    assign leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_join_q or leftShiftStage0Idx1_uid24801_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_37_c_compmm_m1295_vt_join_q;
            1'b1 : leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24801_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(MUX,24807)@147
    assign leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s or leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24806_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = leftShiftStage0_uid24803_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24806_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x(MUX,24812)@147
    assign leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s or leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24811_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = leftShiftStage1_uid24808_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24811_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28(BITSELECT,9631)@147
    assign i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28_b = leftShiftStage2_uid24813_i_shl_i_i_i_i_i77_i_37_c_compmm_m0_shift_x_q[28:13];

    // redist445_i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28_b_1(DELAY,29573)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist445_i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_join(BITJOIN,9630)@148
    assign i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_join_q = {redist445_i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma(CHAINMULTADD,29057)@142 + 5
    // out q@148
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_6594_c_compmm_m182_out_dest_data_out_76_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_6593_c_compmm_m183_out_dest_data_out_75_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ch[0] <= redist578_sync_together4364_aunroll_x_in_c1_eni5_76_tpl_74_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ch[1] <= redist577_sync_together4364_aunroll_x_in_c1_eni5_75_tpl_74_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297(ADD,8877)@148
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_37_i_c_compmm_m1292_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_37_i_c_compmm_m1294_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_37_i_c_compmm_m1293_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_37_c_compmm_m1296_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_o[33:0];

    // rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x(MUX,18134)@148
    assign rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q or rightShiftStage0Idx1_uid18133_dupName_147_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q;
            1'b1 : rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18133_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x(MUX,18139)@148
    assign rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18138_dupName_147_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18135_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18138_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x(MUX,18144)@148
    assign rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18143_dupName_147_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18140_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18143_dupName_147_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1298_vt_select_20(BITSELECT,10453)@148
    assign i_unnamed_c_compmm_m1298_vt_select_20_b = rightShiftStage2_uid18145_dupName_147_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1298_vt_join(BITJOIN,10452)@148
    assign i_unnamed_c_compmm_m1298_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1298_vt_select_20_b};

    // i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x(BITSELECT,3506)@148
    assign i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x_b = i_unnamed_c_compmm_m1298_vt_join_q[15:0];

    // redist1083_i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x_b_1(DELAY,30211)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1083_i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18154_dupName_148_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18153)@148
    assign rightShiftStage1Idx1Rng8_uid18154_dupName_148_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18156_dupName_148_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18155)@148
    assign rightShiftStage1Idx1_uid18156_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18154_dupName_148_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18149_dupName_148_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18148)@148
    assign rightShiftStage0Idx1Rng4_uid18149_dupName_148_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q[33:4];

    // rightShiftStage0Idx1_uid18151_dupName_148_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18150)@148
    assign rightShiftStage0Idx1_uid18151_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18149_dupName_148_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x(MUX,18152)@148
    assign rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q or rightShiftStage0Idx1_uid18151_dupName_148_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_37_i_c_compmm_m1297_q;
            1'b1 : rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18151_dupName_148_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x(MUX,18157)@148
    assign rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18156_dupName_148_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18153_dupName_148_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18156_dupName_148_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1300_vt_select_21(BITSELECT,10456)@148
    assign i_unnamed_c_compmm_m1300_vt_select_21_b = rightShiftStage1_uid18158_dupName_148_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1300_vt_join(BITJOIN,10455)@148
    assign i_unnamed_c_compmm_m1300_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1300_vt_select_21_b};

    // i_unnamed_c_compmm_m1301_sel_x(BITSELECT,6025)@148
    assign i_unnamed_c_compmm_m1301_sel_x_b = i_unnamed_c_compmm_m1300_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1302_BitSelect_for_a(BITSELECT,28402)@148
    assign i_unnamed_c_compmm_m1302_BitSelect_for_a_b = i_unnamed_c_compmm_m1301_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1302_join(BITJOIN,28403)@148
    assign i_unnamed_c_compmm_m1302_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1302_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1302_vt_select_0(BITSELECT,10461)@148
    assign i_unnamed_c_compmm_m1302_vt_select_0_b = i_unnamed_c_compmm_m1302_join_q[0:0];

    // redist233_i_unnamed_c_compmm_m1302_vt_select_0_b_1(DELAY,29361)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist233_i_unnamed_c_compmm_m1302_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1302_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1302_vt_join(BITJOIN,10460)@149
    assign i_unnamed_c_compmm_m1302_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist233_i_unnamed_c_compmm_m1302_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_37_c_compmm_m1303(ADD,7089)@149
    assign i_add_i_i_i_i_i126_i_37_c_compmm_m1303_a = {1'b0, i_unnamed_c_compmm_m1302_vt_join_q};
    assign i_add_i_i_i_i_i126_i_37_c_compmm_m1303_b = {1'b0, redist1083_i_conv_i_i_i_i97_i_37_c_compmm_m1299_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_37_c_compmm_m1303_o = $unsigned(i_add_i_i_i_i_i126_i_37_c_compmm_m1303_a) + $unsigned(i_add_i_i_i_i_i126_i_37_c_compmm_m1303_b);
    assign i_add_i_i_i_i_i126_i_37_c_compmm_m1303_q = i_add_i_i_i_i_i126_i_37_c_compmm_m1303_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_37_c_compmm_m1303_sel_x(BITSELECT,2103)@149
    assign bgTrunc_i_add_i_i_i_i_i126_i_37_c_compmm_m1303_sel_x_b = i_add_i_i_i_i_i126_i_37_c_compmm_m1303_q[15:0];

    // i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_sel_x(BITSELECT,3636)@149
    assign i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_37_c_compmm_m1303_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_select_15(BITSELECT,7655)@149
    assign i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_select_15_b = i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_join(BITJOIN,7654)@149
    assign i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_select_15_b};

    // leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(MUX,24820)@149
    assign leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_join_q or leftShiftStage0Idx1_uid24819_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_38_c_compmm_m1323_vt_join_q;
            1'b1 : leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24819_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(MUX,24825)@149
    assign leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s or leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24824_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = leftShiftStage0_uid24821_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24824_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x(MUX,24830)@149
    assign leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s or leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24829_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = leftShiftStage1_uid24826_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24829_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28(BITSELECT,9634)@149
    assign i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28_b = leftShiftStage2_uid24831_i_shl_i_i_i_i_i77_i_38_c_compmm_m0_shift_x_q[28:13];

    // redist444_i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28_b_1(DELAY,29572)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist444_i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_join(BITJOIN,9633)@150
    assign i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_join_q = {redist444_i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma(CHAINMULTADD,29058)@144 + 5
    // out q@150
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_6596_c_compmm_m180_out_dest_data_out_78_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_6595_c_compmm_m181_out_dest_data_out_77_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ch[0] <= redist580_sync_together4364_aunroll_x_in_c1_eni5_78_tpl_76_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ch[1] <= redist579_sync_together4364_aunroll_x_in_c1_eni5_77_tpl_76_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325(ADD,8878)@150
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_38_i_c_compmm_m1320_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_38_i_c_compmm_m1322_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_38_i_c_compmm_m1321_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_38_c_compmm_m1324_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_o[33:0];

    // rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x(MUX,18196)@150
    assign rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q or rightShiftStage0Idx1_uid18195_dupName_151_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q;
            1'b1 : rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18195_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x(MUX,18201)@150
    assign rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18200_dupName_151_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18197_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18200_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x(MUX,18206)@150
    assign rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18205_dupName_151_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18202_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18205_dupName_151_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1326_vt_select_20(BITSELECT,10475)@150
    assign i_unnamed_c_compmm_m1326_vt_select_20_b = rightShiftStage2_uid18207_dupName_151_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1326_vt_join(BITJOIN,10474)@150
    assign i_unnamed_c_compmm_m1326_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1326_vt_select_20_b};

    // i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x(BITSELECT,3507)@150
    assign i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x_b = i_unnamed_c_compmm_m1326_vt_join_q[15:0];

    // redist1082_i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x_b_1(DELAY,30210)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1082_i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18216_dupName_152_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18215)@150
    assign rightShiftStage1Idx1Rng8_uid18216_dupName_152_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18218_dupName_152_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18217)@150
    assign rightShiftStage1Idx1_uid18218_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18216_dupName_152_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18211_dupName_152_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18210)@150
    assign rightShiftStage0Idx1Rng4_uid18211_dupName_152_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q[33:4];

    // rightShiftStage0Idx1_uid18213_dupName_152_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18212)@150
    assign rightShiftStage0Idx1_uid18213_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18211_dupName_152_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x(MUX,18214)@150
    assign rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q or rightShiftStage0Idx1_uid18213_dupName_152_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_38_i_c_compmm_m1325_q;
            1'b1 : rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18213_dupName_152_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x(MUX,18219)@150
    assign rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18218_dupName_152_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18215_dupName_152_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18218_dupName_152_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1328_vt_select_21(BITSELECT,10478)@150
    assign i_unnamed_c_compmm_m1328_vt_select_21_b = rightShiftStage1_uid18220_dupName_152_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1328_vt_join(BITJOIN,10477)@150
    assign i_unnamed_c_compmm_m1328_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1328_vt_select_21_b};

    // i_unnamed_c_compmm_m1329_sel_x(BITSELECT,6027)@150
    assign i_unnamed_c_compmm_m1329_sel_x_b = i_unnamed_c_compmm_m1328_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1330_BitSelect_for_a(BITSELECT,28406)@150
    assign i_unnamed_c_compmm_m1330_BitSelect_for_a_b = i_unnamed_c_compmm_m1329_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1330_join(BITJOIN,28407)@150
    assign i_unnamed_c_compmm_m1330_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1330_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1330_vt_select_0(BITSELECT,10483)@150
    assign i_unnamed_c_compmm_m1330_vt_select_0_b = i_unnamed_c_compmm_m1330_join_q[0:0];

    // redist231_i_unnamed_c_compmm_m1330_vt_select_0_b_1(DELAY,29359)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist231_i_unnamed_c_compmm_m1330_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1330_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1330_vt_join(BITJOIN,10482)@151
    assign i_unnamed_c_compmm_m1330_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist231_i_unnamed_c_compmm_m1330_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_38_c_compmm_m1331(ADD,7090)@151
    assign i_add_i_i_i_i_i126_i_38_c_compmm_m1331_a = {1'b0, i_unnamed_c_compmm_m1330_vt_join_q};
    assign i_add_i_i_i_i_i126_i_38_c_compmm_m1331_b = {1'b0, redist1082_i_conv_i_i_i_i97_i_38_c_compmm_m1327_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_38_c_compmm_m1331_o = $unsigned(i_add_i_i_i_i_i126_i_38_c_compmm_m1331_a) + $unsigned(i_add_i_i_i_i_i126_i_38_c_compmm_m1331_b);
    assign i_add_i_i_i_i_i126_i_38_c_compmm_m1331_q = i_add_i_i_i_i_i126_i_38_c_compmm_m1331_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_38_c_compmm_m1331_sel_x(BITSELECT,2104)@151
    assign bgTrunc_i_add_i_i_i_i_i126_i_38_c_compmm_m1331_sel_x_b = i_add_i_i_i_i_i126_i_38_c_compmm_m1331_q[15:0];

    // i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_sel_x(BITSELECT,3637)@151
    assign i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_38_c_compmm_m1331_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_select_15(BITSELECT,7659)@151
    assign i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_select_15_b = i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_join(BITJOIN,7658)@151
    assign i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_select_15_b};

    // leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(MUX,24838)@151
    assign leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_join_q or leftShiftStage0Idx1_uid24837_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_39_c_compmm_m1351_vt_join_q;
            1'b1 : leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24837_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(MUX,24843)@151
    assign leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s or leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24842_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = leftShiftStage0_uid24839_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24842_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x(MUX,24848)@151
    assign leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s or leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24847_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = leftShiftStage1_uid24844_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24847_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28(BITSELECT,9637)@151
    assign i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28_b = leftShiftStage2_uid24849_i_shl_i_i_i_i_i77_i_39_c_compmm_m0_shift_x_q[28:13];

    // redist443_i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28_b_1(DELAY,29571)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist443_i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_join(BITJOIN,9636)@152
    assign i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_join_q = {redist443_i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma(CHAINMULTADD,29059)@146 + 5
    // out q@152
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_6598_c_compmm_m178_out_dest_data_out_80_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_6597_c_compmm_m179_out_dest_data_out_79_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ch[0] <= redist582_sync_together4364_aunroll_x_in_c1_eni5_80_tpl_78_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ch[1] <= redist581_sync_together4364_aunroll_x_in_c1_eni5_79_tpl_78_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353(ADD,8879)@152
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_39_i_c_compmm_m1348_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_39_i_c_compmm_m1350_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_39_i_c_compmm_m1349_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_39_c_compmm_m1352_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_o[33:0];

    // rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x(MUX,18258)@152
    assign rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q or rightShiftStage0Idx1_uid18257_dupName_155_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q;
            1'b1 : rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18257_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x(MUX,18263)@152
    assign rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18262_dupName_155_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18259_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18262_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x(MUX,18268)@152
    assign rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18267_dupName_155_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18264_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18267_dupName_155_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1354_vt_select_20(BITSELECT,10497)@152
    assign i_unnamed_c_compmm_m1354_vt_select_20_b = rightShiftStage2_uid18269_dupName_155_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1354_vt_join(BITJOIN,10496)@152
    assign i_unnamed_c_compmm_m1354_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1354_vt_select_20_b};

    // i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x(BITSELECT,3508)@152
    assign i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x_b = i_unnamed_c_compmm_m1354_vt_join_q[15:0];

    // redist1081_i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x_b_1(DELAY,30209)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1081_i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18278_dupName_156_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18277)@152
    assign rightShiftStage1Idx1Rng8_uid18278_dupName_156_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18280_dupName_156_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18279)@152
    assign rightShiftStage1Idx1_uid18280_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18278_dupName_156_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18273_dupName_156_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18272)@152
    assign rightShiftStage0Idx1Rng4_uid18273_dupName_156_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q[33:4];

    // rightShiftStage0Idx1_uid18275_dupName_156_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18274)@152
    assign rightShiftStage0Idx1_uid18275_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18273_dupName_156_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x(MUX,18276)@152
    assign rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q or rightShiftStage0Idx1_uid18275_dupName_156_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_39_i_c_compmm_m1353_q;
            1'b1 : rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18275_dupName_156_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x(MUX,18281)@152
    assign rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18280_dupName_156_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18277_dupName_156_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18280_dupName_156_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1356_vt_select_21(BITSELECT,10500)@152
    assign i_unnamed_c_compmm_m1356_vt_select_21_b = rightShiftStage1_uid18282_dupName_156_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1356_vt_join(BITJOIN,10499)@152
    assign i_unnamed_c_compmm_m1356_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1356_vt_select_21_b};

    // i_unnamed_c_compmm_m1357_sel_x(BITSELECT,6029)@152
    assign i_unnamed_c_compmm_m1357_sel_x_b = i_unnamed_c_compmm_m1356_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1358_BitSelect_for_a(BITSELECT,28410)@152
    assign i_unnamed_c_compmm_m1358_BitSelect_for_a_b = i_unnamed_c_compmm_m1357_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1358_join(BITJOIN,28411)@152
    assign i_unnamed_c_compmm_m1358_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1358_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1358_vt_select_0(BITSELECT,10505)@152
    assign i_unnamed_c_compmm_m1358_vt_select_0_b = i_unnamed_c_compmm_m1358_join_q[0:0];

    // redist229_i_unnamed_c_compmm_m1358_vt_select_0_b_1(DELAY,29357)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist229_i_unnamed_c_compmm_m1358_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1358_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1358_vt_join(BITJOIN,10504)@153
    assign i_unnamed_c_compmm_m1358_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist229_i_unnamed_c_compmm_m1358_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_39_c_compmm_m1359(ADD,7091)@153
    assign i_add_i_i_i_i_i126_i_39_c_compmm_m1359_a = {1'b0, i_unnamed_c_compmm_m1358_vt_join_q};
    assign i_add_i_i_i_i_i126_i_39_c_compmm_m1359_b = {1'b0, redist1081_i_conv_i_i_i_i97_i_39_c_compmm_m1355_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_39_c_compmm_m1359_o = $unsigned(i_add_i_i_i_i_i126_i_39_c_compmm_m1359_a) + $unsigned(i_add_i_i_i_i_i126_i_39_c_compmm_m1359_b);
    assign i_add_i_i_i_i_i126_i_39_c_compmm_m1359_q = i_add_i_i_i_i_i126_i_39_c_compmm_m1359_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_39_c_compmm_m1359_sel_x(BITSELECT,2105)@153
    assign bgTrunc_i_add_i_i_i_i_i126_i_39_c_compmm_m1359_sel_x_b = i_add_i_i_i_i_i126_i_39_c_compmm_m1359_q[15:0];

    // i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_sel_x(BITSELECT,3639)@153
    assign i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_39_c_compmm_m1359_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_select_15(BITSELECT,7667)@153
    assign i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_select_15_b = i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_join(BITJOIN,7666)@153
    assign i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_select_15_b};

    // leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(MUX,24874)@153
    assign leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_join_q or leftShiftStage0Idx1_uid24873_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_40_c_compmm_m1379_vt_join_q;
            1'b1 : leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24873_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(MUX,24879)@153
    assign leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s or leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24878_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = leftShiftStage0_uid24875_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24878_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x(MUX,24884)@153
    assign leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s or leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24883_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = leftShiftStage1_uid24880_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24883_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28(BITSELECT,9643)@153
    assign i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28_b = leftShiftStage2_uid24885_i_shl_i_i_i_i_i77_i_40_c_compmm_m0_shift_x_q[28:13];

    // redist441_i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28_b_1(DELAY,29569)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist441_i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_join(BITJOIN,9642)@154
    assign i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_join_q = {redist441_i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma(CHAINMULTADD,29061)@148 + 5
    // out q@154
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_65100_c_compmm_m176_out_dest_data_out_82_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_6599_c_compmm_m177_out_dest_data_out_81_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ch[0] <= redist584_sync_together4364_aunroll_x_in_c1_eni5_82_tpl_80_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ch[1] <= redist583_sync_together4364_aunroll_x_in_c1_eni5_81_tpl_80_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381(ADD,8881)@154
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_40_i_c_compmm_m1376_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_40_i_c_compmm_m1378_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_40_i_c_compmm_m1377_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_40_c_compmm_m1380_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_o[33:0];

    // rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x(MUX,18320)@154
    assign rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q or rightShiftStage0Idx1_uid18319_dupName_159_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q;
            1'b1 : rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18319_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x(MUX,18325)@154
    assign rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18324_dupName_159_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18321_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18324_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x(MUX,18330)@154
    assign rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18329_dupName_159_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18326_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18329_dupName_159_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1382_vt_select_20(BITSELECT,10519)@154
    assign i_unnamed_c_compmm_m1382_vt_select_20_b = rightShiftStage2_uid18331_dupName_159_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1382_vt_join(BITJOIN,10518)@154
    assign i_unnamed_c_compmm_m1382_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1382_vt_select_20_b};

    // i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x(BITSELECT,3510)@154
    assign i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x_b = i_unnamed_c_compmm_m1382_vt_join_q[15:0];

    // redist1079_i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x_b_1(DELAY,30207)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1079_i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18340_dupName_160_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18339)@154
    assign rightShiftStage1Idx1Rng8_uid18340_dupName_160_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18342_dupName_160_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18341)@154
    assign rightShiftStage1Idx1_uid18342_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18340_dupName_160_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18335_dupName_160_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18334)@154
    assign rightShiftStage0Idx1Rng4_uid18335_dupName_160_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q[33:4];

    // rightShiftStage0Idx1_uid18337_dupName_160_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18336)@154
    assign rightShiftStage0Idx1_uid18337_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18335_dupName_160_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x(MUX,18338)@154
    assign rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q or rightShiftStage0Idx1_uid18337_dupName_160_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_40_i_c_compmm_m1381_q;
            1'b1 : rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18337_dupName_160_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x(MUX,18343)@154
    assign rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18342_dupName_160_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18339_dupName_160_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18342_dupName_160_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1384_vt_select_21(BITSELECT,10522)@154
    assign i_unnamed_c_compmm_m1384_vt_select_21_b = rightShiftStage1_uid18344_dupName_160_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1384_vt_join(BITJOIN,10521)@154
    assign i_unnamed_c_compmm_m1384_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1384_vt_select_21_b};

    // i_unnamed_c_compmm_m1385_sel_x(BITSELECT,6031)@154
    assign i_unnamed_c_compmm_m1385_sel_x_b = i_unnamed_c_compmm_m1384_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1386_BitSelect_for_a(BITSELECT,28414)@154
    assign i_unnamed_c_compmm_m1386_BitSelect_for_a_b = i_unnamed_c_compmm_m1385_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1386_join(BITJOIN,28415)@154
    assign i_unnamed_c_compmm_m1386_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1386_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1386_vt_select_0(BITSELECT,10527)@154
    assign i_unnamed_c_compmm_m1386_vt_select_0_b = i_unnamed_c_compmm_m1386_join_q[0:0];

    // redist227_i_unnamed_c_compmm_m1386_vt_select_0_b_1(DELAY,29355)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist227_i_unnamed_c_compmm_m1386_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1386_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1386_vt_join(BITJOIN,10526)@155
    assign i_unnamed_c_compmm_m1386_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist227_i_unnamed_c_compmm_m1386_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_40_c_compmm_m1387(ADD,7093)@155
    assign i_add_i_i_i_i_i126_i_40_c_compmm_m1387_a = {1'b0, i_unnamed_c_compmm_m1386_vt_join_q};
    assign i_add_i_i_i_i_i126_i_40_c_compmm_m1387_b = {1'b0, redist1079_i_conv_i_i_i_i97_i_40_c_compmm_m1383_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_40_c_compmm_m1387_o = $unsigned(i_add_i_i_i_i_i126_i_40_c_compmm_m1387_a) + $unsigned(i_add_i_i_i_i_i126_i_40_c_compmm_m1387_b);
    assign i_add_i_i_i_i_i126_i_40_c_compmm_m1387_q = i_add_i_i_i_i_i126_i_40_c_compmm_m1387_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_40_c_compmm_m1387_sel_x(BITSELECT,2107)@155
    assign bgTrunc_i_add_i_i_i_i_i126_i_40_c_compmm_m1387_sel_x_b = i_add_i_i_i_i_i126_i_40_c_compmm_m1387_q[15:0];

    // i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_sel_x(BITSELECT,3640)@155
    assign i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_40_c_compmm_m1387_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_select_15(BITSELECT,7671)@155
    assign i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_select_15_b = i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_join(BITJOIN,7670)@155
    assign i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_select_15_b};

    // leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(MUX,24892)@155
    assign leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_join_q or leftShiftStage0Idx1_uid24891_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_41_c_compmm_m1407_vt_join_q;
            1'b1 : leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24891_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(MUX,24897)@155
    assign leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s or leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24896_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = leftShiftStage0_uid24893_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24896_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x(MUX,24902)@155
    assign leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s or leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24901_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = leftShiftStage1_uid24898_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24901_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28(BITSELECT,9646)@155
    assign i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28_b = leftShiftStage2_uid24903_i_shl_i_i_i_i_i77_i_41_c_compmm_m0_shift_x_q[28:13];

    // redist440_i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28_b_1(DELAY,29568)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist440_i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_join(BITJOIN,9645)@156
    assign i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_join_q = {redist440_i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma(CHAINMULTADD,29062)@150 + 5
    // out q@156
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_65102_c_compmm_m174_out_dest_data_out_84_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_65101_c_compmm_m175_out_dest_data_out_83_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ch[0] <= redist586_sync_together4364_aunroll_x_in_c1_eni5_84_tpl_82_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ch[1] <= redist585_sync_together4364_aunroll_x_in_c1_eni5_83_tpl_82_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409(ADD,8882)@156
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_41_i_c_compmm_m1404_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_41_i_c_compmm_m1406_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_41_i_c_compmm_m1405_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_41_c_compmm_m1408_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_o[33:0];

    // rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x(MUX,18382)@156
    assign rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q or rightShiftStage0Idx1_uid18381_dupName_163_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q;
            1'b1 : rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18381_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x(MUX,18387)@156
    assign rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18386_dupName_163_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18383_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18386_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x(MUX,18392)@156
    assign rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18391_dupName_163_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18388_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18391_dupName_163_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1410_vt_select_20(BITSELECT,10541)@156
    assign i_unnamed_c_compmm_m1410_vt_select_20_b = rightShiftStage2_uid18393_dupName_163_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1410_vt_join(BITJOIN,10540)@156
    assign i_unnamed_c_compmm_m1410_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1410_vt_select_20_b};

    // i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x(BITSELECT,3511)@156
    assign i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x_b = i_unnamed_c_compmm_m1410_vt_join_q[15:0];

    // redist1078_i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x_b_1(DELAY,30206)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1078_i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18402_dupName_164_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18401)@156
    assign rightShiftStage1Idx1Rng8_uid18402_dupName_164_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18404_dupName_164_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18403)@156
    assign rightShiftStage1Idx1_uid18404_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18402_dupName_164_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18397_dupName_164_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18396)@156
    assign rightShiftStage0Idx1Rng4_uid18397_dupName_164_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q[33:4];

    // rightShiftStage0Idx1_uid18399_dupName_164_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18398)@156
    assign rightShiftStage0Idx1_uid18399_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18397_dupName_164_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x(MUX,18400)@156
    assign rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q or rightShiftStage0Idx1_uid18399_dupName_164_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_41_i_c_compmm_m1409_q;
            1'b1 : rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18399_dupName_164_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x(MUX,18405)@156
    assign rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18404_dupName_164_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18401_dupName_164_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18404_dupName_164_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1412_vt_select_21(BITSELECT,10544)@156
    assign i_unnamed_c_compmm_m1412_vt_select_21_b = rightShiftStage1_uid18406_dupName_164_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1412_vt_join(BITJOIN,10543)@156
    assign i_unnamed_c_compmm_m1412_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1412_vt_select_21_b};

    // i_unnamed_c_compmm_m1413_sel_x(BITSELECT,6033)@156
    assign i_unnamed_c_compmm_m1413_sel_x_b = i_unnamed_c_compmm_m1412_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1414_BitSelect_for_a(BITSELECT,28418)@156
    assign i_unnamed_c_compmm_m1414_BitSelect_for_a_b = i_unnamed_c_compmm_m1413_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1414_join(BITJOIN,28419)@156
    assign i_unnamed_c_compmm_m1414_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1414_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1414_vt_select_0(BITSELECT,10549)@156
    assign i_unnamed_c_compmm_m1414_vt_select_0_b = i_unnamed_c_compmm_m1414_join_q[0:0];

    // redist225_i_unnamed_c_compmm_m1414_vt_select_0_b_1(DELAY,29353)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist225_i_unnamed_c_compmm_m1414_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1414_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1414_vt_join(BITJOIN,10548)@157
    assign i_unnamed_c_compmm_m1414_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist225_i_unnamed_c_compmm_m1414_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_41_c_compmm_m1415(ADD,7094)@157
    assign i_add_i_i_i_i_i126_i_41_c_compmm_m1415_a = {1'b0, i_unnamed_c_compmm_m1414_vt_join_q};
    assign i_add_i_i_i_i_i126_i_41_c_compmm_m1415_b = {1'b0, redist1078_i_conv_i_i_i_i97_i_41_c_compmm_m1411_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_41_c_compmm_m1415_o = $unsigned(i_add_i_i_i_i_i126_i_41_c_compmm_m1415_a) + $unsigned(i_add_i_i_i_i_i126_i_41_c_compmm_m1415_b);
    assign i_add_i_i_i_i_i126_i_41_c_compmm_m1415_q = i_add_i_i_i_i_i126_i_41_c_compmm_m1415_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_41_c_compmm_m1415_sel_x(BITSELECT,2108)@157
    assign bgTrunc_i_add_i_i_i_i_i126_i_41_c_compmm_m1415_sel_x_b = i_add_i_i_i_i_i126_i_41_c_compmm_m1415_q[15:0];

    // i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_sel_x(BITSELECT,3641)@157
    assign i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_41_c_compmm_m1415_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_select_15(BITSELECT,7675)@157
    assign i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_select_15_b = i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_join(BITJOIN,7674)@157
    assign i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_select_15_b};

    // leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(MUX,24910)@157
    assign leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_join_q or leftShiftStage0Idx1_uid24909_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_42_c_compmm_m1435_vt_join_q;
            1'b1 : leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24909_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(MUX,24915)@157
    assign leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s or leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24914_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = leftShiftStage0_uid24911_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24914_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x(MUX,24920)@157
    assign leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s or leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24919_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = leftShiftStage1_uid24916_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24919_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28(BITSELECT,9649)@157
    assign i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28_b = leftShiftStage2_uid24921_i_shl_i_i_i_i_i77_i_42_c_compmm_m0_shift_x_q[28:13];

    // redist439_i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28_b_1(DELAY,29567)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist439_i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_join(BITJOIN,9648)@158
    assign i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_join_q = {redist439_i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma(CHAINMULTADD,29063)@152 + 5
    // out q@158
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_65104_c_compmm_m172_out_dest_data_out_86_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_65103_c_compmm_m173_out_dest_data_out_85_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ch[0] <= redist588_sync_together4364_aunroll_x_in_c1_eni5_86_tpl_84_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ch[1] <= redist587_sync_together4364_aunroll_x_in_c1_eni5_85_tpl_84_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437(ADD,8883)@158
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_42_i_c_compmm_m1432_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_42_i_c_compmm_m1434_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_42_i_c_compmm_m1433_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_42_c_compmm_m1436_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_o[33:0];

    // rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x(MUX,18444)@158
    assign rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q or rightShiftStage0Idx1_uid18443_dupName_167_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q;
            1'b1 : rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18443_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x(MUX,18449)@158
    assign rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18448_dupName_167_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18445_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18448_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x(MUX,18454)@158
    assign rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18453_dupName_167_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18450_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18453_dupName_167_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1438_vt_select_20(BITSELECT,10563)@158
    assign i_unnamed_c_compmm_m1438_vt_select_20_b = rightShiftStage2_uid18455_dupName_167_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1438_vt_join(BITJOIN,10562)@158
    assign i_unnamed_c_compmm_m1438_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1438_vt_select_20_b};

    // i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x(BITSELECT,3512)@158
    assign i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x_b = i_unnamed_c_compmm_m1438_vt_join_q[15:0];

    // redist1077_i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x_b_1(DELAY,30205)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1077_i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18464_dupName_168_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18463)@158
    assign rightShiftStage1Idx1Rng8_uid18464_dupName_168_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18466_dupName_168_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18465)@158
    assign rightShiftStage1Idx1_uid18466_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18464_dupName_168_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18459_dupName_168_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18458)@158
    assign rightShiftStage0Idx1Rng4_uid18459_dupName_168_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q[33:4];

    // rightShiftStage0Idx1_uid18461_dupName_168_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18460)@158
    assign rightShiftStage0Idx1_uid18461_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18459_dupName_168_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x(MUX,18462)@158
    assign rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q or rightShiftStage0Idx1_uid18461_dupName_168_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_42_i_c_compmm_m1437_q;
            1'b1 : rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18461_dupName_168_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x(MUX,18467)@158
    assign rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18466_dupName_168_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18463_dupName_168_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18466_dupName_168_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1440_vt_select_21(BITSELECT,10566)@158
    assign i_unnamed_c_compmm_m1440_vt_select_21_b = rightShiftStage1_uid18468_dupName_168_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1440_vt_join(BITJOIN,10565)@158
    assign i_unnamed_c_compmm_m1440_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1440_vt_select_21_b};

    // i_unnamed_c_compmm_m1441_sel_x(BITSELECT,6035)@158
    assign i_unnamed_c_compmm_m1441_sel_x_b = i_unnamed_c_compmm_m1440_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1442_BitSelect_for_a(BITSELECT,28422)@158
    assign i_unnamed_c_compmm_m1442_BitSelect_for_a_b = i_unnamed_c_compmm_m1441_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1442_join(BITJOIN,28423)@158
    assign i_unnamed_c_compmm_m1442_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1442_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1442_vt_select_0(BITSELECT,10571)@158
    assign i_unnamed_c_compmm_m1442_vt_select_0_b = i_unnamed_c_compmm_m1442_join_q[0:0];

    // redist223_i_unnamed_c_compmm_m1442_vt_select_0_b_1(DELAY,29351)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist223_i_unnamed_c_compmm_m1442_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1442_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1442_vt_join(BITJOIN,10570)@159
    assign i_unnamed_c_compmm_m1442_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist223_i_unnamed_c_compmm_m1442_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_42_c_compmm_m1443(ADD,7095)@159
    assign i_add_i_i_i_i_i126_i_42_c_compmm_m1443_a = {1'b0, i_unnamed_c_compmm_m1442_vt_join_q};
    assign i_add_i_i_i_i_i126_i_42_c_compmm_m1443_b = {1'b0, redist1077_i_conv_i_i_i_i97_i_42_c_compmm_m1439_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_42_c_compmm_m1443_o = $unsigned(i_add_i_i_i_i_i126_i_42_c_compmm_m1443_a) + $unsigned(i_add_i_i_i_i_i126_i_42_c_compmm_m1443_b);
    assign i_add_i_i_i_i_i126_i_42_c_compmm_m1443_q = i_add_i_i_i_i_i126_i_42_c_compmm_m1443_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_42_c_compmm_m1443_sel_x(BITSELECT,2109)@159
    assign bgTrunc_i_add_i_i_i_i_i126_i_42_c_compmm_m1443_sel_x_b = i_add_i_i_i_i_i126_i_42_c_compmm_m1443_q[15:0];

    // i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_sel_x(BITSELECT,3642)@159
    assign i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_42_c_compmm_m1443_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_select_15(BITSELECT,7679)@159
    assign i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_select_15_b = i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_join(BITJOIN,7678)@159
    assign i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_select_15_b};

    // leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(MUX,24928)@159
    assign leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_join_q or leftShiftStage0Idx1_uid24927_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_43_c_compmm_m1463_vt_join_q;
            1'b1 : leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24927_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(MUX,24933)@159
    assign leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s or leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24932_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = leftShiftStage0_uid24929_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24932_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x(MUX,24938)@159
    assign leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s or leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24937_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = leftShiftStage1_uid24934_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24937_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28(BITSELECT,9652)@159
    assign i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28_b = leftShiftStage2_uid24939_i_shl_i_i_i_i_i77_i_43_c_compmm_m0_shift_x_q[28:13];

    // redist438_i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28_b_1(DELAY,29566)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist438_i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_join(BITJOIN,9651)@160
    assign i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_join_q = {redist438_i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma(CHAINMULTADD,29064)@154 + 5
    // out q@160
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_65106_c_compmm_m170_out_dest_data_out_88_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_65105_c_compmm_m171_out_dest_data_out_87_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ch[0] <= redist590_sync_together4364_aunroll_x_in_c1_eni5_88_tpl_86_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ch[1] <= redist589_sync_together4364_aunroll_x_in_c1_eni5_87_tpl_86_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465(ADD,8884)@160
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_43_i_c_compmm_m1460_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_43_i_c_compmm_m1462_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_43_i_c_compmm_m1461_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_43_c_compmm_m1464_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_o[33:0];

    // rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x(MUX,18506)@160
    assign rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q or rightShiftStage0Idx1_uid18505_dupName_171_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q;
            1'b1 : rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18505_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x(MUX,18511)@160
    assign rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18510_dupName_171_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18507_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18510_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x(MUX,18516)@160
    assign rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18515_dupName_171_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18512_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18515_dupName_171_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1466_vt_select_20(BITSELECT,10585)@160
    assign i_unnamed_c_compmm_m1466_vt_select_20_b = rightShiftStage2_uid18517_dupName_171_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1466_vt_join(BITJOIN,10584)@160
    assign i_unnamed_c_compmm_m1466_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1466_vt_select_20_b};

    // i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x(BITSELECT,3513)@160
    assign i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x_b = i_unnamed_c_compmm_m1466_vt_join_q[15:0];

    // redist1076_i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x_b_1(DELAY,30204)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1076_i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18526_dupName_172_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18525)@160
    assign rightShiftStage1Idx1Rng8_uid18526_dupName_172_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18528_dupName_172_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18527)@160
    assign rightShiftStage1Idx1_uid18528_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18526_dupName_172_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18521_dupName_172_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18520)@160
    assign rightShiftStage0Idx1Rng4_uid18521_dupName_172_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q[33:4];

    // rightShiftStage0Idx1_uid18523_dupName_172_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18522)@160
    assign rightShiftStage0Idx1_uid18523_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18521_dupName_172_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x(MUX,18524)@160
    assign rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q or rightShiftStage0Idx1_uid18523_dupName_172_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_43_i_c_compmm_m1465_q;
            1'b1 : rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18523_dupName_172_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x(MUX,18529)@160
    assign rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18528_dupName_172_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18525_dupName_172_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18528_dupName_172_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1468_vt_select_21(BITSELECT,10588)@160
    assign i_unnamed_c_compmm_m1468_vt_select_21_b = rightShiftStage1_uid18530_dupName_172_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1468_vt_join(BITJOIN,10587)@160
    assign i_unnamed_c_compmm_m1468_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1468_vt_select_21_b};

    // i_unnamed_c_compmm_m1469_sel_x(BITSELECT,6037)@160
    assign i_unnamed_c_compmm_m1469_sel_x_b = i_unnamed_c_compmm_m1468_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1470_BitSelect_for_a(BITSELECT,28426)@160
    assign i_unnamed_c_compmm_m1470_BitSelect_for_a_b = i_unnamed_c_compmm_m1469_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1470_join(BITJOIN,28427)@160
    assign i_unnamed_c_compmm_m1470_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1470_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1470_vt_select_0(BITSELECT,10593)@160
    assign i_unnamed_c_compmm_m1470_vt_select_0_b = i_unnamed_c_compmm_m1470_join_q[0:0];

    // redist221_i_unnamed_c_compmm_m1470_vt_select_0_b_1(DELAY,29349)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist221_i_unnamed_c_compmm_m1470_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1470_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1470_vt_join(BITJOIN,10592)@161
    assign i_unnamed_c_compmm_m1470_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist221_i_unnamed_c_compmm_m1470_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_43_c_compmm_m1471(ADD,7096)@161
    assign i_add_i_i_i_i_i126_i_43_c_compmm_m1471_a = {1'b0, i_unnamed_c_compmm_m1470_vt_join_q};
    assign i_add_i_i_i_i_i126_i_43_c_compmm_m1471_b = {1'b0, redist1076_i_conv_i_i_i_i97_i_43_c_compmm_m1467_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_43_c_compmm_m1471_o = $unsigned(i_add_i_i_i_i_i126_i_43_c_compmm_m1471_a) + $unsigned(i_add_i_i_i_i_i126_i_43_c_compmm_m1471_b);
    assign i_add_i_i_i_i_i126_i_43_c_compmm_m1471_q = i_add_i_i_i_i_i126_i_43_c_compmm_m1471_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_43_c_compmm_m1471_sel_x(BITSELECT,2110)@161
    assign bgTrunc_i_add_i_i_i_i_i126_i_43_c_compmm_m1471_sel_x_b = i_add_i_i_i_i_i126_i_43_c_compmm_m1471_q[15:0];

    // i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_sel_x(BITSELECT,3643)@161
    assign i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_43_c_compmm_m1471_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_select_15(BITSELECT,7683)@161
    assign i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_select_15_b = i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_join(BITJOIN,7682)@161
    assign i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_select_15_b};

    // leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(MUX,24946)@161
    assign leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_join_q or leftShiftStage0Idx1_uid24945_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_44_c_compmm_m1491_vt_join_q;
            1'b1 : leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24945_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(MUX,24951)@161
    assign leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s or leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24950_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = leftShiftStage0_uid24947_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24950_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x(MUX,24956)@161
    assign leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s or leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24955_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = leftShiftStage1_uid24952_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24955_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28(BITSELECT,9655)@161
    assign i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28_b = leftShiftStage2_uid24957_i_shl_i_i_i_i_i77_i_44_c_compmm_m0_shift_x_q[28:13];

    // redist437_i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28_b_1(DELAY,29565)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist437_i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_join(BITJOIN,9654)@162
    assign i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_join_q = {redist437_i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma(CHAINMULTADD,29065)@156 + 5
    // out q@162
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_65108_c_compmm_m168_out_dest_data_out_90_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_65107_c_compmm_m169_out_dest_data_out_89_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ch[0] <= redist592_sync_together4364_aunroll_x_in_c1_eni5_90_tpl_88_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ch[1] <= redist591_sync_together4364_aunroll_x_in_c1_eni5_89_tpl_88_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493(ADD,8885)@162
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_44_i_c_compmm_m1488_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_44_i_c_compmm_m1490_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_44_i_c_compmm_m1489_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_44_c_compmm_m1492_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_o[33:0];

    // rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x(MUX,18568)@162
    assign rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q or rightShiftStage0Idx1_uid18567_dupName_175_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q;
            1'b1 : rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18567_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x(MUX,18573)@162
    assign rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18572_dupName_175_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18569_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18572_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x(MUX,18578)@162
    assign rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18577_dupName_175_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18574_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18577_dupName_175_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1494_vt_select_20(BITSELECT,10607)@162
    assign i_unnamed_c_compmm_m1494_vt_select_20_b = rightShiftStage2_uid18579_dupName_175_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1494_vt_join(BITJOIN,10606)@162
    assign i_unnamed_c_compmm_m1494_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1494_vt_select_20_b};

    // i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x(BITSELECT,3514)@162
    assign i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x_b = i_unnamed_c_compmm_m1494_vt_join_q[15:0];

    // redist1075_i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x_b_1(DELAY,30203)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1075_i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18588_dupName_176_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18587)@162
    assign rightShiftStage1Idx1Rng8_uid18588_dupName_176_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18590_dupName_176_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18589)@162
    assign rightShiftStage1Idx1_uid18590_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18588_dupName_176_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18583_dupName_176_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18582)@162
    assign rightShiftStage0Idx1Rng4_uid18583_dupName_176_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q[33:4];

    // rightShiftStage0Idx1_uid18585_dupName_176_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18584)@162
    assign rightShiftStage0Idx1_uid18585_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18583_dupName_176_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x(MUX,18586)@162
    assign rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q or rightShiftStage0Idx1_uid18585_dupName_176_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_44_i_c_compmm_m1493_q;
            1'b1 : rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18585_dupName_176_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x(MUX,18591)@162
    assign rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18590_dupName_176_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18587_dupName_176_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18590_dupName_176_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1496_vt_select_21(BITSELECT,10610)@162
    assign i_unnamed_c_compmm_m1496_vt_select_21_b = rightShiftStage1_uid18592_dupName_176_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1496_vt_join(BITJOIN,10609)@162
    assign i_unnamed_c_compmm_m1496_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1496_vt_select_21_b};

    // i_unnamed_c_compmm_m1497_sel_x(BITSELECT,6039)@162
    assign i_unnamed_c_compmm_m1497_sel_x_b = i_unnamed_c_compmm_m1496_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1498_BitSelect_for_a(BITSELECT,28430)@162
    assign i_unnamed_c_compmm_m1498_BitSelect_for_a_b = i_unnamed_c_compmm_m1497_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1498_join(BITJOIN,28431)@162
    assign i_unnamed_c_compmm_m1498_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1498_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1498_vt_select_0(BITSELECT,10615)@162
    assign i_unnamed_c_compmm_m1498_vt_select_0_b = i_unnamed_c_compmm_m1498_join_q[0:0];

    // redist219_i_unnamed_c_compmm_m1498_vt_select_0_b_1(DELAY,29347)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist219_i_unnamed_c_compmm_m1498_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1498_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1498_vt_join(BITJOIN,10614)@163
    assign i_unnamed_c_compmm_m1498_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist219_i_unnamed_c_compmm_m1498_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_44_c_compmm_m1499(ADD,7097)@163
    assign i_add_i_i_i_i_i126_i_44_c_compmm_m1499_a = {1'b0, i_unnamed_c_compmm_m1498_vt_join_q};
    assign i_add_i_i_i_i_i126_i_44_c_compmm_m1499_b = {1'b0, redist1075_i_conv_i_i_i_i97_i_44_c_compmm_m1495_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_44_c_compmm_m1499_o = $unsigned(i_add_i_i_i_i_i126_i_44_c_compmm_m1499_a) + $unsigned(i_add_i_i_i_i_i126_i_44_c_compmm_m1499_b);
    assign i_add_i_i_i_i_i126_i_44_c_compmm_m1499_q = i_add_i_i_i_i_i126_i_44_c_compmm_m1499_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_44_c_compmm_m1499_sel_x(BITSELECT,2111)@163
    assign bgTrunc_i_add_i_i_i_i_i126_i_44_c_compmm_m1499_sel_x_b = i_add_i_i_i_i_i126_i_44_c_compmm_m1499_q[15:0];

    // i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_sel_x(BITSELECT,3644)@163
    assign i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_44_c_compmm_m1499_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_select_15(BITSELECT,7687)@163
    assign i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_select_15_b = i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_join(BITJOIN,7686)@163
    assign i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_select_15_b};

    // leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(MUX,24964)@163
    assign leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_join_q or leftShiftStage0Idx1_uid24963_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_45_c_compmm_m1519_vt_join_q;
            1'b1 : leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24963_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(MUX,24969)@163
    assign leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s or leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24968_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = leftShiftStage0_uid24965_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24968_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x(MUX,24974)@163
    assign leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s or leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24973_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = leftShiftStage1_uid24970_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24973_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28(BITSELECT,9658)@163
    assign i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28_b = leftShiftStage2_uid24975_i_shl_i_i_i_i_i77_i_45_c_compmm_m0_shift_x_q[28:13];

    // redist436_i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28_b_1(DELAY,29564)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist436_i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_join(BITJOIN,9657)@164
    assign i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_join_q = {redist436_i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma(CHAINMULTADD,29066)@158 + 5
    // out q@164
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_65110_c_compmm_m166_out_dest_data_out_92_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_65109_c_compmm_m167_out_dest_data_out_91_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ch[0] <= redist594_sync_together4364_aunroll_x_in_c1_eni5_92_tpl_90_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ch[1] <= redist593_sync_together4364_aunroll_x_in_c1_eni5_91_tpl_90_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521(ADD,8886)@164
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_45_i_c_compmm_m1516_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_45_i_c_compmm_m1518_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_45_i_c_compmm_m1517_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_45_c_compmm_m1520_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_o[33:0];

    // rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x(MUX,18630)@164
    assign rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q or rightShiftStage0Idx1_uid18629_dupName_179_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q;
            1'b1 : rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18629_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x(MUX,18635)@164
    assign rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18634_dupName_179_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18631_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18634_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x(MUX,18640)@164
    assign rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18639_dupName_179_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18636_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18639_dupName_179_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1522_vt_select_20(BITSELECT,10629)@164
    assign i_unnamed_c_compmm_m1522_vt_select_20_b = rightShiftStage2_uid18641_dupName_179_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1522_vt_join(BITJOIN,10628)@164
    assign i_unnamed_c_compmm_m1522_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1522_vt_select_20_b};

    // i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x(BITSELECT,3515)@164
    assign i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x_b = i_unnamed_c_compmm_m1522_vt_join_q[15:0];

    // redist1074_i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x_b_1(DELAY,30202)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1074_i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18650_dupName_180_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18649)@164
    assign rightShiftStage1Idx1Rng8_uid18650_dupName_180_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18652_dupName_180_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18651)@164
    assign rightShiftStage1Idx1_uid18652_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18650_dupName_180_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18645_dupName_180_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18644)@164
    assign rightShiftStage0Idx1Rng4_uid18645_dupName_180_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q[33:4];

    // rightShiftStage0Idx1_uid18647_dupName_180_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18646)@164
    assign rightShiftStage0Idx1_uid18647_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18645_dupName_180_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x(MUX,18648)@164
    assign rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q or rightShiftStage0Idx1_uid18647_dupName_180_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_45_i_c_compmm_m1521_q;
            1'b1 : rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18647_dupName_180_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x(MUX,18653)@164
    assign rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18652_dupName_180_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18649_dupName_180_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18652_dupName_180_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1524_vt_select_21(BITSELECT,10632)@164
    assign i_unnamed_c_compmm_m1524_vt_select_21_b = rightShiftStage1_uid18654_dupName_180_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1524_vt_join(BITJOIN,10631)@164
    assign i_unnamed_c_compmm_m1524_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1524_vt_select_21_b};

    // i_unnamed_c_compmm_m1525_sel_x(BITSELECT,6041)@164
    assign i_unnamed_c_compmm_m1525_sel_x_b = i_unnamed_c_compmm_m1524_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1526_BitSelect_for_a(BITSELECT,28434)@164
    assign i_unnamed_c_compmm_m1526_BitSelect_for_a_b = i_unnamed_c_compmm_m1525_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1526_join(BITJOIN,28435)@164
    assign i_unnamed_c_compmm_m1526_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1526_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1526_vt_select_0(BITSELECT,10637)@164
    assign i_unnamed_c_compmm_m1526_vt_select_0_b = i_unnamed_c_compmm_m1526_join_q[0:0];

    // redist217_i_unnamed_c_compmm_m1526_vt_select_0_b_1(DELAY,29345)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist217_i_unnamed_c_compmm_m1526_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1526_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1526_vt_join(BITJOIN,10636)@165
    assign i_unnamed_c_compmm_m1526_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist217_i_unnamed_c_compmm_m1526_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_45_c_compmm_m1527(ADD,7098)@165
    assign i_add_i_i_i_i_i126_i_45_c_compmm_m1527_a = {1'b0, i_unnamed_c_compmm_m1526_vt_join_q};
    assign i_add_i_i_i_i_i126_i_45_c_compmm_m1527_b = {1'b0, redist1074_i_conv_i_i_i_i97_i_45_c_compmm_m1523_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_45_c_compmm_m1527_o = $unsigned(i_add_i_i_i_i_i126_i_45_c_compmm_m1527_a) + $unsigned(i_add_i_i_i_i_i126_i_45_c_compmm_m1527_b);
    assign i_add_i_i_i_i_i126_i_45_c_compmm_m1527_q = i_add_i_i_i_i_i126_i_45_c_compmm_m1527_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_45_c_compmm_m1527_sel_x(BITSELECT,2112)@165
    assign bgTrunc_i_add_i_i_i_i_i126_i_45_c_compmm_m1527_sel_x_b = i_add_i_i_i_i_i126_i_45_c_compmm_m1527_q[15:0];

    // i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_sel_x(BITSELECT,3645)@165
    assign i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_45_c_compmm_m1527_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_select_15(BITSELECT,7691)@165
    assign i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_select_15_b = i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_join(BITJOIN,7690)@165
    assign i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_select_15_b};

    // leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(MUX,24982)@165
    assign leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_join_q or leftShiftStage0Idx1_uid24981_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_46_c_compmm_m1547_vt_join_q;
            1'b1 : leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24981_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(MUX,24987)@165
    assign leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s or leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24986_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = leftShiftStage0_uid24983_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24986_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x(MUX,24992)@165
    assign leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s or leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24991_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = leftShiftStage1_uid24988_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24991_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28(BITSELECT,9661)@165
    assign i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28_b = leftShiftStage2_uid24993_i_shl_i_i_i_i_i77_i_46_c_compmm_m0_shift_x_q[28:13];

    // redist435_i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28_b_1(DELAY,29563)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist435_i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_join(BITJOIN,9660)@166
    assign i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_join_q = {redist435_i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma(CHAINMULTADD,29067)@160 + 5
    // out q@166
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_65112_c_compmm_m164_out_dest_data_out_94_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_65111_c_compmm_m165_out_dest_data_out_93_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ch[0] <= redist596_sync_together4364_aunroll_x_in_c1_eni5_94_tpl_92_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ch[1] <= redist595_sync_together4364_aunroll_x_in_c1_eni5_93_tpl_92_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549(ADD,8887)@166
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_46_i_c_compmm_m1544_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_46_i_c_compmm_m1546_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_46_i_c_compmm_m1545_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_46_c_compmm_m1548_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_o[33:0];

    // rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x(MUX,18692)@166
    assign rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q or rightShiftStage0Idx1_uid18691_dupName_183_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q;
            1'b1 : rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18691_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x(MUX,18697)@166
    assign rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18696_dupName_183_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18693_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18696_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x(MUX,18702)@166
    assign rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18701_dupName_183_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18698_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18701_dupName_183_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1550_vt_select_20(BITSELECT,10651)@166
    assign i_unnamed_c_compmm_m1550_vt_select_20_b = rightShiftStage2_uid18703_dupName_183_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1550_vt_join(BITJOIN,10650)@166
    assign i_unnamed_c_compmm_m1550_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1550_vt_select_20_b};

    // i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x(BITSELECT,3516)@166
    assign i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x_b = i_unnamed_c_compmm_m1550_vt_join_q[15:0];

    // redist1073_i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x_b_1(DELAY,30201)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1073_i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18712_dupName_184_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18711)@166
    assign rightShiftStage1Idx1Rng8_uid18712_dupName_184_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18714_dupName_184_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18713)@166
    assign rightShiftStage1Idx1_uid18714_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18712_dupName_184_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18707_dupName_184_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18706)@166
    assign rightShiftStage0Idx1Rng4_uid18707_dupName_184_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q[33:4];

    // rightShiftStage0Idx1_uid18709_dupName_184_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18708)@166
    assign rightShiftStage0Idx1_uid18709_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18707_dupName_184_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x(MUX,18710)@166
    assign rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q or rightShiftStage0Idx1_uid18709_dupName_184_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_46_i_c_compmm_m1549_q;
            1'b1 : rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18709_dupName_184_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x(MUX,18715)@166
    assign rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18714_dupName_184_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18711_dupName_184_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18714_dupName_184_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1552_vt_select_21(BITSELECT,10654)@166
    assign i_unnamed_c_compmm_m1552_vt_select_21_b = rightShiftStage1_uid18716_dupName_184_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1552_vt_join(BITJOIN,10653)@166
    assign i_unnamed_c_compmm_m1552_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1552_vt_select_21_b};

    // i_unnamed_c_compmm_m1553_sel_x(BITSELECT,6043)@166
    assign i_unnamed_c_compmm_m1553_sel_x_b = i_unnamed_c_compmm_m1552_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1554_BitSelect_for_a(BITSELECT,28438)@166
    assign i_unnamed_c_compmm_m1554_BitSelect_for_a_b = i_unnamed_c_compmm_m1553_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1554_join(BITJOIN,28439)@166
    assign i_unnamed_c_compmm_m1554_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1554_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1554_vt_select_0(BITSELECT,10659)@166
    assign i_unnamed_c_compmm_m1554_vt_select_0_b = i_unnamed_c_compmm_m1554_join_q[0:0];

    // redist215_i_unnamed_c_compmm_m1554_vt_select_0_b_1(DELAY,29343)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist215_i_unnamed_c_compmm_m1554_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1554_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1554_vt_join(BITJOIN,10658)@167
    assign i_unnamed_c_compmm_m1554_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist215_i_unnamed_c_compmm_m1554_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_46_c_compmm_m1555(ADD,7099)@167
    assign i_add_i_i_i_i_i126_i_46_c_compmm_m1555_a = {1'b0, i_unnamed_c_compmm_m1554_vt_join_q};
    assign i_add_i_i_i_i_i126_i_46_c_compmm_m1555_b = {1'b0, redist1073_i_conv_i_i_i_i97_i_46_c_compmm_m1551_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_46_c_compmm_m1555_o = $unsigned(i_add_i_i_i_i_i126_i_46_c_compmm_m1555_a) + $unsigned(i_add_i_i_i_i_i126_i_46_c_compmm_m1555_b);
    assign i_add_i_i_i_i_i126_i_46_c_compmm_m1555_q = i_add_i_i_i_i_i126_i_46_c_compmm_m1555_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_46_c_compmm_m1555_sel_x(BITSELECT,2113)@167
    assign bgTrunc_i_add_i_i_i_i_i126_i_46_c_compmm_m1555_sel_x_b = i_add_i_i_i_i_i126_i_46_c_compmm_m1555_q[15:0];

    // i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_sel_x(BITSELECT,3646)@167
    assign i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_46_c_compmm_m1555_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_select_15(BITSELECT,7695)@167
    assign i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_select_15_b = i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_join(BITJOIN,7694)@167
    assign i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_select_15_b};

    // leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(MUX,25000)@167
    assign leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_join_q or leftShiftStage0Idx1_uid24999_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_47_c_compmm_m1575_vt_join_q;
            1'b1 : leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24999_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(MUX,25005)@167
    assign leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s or leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25004_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = leftShiftStage0_uid25001_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25004_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x(MUX,25010)@167
    assign leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s or leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25009_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = leftShiftStage1_uid25006_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25009_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28(BITSELECT,9664)@167
    assign i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28_b = leftShiftStage2_uid25011_i_shl_i_i_i_i_i77_i_47_c_compmm_m0_shift_x_q[28:13];

    // redist434_i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28_b_1(DELAY,29562)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist434_i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_join(BITJOIN,9663)@168
    assign i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_join_q = {redist434_i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma(CHAINMULTADD,29068)@162 + 5
    // out q@168
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_65114_c_compmm_m162_out_dest_data_out_96_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_65113_c_compmm_m163_out_dest_data_out_95_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ch[0] <= redist598_sync_together4364_aunroll_x_in_c1_eni5_96_tpl_94_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ch[1] <= redist597_sync_together4364_aunroll_x_in_c1_eni5_95_tpl_94_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577(ADD,8888)@168
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_47_i_c_compmm_m1572_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_47_i_c_compmm_m1574_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_47_i_c_compmm_m1573_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_47_c_compmm_m1576_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_o[33:0];

    // rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x(MUX,18754)@168
    assign rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q or rightShiftStage0Idx1_uid18753_dupName_187_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q;
            1'b1 : rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18753_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x(MUX,18759)@168
    assign rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18758_dupName_187_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18755_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18758_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x(MUX,18764)@168
    assign rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18763_dupName_187_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18760_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18763_dupName_187_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1578_vt_select_20(BITSELECT,10673)@168
    assign i_unnamed_c_compmm_m1578_vt_select_20_b = rightShiftStage2_uid18765_dupName_187_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1578_vt_join(BITJOIN,10672)@168
    assign i_unnamed_c_compmm_m1578_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1578_vt_select_20_b};

    // i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x(BITSELECT,3517)@168
    assign i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x_b = i_unnamed_c_compmm_m1578_vt_join_q[15:0];

    // redist1072_i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x_b_1(DELAY,30200)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1072_i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18774_dupName_188_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18773)@168
    assign rightShiftStage1Idx1Rng8_uid18774_dupName_188_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18776_dupName_188_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18775)@168
    assign rightShiftStage1Idx1_uid18776_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18774_dupName_188_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18769_dupName_188_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18768)@168
    assign rightShiftStage0Idx1Rng4_uid18769_dupName_188_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q[33:4];

    // rightShiftStage0Idx1_uid18771_dupName_188_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18770)@168
    assign rightShiftStage0Idx1_uid18771_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18769_dupName_188_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x(MUX,18772)@168
    assign rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q or rightShiftStage0Idx1_uid18771_dupName_188_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_47_i_c_compmm_m1577_q;
            1'b1 : rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18771_dupName_188_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x(MUX,18777)@168
    assign rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18776_dupName_188_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18773_dupName_188_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18776_dupName_188_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1580_vt_select_21(BITSELECT,10676)@168
    assign i_unnamed_c_compmm_m1580_vt_select_21_b = rightShiftStage1_uid18778_dupName_188_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1580_vt_join(BITJOIN,10675)@168
    assign i_unnamed_c_compmm_m1580_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1580_vt_select_21_b};

    // i_unnamed_c_compmm_m1581_sel_x(BITSELECT,6045)@168
    assign i_unnamed_c_compmm_m1581_sel_x_b = i_unnamed_c_compmm_m1580_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1582_BitSelect_for_a(BITSELECT,28442)@168
    assign i_unnamed_c_compmm_m1582_BitSelect_for_a_b = i_unnamed_c_compmm_m1581_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1582_join(BITJOIN,28443)@168
    assign i_unnamed_c_compmm_m1582_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1582_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1582_vt_select_0(BITSELECT,10681)@168
    assign i_unnamed_c_compmm_m1582_vt_select_0_b = i_unnamed_c_compmm_m1582_join_q[0:0];

    // redist213_i_unnamed_c_compmm_m1582_vt_select_0_b_1(DELAY,29341)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist213_i_unnamed_c_compmm_m1582_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1582_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1582_vt_join(BITJOIN,10680)@169
    assign i_unnamed_c_compmm_m1582_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist213_i_unnamed_c_compmm_m1582_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_47_c_compmm_m1583(ADD,7100)@169
    assign i_add_i_i_i_i_i126_i_47_c_compmm_m1583_a = {1'b0, i_unnamed_c_compmm_m1582_vt_join_q};
    assign i_add_i_i_i_i_i126_i_47_c_compmm_m1583_b = {1'b0, redist1072_i_conv_i_i_i_i97_i_47_c_compmm_m1579_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_47_c_compmm_m1583_o = $unsigned(i_add_i_i_i_i_i126_i_47_c_compmm_m1583_a) + $unsigned(i_add_i_i_i_i_i126_i_47_c_compmm_m1583_b);
    assign i_add_i_i_i_i_i126_i_47_c_compmm_m1583_q = i_add_i_i_i_i_i126_i_47_c_compmm_m1583_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_47_c_compmm_m1583_sel_x(BITSELECT,2114)@169
    assign bgTrunc_i_add_i_i_i_i_i126_i_47_c_compmm_m1583_sel_x_b = i_add_i_i_i_i_i126_i_47_c_compmm_m1583_q[15:0];

    // i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_sel_x(BITSELECT,3647)@169
    assign i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_47_c_compmm_m1583_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_select_15(BITSELECT,7699)@169
    assign i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_select_15_b = i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_join(BITJOIN,7698)@169
    assign i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_select_15_b};

    // leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(MUX,25018)@169
    assign leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_join_q or leftShiftStage0Idx1_uid25017_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_48_c_compmm_m1603_vt_join_q;
            1'b1 : leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25017_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(MUX,25023)@169
    assign leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s or leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25022_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = leftShiftStage0_uid25019_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25022_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x(MUX,25028)@169
    assign leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s or leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25027_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = leftShiftStage1_uid25024_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25027_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28(BITSELECT,9667)@169
    assign i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28_b = leftShiftStage2_uid25029_i_shl_i_i_i_i_i77_i_48_c_compmm_m0_shift_x_q[28:13];

    // redist433_i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28_b_1(DELAY,29561)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist433_i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_join(BITJOIN,9666)@170
    assign i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_join_q = {redist433_i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma(CHAINMULTADD,29069)@164 + 5
    // out q@170
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_65116_c_compmm_m160_out_dest_data_out_98_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_65115_c_compmm_m161_out_dest_data_out_97_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ch[0] <= redist600_sync_together4364_aunroll_x_in_c1_eni5_98_tpl_96_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ch[1] <= redist599_sync_together4364_aunroll_x_in_c1_eni5_97_tpl_96_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605(ADD,8889)@170
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_48_i_c_compmm_m1600_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_48_i_c_compmm_m1602_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_48_i_c_compmm_m1601_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_48_c_compmm_m1604_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_o[33:0];

    // rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x(MUX,18816)@170
    assign rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q or rightShiftStage0Idx1_uid18815_dupName_191_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q;
            1'b1 : rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18815_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x(MUX,18821)@170
    assign rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18820_dupName_191_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18817_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18820_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x(MUX,18826)@170
    assign rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18825_dupName_191_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18822_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18825_dupName_191_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1606_vt_select_20(BITSELECT,10695)@170
    assign i_unnamed_c_compmm_m1606_vt_select_20_b = rightShiftStage2_uid18827_dupName_191_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1606_vt_join(BITJOIN,10694)@170
    assign i_unnamed_c_compmm_m1606_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1606_vt_select_20_b};

    // i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x(BITSELECT,3518)@170
    assign i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x_b = i_unnamed_c_compmm_m1606_vt_join_q[15:0];

    // redist1071_i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x_b_1(DELAY,30199)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1071_i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18836_dupName_192_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18835)@170
    assign rightShiftStage1Idx1Rng8_uid18836_dupName_192_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18838_dupName_192_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18837)@170
    assign rightShiftStage1Idx1_uid18838_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18836_dupName_192_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18831_dupName_192_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18830)@170
    assign rightShiftStage0Idx1Rng4_uid18831_dupName_192_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q[33:4];

    // rightShiftStage0Idx1_uid18833_dupName_192_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18832)@170
    assign rightShiftStage0Idx1_uid18833_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18831_dupName_192_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x(MUX,18834)@170
    assign rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q or rightShiftStage0Idx1_uid18833_dupName_192_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_48_i_c_compmm_m1605_q;
            1'b1 : rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18833_dupName_192_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x(MUX,18839)@170
    assign rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18838_dupName_192_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18835_dupName_192_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18838_dupName_192_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1608_vt_select_21(BITSELECT,10698)@170
    assign i_unnamed_c_compmm_m1608_vt_select_21_b = rightShiftStage1_uid18840_dupName_192_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1608_vt_join(BITJOIN,10697)@170
    assign i_unnamed_c_compmm_m1608_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1608_vt_select_21_b};

    // i_unnamed_c_compmm_m1609_sel_x(BITSELECT,6047)@170
    assign i_unnamed_c_compmm_m1609_sel_x_b = i_unnamed_c_compmm_m1608_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1610_BitSelect_for_a(BITSELECT,28446)@170
    assign i_unnamed_c_compmm_m1610_BitSelect_for_a_b = i_unnamed_c_compmm_m1609_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1610_join(BITJOIN,28447)@170
    assign i_unnamed_c_compmm_m1610_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1610_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1610_vt_select_0(BITSELECT,10703)@170
    assign i_unnamed_c_compmm_m1610_vt_select_0_b = i_unnamed_c_compmm_m1610_join_q[0:0];

    // redist211_i_unnamed_c_compmm_m1610_vt_select_0_b_1(DELAY,29339)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist211_i_unnamed_c_compmm_m1610_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1610_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1610_vt_join(BITJOIN,10702)@171
    assign i_unnamed_c_compmm_m1610_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist211_i_unnamed_c_compmm_m1610_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_48_c_compmm_m1611(ADD,7101)@171
    assign i_add_i_i_i_i_i126_i_48_c_compmm_m1611_a = {1'b0, i_unnamed_c_compmm_m1610_vt_join_q};
    assign i_add_i_i_i_i_i126_i_48_c_compmm_m1611_b = {1'b0, redist1071_i_conv_i_i_i_i97_i_48_c_compmm_m1607_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_48_c_compmm_m1611_o = $unsigned(i_add_i_i_i_i_i126_i_48_c_compmm_m1611_a) + $unsigned(i_add_i_i_i_i_i126_i_48_c_compmm_m1611_b);
    assign i_add_i_i_i_i_i126_i_48_c_compmm_m1611_q = i_add_i_i_i_i_i126_i_48_c_compmm_m1611_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_48_c_compmm_m1611_sel_x(BITSELECT,2115)@171
    assign bgTrunc_i_add_i_i_i_i_i126_i_48_c_compmm_m1611_sel_x_b = i_add_i_i_i_i_i126_i_48_c_compmm_m1611_q[15:0];

    // i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_sel_x(BITSELECT,3648)@171
    assign i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_48_c_compmm_m1611_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_select_15(BITSELECT,7703)@171
    assign i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_select_15_b = i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_join(BITJOIN,7702)@171
    assign i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_select_15_b};

    // leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(MUX,25036)@171
    assign leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_join_q or leftShiftStage0Idx1_uid25035_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_49_c_compmm_m1631_vt_join_q;
            1'b1 : leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25035_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(MUX,25041)@171
    assign leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s or leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25040_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = leftShiftStage0_uid25037_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25040_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x(MUX,25046)@171
    assign leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s or leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25045_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = leftShiftStage1_uid25042_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25045_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28(BITSELECT,9670)@171
    assign i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28_b = leftShiftStage2_uid25047_i_shl_i_i_i_i_i77_i_49_c_compmm_m0_shift_x_q[28:13];

    // redist432_i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28_b_1(DELAY,29560)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist432_i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_join(BITJOIN,9669)@172
    assign i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_join_q = {redist432_i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma(CHAINMULTADD,29070)@166 + 5
    // out q@172
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_65118_c_compmm_m158_out_dest_data_out_100_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_65117_c_compmm_m159_out_dest_data_out_99_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ch[0] <= redist602_sync_together4364_aunroll_x_in_c1_eni5_100_tpl_98_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ch[1] <= redist601_sync_together4364_aunroll_x_in_c1_eni5_99_tpl_98_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633(ADD,8890)@172
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_49_i_c_compmm_m1628_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_49_i_c_compmm_m1630_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_49_i_c_compmm_m1629_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_49_c_compmm_m1632_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_o[33:0];

    // rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x(MUX,18878)@172
    assign rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q or rightShiftStage0Idx1_uid18877_dupName_195_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q;
            1'b1 : rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18877_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x(MUX,18883)@172
    assign rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18882_dupName_195_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18879_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18882_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x(MUX,18888)@172
    assign rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18887_dupName_195_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18884_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18887_dupName_195_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1634_vt_select_20(BITSELECT,10717)@172
    assign i_unnamed_c_compmm_m1634_vt_select_20_b = rightShiftStage2_uid18889_dupName_195_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1634_vt_join(BITJOIN,10716)@172
    assign i_unnamed_c_compmm_m1634_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1634_vt_select_20_b};

    // i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x(BITSELECT,3519)@172
    assign i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x_b = i_unnamed_c_compmm_m1634_vt_join_q[15:0];

    // redist1070_i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x_b_1(DELAY,30198)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1070_i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18898_dupName_196_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18897)@172
    assign rightShiftStage1Idx1Rng8_uid18898_dupName_196_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18900_dupName_196_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18899)@172
    assign rightShiftStage1Idx1_uid18900_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18898_dupName_196_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18893_dupName_196_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18892)@172
    assign rightShiftStage0Idx1Rng4_uid18893_dupName_196_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q[33:4];

    // rightShiftStage0Idx1_uid18895_dupName_196_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18894)@172
    assign rightShiftStage0Idx1_uid18895_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18893_dupName_196_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x(MUX,18896)@172
    assign rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q or rightShiftStage0Idx1_uid18895_dupName_196_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_49_i_c_compmm_m1633_q;
            1'b1 : rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18895_dupName_196_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x(MUX,18901)@172
    assign rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18900_dupName_196_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18897_dupName_196_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18900_dupName_196_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1636_vt_select_21(BITSELECT,10720)@172
    assign i_unnamed_c_compmm_m1636_vt_select_21_b = rightShiftStage1_uid18902_dupName_196_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1636_vt_join(BITJOIN,10719)@172
    assign i_unnamed_c_compmm_m1636_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1636_vt_select_21_b};

    // i_unnamed_c_compmm_m1637_sel_x(BITSELECT,6049)@172
    assign i_unnamed_c_compmm_m1637_sel_x_b = i_unnamed_c_compmm_m1636_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1638_BitSelect_for_a(BITSELECT,28450)@172
    assign i_unnamed_c_compmm_m1638_BitSelect_for_a_b = i_unnamed_c_compmm_m1637_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1638_join(BITJOIN,28451)@172
    assign i_unnamed_c_compmm_m1638_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1638_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1638_vt_select_0(BITSELECT,10725)@172
    assign i_unnamed_c_compmm_m1638_vt_select_0_b = i_unnamed_c_compmm_m1638_join_q[0:0];

    // redist209_i_unnamed_c_compmm_m1638_vt_select_0_b_1(DELAY,29337)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist209_i_unnamed_c_compmm_m1638_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1638_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1638_vt_join(BITJOIN,10724)@173
    assign i_unnamed_c_compmm_m1638_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist209_i_unnamed_c_compmm_m1638_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_49_c_compmm_m1639(ADD,7102)@173
    assign i_add_i_i_i_i_i126_i_49_c_compmm_m1639_a = {1'b0, i_unnamed_c_compmm_m1638_vt_join_q};
    assign i_add_i_i_i_i_i126_i_49_c_compmm_m1639_b = {1'b0, redist1070_i_conv_i_i_i_i97_i_49_c_compmm_m1635_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_49_c_compmm_m1639_o = $unsigned(i_add_i_i_i_i_i126_i_49_c_compmm_m1639_a) + $unsigned(i_add_i_i_i_i_i126_i_49_c_compmm_m1639_b);
    assign i_add_i_i_i_i_i126_i_49_c_compmm_m1639_q = i_add_i_i_i_i_i126_i_49_c_compmm_m1639_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_49_c_compmm_m1639_sel_x(BITSELECT,2116)@173
    assign bgTrunc_i_add_i_i_i_i_i126_i_49_c_compmm_m1639_sel_x_b = i_add_i_i_i_i_i126_i_49_c_compmm_m1639_q[15:0];

    // i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_sel_x(BITSELECT,3650)@173
    assign i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_49_c_compmm_m1639_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_select_15(BITSELECT,7711)@173
    assign i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_select_15_b = i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_join(BITJOIN,7710)@173
    assign i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_select_15_b};

    // leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(MUX,25072)@173
    assign leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_join_q or leftShiftStage0Idx1_uid25071_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_50_c_compmm_m1659_vt_join_q;
            1'b1 : leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25071_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(MUX,25077)@173
    assign leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s or leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25076_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = leftShiftStage0_uid25073_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25076_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x(MUX,25082)@173
    assign leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s or leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25081_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = leftShiftStage1_uid25078_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25081_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28(BITSELECT,9676)@173
    assign i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28_b = leftShiftStage2_uid25083_i_shl_i_i_i_i_i77_i_50_c_compmm_m0_shift_x_q[28:13];

    // redist430_i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28_b_1(DELAY,29558)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist430_i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_join(BITJOIN,9675)@174
    assign i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_join_q = {redist430_i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma(CHAINMULTADD,29072)@168 + 5
    // out q@174
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_65120_c_compmm_m156_out_dest_data_out_102_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_65119_c_compmm_m157_out_dest_data_out_101_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ch[0] <= redist604_sync_together4364_aunroll_x_in_c1_eni5_102_tpl_100_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ch[1] <= redist603_sync_together4364_aunroll_x_in_c1_eni5_101_tpl_100_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661(ADD,8892)@174
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_50_i_c_compmm_m1656_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_50_i_c_compmm_m1658_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_50_i_c_compmm_m1657_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_50_c_compmm_m1660_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_o[33:0];

    // rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x(MUX,18940)@174
    assign rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q or rightShiftStage0Idx1_uid18939_dupName_199_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q;
            1'b1 : rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18939_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x(MUX,18945)@174
    assign rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18944_dupName_199_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18941_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18944_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x(MUX,18950)@174
    assign rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid18949_dupName_199_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid18946_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid18949_dupName_199_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1662_vt_select_20(BITSELECT,10739)@174
    assign i_unnamed_c_compmm_m1662_vt_select_20_b = rightShiftStage2_uid18951_dupName_199_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1662_vt_join(BITJOIN,10738)@174
    assign i_unnamed_c_compmm_m1662_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1662_vt_select_20_b};

    // i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x(BITSELECT,3521)@174
    assign i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x_b = i_unnamed_c_compmm_m1662_vt_join_q[15:0];

    // redist1068_i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x_b_1(DELAY,30196)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1068_i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid18960_dupName_200_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18959)@174
    assign rightShiftStage1Idx1Rng8_uid18960_dupName_200_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid18962_dupName_200_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18961)@174
    assign rightShiftStage1Idx1_uid18962_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid18960_dupName_200_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid18955_dupName_200_i_unnamed_c_compmm_m0_shift_x(BITSELECT,18954)@174
    assign rightShiftStage0Idx1Rng4_uid18955_dupName_200_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q[33:4];

    // rightShiftStage0Idx1_uid18957_dupName_200_i_unnamed_c_compmm_m0_shift_x(BITJOIN,18956)@174
    assign rightShiftStage0Idx1_uid18957_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid18955_dupName_200_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x(MUX,18958)@174
    assign rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q or rightShiftStage0Idx1_uid18957_dupName_200_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_50_i_c_compmm_m1661_q;
            1'b1 : rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid18957_dupName_200_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x(MUX,18963)@174
    assign rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid18962_dupName_200_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid18959_dupName_200_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid18962_dupName_200_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1664_vt_select_21(BITSELECT,10742)@174
    assign i_unnamed_c_compmm_m1664_vt_select_21_b = rightShiftStage1_uid18964_dupName_200_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1664_vt_join(BITJOIN,10741)@174
    assign i_unnamed_c_compmm_m1664_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1664_vt_select_21_b};

    // i_unnamed_c_compmm_m1665_sel_x(BITSELECT,6051)@174
    assign i_unnamed_c_compmm_m1665_sel_x_b = i_unnamed_c_compmm_m1664_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1666_BitSelect_for_a(BITSELECT,28454)@174
    assign i_unnamed_c_compmm_m1666_BitSelect_for_a_b = i_unnamed_c_compmm_m1665_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1666_join(BITJOIN,28455)@174
    assign i_unnamed_c_compmm_m1666_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1666_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1666_vt_select_0(BITSELECT,10747)@174
    assign i_unnamed_c_compmm_m1666_vt_select_0_b = i_unnamed_c_compmm_m1666_join_q[0:0];

    // redist207_i_unnamed_c_compmm_m1666_vt_select_0_b_1(DELAY,29335)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist207_i_unnamed_c_compmm_m1666_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1666_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1666_vt_join(BITJOIN,10746)@175
    assign i_unnamed_c_compmm_m1666_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist207_i_unnamed_c_compmm_m1666_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_50_c_compmm_m1667(ADD,7104)@175
    assign i_add_i_i_i_i_i126_i_50_c_compmm_m1667_a = {1'b0, i_unnamed_c_compmm_m1666_vt_join_q};
    assign i_add_i_i_i_i_i126_i_50_c_compmm_m1667_b = {1'b0, redist1068_i_conv_i_i_i_i97_i_50_c_compmm_m1663_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_50_c_compmm_m1667_o = $unsigned(i_add_i_i_i_i_i126_i_50_c_compmm_m1667_a) + $unsigned(i_add_i_i_i_i_i126_i_50_c_compmm_m1667_b);
    assign i_add_i_i_i_i_i126_i_50_c_compmm_m1667_q = i_add_i_i_i_i_i126_i_50_c_compmm_m1667_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_50_c_compmm_m1667_sel_x(BITSELECT,2118)@175
    assign bgTrunc_i_add_i_i_i_i_i126_i_50_c_compmm_m1667_sel_x_b = i_add_i_i_i_i_i126_i_50_c_compmm_m1667_q[15:0];

    // i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_sel_x(BITSELECT,3651)@175
    assign i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_50_c_compmm_m1667_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_select_15(BITSELECT,7715)@175
    assign i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_select_15_b = i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_join(BITJOIN,7714)@175
    assign i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_select_15_b};

    // leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(MUX,25090)@175
    assign leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_join_q or leftShiftStage0Idx1_uid25089_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_51_c_compmm_m1687_vt_join_q;
            1'b1 : leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25089_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(MUX,25095)@175
    assign leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s or leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25094_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = leftShiftStage0_uid25091_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25094_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x(MUX,25100)@175
    assign leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s or leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25099_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = leftShiftStage1_uid25096_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25099_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28(BITSELECT,9679)@175
    assign i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28_b = leftShiftStage2_uid25101_i_shl_i_i_i_i_i77_i_51_c_compmm_m0_shift_x_q[28:13];

    // redist429_i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28_b_1(DELAY,29557)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist429_i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_join(BITJOIN,9678)@176
    assign i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_join_q = {redist429_i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma(CHAINMULTADD,29073)@170 + 5
    // out q@176
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_65122_c_compmm_m154_out_dest_data_out_104_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_65121_c_compmm_m155_out_dest_data_out_103_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ch[0] <= redist606_sync_together4364_aunroll_x_in_c1_eni5_104_tpl_102_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ch[1] <= redist605_sync_together4364_aunroll_x_in_c1_eni5_103_tpl_102_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689(ADD,8893)@176
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_51_i_c_compmm_m1684_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_51_i_c_compmm_m1686_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_51_i_c_compmm_m1685_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_51_c_compmm_m1688_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_o[33:0];

    // rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x(MUX,19002)@176
    assign rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q or rightShiftStage0Idx1_uid19001_dupName_203_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q;
            1'b1 : rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19001_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x(MUX,19007)@176
    assign rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19006_dupName_203_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19003_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19006_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x(MUX,19012)@176
    assign rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19011_dupName_203_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19008_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19011_dupName_203_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1690_vt_select_20(BITSELECT,10761)@176
    assign i_unnamed_c_compmm_m1690_vt_select_20_b = rightShiftStage2_uid19013_dupName_203_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1690_vt_join(BITJOIN,10760)@176
    assign i_unnamed_c_compmm_m1690_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1690_vt_select_20_b};

    // i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x(BITSELECT,3522)@176
    assign i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x_b = i_unnamed_c_compmm_m1690_vt_join_q[15:0];

    // redist1067_i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x_b_1(DELAY,30195)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1067_i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19022_dupName_204_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19021)@176
    assign rightShiftStage1Idx1Rng8_uid19022_dupName_204_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19024_dupName_204_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19023)@176
    assign rightShiftStage1Idx1_uid19024_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19022_dupName_204_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19017_dupName_204_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19016)@176
    assign rightShiftStage0Idx1Rng4_uid19017_dupName_204_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q[33:4];

    // rightShiftStage0Idx1_uid19019_dupName_204_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19018)@176
    assign rightShiftStage0Idx1_uid19019_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19017_dupName_204_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x(MUX,19020)@176
    assign rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q or rightShiftStage0Idx1_uid19019_dupName_204_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_51_i_c_compmm_m1689_q;
            1'b1 : rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19019_dupName_204_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x(MUX,19025)@176
    assign rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19024_dupName_204_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19021_dupName_204_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19024_dupName_204_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1692_vt_select_21(BITSELECT,10764)@176
    assign i_unnamed_c_compmm_m1692_vt_select_21_b = rightShiftStage1_uid19026_dupName_204_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1692_vt_join(BITJOIN,10763)@176
    assign i_unnamed_c_compmm_m1692_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1692_vt_select_21_b};

    // i_unnamed_c_compmm_m1693_sel_x(BITSELECT,6053)@176
    assign i_unnamed_c_compmm_m1693_sel_x_b = i_unnamed_c_compmm_m1692_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1694_BitSelect_for_a(BITSELECT,28458)@176
    assign i_unnamed_c_compmm_m1694_BitSelect_for_a_b = i_unnamed_c_compmm_m1693_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1694_join(BITJOIN,28459)@176
    assign i_unnamed_c_compmm_m1694_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1694_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1694_vt_select_0(BITSELECT,10769)@176
    assign i_unnamed_c_compmm_m1694_vt_select_0_b = i_unnamed_c_compmm_m1694_join_q[0:0];

    // redist205_i_unnamed_c_compmm_m1694_vt_select_0_b_1(DELAY,29333)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist205_i_unnamed_c_compmm_m1694_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1694_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1694_vt_join(BITJOIN,10768)@177
    assign i_unnamed_c_compmm_m1694_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist205_i_unnamed_c_compmm_m1694_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_51_c_compmm_m1695(ADD,7105)@177
    assign i_add_i_i_i_i_i126_i_51_c_compmm_m1695_a = {1'b0, i_unnamed_c_compmm_m1694_vt_join_q};
    assign i_add_i_i_i_i_i126_i_51_c_compmm_m1695_b = {1'b0, redist1067_i_conv_i_i_i_i97_i_51_c_compmm_m1691_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_51_c_compmm_m1695_o = $unsigned(i_add_i_i_i_i_i126_i_51_c_compmm_m1695_a) + $unsigned(i_add_i_i_i_i_i126_i_51_c_compmm_m1695_b);
    assign i_add_i_i_i_i_i126_i_51_c_compmm_m1695_q = i_add_i_i_i_i_i126_i_51_c_compmm_m1695_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_51_c_compmm_m1695_sel_x(BITSELECT,2119)@177
    assign bgTrunc_i_add_i_i_i_i_i126_i_51_c_compmm_m1695_sel_x_b = i_add_i_i_i_i_i126_i_51_c_compmm_m1695_q[15:0];

    // i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_sel_x(BITSELECT,3652)@177
    assign i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_51_c_compmm_m1695_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_select_15(BITSELECT,7719)@177
    assign i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_select_15_b = i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_join(BITJOIN,7718)@177
    assign i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_select_15_b};

    // leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(MUX,25108)@177
    assign leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_join_q or leftShiftStage0Idx1_uid25107_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_52_c_compmm_m1715_vt_join_q;
            1'b1 : leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25107_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(MUX,25113)@177
    assign leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s or leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25112_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = leftShiftStage0_uid25109_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25112_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x(MUX,25118)@177
    assign leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s or leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25117_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = leftShiftStage1_uid25114_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25117_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28(BITSELECT,9682)@177
    assign i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28_b = leftShiftStage2_uid25119_i_shl_i_i_i_i_i77_i_52_c_compmm_m0_shift_x_q[28:13];

    // redist428_i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28_b_1(DELAY,29556)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist428_i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_join(BITJOIN,9681)@178
    assign i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_join_q = {redist428_i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma(CHAINMULTADD,29074)@172 + 5
    // out q@178
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_65124_c_compmm_m152_out_dest_data_out_106_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_65123_c_compmm_m153_out_dest_data_out_105_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ch[0] <= redist608_sync_together4364_aunroll_x_in_c1_eni5_106_tpl_104_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ch[1] <= redist607_sync_together4364_aunroll_x_in_c1_eni5_105_tpl_104_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717(ADD,8894)@178
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_52_i_c_compmm_m1712_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_52_i_c_compmm_m1714_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_52_i_c_compmm_m1713_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_52_c_compmm_m1716_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_o[33:0];

    // rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x(MUX,19064)@178
    assign rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q or rightShiftStage0Idx1_uid19063_dupName_207_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q;
            1'b1 : rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19063_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x(MUX,19069)@178
    assign rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19068_dupName_207_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19065_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19068_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x(MUX,19074)@178
    assign rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19073_dupName_207_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19070_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19073_dupName_207_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1718_vt_select_20(BITSELECT,10783)@178
    assign i_unnamed_c_compmm_m1718_vt_select_20_b = rightShiftStage2_uid19075_dupName_207_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1718_vt_join(BITJOIN,10782)@178
    assign i_unnamed_c_compmm_m1718_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1718_vt_select_20_b};

    // i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x(BITSELECT,3523)@178
    assign i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x_b = i_unnamed_c_compmm_m1718_vt_join_q[15:0];

    // redist1066_i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x_b_1(DELAY,30194)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1066_i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19084_dupName_208_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19083)@178
    assign rightShiftStage1Idx1Rng8_uid19084_dupName_208_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19086_dupName_208_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19085)@178
    assign rightShiftStage1Idx1_uid19086_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19084_dupName_208_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19079_dupName_208_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19078)@178
    assign rightShiftStage0Idx1Rng4_uid19079_dupName_208_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q[33:4];

    // rightShiftStage0Idx1_uid19081_dupName_208_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19080)@178
    assign rightShiftStage0Idx1_uid19081_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19079_dupName_208_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x(MUX,19082)@178
    assign rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q or rightShiftStage0Idx1_uid19081_dupName_208_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_52_i_c_compmm_m1717_q;
            1'b1 : rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19081_dupName_208_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x(MUX,19087)@178
    assign rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19086_dupName_208_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19083_dupName_208_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19086_dupName_208_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1720_vt_select_21(BITSELECT,10786)@178
    assign i_unnamed_c_compmm_m1720_vt_select_21_b = rightShiftStage1_uid19088_dupName_208_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1720_vt_join(BITJOIN,10785)@178
    assign i_unnamed_c_compmm_m1720_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1720_vt_select_21_b};

    // i_unnamed_c_compmm_m1721_sel_x(BITSELECT,6055)@178
    assign i_unnamed_c_compmm_m1721_sel_x_b = i_unnamed_c_compmm_m1720_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1722_BitSelect_for_a(BITSELECT,28462)@178
    assign i_unnamed_c_compmm_m1722_BitSelect_for_a_b = i_unnamed_c_compmm_m1721_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1722_join(BITJOIN,28463)@178
    assign i_unnamed_c_compmm_m1722_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1722_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1722_vt_select_0(BITSELECT,10791)@178
    assign i_unnamed_c_compmm_m1722_vt_select_0_b = i_unnamed_c_compmm_m1722_join_q[0:0];

    // redist203_i_unnamed_c_compmm_m1722_vt_select_0_b_1(DELAY,29331)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist203_i_unnamed_c_compmm_m1722_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1722_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1722_vt_join(BITJOIN,10790)@179
    assign i_unnamed_c_compmm_m1722_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist203_i_unnamed_c_compmm_m1722_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_52_c_compmm_m1723(ADD,7106)@179
    assign i_add_i_i_i_i_i126_i_52_c_compmm_m1723_a = {1'b0, i_unnamed_c_compmm_m1722_vt_join_q};
    assign i_add_i_i_i_i_i126_i_52_c_compmm_m1723_b = {1'b0, redist1066_i_conv_i_i_i_i97_i_52_c_compmm_m1719_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_52_c_compmm_m1723_o = $unsigned(i_add_i_i_i_i_i126_i_52_c_compmm_m1723_a) + $unsigned(i_add_i_i_i_i_i126_i_52_c_compmm_m1723_b);
    assign i_add_i_i_i_i_i126_i_52_c_compmm_m1723_q = i_add_i_i_i_i_i126_i_52_c_compmm_m1723_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_52_c_compmm_m1723_sel_x(BITSELECT,2120)@179
    assign bgTrunc_i_add_i_i_i_i_i126_i_52_c_compmm_m1723_sel_x_b = i_add_i_i_i_i_i126_i_52_c_compmm_m1723_q[15:0];

    // i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_sel_x(BITSELECT,3653)@179
    assign i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_52_c_compmm_m1723_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_select_15(BITSELECT,7723)@179
    assign i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_select_15_b = i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_join(BITJOIN,7722)@179
    assign i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_select_15_b};

    // leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(MUX,25126)@179
    assign leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_join_q or leftShiftStage0Idx1_uid25125_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_53_c_compmm_m1743_vt_join_q;
            1'b1 : leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25125_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(MUX,25131)@179
    assign leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s or leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25130_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = leftShiftStage0_uid25127_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25130_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x(MUX,25136)@179
    assign leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s or leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25135_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = leftShiftStage1_uid25132_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25135_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28(BITSELECT,9685)@179
    assign i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28_b = leftShiftStage2_uid25137_i_shl_i_i_i_i_i77_i_53_c_compmm_m0_shift_x_q[28:13];

    // redist427_i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28_b_1(DELAY,29555)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist427_i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_join(BITJOIN,9684)@180
    assign i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_join_q = {redist427_i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma(CHAINMULTADD,29075)@174 + 5
    // out q@180
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_65126_c_compmm_m150_out_dest_data_out_108_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_65125_c_compmm_m151_out_dest_data_out_107_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ch[0] <= redist610_sync_together4364_aunroll_x_in_c1_eni5_108_tpl_106_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ch[1] <= redist609_sync_together4364_aunroll_x_in_c1_eni5_107_tpl_106_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745(ADD,8895)@180
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_53_i_c_compmm_m1740_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_53_i_c_compmm_m1742_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_53_i_c_compmm_m1741_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_53_c_compmm_m1744_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_o[33:0];

    // rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x(MUX,19126)@180
    assign rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q or rightShiftStage0Idx1_uid19125_dupName_211_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q;
            1'b1 : rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19125_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x(MUX,19131)@180
    assign rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19130_dupName_211_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19127_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19130_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x(MUX,19136)@180
    assign rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19135_dupName_211_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19132_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19135_dupName_211_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1746_vt_select_20(BITSELECT,10805)@180
    assign i_unnamed_c_compmm_m1746_vt_select_20_b = rightShiftStage2_uid19137_dupName_211_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1746_vt_join(BITJOIN,10804)@180
    assign i_unnamed_c_compmm_m1746_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1746_vt_select_20_b};

    // i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x(BITSELECT,3524)@180
    assign i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x_b = i_unnamed_c_compmm_m1746_vt_join_q[15:0];

    // redist1065_i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x_b_1(DELAY,30193)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1065_i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19146_dupName_212_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19145)@180
    assign rightShiftStage1Idx1Rng8_uid19146_dupName_212_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19148_dupName_212_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19147)@180
    assign rightShiftStage1Idx1_uid19148_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19146_dupName_212_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19141_dupName_212_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19140)@180
    assign rightShiftStage0Idx1Rng4_uid19141_dupName_212_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q[33:4];

    // rightShiftStage0Idx1_uid19143_dupName_212_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19142)@180
    assign rightShiftStage0Idx1_uid19143_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19141_dupName_212_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x(MUX,19144)@180
    assign rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q or rightShiftStage0Idx1_uid19143_dupName_212_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_53_i_c_compmm_m1745_q;
            1'b1 : rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19143_dupName_212_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x(MUX,19149)@180
    assign rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19148_dupName_212_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19145_dupName_212_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19148_dupName_212_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1748_vt_select_21(BITSELECT,10808)@180
    assign i_unnamed_c_compmm_m1748_vt_select_21_b = rightShiftStage1_uid19150_dupName_212_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1748_vt_join(BITJOIN,10807)@180
    assign i_unnamed_c_compmm_m1748_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1748_vt_select_21_b};

    // i_unnamed_c_compmm_m1749_sel_x(BITSELECT,6057)@180
    assign i_unnamed_c_compmm_m1749_sel_x_b = i_unnamed_c_compmm_m1748_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1750_BitSelect_for_a(BITSELECT,28466)@180
    assign i_unnamed_c_compmm_m1750_BitSelect_for_a_b = i_unnamed_c_compmm_m1749_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1750_join(BITJOIN,28467)@180
    assign i_unnamed_c_compmm_m1750_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1750_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1750_vt_select_0(BITSELECT,10813)@180
    assign i_unnamed_c_compmm_m1750_vt_select_0_b = i_unnamed_c_compmm_m1750_join_q[0:0];

    // redist201_i_unnamed_c_compmm_m1750_vt_select_0_b_1(DELAY,29329)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist201_i_unnamed_c_compmm_m1750_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1750_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1750_vt_join(BITJOIN,10812)@181
    assign i_unnamed_c_compmm_m1750_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist201_i_unnamed_c_compmm_m1750_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_53_c_compmm_m1751(ADD,7107)@181
    assign i_add_i_i_i_i_i126_i_53_c_compmm_m1751_a = {1'b0, i_unnamed_c_compmm_m1750_vt_join_q};
    assign i_add_i_i_i_i_i126_i_53_c_compmm_m1751_b = {1'b0, redist1065_i_conv_i_i_i_i97_i_53_c_compmm_m1747_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_53_c_compmm_m1751_o = $unsigned(i_add_i_i_i_i_i126_i_53_c_compmm_m1751_a) + $unsigned(i_add_i_i_i_i_i126_i_53_c_compmm_m1751_b);
    assign i_add_i_i_i_i_i126_i_53_c_compmm_m1751_q = i_add_i_i_i_i_i126_i_53_c_compmm_m1751_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_53_c_compmm_m1751_sel_x(BITSELECT,2121)@181
    assign bgTrunc_i_add_i_i_i_i_i126_i_53_c_compmm_m1751_sel_x_b = i_add_i_i_i_i_i126_i_53_c_compmm_m1751_q[15:0];

    // i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_sel_x(BITSELECT,3654)@181
    assign i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_53_c_compmm_m1751_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_select_15(BITSELECT,7727)@181
    assign i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_select_15_b = i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_join(BITJOIN,7726)@181
    assign i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_select_15_b};

    // leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(MUX,25144)@181
    assign leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_join_q or leftShiftStage0Idx1_uid25143_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_54_c_compmm_m1771_vt_join_q;
            1'b1 : leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25143_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(MUX,25149)@181
    assign leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s or leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25148_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = leftShiftStage0_uid25145_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25148_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x(MUX,25154)@181
    assign leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s or leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25153_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = leftShiftStage1_uid25150_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25153_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28(BITSELECT,9688)@181
    assign i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28_b = leftShiftStage2_uid25155_i_shl_i_i_i_i_i77_i_54_c_compmm_m0_shift_x_q[28:13];

    // redist426_i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28_b_1(DELAY,29554)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist426_i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_join(BITJOIN,9687)@182
    assign i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_join_q = {redist426_i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma(CHAINMULTADD,29076)@176 + 5
    // out q@182
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_65128_c_compmm_m148_out_dest_data_out_110_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_65127_c_compmm_m149_out_dest_data_out_109_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ch[0] <= redist612_sync_together4364_aunroll_x_in_c1_eni5_110_tpl_108_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ch[1] <= redist611_sync_together4364_aunroll_x_in_c1_eni5_109_tpl_108_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773(ADD,8896)@182
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_54_i_c_compmm_m1768_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_54_i_c_compmm_m1770_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_54_i_c_compmm_m1769_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_54_c_compmm_m1772_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_o[33:0];

    // rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x(MUX,19188)@182
    assign rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q or rightShiftStage0Idx1_uid19187_dupName_215_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q;
            1'b1 : rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19187_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x(MUX,19193)@182
    assign rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19192_dupName_215_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19189_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19192_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x(MUX,19198)@182
    assign rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19197_dupName_215_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19194_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19197_dupName_215_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1774_vt_select_20(BITSELECT,10827)@182
    assign i_unnamed_c_compmm_m1774_vt_select_20_b = rightShiftStage2_uid19199_dupName_215_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1774_vt_join(BITJOIN,10826)@182
    assign i_unnamed_c_compmm_m1774_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1774_vt_select_20_b};

    // i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x(BITSELECT,3525)@182
    assign i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x_b = i_unnamed_c_compmm_m1774_vt_join_q[15:0];

    // redist1064_i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x_b_1(DELAY,30192)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1064_i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19208_dupName_216_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19207)@182
    assign rightShiftStage1Idx1Rng8_uid19208_dupName_216_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19210_dupName_216_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19209)@182
    assign rightShiftStage1Idx1_uid19210_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19208_dupName_216_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19203_dupName_216_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19202)@182
    assign rightShiftStage0Idx1Rng4_uid19203_dupName_216_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q[33:4];

    // rightShiftStage0Idx1_uid19205_dupName_216_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19204)@182
    assign rightShiftStage0Idx1_uid19205_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19203_dupName_216_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x(MUX,19206)@182
    assign rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q or rightShiftStage0Idx1_uid19205_dupName_216_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_54_i_c_compmm_m1773_q;
            1'b1 : rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19205_dupName_216_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x(MUX,19211)@182
    assign rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19210_dupName_216_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19207_dupName_216_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19210_dupName_216_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1776_vt_select_21(BITSELECT,10830)@182
    assign i_unnamed_c_compmm_m1776_vt_select_21_b = rightShiftStage1_uid19212_dupName_216_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1776_vt_join(BITJOIN,10829)@182
    assign i_unnamed_c_compmm_m1776_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1776_vt_select_21_b};

    // i_unnamed_c_compmm_m1777_sel_x(BITSELECT,6059)@182
    assign i_unnamed_c_compmm_m1777_sel_x_b = i_unnamed_c_compmm_m1776_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1778_BitSelect_for_a(BITSELECT,28470)@182
    assign i_unnamed_c_compmm_m1778_BitSelect_for_a_b = i_unnamed_c_compmm_m1777_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1778_join(BITJOIN,28471)@182
    assign i_unnamed_c_compmm_m1778_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1778_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1778_vt_select_0(BITSELECT,10835)@182
    assign i_unnamed_c_compmm_m1778_vt_select_0_b = i_unnamed_c_compmm_m1778_join_q[0:0];

    // redist199_i_unnamed_c_compmm_m1778_vt_select_0_b_1(DELAY,29327)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist199_i_unnamed_c_compmm_m1778_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1778_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1778_vt_join(BITJOIN,10834)@183
    assign i_unnamed_c_compmm_m1778_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist199_i_unnamed_c_compmm_m1778_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_54_c_compmm_m1779(ADD,7108)@183
    assign i_add_i_i_i_i_i126_i_54_c_compmm_m1779_a = {1'b0, i_unnamed_c_compmm_m1778_vt_join_q};
    assign i_add_i_i_i_i_i126_i_54_c_compmm_m1779_b = {1'b0, redist1064_i_conv_i_i_i_i97_i_54_c_compmm_m1775_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_54_c_compmm_m1779_o = $unsigned(i_add_i_i_i_i_i126_i_54_c_compmm_m1779_a) + $unsigned(i_add_i_i_i_i_i126_i_54_c_compmm_m1779_b);
    assign i_add_i_i_i_i_i126_i_54_c_compmm_m1779_q = i_add_i_i_i_i_i126_i_54_c_compmm_m1779_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_54_c_compmm_m1779_sel_x(BITSELECT,2122)@183
    assign bgTrunc_i_add_i_i_i_i_i126_i_54_c_compmm_m1779_sel_x_b = i_add_i_i_i_i_i126_i_54_c_compmm_m1779_q[15:0];

    // i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_sel_x(BITSELECT,3655)@183
    assign i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_54_c_compmm_m1779_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_select_15(BITSELECT,7731)@183
    assign i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_select_15_b = i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_join(BITJOIN,7730)@183
    assign i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_select_15_b};

    // leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(MUX,25162)@183
    assign leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_join_q or leftShiftStage0Idx1_uid25161_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_55_c_compmm_m1799_vt_join_q;
            1'b1 : leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25161_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(MUX,25167)@183
    assign leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s or leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25166_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = leftShiftStage0_uid25163_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25166_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x(MUX,25172)@183
    assign leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s or leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25171_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = leftShiftStage1_uid25168_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25171_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28(BITSELECT,9691)@183
    assign i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28_b = leftShiftStage2_uid25173_i_shl_i_i_i_i_i77_i_55_c_compmm_m0_shift_x_q[28:13];

    // redist425_i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28_b_1(DELAY,29553)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist425_i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_join(BITJOIN,9690)@184
    assign i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_join_q = {redist425_i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma(CHAINMULTADD,29077)@178 + 5
    // out q@184
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_65130_c_compmm_m146_out_dest_data_out_112_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_65129_c_compmm_m147_out_dest_data_out_111_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ch[0] <= redist614_sync_together4364_aunroll_x_in_c1_eni5_112_tpl_110_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ch[1] <= redist613_sync_together4364_aunroll_x_in_c1_eni5_111_tpl_110_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801(ADD,8897)@184
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_55_i_c_compmm_m1796_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_55_i_c_compmm_m1798_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_55_i_c_compmm_m1797_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_55_c_compmm_m1800_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_o[33:0];

    // rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x(MUX,19250)@184
    assign rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q or rightShiftStage0Idx1_uid19249_dupName_219_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q;
            1'b1 : rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19249_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x(MUX,19255)@184
    assign rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19254_dupName_219_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19251_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19254_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x(MUX,19260)@184
    assign rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19259_dupName_219_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19256_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19259_dupName_219_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1802_vt_select_20(BITSELECT,10849)@184
    assign i_unnamed_c_compmm_m1802_vt_select_20_b = rightShiftStage2_uid19261_dupName_219_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1802_vt_join(BITJOIN,10848)@184
    assign i_unnamed_c_compmm_m1802_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1802_vt_select_20_b};

    // i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x(BITSELECT,3526)@184
    assign i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x_b = i_unnamed_c_compmm_m1802_vt_join_q[15:0];

    // redist1063_i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x_b_1(DELAY,30191)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1063_i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19270_dupName_220_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19269)@184
    assign rightShiftStage1Idx1Rng8_uid19270_dupName_220_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19272_dupName_220_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19271)@184
    assign rightShiftStage1Idx1_uid19272_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19270_dupName_220_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19265_dupName_220_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19264)@184
    assign rightShiftStage0Idx1Rng4_uid19265_dupName_220_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q[33:4];

    // rightShiftStage0Idx1_uid19267_dupName_220_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19266)@184
    assign rightShiftStage0Idx1_uid19267_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19265_dupName_220_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x(MUX,19268)@184
    assign rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q or rightShiftStage0Idx1_uid19267_dupName_220_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_55_i_c_compmm_m1801_q;
            1'b1 : rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19267_dupName_220_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x(MUX,19273)@184
    assign rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19272_dupName_220_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19269_dupName_220_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19272_dupName_220_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1804_vt_select_21(BITSELECT,10852)@184
    assign i_unnamed_c_compmm_m1804_vt_select_21_b = rightShiftStage1_uid19274_dupName_220_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1804_vt_join(BITJOIN,10851)@184
    assign i_unnamed_c_compmm_m1804_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1804_vt_select_21_b};

    // i_unnamed_c_compmm_m1805_sel_x(BITSELECT,6061)@184
    assign i_unnamed_c_compmm_m1805_sel_x_b = i_unnamed_c_compmm_m1804_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1806_BitSelect_for_a(BITSELECT,28474)@184
    assign i_unnamed_c_compmm_m1806_BitSelect_for_a_b = i_unnamed_c_compmm_m1805_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1806_join(BITJOIN,28475)@184
    assign i_unnamed_c_compmm_m1806_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1806_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1806_vt_select_0(BITSELECT,10857)@184
    assign i_unnamed_c_compmm_m1806_vt_select_0_b = i_unnamed_c_compmm_m1806_join_q[0:0];

    // redist197_i_unnamed_c_compmm_m1806_vt_select_0_b_1(DELAY,29325)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist197_i_unnamed_c_compmm_m1806_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1806_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1806_vt_join(BITJOIN,10856)@185
    assign i_unnamed_c_compmm_m1806_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist197_i_unnamed_c_compmm_m1806_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_55_c_compmm_m1807(ADD,7109)@185
    assign i_add_i_i_i_i_i126_i_55_c_compmm_m1807_a = {1'b0, i_unnamed_c_compmm_m1806_vt_join_q};
    assign i_add_i_i_i_i_i126_i_55_c_compmm_m1807_b = {1'b0, redist1063_i_conv_i_i_i_i97_i_55_c_compmm_m1803_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_55_c_compmm_m1807_o = $unsigned(i_add_i_i_i_i_i126_i_55_c_compmm_m1807_a) + $unsigned(i_add_i_i_i_i_i126_i_55_c_compmm_m1807_b);
    assign i_add_i_i_i_i_i126_i_55_c_compmm_m1807_q = i_add_i_i_i_i_i126_i_55_c_compmm_m1807_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_55_c_compmm_m1807_sel_x(BITSELECT,2123)@185
    assign bgTrunc_i_add_i_i_i_i_i126_i_55_c_compmm_m1807_sel_x_b = i_add_i_i_i_i_i126_i_55_c_compmm_m1807_q[15:0];

    // i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_sel_x(BITSELECT,3656)@185
    assign i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_55_c_compmm_m1807_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_select_15(BITSELECT,7735)@185
    assign i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_select_15_b = i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_join(BITJOIN,7734)@185
    assign i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_select_15_b};

    // leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(MUX,25180)@185
    assign leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_join_q or leftShiftStage0Idx1_uid25179_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_56_c_compmm_m1827_vt_join_q;
            1'b1 : leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25179_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(MUX,25185)@185
    assign leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s or leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25184_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = leftShiftStage0_uid25181_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25184_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x(MUX,25190)@185
    assign leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s or leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25189_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = leftShiftStage1_uid25186_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25189_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28(BITSELECT,9694)@185
    assign i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28_b = leftShiftStage2_uid25191_i_shl_i_i_i_i_i77_i_56_c_compmm_m0_shift_x_q[28:13];

    // redist424_i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28_b_1(DELAY,29552)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist424_i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_join(BITJOIN,9693)@186
    assign i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_join_q = {redist424_i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma(CHAINMULTADD,29078)@180 + 5
    // out q@186
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_65132_c_compmm_m144_out_dest_data_out_114_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_65131_c_compmm_m145_out_dest_data_out_113_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ch[0] <= redist616_sync_together4364_aunroll_x_in_c1_eni5_114_tpl_112_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ch[1] <= redist615_sync_together4364_aunroll_x_in_c1_eni5_113_tpl_112_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829(ADD,8898)@186
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_56_i_c_compmm_m1824_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_56_i_c_compmm_m1826_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_56_i_c_compmm_m1825_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_56_c_compmm_m1828_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_o[33:0];

    // rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x(MUX,19312)@186
    assign rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q or rightShiftStage0Idx1_uid19311_dupName_223_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q;
            1'b1 : rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19311_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x(MUX,19317)@186
    assign rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19316_dupName_223_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19313_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19316_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x(MUX,19322)@186
    assign rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19321_dupName_223_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19318_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19321_dupName_223_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1830_vt_select_20(BITSELECT,10871)@186
    assign i_unnamed_c_compmm_m1830_vt_select_20_b = rightShiftStage2_uid19323_dupName_223_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1830_vt_join(BITJOIN,10870)@186
    assign i_unnamed_c_compmm_m1830_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1830_vt_select_20_b};

    // i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x(BITSELECT,3527)@186
    assign i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x_b = i_unnamed_c_compmm_m1830_vt_join_q[15:0];

    // redist1062_i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x_b_1(DELAY,30190)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1062_i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19332_dupName_224_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19331)@186
    assign rightShiftStage1Idx1Rng8_uid19332_dupName_224_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19334_dupName_224_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19333)@186
    assign rightShiftStage1Idx1_uid19334_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19332_dupName_224_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19327_dupName_224_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19326)@186
    assign rightShiftStage0Idx1Rng4_uid19327_dupName_224_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q[33:4];

    // rightShiftStage0Idx1_uid19329_dupName_224_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19328)@186
    assign rightShiftStage0Idx1_uid19329_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19327_dupName_224_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x(MUX,19330)@186
    assign rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q or rightShiftStage0Idx1_uid19329_dupName_224_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_56_i_c_compmm_m1829_q;
            1'b1 : rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19329_dupName_224_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x(MUX,19335)@186
    assign rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19334_dupName_224_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19331_dupName_224_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19334_dupName_224_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1832_vt_select_21(BITSELECT,10874)@186
    assign i_unnamed_c_compmm_m1832_vt_select_21_b = rightShiftStage1_uid19336_dupName_224_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1832_vt_join(BITJOIN,10873)@186
    assign i_unnamed_c_compmm_m1832_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1832_vt_select_21_b};

    // i_unnamed_c_compmm_m1833_sel_x(BITSELECT,6063)@186
    assign i_unnamed_c_compmm_m1833_sel_x_b = i_unnamed_c_compmm_m1832_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1834_BitSelect_for_a(BITSELECT,28478)@186
    assign i_unnamed_c_compmm_m1834_BitSelect_for_a_b = i_unnamed_c_compmm_m1833_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1834_join(BITJOIN,28479)@186
    assign i_unnamed_c_compmm_m1834_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1834_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1834_vt_select_0(BITSELECT,10879)@186
    assign i_unnamed_c_compmm_m1834_vt_select_0_b = i_unnamed_c_compmm_m1834_join_q[0:0];

    // redist195_i_unnamed_c_compmm_m1834_vt_select_0_b_1(DELAY,29323)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist195_i_unnamed_c_compmm_m1834_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1834_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1834_vt_join(BITJOIN,10878)@187
    assign i_unnamed_c_compmm_m1834_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist195_i_unnamed_c_compmm_m1834_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_56_c_compmm_m1835(ADD,7110)@187
    assign i_add_i_i_i_i_i126_i_56_c_compmm_m1835_a = {1'b0, i_unnamed_c_compmm_m1834_vt_join_q};
    assign i_add_i_i_i_i_i126_i_56_c_compmm_m1835_b = {1'b0, redist1062_i_conv_i_i_i_i97_i_56_c_compmm_m1831_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_56_c_compmm_m1835_o = $unsigned(i_add_i_i_i_i_i126_i_56_c_compmm_m1835_a) + $unsigned(i_add_i_i_i_i_i126_i_56_c_compmm_m1835_b);
    assign i_add_i_i_i_i_i126_i_56_c_compmm_m1835_q = i_add_i_i_i_i_i126_i_56_c_compmm_m1835_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_56_c_compmm_m1835_sel_x(BITSELECT,2124)@187
    assign bgTrunc_i_add_i_i_i_i_i126_i_56_c_compmm_m1835_sel_x_b = i_add_i_i_i_i_i126_i_56_c_compmm_m1835_q[15:0];

    // i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_sel_x(BITSELECT,3657)@187
    assign i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_56_c_compmm_m1835_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_select_15(BITSELECT,7739)@187
    assign i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_select_15_b = i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_join(BITJOIN,7738)@187
    assign i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_select_15_b};

    // leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(MUX,25198)@187
    assign leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_join_q or leftShiftStage0Idx1_uid25197_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_57_c_compmm_m1855_vt_join_q;
            1'b1 : leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25197_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(MUX,25203)@187
    assign leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s or leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25202_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = leftShiftStage0_uid25199_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25202_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x(MUX,25208)@187
    assign leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s or leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25207_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = leftShiftStage1_uid25204_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25207_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28(BITSELECT,9697)@187
    assign i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28_b = leftShiftStage2_uid25209_i_shl_i_i_i_i_i77_i_57_c_compmm_m0_shift_x_q[28:13];

    // redist423_i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28_b_1(DELAY,29551)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist423_i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_join(BITJOIN,9696)@188
    assign i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_join_q = {redist423_i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma(CHAINMULTADD,29079)@182 + 5
    // out q@188
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_65134_c_compmm_m142_out_dest_data_out_116_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_65133_c_compmm_m143_out_dest_data_out_115_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ch[0] <= redist618_sync_together4364_aunroll_x_in_c1_eni5_116_tpl_114_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ch[1] <= redist617_sync_together4364_aunroll_x_in_c1_eni5_115_tpl_114_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857(ADD,8899)@188
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_57_i_c_compmm_m1852_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_57_i_c_compmm_m1854_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_57_i_c_compmm_m1853_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_57_c_compmm_m1856_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_o[33:0];

    // rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x(MUX,19374)@188
    assign rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q or rightShiftStage0Idx1_uid19373_dupName_227_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q;
            1'b1 : rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19373_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x(MUX,19379)@188
    assign rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19378_dupName_227_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19375_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19378_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x(MUX,19384)@188
    assign rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19383_dupName_227_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19380_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19383_dupName_227_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1858_vt_select_20(BITSELECT,10893)@188
    assign i_unnamed_c_compmm_m1858_vt_select_20_b = rightShiftStage2_uid19385_dupName_227_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1858_vt_join(BITJOIN,10892)@188
    assign i_unnamed_c_compmm_m1858_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1858_vt_select_20_b};

    // i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x(BITSELECT,3528)@188
    assign i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x_b = i_unnamed_c_compmm_m1858_vt_join_q[15:0];

    // redist1061_i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x_b_1(DELAY,30189)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1061_i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19394_dupName_228_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19393)@188
    assign rightShiftStage1Idx1Rng8_uid19394_dupName_228_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19396_dupName_228_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19395)@188
    assign rightShiftStage1Idx1_uid19396_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19394_dupName_228_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19389_dupName_228_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19388)@188
    assign rightShiftStage0Idx1Rng4_uid19389_dupName_228_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q[33:4];

    // rightShiftStage0Idx1_uid19391_dupName_228_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19390)@188
    assign rightShiftStage0Idx1_uid19391_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19389_dupName_228_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x(MUX,19392)@188
    assign rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q or rightShiftStage0Idx1_uid19391_dupName_228_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_57_i_c_compmm_m1857_q;
            1'b1 : rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19391_dupName_228_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x(MUX,19397)@188
    assign rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19396_dupName_228_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19393_dupName_228_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19396_dupName_228_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1860_vt_select_21(BITSELECT,10896)@188
    assign i_unnamed_c_compmm_m1860_vt_select_21_b = rightShiftStage1_uid19398_dupName_228_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1860_vt_join(BITJOIN,10895)@188
    assign i_unnamed_c_compmm_m1860_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1860_vt_select_21_b};

    // i_unnamed_c_compmm_m1861_sel_x(BITSELECT,6065)@188
    assign i_unnamed_c_compmm_m1861_sel_x_b = i_unnamed_c_compmm_m1860_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1862_BitSelect_for_a(BITSELECT,28482)@188
    assign i_unnamed_c_compmm_m1862_BitSelect_for_a_b = i_unnamed_c_compmm_m1861_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1862_join(BITJOIN,28483)@188
    assign i_unnamed_c_compmm_m1862_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1862_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1862_vt_select_0(BITSELECT,10901)@188
    assign i_unnamed_c_compmm_m1862_vt_select_0_b = i_unnamed_c_compmm_m1862_join_q[0:0];

    // redist193_i_unnamed_c_compmm_m1862_vt_select_0_b_1(DELAY,29321)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist193_i_unnamed_c_compmm_m1862_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1862_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1862_vt_join(BITJOIN,10900)@189
    assign i_unnamed_c_compmm_m1862_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist193_i_unnamed_c_compmm_m1862_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_57_c_compmm_m1863(ADD,7111)@189
    assign i_add_i_i_i_i_i126_i_57_c_compmm_m1863_a = {1'b0, i_unnamed_c_compmm_m1862_vt_join_q};
    assign i_add_i_i_i_i_i126_i_57_c_compmm_m1863_b = {1'b0, redist1061_i_conv_i_i_i_i97_i_57_c_compmm_m1859_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_57_c_compmm_m1863_o = $unsigned(i_add_i_i_i_i_i126_i_57_c_compmm_m1863_a) + $unsigned(i_add_i_i_i_i_i126_i_57_c_compmm_m1863_b);
    assign i_add_i_i_i_i_i126_i_57_c_compmm_m1863_q = i_add_i_i_i_i_i126_i_57_c_compmm_m1863_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_57_c_compmm_m1863_sel_x(BITSELECT,2125)@189
    assign bgTrunc_i_add_i_i_i_i_i126_i_57_c_compmm_m1863_sel_x_b = i_add_i_i_i_i_i126_i_57_c_compmm_m1863_q[15:0];

    // i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_sel_x(BITSELECT,3658)@189
    assign i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_57_c_compmm_m1863_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_select_15(BITSELECT,7743)@189
    assign i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_select_15_b = i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_join(BITJOIN,7742)@189
    assign i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_select_15_b};

    // leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(MUX,25216)@189
    assign leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_join_q or leftShiftStage0Idx1_uid25215_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_58_c_compmm_m1883_vt_join_q;
            1'b1 : leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25215_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(MUX,25221)@189
    assign leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s or leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25220_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = leftShiftStage0_uid25217_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25220_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x(MUX,25226)@189
    assign leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s or leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25225_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = leftShiftStage1_uid25222_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25225_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28(BITSELECT,9700)@189
    assign i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28_b = leftShiftStage2_uid25227_i_shl_i_i_i_i_i77_i_58_c_compmm_m0_shift_x_q[28:13];

    // redist422_i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28_b_1(DELAY,29550)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist422_i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_join(BITJOIN,9699)@190
    assign i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_join_q = {redist422_i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma(CHAINMULTADD,29080)@184 + 5
    // out q@190
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_65136_c_compmm_m140_out_dest_data_out_118_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_65135_c_compmm_m141_out_dest_data_out_117_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ch[0] <= redist620_sync_together4364_aunroll_x_in_c1_eni5_118_tpl_116_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ch[1] <= redist619_sync_together4364_aunroll_x_in_c1_eni5_117_tpl_116_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885(ADD,8900)@190
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_58_i_c_compmm_m1880_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_58_i_c_compmm_m1882_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_58_i_c_compmm_m1881_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_58_c_compmm_m1884_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_o[33:0];

    // rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x(MUX,19436)@190
    assign rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q or rightShiftStage0Idx1_uid19435_dupName_231_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q;
            1'b1 : rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19435_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x(MUX,19441)@190
    assign rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19440_dupName_231_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19437_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19440_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x(MUX,19446)@190
    assign rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19445_dupName_231_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19442_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19445_dupName_231_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1886_vt_select_20(BITSELECT,10915)@190
    assign i_unnamed_c_compmm_m1886_vt_select_20_b = rightShiftStage2_uid19447_dupName_231_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1886_vt_join(BITJOIN,10914)@190
    assign i_unnamed_c_compmm_m1886_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1886_vt_select_20_b};

    // i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x(BITSELECT,3529)@190
    assign i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x_b = i_unnamed_c_compmm_m1886_vt_join_q[15:0];

    // redist1060_i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x_b_1(DELAY,30188)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1060_i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19456_dupName_232_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19455)@190
    assign rightShiftStage1Idx1Rng8_uid19456_dupName_232_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19458_dupName_232_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19457)@190
    assign rightShiftStage1Idx1_uid19458_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19456_dupName_232_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19451_dupName_232_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19450)@190
    assign rightShiftStage0Idx1Rng4_uid19451_dupName_232_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q[33:4];

    // rightShiftStage0Idx1_uid19453_dupName_232_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19452)@190
    assign rightShiftStage0Idx1_uid19453_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19451_dupName_232_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x(MUX,19454)@190
    assign rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q or rightShiftStage0Idx1_uid19453_dupName_232_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_58_i_c_compmm_m1885_q;
            1'b1 : rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19453_dupName_232_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x(MUX,19459)@190
    assign rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19458_dupName_232_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19455_dupName_232_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19458_dupName_232_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1888_vt_select_21(BITSELECT,10918)@190
    assign i_unnamed_c_compmm_m1888_vt_select_21_b = rightShiftStage1_uid19460_dupName_232_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1888_vt_join(BITJOIN,10917)@190
    assign i_unnamed_c_compmm_m1888_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1888_vt_select_21_b};

    // i_unnamed_c_compmm_m1889_sel_x(BITSELECT,6067)@190
    assign i_unnamed_c_compmm_m1889_sel_x_b = i_unnamed_c_compmm_m1888_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1890_BitSelect_for_a(BITSELECT,28486)@190
    assign i_unnamed_c_compmm_m1890_BitSelect_for_a_b = i_unnamed_c_compmm_m1889_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1890_join(BITJOIN,28487)@190
    assign i_unnamed_c_compmm_m1890_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1890_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1890_vt_select_0(BITSELECT,10923)@190
    assign i_unnamed_c_compmm_m1890_vt_select_0_b = i_unnamed_c_compmm_m1890_join_q[0:0];

    // redist191_i_unnamed_c_compmm_m1890_vt_select_0_b_1(DELAY,29319)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist191_i_unnamed_c_compmm_m1890_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1890_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1890_vt_join(BITJOIN,10922)@191
    assign i_unnamed_c_compmm_m1890_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist191_i_unnamed_c_compmm_m1890_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_58_c_compmm_m1891(ADD,7112)@191
    assign i_add_i_i_i_i_i126_i_58_c_compmm_m1891_a = {1'b0, i_unnamed_c_compmm_m1890_vt_join_q};
    assign i_add_i_i_i_i_i126_i_58_c_compmm_m1891_b = {1'b0, redist1060_i_conv_i_i_i_i97_i_58_c_compmm_m1887_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_58_c_compmm_m1891_o = $unsigned(i_add_i_i_i_i_i126_i_58_c_compmm_m1891_a) + $unsigned(i_add_i_i_i_i_i126_i_58_c_compmm_m1891_b);
    assign i_add_i_i_i_i_i126_i_58_c_compmm_m1891_q = i_add_i_i_i_i_i126_i_58_c_compmm_m1891_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_58_c_compmm_m1891_sel_x(BITSELECT,2126)@191
    assign bgTrunc_i_add_i_i_i_i_i126_i_58_c_compmm_m1891_sel_x_b = i_add_i_i_i_i_i126_i_58_c_compmm_m1891_q[15:0];

    // i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_sel_x(BITSELECT,3659)@191
    assign i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_58_c_compmm_m1891_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_select_15(BITSELECT,7747)@191
    assign i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_select_15_b = i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_join(BITJOIN,7746)@191
    assign i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_select_15_b};

    // leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(MUX,25234)@191
    assign leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_join_q or leftShiftStage0Idx1_uid25233_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_59_c_compmm_m1911_vt_join_q;
            1'b1 : leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25233_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(MUX,25239)@191
    assign leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s or leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25238_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = leftShiftStage0_uid25235_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25238_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x(MUX,25244)@191
    assign leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s or leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25243_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = leftShiftStage1_uid25240_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25243_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28(BITSELECT,9703)@191
    assign i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28_b = leftShiftStage2_uid25245_i_shl_i_i_i_i_i77_i_59_c_compmm_m0_shift_x_q[28:13];

    // redist421_i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28_b_1(DELAY,29549)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist421_i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_join(BITJOIN,9702)@192
    assign i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_join_q = {redist421_i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma(CHAINMULTADD,29081)@186 + 5
    // out q@192
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_65138_c_compmm_m138_out_dest_data_out_120_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_65137_c_compmm_m139_out_dest_data_out_119_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ch[0] <= redist622_sync_together4364_aunroll_x_in_c1_eni5_120_tpl_118_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ch[1] <= redist621_sync_together4364_aunroll_x_in_c1_eni5_119_tpl_118_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913(ADD,8901)@192
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_59_i_c_compmm_m1908_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_59_i_c_compmm_m1910_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_59_i_c_compmm_m1909_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_59_c_compmm_m1912_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_o[33:0];

    // rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x(MUX,19498)@192
    assign rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q or rightShiftStage0Idx1_uid19497_dupName_235_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q;
            1'b1 : rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19497_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x(MUX,19503)@192
    assign rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19502_dupName_235_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19499_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19502_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x(MUX,19508)@192
    assign rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19507_dupName_235_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19504_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19507_dupName_235_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1914_vt_select_20(BITSELECT,10937)@192
    assign i_unnamed_c_compmm_m1914_vt_select_20_b = rightShiftStage2_uid19509_dupName_235_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1914_vt_join(BITJOIN,10936)@192
    assign i_unnamed_c_compmm_m1914_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1914_vt_select_20_b};

    // i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x(BITSELECT,3530)@192
    assign i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x_b = i_unnamed_c_compmm_m1914_vt_join_q[15:0];

    // redist1059_i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x_b_1(DELAY,30187)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1059_i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19518_dupName_236_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19517)@192
    assign rightShiftStage1Idx1Rng8_uid19518_dupName_236_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19520_dupName_236_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19519)@192
    assign rightShiftStage1Idx1_uid19520_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19518_dupName_236_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19513_dupName_236_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19512)@192
    assign rightShiftStage0Idx1Rng4_uid19513_dupName_236_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q[33:4];

    // rightShiftStage0Idx1_uid19515_dupName_236_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19514)@192
    assign rightShiftStage0Idx1_uid19515_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19513_dupName_236_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x(MUX,19516)@192
    assign rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q or rightShiftStage0Idx1_uid19515_dupName_236_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_59_i_c_compmm_m1913_q;
            1'b1 : rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19515_dupName_236_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x(MUX,19521)@192
    assign rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19520_dupName_236_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19517_dupName_236_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19520_dupName_236_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1916_vt_select_21(BITSELECT,10940)@192
    assign i_unnamed_c_compmm_m1916_vt_select_21_b = rightShiftStage1_uid19522_dupName_236_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1916_vt_join(BITJOIN,10939)@192
    assign i_unnamed_c_compmm_m1916_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1916_vt_select_21_b};

    // i_unnamed_c_compmm_m1917_sel_x(BITSELECT,6069)@192
    assign i_unnamed_c_compmm_m1917_sel_x_b = i_unnamed_c_compmm_m1916_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1918_BitSelect_for_a(BITSELECT,28490)@192
    assign i_unnamed_c_compmm_m1918_BitSelect_for_a_b = i_unnamed_c_compmm_m1917_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1918_join(BITJOIN,28491)@192
    assign i_unnamed_c_compmm_m1918_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1918_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1918_vt_select_0(BITSELECT,10945)@192
    assign i_unnamed_c_compmm_m1918_vt_select_0_b = i_unnamed_c_compmm_m1918_join_q[0:0];

    // redist189_i_unnamed_c_compmm_m1918_vt_select_0_b_1(DELAY,29317)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist189_i_unnamed_c_compmm_m1918_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1918_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1918_vt_join(BITJOIN,10944)@193
    assign i_unnamed_c_compmm_m1918_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist189_i_unnamed_c_compmm_m1918_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_59_c_compmm_m1919(ADD,7113)@193
    assign i_add_i_i_i_i_i126_i_59_c_compmm_m1919_a = {1'b0, i_unnamed_c_compmm_m1918_vt_join_q};
    assign i_add_i_i_i_i_i126_i_59_c_compmm_m1919_b = {1'b0, redist1059_i_conv_i_i_i_i97_i_59_c_compmm_m1915_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_59_c_compmm_m1919_o = $unsigned(i_add_i_i_i_i_i126_i_59_c_compmm_m1919_a) + $unsigned(i_add_i_i_i_i_i126_i_59_c_compmm_m1919_b);
    assign i_add_i_i_i_i_i126_i_59_c_compmm_m1919_q = i_add_i_i_i_i_i126_i_59_c_compmm_m1919_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_59_c_compmm_m1919_sel_x(BITSELECT,2127)@193
    assign bgTrunc_i_add_i_i_i_i_i126_i_59_c_compmm_m1919_sel_x_b = i_add_i_i_i_i_i126_i_59_c_compmm_m1919_q[15:0];

    // i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_sel_x(BITSELECT,3661)@193
    assign i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_59_c_compmm_m1919_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_select_15(BITSELECT,7755)@193
    assign i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_select_15_b = i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_join(BITJOIN,7754)@193
    assign i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_select_15_b};

    // leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(MUX,25270)@193
    assign leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_join_q or leftShiftStage0Idx1_uid25269_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_60_c_compmm_m1939_vt_join_q;
            1'b1 : leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25269_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(MUX,25275)@193
    assign leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s or leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25274_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = leftShiftStage0_uid25271_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25274_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x(MUX,25280)@193
    assign leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s or leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25279_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = leftShiftStage1_uid25276_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25279_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28(BITSELECT,9709)@193
    assign i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28_b = leftShiftStage2_uid25281_i_shl_i_i_i_i_i77_i_60_c_compmm_m0_shift_x_q[28:13];

    // redist419_i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28_b_1(DELAY,29547)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist419_i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_join(BITJOIN,9708)@194
    assign i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_join_q = {redist419_i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma(CHAINMULTADD,29083)@188 + 5
    // out q@194
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_65140_c_compmm_m136_out_dest_data_out_122_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_65139_c_compmm_m137_out_dest_data_out_121_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ch[0] <= redist624_sync_together4364_aunroll_x_in_c1_eni5_122_tpl_120_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ch[1] <= redist623_sync_together4364_aunroll_x_in_c1_eni5_121_tpl_120_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941(ADD,8903)@194
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_60_i_c_compmm_m1936_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_60_i_c_compmm_m1938_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_60_i_c_compmm_m1937_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_60_c_compmm_m1940_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_o[33:0];

    // rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x(MUX,19560)@194
    assign rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q or rightShiftStage0Idx1_uid19559_dupName_239_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q;
            1'b1 : rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19559_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x(MUX,19565)@194
    assign rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19564_dupName_239_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19561_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19564_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x(MUX,19570)@194
    assign rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19569_dupName_239_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19566_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19569_dupName_239_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1942_vt_select_20(BITSELECT,10959)@194
    assign i_unnamed_c_compmm_m1942_vt_select_20_b = rightShiftStage2_uid19571_dupName_239_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1942_vt_join(BITJOIN,10958)@194
    assign i_unnamed_c_compmm_m1942_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1942_vt_select_20_b};

    // i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x(BITSELECT,3532)@194
    assign i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x_b = i_unnamed_c_compmm_m1942_vt_join_q[15:0];

    // redist1057_i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x_b_1(DELAY,30185)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1057_i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19580_dupName_240_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19579)@194
    assign rightShiftStage1Idx1Rng8_uid19580_dupName_240_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19582_dupName_240_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19581)@194
    assign rightShiftStage1Idx1_uid19582_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19580_dupName_240_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19575_dupName_240_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19574)@194
    assign rightShiftStage0Idx1Rng4_uid19575_dupName_240_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q[33:4];

    // rightShiftStage0Idx1_uid19577_dupName_240_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19576)@194
    assign rightShiftStage0Idx1_uid19577_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19575_dupName_240_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x(MUX,19578)@194
    assign rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q or rightShiftStage0Idx1_uid19577_dupName_240_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_60_i_c_compmm_m1941_q;
            1'b1 : rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19577_dupName_240_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x(MUX,19583)@194
    assign rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19582_dupName_240_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19579_dupName_240_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19582_dupName_240_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1944_vt_select_21(BITSELECT,10962)@194
    assign i_unnamed_c_compmm_m1944_vt_select_21_b = rightShiftStage1_uid19584_dupName_240_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1944_vt_join(BITJOIN,10961)@194
    assign i_unnamed_c_compmm_m1944_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1944_vt_select_21_b};

    // i_unnamed_c_compmm_m1945_sel_x(BITSELECT,6071)@194
    assign i_unnamed_c_compmm_m1945_sel_x_b = i_unnamed_c_compmm_m1944_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1946_BitSelect_for_a(BITSELECT,28494)@194
    assign i_unnamed_c_compmm_m1946_BitSelect_for_a_b = i_unnamed_c_compmm_m1945_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1946_join(BITJOIN,28495)@194
    assign i_unnamed_c_compmm_m1946_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1946_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1946_vt_select_0(BITSELECT,10967)@194
    assign i_unnamed_c_compmm_m1946_vt_select_0_b = i_unnamed_c_compmm_m1946_join_q[0:0];

    // redist187_i_unnamed_c_compmm_m1946_vt_select_0_b_1(DELAY,29315)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist187_i_unnamed_c_compmm_m1946_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1946_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1946_vt_join(BITJOIN,10966)@195
    assign i_unnamed_c_compmm_m1946_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist187_i_unnamed_c_compmm_m1946_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_60_c_compmm_m1947(ADD,7115)@195
    assign i_add_i_i_i_i_i126_i_60_c_compmm_m1947_a = {1'b0, i_unnamed_c_compmm_m1946_vt_join_q};
    assign i_add_i_i_i_i_i126_i_60_c_compmm_m1947_b = {1'b0, redist1057_i_conv_i_i_i_i97_i_60_c_compmm_m1943_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_60_c_compmm_m1947_o = $unsigned(i_add_i_i_i_i_i126_i_60_c_compmm_m1947_a) + $unsigned(i_add_i_i_i_i_i126_i_60_c_compmm_m1947_b);
    assign i_add_i_i_i_i_i126_i_60_c_compmm_m1947_q = i_add_i_i_i_i_i126_i_60_c_compmm_m1947_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_60_c_compmm_m1947_sel_x(BITSELECT,2129)@195
    assign bgTrunc_i_add_i_i_i_i_i126_i_60_c_compmm_m1947_sel_x_b = i_add_i_i_i_i_i126_i_60_c_compmm_m1947_q[15:0];

    // i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_sel_x(BITSELECT,3662)@195
    assign i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_60_c_compmm_m1947_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_select_15(BITSELECT,7759)@195
    assign i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_select_15_b = i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_join(BITJOIN,7758)@195
    assign i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_select_15_b};

    // leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(MUX,25288)@195
    assign leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_join_q or leftShiftStage0Idx1_uid25287_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_61_c_compmm_m1967_vt_join_q;
            1'b1 : leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25287_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(MUX,25293)@195
    assign leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s or leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25292_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = leftShiftStage0_uid25289_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25292_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x(MUX,25298)@195
    assign leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s or leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25297_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = leftShiftStage1_uid25294_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25297_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28(BITSELECT,9712)@195
    assign i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28_b = leftShiftStage2_uid25299_i_shl_i_i_i_i_i77_i_61_c_compmm_m0_shift_x_q[28:13];

    // redist418_i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28_b_1(DELAY,29546)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist418_i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_join(BITJOIN,9711)@196
    assign i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_join_q = {redist418_i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma(CHAINMULTADD,29084)@190 + 5
    // out q@196
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_65142_c_compmm_m134_out_dest_data_out_124_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_65141_c_compmm_m135_out_dest_data_out_123_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ch[0] <= redist626_sync_together4364_aunroll_x_in_c1_eni5_124_tpl_122_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ch[1] <= redist625_sync_together4364_aunroll_x_in_c1_eni5_123_tpl_122_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969(ADD,8904)@196
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_61_i_c_compmm_m1964_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_61_i_c_compmm_m1966_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_61_i_c_compmm_m1965_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_61_c_compmm_m1968_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_o[33:0];

    // rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x(MUX,19622)@196
    assign rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q or rightShiftStage0Idx1_uid19621_dupName_243_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q;
            1'b1 : rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19621_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x(MUX,19627)@196
    assign rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19626_dupName_243_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19623_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19626_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x(MUX,19632)@196
    assign rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19631_dupName_243_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19628_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19631_dupName_243_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1970_vt_select_20(BITSELECT,10981)@196
    assign i_unnamed_c_compmm_m1970_vt_select_20_b = rightShiftStage2_uid19633_dupName_243_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1970_vt_join(BITJOIN,10980)@196
    assign i_unnamed_c_compmm_m1970_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1970_vt_select_20_b};

    // i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x(BITSELECT,3533)@196
    assign i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x_b = i_unnamed_c_compmm_m1970_vt_join_q[15:0];

    // redist1056_i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x_b_1(DELAY,30184)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1056_i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19642_dupName_244_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19641)@196
    assign rightShiftStage1Idx1Rng8_uid19642_dupName_244_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19644_dupName_244_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19643)@196
    assign rightShiftStage1Idx1_uid19644_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19642_dupName_244_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19637_dupName_244_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19636)@196
    assign rightShiftStage0Idx1Rng4_uid19637_dupName_244_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q[33:4];

    // rightShiftStage0Idx1_uid19639_dupName_244_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19638)@196
    assign rightShiftStage0Idx1_uid19639_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19637_dupName_244_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x(MUX,19640)@196
    assign rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q or rightShiftStage0Idx1_uid19639_dupName_244_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_61_i_c_compmm_m1969_q;
            1'b1 : rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19639_dupName_244_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x(MUX,19645)@196
    assign rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19644_dupName_244_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19641_dupName_244_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19644_dupName_244_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1972_vt_select_21(BITSELECT,10984)@196
    assign i_unnamed_c_compmm_m1972_vt_select_21_b = rightShiftStage1_uid19646_dupName_244_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m1972_vt_join(BITJOIN,10983)@196
    assign i_unnamed_c_compmm_m1972_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m1972_vt_select_21_b};

    // i_unnamed_c_compmm_m1973_sel_x(BITSELECT,6073)@196
    assign i_unnamed_c_compmm_m1973_sel_x_b = i_unnamed_c_compmm_m1972_vt_join_q[15:0];

    // i_unnamed_c_compmm_m1974_BitSelect_for_a(BITSELECT,28498)@196
    assign i_unnamed_c_compmm_m1974_BitSelect_for_a_b = i_unnamed_c_compmm_m1973_sel_x_b[0:0];

    // i_unnamed_c_compmm_m1974_join(BITJOIN,28499)@196
    assign i_unnamed_c_compmm_m1974_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m1974_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m1974_vt_select_0(BITSELECT,10989)@196
    assign i_unnamed_c_compmm_m1974_vt_select_0_b = i_unnamed_c_compmm_m1974_join_q[0:0];

    // redist185_i_unnamed_c_compmm_m1974_vt_select_0_b_1(DELAY,29313)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist185_i_unnamed_c_compmm_m1974_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m1974_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m1974_vt_join(BITJOIN,10988)@197
    assign i_unnamed_c_compmm_m1974_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist185_i_unnamed_c_compmm_m1974_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_61_c_compmm_m1975(ADD,7116)@197
    assign i_add_i_i_i_i_i126_i_61_c_compmm_m1975_a = {1'b0, i_unnamed_c_compmm_m1974_vt_join_q};
    assign i_add_i_i_i_i_i126_i_61_c_compmm_m1975_b = {1'b0, redist1056_i_conv_i_i_i_i97_i_61_c_compmm_m1971_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_61_c_compmm_m1975_o = $unsigned(i_add_i_i_i_i_i126_i_61_c_compmm_m1975_a) + $unsigned(i_add_i_i_i_i_i126_i_61_c_compmm_m1975_b);
    assign i_add_i_i_i_i_i126_i_61_c_compmm_m1975_q = i_add_i_i_i_i_i126_i_61_c_compmm_m1975_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_61_c_compmm_m1975_sel_x(BITSELECT,2130)@197
    assign bgTrunc_i_add_i_i_i_i_i126_i_61_c_compmm_m1975_sel_x_b = i_add_i_i_i_i_i126_i_61_c_compmm_m1975_q[15:0];

    // i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_sel_x(BITSELECT,3663)@197
    assign i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_61_c_compmm_m1975_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_select_15(BITSELECT,7763)@197
    assign i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_select_15_b = i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_join(BITJOIN,7762)@197
    assign i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_select_15_b};

    // leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(MUX,25306)@197
    assign leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_join_q or leftShiftStage0Idx1_uid25305_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_62_c_compmm_m1995_vt_join_q;
            1'b1 : leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25305_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(MUX,25311)@197
    assign leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s or leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25310_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = leftShiftStage0_uid25307_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25310_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x(MUX,25316)@197
    assign leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s or leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25315_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = leftShiftStage1_uid25312_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25315_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28(BITSELECT,9715)@197
    assign i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28_b = leftShiftStage2_uid25317_i_shl_i_i_i_i_i77_i_62_c_compmm_m0_shift_x_q[28:13];

    // redist417_i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28_b_1(DELAY,29545)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist417_i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_join(BITJOIN,9714)@198
    assign i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_join_q = {redist417_i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma(CHAINMULTADD,29085)@192 + 5
    // out q@198
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_65144_c_compmm_m132_out_dest_data_out_126_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_65143_c_compmm_m133_out_dest_data_out_125_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ch[0] <= redist628_sync_together4364_aunroll_x_in_c1_eni5_126_tpl_124_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ch[1] <= redist627_sync_together4364_aunroll_x_in_c1_eni5_125_tpl_124_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997(ADD,8905)@198
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_62_i_c_compmm_m1992_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_62_i_c_compmm_m1994_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_62_i_c_compmm_m1993_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_62_c_compmm_m1996_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_o[33:0];

    // rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x(MUX,19684)@198
    assign rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q or rightShiftStage0Idx1_uid19683_dupName_247_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q;
            1'b1 : rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19683_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x(MUX,19689)@198
    assign rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19688_dupName_247_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19685_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19688_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x(MUX,19694)@198
    assign rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19693_dupName_247_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19690_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19693_dupName_247_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m1998_vt_select_20(BITSELECT,11003)@198
    assign i_unnamed_c_compmm_m1998_vt_select_20_b = rightShiftStage2_uid19695_dupName_247_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m1998_vt_join(BITJOIN,11002)@198
    assign i_unnamed_c_compmm_m1998_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m1998_vt_select_20_b};

    // i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x(BITSELECT,3534)@198
    assign i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x_b = i_unnamed_c_compmm_m1998_vt_join_q[15:0];

    // redist1055_i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x_b_1(DELAY,30183)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1055_i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19704_dupName_248_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19703)@198
    assign rightShiftStage1Idx1Rng8_uid19704_dupName_248_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19706_dupName_248_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19705)@198
    assign rightShiftStage1Idx1_uid19706_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19704_dupName_248_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19699_dupName_248_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19698)@198
    assign rightShiftStage0Idx1Rng4_uid19699_dupName_248_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q[33:4];

    // rightShiftStage0Idx1_uid19701_dupName_248_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19700)@198
    assign rightShiftStage0Idx1_uid19701_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19699_dupName_248_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x(MUX,19702)@198
    assign rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q or rightShiftStage0Idx1_uid19701_dupName_248_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_62_i_c_compmm_m1997_q;
            1'b1 : rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19701_dupName_248_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x(MUX,19707)@198
    assign rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19706_dupName_248_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19703_dupName_248_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19706_dupName_248_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2000_vt_select_21(BITSELECT,11006)@198
    assign i_unnamed_c_compmm_m2000_vt_select_21_b = rightShiftStage1_uid19708_dupName_248_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2000_vt_join(BITJOIN,11005)@198
    assign i_unnamed_c_compmm_m2000_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2000_vt_select_21_b};

    // i_unnamed_c_compmm_m2001_sel_x(BITSELECT,6075)@198
    assign i_unnamed_c_compmm_m2001_sel_x_b = i_unnamed_c_compmm_m2000_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2002_BitSelect_for_a(BITSELECT,28502)@198
    assign i_unnamed_c_compmm_m2002_BitSelect_for_a_b = i_unnamed_c_compmm_m2001_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2002_join(BITJOIN,28503)@198
    assign i_unnamed_c_compmm_m2002_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2002_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2002_vt_select_0(BITSELECT,11011)@198
    assign i_unnamed_c_compmm_m2002_vt_select_0_b = i_unnamed_c_compmm_m2002_join_q[0:0];

    // redist183_i_unnamed_c_compmm_m2002_vt_select_0_b_1(DELAY,29311)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist183_i_unnamed_c_compmm_m2002_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2002_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2002_vt_join(BITJOIN,11010)@199
    assign i_unnamed_c_compmm_m2002_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist183_i_unnamed_c_compmm_m2002_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_62_c_compmm_m2003(ADD,7117)@199
    assign i_add_i_i_i_i_i126_i_62_c_compmm_m2003_a = {1'b0, i_unnamed_c_compmm_m2002_vt_join_q};
    assign i_add_i_i_i_i_i126_i_62_c_compmm_m2003_b = {1'b0, redist1055_i_conv_i_i_i_i97_i_62_c_compmm_m1999_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_62_c_compmm_m2003_o = $unsigned(i_add_i_i_i_i_i126_i_62_c_compmm_m2003_a) + $unsigned(i_add_i_i_i_i_i126_i_62_c_compmm_m2003_b);
    assign i_add_i_i_i_i_i126_i_62_c_compmm_m2003_q = i_add_i_i_i_i_i126_i_62_c_compmm_m2003_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_62_c_compmm_m2003_sel_x(BITSELECT,2131)@199
    assign bgTrunc_i_add_i_i_i_i_i126_i_62_c_compmm_m2003_sel_x_b = i_add_i_i_i_i_i126_i_62_c_compmm_m2003_q[15:0];

    // i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_sel_x(BITSELECT,3664)@199
    assign i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_62_c_compmm_m2003_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_select_15(BITSELECT,7767)@199
    assign i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_select_15_b = i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_join(BITJOIN,7766)@199
    assign i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_select_15_b};

    // leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(MUX,25324)@199
    assign leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_join_q or leftShiftStage0Idx1_uid25323_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_63_c_compmm_m2023_vt_join_q;
            1'b1 : leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25323_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(MUX,25329)@199
    assign leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s or leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25328_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = leftShiftStage0_uid25325_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25328_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x(MUX,25334)@199
    assign leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s or leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25333_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = leftShiftStage1_uid25330_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25333_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28(BITSELECT,9718)@199
    assign i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28_b = leftShiftStage2_uid25335_i_shl_i_i_i_i_i77_i_63_c_compmm_m0_shift_x_q[28:13];

    // redist416_i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28_b_1(DELAY,29544)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist416_i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_join(BITJOIN,9717)@200
    assign i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_join_q = {redist416_i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma(CHAINMULTADD,29086)@194 + 5
    // out q@200
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_65146_c_compmm_m130_out_dest_data_out_128_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_65145_c_compmm_m131_out_dest_data_out_127_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ch[0] <= redist630_sync_together4364_aunroll_x_in_c1_eni5_128_tpl_126_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ch[1] <= redist629_sync_together4364_aunroll_x_in_c1_eni5_127_tpl_126_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025(ADD,8906)@200
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_63_i_c_compmm_m2020_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_63_i_c_compmm_m2022_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_63_i_c_compmm_m2021_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_63_c_compmm_m2024_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_o[33:0];

    // rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x(MUX,19746)@200
    assign rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q or rightShiftStage0Idx1_uid19745_dupName_251_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q;
            1'b1 : rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19745_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x(MUX,19751)@200
    assign rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19750_dupName_251_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19747_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19750_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x(MUX,19756)@200
    assign rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19755_dupName_251_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19752_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19755_dupName_251_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2026_vt_select_20(BITSELECT,11025)@200
    assign i_unnamed_c_compmm_m2026_vt_select_20_b = rightShiftStage2_uid19757_dupName_251_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2026_vt_join(BITJOIN,11024)@200
    assign i_unnamed_c_compmm_m2026_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2026_vt_select_20_b};

    // i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x(BITSELECT,3535)@200
    assign i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x_b = i_unnamed_c_compmm_m2026_vt_join_q[15:0];

    // redist1054_i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x_b_1(DELAY,30182)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1054_i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19766_dupName_252_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19765)@200
    assign rightShiftStage1Idx1Rng8_uid19766_dupName_252_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19768_dupName_252_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19767)@200
    assign rightShiftStage1Idx1_uid19768_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19766_dupName_252_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19761_dupName_252_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19760)@200
    assign rightShiftStage0Idx1Rng4_uid19761_dupName_252_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q[33:4];

    // rightShiftStage0Idx1_uid19763_dupName_252_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19762)@200
    assign rightShiftStage0Idx1_uid19763_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19761_dupName_252_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x(MUX,19764)@200
    assign rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q or rightShiftStage0Idx1_uid19763_dupName_252_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_63_i_c_compmm_m2025_q;
            1'b1 : rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19763_dupName_252_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x(MUX,19769)@200
    assign rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19768_dupName_252_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19765_dupName_252_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19768_dupName_252_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2028_vt_select_21(BITSELECT,11028)@200
    assign i_unnamed_c_compmm_m2028_vt_select_21_b = rightShiftStage1_uid19770_dupName_252_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2028_vt_join(BITJOIN,11027)@200
    assign i_unnamed_c_compmm_m2028_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2028_vt_select_21_b};

    // i_unnamed_c_compmm_m2029_sel_x(BITSELECT,6077)@200
    assign i_unnamed_c_compmm_m2029_sel_x_b = i_unnamed_c_compmm_m2028_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2030_BitSelect_for_a(BITSELECT,28506)@200
    assign i_unnamed_c_compmm_m2030_BitSelect_for_a_b = i_unnamed_c_compmm_m2029_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2030_join(BITJOIN,28507)@200
    assign i_unnamed_c_compmm_m2030_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2030_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2030_vt_select_0(BITSELECT,11033)@200
    assign i_unnamed_c_compmm_m2030_vt_select_0_b = i_unnamed_c_compmm_m2030_join_q[0:0];

    // redist181_i_unnamed_c_compmm_m2030_vt_select_0_b_1(DELAY,29309)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist181_i_unnamed_c_compmm_m2030_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2030_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2030_vt_join(BITJOIN,11032)@201
    assign i_unnamed_c_compmm_m2030_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist181_i_unnamed_c_compmm_m2030_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_63_c_compmm_m2031(ADD,7118)@201
    assign i_add_i_i_i_i_i126_i_63_c_compmm_m2031_a = {1'b0, i_unnamed_c_compmm_m2030_vt_join_q};
    assign i_add_i_i_i_i_i126_i_63_c_compmm_m2031_b = {1'b0, redist1054_i_conv_i_i_i_i97_i_63_c_compmm_m2027_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_63_c_compmm_m2031_o = $unsigned(i_add_i_i_i_i_i126_i_63_c_compmm_m2031_a) + $unsigned(i_add_i_i_i_i_i126_i_63_c_compmm_m2031_b);
    assign i_add_i_i_i_i_i126_i_63_c_compmm_m2031_q = i_add_i_i_i_i_i126_i_63_c_compmm_m2031_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_63_c_compmm_m2031_sel_x(BITSELECT,2132)@201
    assign bgTrunc_i_add_i_i_i_i_i126_i_63_c_compmm_m2031_sel_x_b = i_add_i_i_i_i_i126_i_63_c_compmm_m2031_q[15:0];

    // i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_sel_x(BITSELECT,3665)@201
    assign i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_63_c_compmm_m2031_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_select_15(BITSELECT,7771)@201
    assign i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_select_15_b = i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_join(BITJOIN,7770)@201
    assign i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_select_15_b};

    // leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(MUX,25342)@201
    assign leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_join_q or leftShiftStage0Idx1_uid25341_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_64_c_compmm_m2052_vt_join_q;
            1'b1 : leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25341_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(MUX,25347)@201
    assign leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s or leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25346_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = leftShiftStage0_uid25343_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25346_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x(MUX,25352)@201
    assign leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s or leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25351_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = leftShiftStage1_uid25348_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25351_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28(BITSELECT,9721)@201
    assign i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28_b = leftShiftStage2_uid25353_i_shl_i_i_i_i_i77_i_64_c_compmm_m0_shift_x_q[28:13];

    // redist415_i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28_b_1(DELAY,29543)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist415_i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_join(BITJOIN,9720)@202
    assign i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_join_q = {redist415_i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma(CHAINMULTADD,29087)@196 + 5
    // out q@202
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_66148_c_compmm_m128_out_dest_data_out_130_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_66147_c_compmm_m129_out_dest_data_out_129_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ch[0] <= redist632_sync_together4364_aunroll_x_in_c1_eni5_130_tpl_128_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ch[1] <= redist631_sync_together4364_aunroll_x_in_c1_eni5_129_tpl_128_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054(ADD,8907)@202
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_64_i_c_compmm_m2049_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_64_i_c_compmm_m2051_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_64_i_c_compmm_m2050_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_64_c_compmm_m2053_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_o[33:0];

    // rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x(MUX,19808)@202
    assign rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q or rightShiftStage0Idx1_uid19807_dupName_255_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q;
            1'b1 : rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19807_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x(MUX,19813)@202
    assign rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19812_dupName_255_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19809_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19812_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x(MUX,19818)@202
    assign rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19817_dupName_255_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19814_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19817_dupName_255_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2055_vt_select_20(BITSELECT,11047)@202
    assign i_unnamed_c_compmm_m2055_vt_select_20_b = rightShiftStage2_uid19819_dupName_255_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2055_vt_join(BITJOIN,11046)@202
    assign i_unnamed_c_compmm_m2055_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2055_vt_select_20_b};

    // i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x(BITSELECT,3536)@202
    assign i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x_b = i_unnamed_c_compmm_m2055_vt_join_q[15:0];

    // redist1053_i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x_b_1(DELAY,30181)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1053_i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19828_dupName_256_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19827)@202
    assign rightShiftStage1Idx1Rng8_uid19828_dupName_256_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19830_dupName_256_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19829)@202
    assign rightShiftStage1Idx1_uid19830_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19828_dupName_256_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19823_dupName_256_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19822)@202
    assign rightShiftStage0Idx1Rng4_uid19823_dupName_256_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q[33:4];

    // rightShiftStage0Idx1_uid19825_dupName_256_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19824)@202
    assign rightShiftStage0Idx1_uid19825_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19823_dupName_256_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x(MUX,19826)@202
    assign rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q or rightShiftStage0Idx1_uid19825_dupName_256_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_64_i_c_compmm_m2054_q;
            1'b1 : rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19825_dupName_256_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x(MUX,19831)@202
    assign rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19830_dupName_256_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19827_dupName_256_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19830_dupName_256_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2057_vt_select_21(BITSELECT,11050)@202
    assign i_unnamed_c_compmm_m2057_vt_select_21_b = rightShiftStage1_uid19832_dupName_256_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2057_vt_join(BITJOIN,11049)@202
    assign i_unnamed_c_compmm_m2057_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2057_vt_select_21_b};

    // i_unnamed_c_compmm_m2058_sel_x(BITSELECT,6079)@202
    assign i_unnamed_c_compmm_m2058_sel_x_b = i_unnamed_c_compmm_m2057_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2059_BitSelect_for_a(BITSELECT,28510)@202
    assign i_unnamed_c_compmm_m2059_BitSelect_for_a_b = i_unnamed_c_compmm_m2058_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2059_join(BITJOIN,28511)@202
    assign i_unnamed_c_compmm_m2059_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2059_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2059_vt_select_0(BITSELECT,11055)@202
    assign i_unnamed_c_compmm_m2059_vt_select_0_b = i_unnamed_c_compmm_m2059_join_q[0:0];

    // redist179_i_unnamed_c_compmm_m2059_vt_select_0_b_1(DELAY,29307)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist179_i_unnamed_c_compmm_m2059_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2059_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2059_vt_join(BITJOIN,11054)@203
    assign i_unnamed_c_compmm_m2059_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist179_i_unnamed_c_compmm_m2059_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_64_c_compmm_m2060(ADD,7119)@203
    assign i_add_i_i_i_i_i126_i_64_c_compmm_m2060_a = {1'b0, i_unnamed_c_compmm_m2059_vt_join_q};
    assign i_add_i_i_i_i_i126_i_64_c_compmm_m2060_b = {1'b0, redist1053_i_conv_i_i_i_i97_i_64_c_compmm_m2056_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_64_c_compmm_m2060_o = $unsigned(i_add_i_i_i_i_i126_i_64_c_compmm_m2060_a) + $unsigned(i_add_i_i_i_i_i126_i_64_c_compmm_m2060_b);
    assign i_add_i_i_i_i_i126_i_64_c_compmm_m2060_q = i_add_i_i_i_i_i126_i_64_c_compmm_m2060_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_64_c_compmm_m2060_sel_x(BITSELECT,2133)@203
    assign bgTrunc_i_add_i_i_i_i_i126_i_64_c_compmm_m2060_sel_x_b = i_add_i_i_i_i_i126_i_64_c_compmm_m2060_q[15:0];

    // i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_sel_x(BITSELECT,3666)@203
    assign i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_64_c_compmm_m2060_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_select_15(BITSELECT,7775)@203
    assign i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_select_15_b = i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_join(BITJOIN,7774)@203
    assign i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_select_15_b};

    // leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(MUX,25360)@203
    assign leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_join_q or leftShiftStage0Idx1_uid25359_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_65_c_compmm_m2080_vt_join_q;
            1'b1 : leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25359_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(MUX,25365)@203
    assign leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s or leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25364_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = leftShiftStage0_uid25361_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25364_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x(MUX,25370)@203
    assign leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s or leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25369_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = leftShiftStage1_uid25366_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25369_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28(BITSELECT,9724)@203
    assign i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28_b = leftShiftStage2_uid25371_i_shl_i_i_i_i_i77_i_65_c_compmm_m0_shift_x_q[28:13];

    // redist414_i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28_b_1(DELAY,29542)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist414_i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_join(BITJOIN,9723)@204
    assign i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_join_q = {redist414_i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma(CHAINMULTADD,29088)@198 + 5
    // out q@204
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_66150_c_compmm_m126_out_dest_data_out_132_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_66149_c_compmm_m127_out_dest_data_out_131_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ch[0] <= redist634_sync_together4364_aunroll_x_in_c1_eni5_132_tpl_130_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ch[1] <= redist633_sync_together4364_aunroll_x_in_c1_eni5_131_tpl_130_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082(ADD,8908)@204
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_65_i_c_compmm_m2077_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_65_i_c_compmm_m2079_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_65_i_c_compmm_m2078_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_65_c_compmm_m2081_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_o[33:0];

    // rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x(MUX,19870)@204
    assign rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q or rightShiftStage0Idx1_uid19869_dupName_259_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q;
            1'b1 : rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19869_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x(MUX,19875)@204
    assign rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19874_dupName_259_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19871_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19874_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x(MUX,19880)@204
    assign rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19879_dupName_259_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19876_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19879_dupName_259_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2083_vt_select_20(BITSELECT,11069)@204
    assign i_unnamed_c_compmm_m2083_vt_select_20_b = rightShiftStage2_uid19881_dupName_259_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2083_vt_join(BITJOIN,11068)@204
    assign i_unnamed_c_compmm_m2083_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2083_vt_select_20_b};

    // i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x(BITSELECT,3537)@204
    assign i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x_b = i_unnamed_c_compmm_m2083_vt_join_q[15:0];

    // redist1052_i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x_b_1(DELAY,30180)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1052_i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19890_dupName_260_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19889)@204
    assign rightShiftStage1Idx1Rng8_uid19890_dupName_260_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19892_dupName_260_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19891)@204
    assign rightShiftStage1Idx1_uid19892_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19890_dupName_260_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19885_dupName_260_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19884)@204
    assign rightShiftStage0Idx1Rng4_uid19885_dupName_260_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q[33:4];

    // rightShiftStage0Idx1_uid19887_dupName_260_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19886)@204
    assign rightShiftStage0Idx1_uid19887_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19885_dupName_260_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x(MUX,19888)@204
    assign rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q or rightShiftStage0Idx1_uid19887_dupName_260_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_65_i_c_compmm_m2082_q;
            1'b1 : rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19887_dupName_260_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x(MUX,19893)@204
    assign rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19892_dupName_260_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19889_dupName_260_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19892_dupName_260_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2085_vt_select_21(BITSELECT,11072)@204
    assign i_unnamed_c_compmm_m2085_vt_select_21_b = rightShiftStage1_uid19894_dupName_260_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2085_vt_join(BITJOIN,11071)@204
    assign i_unnamed_c_compmm_m2085_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2085_vt_select_21_b};

    // i_unnamed_c_compmm_m2086_sel_x(BITSELECT,6081)@204
    assign i_unnamed_c_compmm_m2086_sel_x_b = i_unnamed_c_compmm_m2085_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2087_BitSelect_for_a(BITSELECT,28514)@204
    assign i_unnamed_c_compmm_m2087_BitSelect_for_a_b = i_unnamed_c_compmm_m2086_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2087_join(BITJOIN,28515)@204
    assign i_unnamed_c_compmm_m2087_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2087_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2087_vt_select_0(BITSELECT,11077)@204
    assign i_unnamed_c_compmm_m2087_vt_select_0_b = i_unnamed_c_compmm_m2087_join_q[0:0];

    // redist177_i_unnamed_c_compmm_m2087_vt_select_0_b_1(DELAY,29305)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist177_i_unnamed_c_compmm_m2087_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2087_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2087_vt_join(BITJOIN,11076)@205
    assign i_unnamed_c_compmm_m2087_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist177_i_unnamed_c_compmm_m2087_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_65_c_compmm_m2088(ADD,7120)@205
    assign i_add_i_i_i_i_i126_i_65_c_compmm_m2088_a = {1'b0, i_unnamed_c_compmm_m2087_vt_join_q};
    assign i_add_i_i_i_i_i126_i_65_c_compmm_m2088_b = {1'b0, redist1052_i_conv_i_i_i_i97_i_65_c_compmm_m2084_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_65_c_compmm_m2088_o = $unsigned(i_add_i_i_i_i_i126_i_65_c_compmm_m2088_a) + $unsigned(i_add_i_i_i_i_i126_i_65_c_compmm_m2088_b);
    assign i_add_i_i_i_i_i126_i_65_c_compmm_m2088_q = i_add_i_i_i_i_i126_i_65_c_compmm_m2088_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_65_c_compmm_m2088_sel_x(BITSELECT,2134)@205
    assign bgTrunc_i_add_i_i_i_i_i126_i_65_c_compmm_m2088_sel_x_b = i_add_i_i_i_i_i126_i_65_c_compmm_m2088_q[15:0];

    // i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_sel_x(BITSELECT,3667)@205
    assign i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_65_c_compmm_m2088_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_select_15(BITSELECT,7779)@205
    assign i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_select_15_b = i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_join(BITJOIN,7778)@205
    assign i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_select_15_b};

    // leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(MUX,25378)@205
    assign leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_join_q or leftShiftStage0Idx1_uid25377_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_66_c_compmm_m2108_vt_join_q;
            1'b1 : leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25377_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(MUX,25383)@205
    assign leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s or leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25382_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = leftShiftStage0_uid25379_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25382_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x(MUX,25388)@205
    assign leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s or leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25387_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = leftShiftStage1_uid25384_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25387_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28(BITSELECT,9727)@205
    assign i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28_b = leftShiftStage2_uid25389_i_shl_i_i_i_i_i77_i_66_c_compmm_m0_shift_x_q[28:13];

    // redist413_i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28_b_1(DELAY,29541)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist413_i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_join(BITJOIN,9726)@206
    assign i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_join_q = {redist413_i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma(CHAINMULTADD,29089)@200 + 5
    // out q@206
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_66152_c_compmm_m124_out_dest_data_out_134_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_66151_c_compmm_m125_out_dest_data_out_133_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ch[0] <= redist636_sync_together4364_aunroll_x_in_c1_eni5_134_tpl_132_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ch[1] <= redist635_sync_together4364_aunroll_x_in_c1_eni5_133_tpl_132_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110(ADD,8909)@206
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_66_i_c_compmm_m2105_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_66_i_c_compmm_m2107_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_66_i_c_compmm_m2106_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_66_c_compmm_m2109_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_o[33:0];

    // rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x(MUX,19932)@206
    assign rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q or rightShiftStage0Idx1_uid19931_dupName_263_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q;
            1'b1 : rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19931_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x(MUX,19937)@206
    assign rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19936_dupName_263_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19933_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19936_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x(MUX,19942)@206
    assign rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid19941_dupName_263_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid19938_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid19941_dupName_263_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2111_vt_select_20(BITSELECT,11091)@206
    assign i_unnamed_c_compmm_m2111_vt_select_20_b = rightShiftStage2_uid19943_dupName_263_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2111_vt_join(BITJOIN,11090)@206
    assign i_unnamed_c_compmm_m2111_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2111_vt_select_20_b};

    // i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x(BITSELECT,3538)@206
    assign i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x_b = i_unnamed_c_compmm_m2111_vt_join_q[15:0];

    // redist1051_i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x_b_1(DELAY,30179)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1051_i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid19952_dupName_264_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19951)@206
    assign rightShiftStage1Idx1Rng8_uid19952_dupName_264_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid19954_dupName_264_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19953)@206
    assign rightShiftStage1Idx1_uid19954_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid19952_dupName_264_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid19947_dupName_264_i_unnamed_c_compmm_m0_shift_x(BITSELECT,19946)@206
    assign rightShiftStage0Idx1Rng4_uid19947_dupName_264_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q[33:4];

    // rightShiftStage0Idx1_uid19949_dupName_264_i_unnamed_c_compmm_m0_shift_x(BITJOIN,19948)@206
    assign rightShiftStage0Idx1_uid19949_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid19947_dupName_264_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x(MUX,19950)@206
    assign rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q or rightShiftStage0Idx1_uid19949_dupName_264_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_66_i_c_compmm_m2110_q;
            1'b1 : rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19949_dupName_264_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x(MUX,19955)@206
    assign rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19954_dupName_264_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19951_dupName_264_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19954_dupName_264_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2113_vt_select_21(BITSELECT,11094)@206
    assign i_unnamed_c_compmm_m2113_vt_select_21_b = rightShiftStage1_uid19956_dupName_264_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2113_vt_join(BITJOIN,11093)@206
    assign i_unnamed_c_compmm_m2113_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2113_vt_select_21_b};

    // i_unnamed_c_compmm_m2114_sel_x(BITSELECT,6083)@206
    assign i_unnamed_c_compmm_m2114_sel_x_b = i_unnamed_c_compmm_m2113_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2115_BitSelect_for_a(BITSELECT,28518)@206
    assign i_unnamed_c_compmm_m2115_BitSelect_for_a_b = i_unnamed_c_compmm_m2114_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2115_join(BITJOIN,28519)@206
    assign i_unnamed_c_compmm_m2115_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2115_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2115_vt_select_0(BITSELECT,11099)@206
    assign i_unnamed_c_compmm_m2115_vt_select_0_b = i_unnamed_c_compmm_m2115_join_q[0:0];

    // redist175_i_unnamed_c_compmm_m2115_vt_select_0_b_1(DELAY,29303)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist175_i_unnamed_c_compmm_m2115_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2115_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2115_vt_join(BITJOIN,11098)@207
    assign i_unnamed_c_compmm_m2115_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist175_i_unnamed_c_compmm_m2115_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_66_c_compmm_m2116(ADD,7121)@207
    assign i_add_i_i_i_i_i126_i_66_c_compmm_m2116_a = {1'b0, i_unnamed_c_compmm_m2115_vt_join_q};
    assign i_add_i_i_i_i_i126_i_66_c_compmm_m2116_b = {1'b0, redist1051_i_conv_i_i_i_i97_i_66_c_compmm_m2112_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_66_c_compmm_m2116_o = $unsigned(i_add_i_i_i_i_i126_i_66_c_compmm_m2116_a) + $unsigned(i_add_i_i_i_i_i126_i_66_c_compmm_m2116_b);
    assign i_add_i_i_i_i_i126_i_66_c_compmm_m2116_q = i_add_i_i_i_i_i126_i_66_c_compmm_m2116_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_66_c_compmm_m2116_sel_x(BITSELECT,2135)@207
    assign bgTrunc_i_add_i_i_i_i_i126_i_66_c_compmm_m2116_sel_x_b = i_add_i_i_i_i_i126_i_66_c_compmm_m2116_q[15:0];

    // i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_sel_x(BITSELECT,3668)@207
    assign i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_66_c_compmm_m2116_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_select_15(BITSELECT,7783)@207
    assign i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_select_15_b = i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_join(BITJOIN,7782)@207
    assign i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_select_15_b};

    // leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(MUX,25396)@207
    assign leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_join_q or leftShiftStage0Idx1_uid25395_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_67_c_compmm_m2136_vt_join_q;
            1'b1 : leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25395_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(MUX,25401)@207
    assign leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s or leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25400_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = leftShiftStage0_uid25397_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25400_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x(MUX,25406)@207
    assign leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s or leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25405_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = leftShiftStage1_uid25402_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25405_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28(BITSELECT,9730)@207
    assign i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28_b = leftShiftStage2_uid25407_i_shl_i_i_i_i_i77_i_67_c_compmm_m0_shift_x_q[28:13];

    // redist412_i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28_b_1(DELAY,29540)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist412_i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_join(BITJOIN,9729)@208
    assign i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_join_q = {redist412_i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma(CHAINMULTADD,29090)@202 + 5
    // out q@208
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_66154_c_compmm_m122_out_dest_data_out_136_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_66153_c_compmm_m123_out_dest_data_out_135_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ch[0] <= redist638_sync_together4364_aunroll_x_in_c1_eni5_136_tpl_134_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ch[1] <= redist637_sync_together4364_aunroll_x_in_c1_eni5_135_tpl_134_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138(ADD,8910)@208
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_67_i_c_compmm_m2133_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_67_i_c_compmm_m2135_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_67_i_c_compmm_m2134_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_67_c_compmm_m2137_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_o[33:0];

    // rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x(MUX,19994)@208
    assign rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q or rightShiftStage0Idx1_uid19993_dupName_267_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q;
            1'b1 : rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid19993_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x(MUX,19999)@208
    assign rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid19998_dupName_267_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid19995_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid19998_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x(MUX,20004)@208
    assign rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20003_dupName_267_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20000_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20003_dupName_267_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2139_vt_select_20(BITSELECT,11113)@208
    assign i_unnamed_c_compmm_m2139_vt_select_20_b = rightShiftStage2_uid20005_dupName_267_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2139_vt_join(BITJOIN,11112)@208
    assign i_unnamed_c_compmm_m2139_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2139_vt_select_20_b};

    // i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x(BITSELECT,3539)@208
    assign i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x_b = i_unnamed_c_compmm_m2139_vt_join_q[15:0];

    // redist1050_i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x_b_1(DELAY,30178)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1050_i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20014_dupName_268_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20013)@208
    assign rightShiftStage1Idx1Rng8_uid20014_dupName_268_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20016_dupName_268_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20015)@208
    assign rightShiftStage1Idx1_uid20016_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20014_dupName_268_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20009_dupName_268_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20008)@208
    assign rightShiftStage0Idx1Rng4_uid20009_dupName_268_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q[33:4];

    // rightShiftStage0Idx1_uid20011_dupName_268_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20010)@208
    assign rightShiftStage0Idx1_uid20011_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20009_dupName_268_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x(MUX,20012)@208
    assign rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q or rightShiftStage0Idx1_uid20011_dupName_268_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_67_i_c_compmm_m2138_q;
            1'b1 : rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20011_dupName_268_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x(MUX,20017)@208
    assign rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20016_dupName_268_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20013_dupName_268_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20016_dupName_268_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2141_vt_select_21(BITSELECT,11116)@208
    assign i_unnamed_c_compmm_m2141_vt_select_21_b = rightShiftStage1_uid20018_dupName_268_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2141_vt_join(BITJOIN,11115)@208
    assign i_unnamed_c_compmm_m2141_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2141_vt_select_21_b};

    // i_unnamed_c_compmm_m2142_sel_x(BITSELECT,6085)@208
    assign i_unnamed_c_compmm_m2142_sel_x_b = i_unnamed_c_compmm_m2141_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2143_BitSelect_for_a(BITSELECT,28522)@208
    assign i_unnamed_c_compmm_m2143_BitSelect_for_a_b = i_unnamed_c_compmm_m2142_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2143_join(BITJOIN,28523)@208
    assign i_unnamed_c_compmm_m2143_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2143_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2143_vt_select_0(BITSELECT,11121)@208
    assign i_unnamed_c_compmm_m2143_vt_select_0_b = i_unnamed_c_compmm_m2143_join_q[0:0];

    // redist173_i_unnamed_c_compmm_m2143_vt_select_0_b_1(DELAY,29301)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist173_i_unnamed_c_compmm_m2143_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2143_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2143_vt_join(BITJOIN,11120)@209
    assign i_unnamed_c_compmm_m2143_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist173_i_unnamed_c_compmm_m2143_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_67_c_compmm_m2144(ADD,7122)@209
    assign i_add_i_i_i_i_i126_i_67_c_compmm_m2144_a = {1'b0, i_unnamed_c_compmm_m2143_vt_join_q};
    assign i_add_i_i_i_i_i126_i_67_c_compmm_m2144_b = {1'b0, redist1050_i_conv_i_i_i_i97_i_67_c_compmm_m2140_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_67_c_compmm_m2144_o = $unsigned(i_add_i_i_i_i_i126_i_67_c_compmm_m2144_a) + $unsigned(i_add_i_i_i_i_i126_i_67_c_compmm_m2144_b);
    assign i_add_i_i_i_i_i126_i_67_c_compmm_m2144_q = i_add_i_i_i_i_i126_i_67_c_compmm_m2144_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_67_c_compmm_m2144_sel_x(BITSELECT,2136)@209
    assign bgTrunc_i_add_i_i_i_i_i126_i_67_c_compmm_m2144_sel_x_b = i_add_i_i_i_i_i126_i_67_c_compmm_m2144_q[15:0];

    // i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_sel_x(BITSELECT,3669)@209
    assign i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_67_c_compmm_m2144_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_select_15(BITSELECT,7787)@209
    assign i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_select_15_b = i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_join(BITJOIN,7786)@209
    assign i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_select_15_b};

    // leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(MUX,25414)@209
    assign leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_join_q or leftShiftStage0Idx1_uid25413_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_68_c_compmm_m2164_vt_join_q;
            1'b1 : leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25413_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(MUX,25419)@209
    assign leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s or leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25418_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = leftShiftStage0_uid25415_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25418_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x(MUX,25424)@209
    assign leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s or leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25423_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = leftShiftStage1_uid25420_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25423_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28(BITSELECT,9733)@209
    assign i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28_b = leftShiftStage2_uid25425_i_shl_i_i_i_i_i77_i_68_c_compmm_m0_shift_x_q[28:13];

    // redist411_i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28_b_1(DELAY,29539)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist411_i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_join(BITJOIN,9732)@210
    assign i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_join_q = {redist411_i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma(CHAINMULTADD,29091)@204 + 5
    // out q@210
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_66156_c_compmm_m120_out_dest_data_out_138_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_66155_c_compmm_m121_out_dest_data_out_137_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ch[0] <= redist640_sync_together4364_aunroll_x_in_c1_eni5_138_tpl_136_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ch[1] <= redist639_sync_together4364_aunroll_x_in_c1_eni5_137_tpl_136_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166(ADD,8911)@210
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_68_i_c_compmm_m2161_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_68_i_c_compmm_m2163_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_68_i_c_compmm_m2162_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_68_c_compmm_m2165_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_o[33:0];

    // rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x(MUX,20056)@210
    assign rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q or rightShiftStage0Idx1_uid20055_dupName_271_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q;
            1'b1 : rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20055_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x(MUX,20061)@210
    assign rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20060_dupName_271_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20057_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20060_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x(MUX,20066)@210
    assign rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20065_dupName_271_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20062_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20065_dupName_271_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2167_vt_select_20(BITSELECT,11135)@210
    assign i_unnamed_c_compmm_m2167_vt_select_20_b = rightShiftStage2_uid20067_dupName_271_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2167_vt_join(BITJOIN,11134)@210
    assign i_unnamed_c_compmm_m2167_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2167_vt_select_20_b};

    // i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x(BITSELECT,3540)@210
    assign i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x_b = i_unnamed_c_compmm_m2167_vt_join_q[15:0];

    // redist1049_i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x_b_1(DELAY,30177)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1049_i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20076_dupName_272_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20075)@210
    assign rightShiftStage1Idx1Rng8_uid20076_dupName_272_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20078_dupName_272_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20077)@210
    assign rightShiftStage1Idx1_uid20078_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20076_dupName_272_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20071_dupName_272_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20070)@210
    assign rightShiftStage0Idx1Rng4_uid20071_dupName_272_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q[33:4];

    // rightShiftStage0Idx1_uid20073_dupName_272_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20072)@210
    assign rightShiftStage0Idx1_uid20073_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20071_dupName_272_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x(MUX,20074)@210
    assign rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q or rightShiftStage0Idx1_uid20073_dupName_272_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_68_i_c_compmm_m2166_q;
            1'b1 : rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20073_dupName_272_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x(MUX,20079)@210
    assign rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20078_dupName_272_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20075_dupName_272_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20078_dupName_272_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2169_vt_select_21(BITSELECT,11138)@210
    assign i_unnamed_c_compmm_m2169_vt_select_21_b = rightShiftStage1_uid20080_dupName_272_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2169_vt_join(BITJOIN,11137)@210
    assign i_unnamed_c_compmm_m2169_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2169_vt_select_21_b};

    // i_unnamed_c_compmm_m2170_sel_x(BITSELECT,6087)@210
    assign i_unnamed_c_compmm_m2170_sel_x_b = i_unnamed_c_compmm_m2169_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2171_BitSelect_for_a(BITSELECT,28526)@210
    assign i_unnamed_c_compmm_m2171_BitSelect_for_a_b = i_unnamed_c_compmm_m2170_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2171_join(BITJOIN,28527)@210
    assign i_unnamed_c_compmm_m2171_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2171_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2171_vt_select_0(BITSELECT,11143)@210
    assign i_unnamed_c_compmm_m2171_vt_select_0_b = i_unnamed_c_compmm_m2171_join_q[0:0];

    // redist171_i_unnamed_c_compmm_m2171_vt_select_0_b_1(DELAY,29299)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist171_i_unnamed_c_compmm_m2171_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2171_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2171_vt_join(BITJOIN,11142)@211
    assign i_unnamed_c_compmm_m2171_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist171_i_unnamed_c_compmm_m2171_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_68_c_compmm_m2172(ADD,7123)@211
    assign i_add_i_i_i_i_i126_i_68_c_compmm_m2172_a = {1'b0, i_unnamed_c_compmm_m2171_vt_join_q};
    assign i_add_i_i_i_i_i126_i_68_c_compmm_m2172_b = {1'b0, redist1049_i_conv_i_i_i_i97_i_68_c_compmm_m2168_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_68_c_compmm_m2172_o = $unsigned(i_add_i_i_i_i_i126_i_68_c_compmm_m2172_a) + $unsigned(i_add_i_i_i_i_i126_i_68_c_compmm_m2172_b);
    assign i_add_i_i_i_i_i126_i_68_c_compmm_m2172_q = i_add_i_i_i_i_i126_i_68_c_compmm_m2172_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_68_c_compmm_m2172_sel_x(BITSELECT,2137)@211
    assign bgTrunc_i_add_i_i_i_i_i126_i_68_c_compmm_m2172_sel_x_b = i_add_i_i_i_i_i126_i_68_c_compmm_m2172_q[15:0];

    // i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_sel_x(BITSELECT,3670)@211
    assign i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_68_c_compmm_m2172_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_select_15(BITSELECT,7791)@211
    assign i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_select_15_b = i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_join(BITJOIN,7790)@211
    assign i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_select_15_b};

    // leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(MUX,25432)@211
    assign leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_join_q or leftShiftStage0Idx1_uid25431_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_69_c_compmm_m2192_vt_join_q;
            1'b1 : leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25431_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(MUX,25437)@211
    assign leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s or leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25436_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = leftShiftStage0_uid25433_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25436_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x(MUX,25442)@211
    assign leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s or leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25441_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = leftShiftStage1_uid25438_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25441_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28(BITSELECT,9736)@211
    assign i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28_b = leftShiftStage2_uid25443_i_shl_i_i_i_i_i77_i_69_c_compmm_m0_shift_x_q[28:13];

    // redist410_i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28_b_1(DELAY,29538)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist410_i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_join(BITJOIN,9735)@212
    assign i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_join_q = {redist410_i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma(CHAINMULTADD,29092)@206 + 5
    // out q@212
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_66158_c_compmm_m118_out_dest_data_out_140_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_66157_c_compmm_m119_out_dest_data_out_139_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ch[0] <= redist642_sync_together4364_aunroll_x_in_c1_eni5_140_tpl_138_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ch[1] <= redist641_sync_together4364_aunroll_x_in_c1_eni5_139_tpl_138_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194(ADD,8912)@212
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_69_i_c_compmm_m2189_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_69_i_c_compmm_m2191_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_69_i_c_compmm_m2190_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_69_c_compmm_m2193_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_o[33:0];

    // rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x(MUX,20118)@212
    assign rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q or rightShiftStage0Idx1_uid20117_dupName_275_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q;
            1'b1 : rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20117_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x(MUX,20123)@212
    assign rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20122_dupName_275_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20119_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20122_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x(MUX,20128)@212
    assign rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20127_dupName_275_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20124_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20127_dupName_275_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2195_vt_select_20(BITSELECT,11157)@212
    assign i_unnamed_c_compmm_m2195_vt_select_20_b = rightShiftStage2_uid20129_dupName_275_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2195_vt_join(BITJOIN,11156)@212
    assign i_unnamed_c_compmm_m2195_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2195_vt_select_20_b};

    // i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x(BITSELECT,3541)@212
    assign i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x_b = i_unnamed_c_compmm_m2195_vt_join_q[15:0];

    // redist1048_i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x_b_1(DELAY,30176)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1048_i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20138_dupName_276_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20137)@212
    assign rightShiftStage1Idx1Rng8_uid20138_dupName_276_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20140_dupName_276_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20139)@212
    assign rightShiftStage1Idx1_uid20140_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20138_dupName_276_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20133_dupName_276_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20132)@212
    assign rightShiftStage0Idx1Rng4_uid20133_dupName_276_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q[33:4];

    // rightShiftStage0Idx1_uid20135_dupName_276_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20134)@212
    assign rightShiftStage0Idx1_uid20135_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20133_dupName_276_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x(MUX,20136)@212
    assign rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q or rightShiftStage0Idx1_uid20135_dupName_276_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_69_i_c_compmm_m2194_q;
            1'b1 : rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20135_dupName_276_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x(MUX,20141)@212
    assign rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20140_dupName_276_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20137_dupName_276_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20140_dupName_276_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2197_vt_select_21(BITSELECT,11160)@212
    assign i_unnamed_c_compmm_m2197_vt_select_21_b = rightShiftStage1_uid20142_dupName_276_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2197_vt_join(BITJOIN,11159)@212
    assign i_unnamed_c_compmm_m2197_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2197_vt_select_21_b};

    // i_unnamed_c_compmm_m2198_sel_x(BITSELECT,6089)@212
    assign i_unnamed_c_compmm_m2198_sel_x_b = i_unnamed_c_compmm_m2197_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2199_BitSelect_for_a(BITSELECT,28530)@212
    assign i_unnamed_c_compmm_m2199_BitSelect_for_a_b = i_unnamed_c_compmm_m2198_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2199_join(BITJOIN,28531)@212
    assign i_unnamed_c_compmm_m2199_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2199_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2199_vt_select_0(BITSELECT,11165)@212
    assign i_unnamed_c_compmm_m2199_vt_select_0_b = i_unnamed_c_compmm_m2199_join_q[0:0];

    // redist169_i_unnamed_c_compmm_m2199_vt_select_0_b_1(DELAY,29297)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist169_i_unnamed_c_compmm_m2199_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2199_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2199_vt_join(BITJOIN,11164)@213
    assign i_unnamed_c_compmm_m2199_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist169_i_unnamed_c_compmm_m2199_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_69_c_compmm_m2200(ADD,7124)@213
    assign i_add_i_i_i_i_i126_i_69_c_compmm_m2200_a = {1'b0, i_unnamed_c_compmm_m2199_vt_join_q};
    assign i_add_i_i_i_i_i126_i_69_c_compmm_m2200_b = {1'b0, redist1048_i_conv_i_i_i_i97_i_69_c_compmm_m2196_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_69_c_compmm_m2200_o = $unsigned(i_add_i_i_i_i_i126_i_69_c_compmm_m2200_a) + $unsigned(i_add_i_i_i_i_i126_i_69_c_compmm_m2200_b);
    assign i_add_i_i_i_i_i126_i_69_c_compmm_m2200_q = i_add_i_i_i_i_i126_i_69_c_compmm_m2200_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_69_c_compmm_m2200_sel_x(BITSELECT,2138)@213
    assign bgTrunc_i_add_i_i_i_i_i126_i_69_c_compmm_m2200_sel_x_b = i_add_i_i_i_i_i126_i_69_c_compmm_m2200_q[15:0];

    // i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_sel_x(BITSELECT,3672)@213
    assign i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_69_c_compmm_m2200_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_select_15(BITSELECT,7799)@213
    assign i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_select_15_b = i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_join(BITJOIN,7798)@213
    assign i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_select_15_b};

    // leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(MUX,25468)@213
    assign leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_join_q or leftShiftStage0Idx1_uid25467_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_70_c_compmm_m2220_vt_join_q;
            1'b1 : leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25467_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(MUX,25473)@213
    assign leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s or leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25472_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = leftShiftStage0_uid25469_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25472_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x(MUX,25478)@213
    assign leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s or leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25477_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = leftShiftStage1_uid25474_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25477_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28(BITSELECT,9742)@213
    assign i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28_b = leftShiftStage2_uid25479_i_shl_i_i_i_i_i77_i_70_c_compmm_m0_shift_x_q[28:13];

    // redist408_i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28_b_1(DELAY,29536)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist408_i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_join(BITJOIN,9741)@214
    assign i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_join_q = {redist408_i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma(CHAINMULTADD,29094)@208 + 5
    // out q@214
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_66160_c_compmm_m116_out_dest_data_out_142_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_66159_c_compmm_m117_out_dest_data_out_141_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ch[0] <= redist644_sync_together4364_aunroll_x_in_c1_eni5_142_tpl_140_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ch[1] <= redist643_sync_together4364_aunroll_x_in_c1_eni5_141_tpl_140_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222(ADD,8914)@214
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_70_i_c_compmm_m2217_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_70_i_c_compmm_m2219_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_70_i_c_compmm_m2218_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_70_c_compmm_m2221_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_o[33:0];

    // rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x(MUX,20180)@214
    assign rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q or rightShiftStage0Idx1_uid20179_dupName_279_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q;
            1'b1 : rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20179_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x(MUX,20185)@214
    assign rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20184_dupName_279_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20181_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20184_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x(MUX,20190)@214
    assign rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20189_dupName_279_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20186_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20189_dupName_279_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2223_vt_select_20(BITSELECT,11179)@214
    assign i_unnamed_c_compmm_m2223_vt_select_20_b = rightShiftStage2_uid20191_dupName_279_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2223_vt_join(BITJOIN,11178)@214
    assign i_unnamed_c_compmm_m2223_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2223_vt_select_20_b};

    // i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x(BITSELECT,3543)@214
    assign i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x_b = i_unnamed_c_compmm_m2223_vt_join_q[15:0];

    // redist1046_i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x_b_1(DELAY,30174)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1046_i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20200_dupName_280_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20199)@214
    assign rightShiftStage1Idx1Rng8_uid20200_dupName_280_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20202_dupName_280_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20201)@214
    assign rightShiftStage1Idx1_uid20202_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20200_dupName_280_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20195_dupName_280_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20194)@214
    assign rightShiftStage0Idx1Rng4_uid20195_dupName_280_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q[33:4];

    // rightShiftStage0Idx1_uid20197_dupName_280_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20196)@214
    assign rightShiftStage0Idx1_uid20197_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20195_dupName_280_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x(MUX,20198)@214
    assign rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q or rightShiftStage0Idx1_uid20197_dupName_280_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_70_i_c_compmm_m2222_q;
            1'b1 : rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20197_dupName_280_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x(MUX,20203)@214
    assign rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20202_dupName_280_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20199_dupName_280_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20202_dupName_280_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2225_vt_select_21(BITSELECT,11182)@214
    assign i_unnamed_c_compmm_m2225_vt_select_21_b = rightShiftStage1_uid20204_dupName_280_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2225_vt_join(BITJOIN,11181)@214
    assign i_unnamed_c_compmm_m2225_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2225_vt_select_21_b};

    // i_unnamed_c_compmm_m2226_sel_x(BITSELECT,6091)@214
    assign i_unnamed_c_compmm_m2226_sel_x_b = i_unnamed_c_compmm_m2225_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2227_BitSelect_for_a(BITSELECT,28534)@214
    assign i_unnamed_c_compmm_m2227_BitSelect_for_a_b = i_unnamed_c_compmm_m2226_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2227_join(BITJOIN,28535)@214
    assign i_unnamed_c_compmm_m2227_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2227_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2227_vt_select_0(BITSELECT,11187)@214
    assign i_unnamed_c_compmm_m2227_vt_select_0_b = i_unnamed_c_compmm_m2227_join_q[0:0];

    // redist167_i_unnamed_c_compmm_m2227_vt_select_0_b_1(DELAY,29295)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist167_i_unnamed_c_compmm_m2227_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2227_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2227_vt_join(BITJOIN,11186)@215
    assign i_unnamed_c_compmm_m2227_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist167_i_unnamed_c_compmm_m2227_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_70_c_compmm_m2228(ADD,7126)@215
    assign i_add_i_i_i_i_i126_i_70_c_compmm_m2228_a = {1'b0, i_unnamed_c_compmm_m2227_vt_join_q};
    assign i_add_i_i_i_i_i126_i_70_c_compmm_m2228_b = {1'b0, redist1046_i_conv_i_i_i_i97_i_70_c_compmm_m2224_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_70_c_compmm_m2228_o = $unsigned(i_add_i_i_i_i_i126_i_70_c_compmm_m2228_a) + $unsigned(i_add_i_i_i_i_i126_i_70_c_compmm_m2228_b);
    assign i_add_i_i_i_i_i126_i_70_c_compmm_m2228_q = i_add_i_i_i_i_i126_i_70_c_compmm_m2228_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_70_c_compmm_m2228_sel_x(BITSELECT,2140)@215
    assign bgTrunc_i_add_i_i_i_i_i126_i_70_c_compmm_m2228_sel_x_b = i_add_i_i_i_i_i126_i_70_c_compmm_m2228_q[15:0];

    // i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_sel_x(BITSELECT,3673)@215
    assign i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_70_c_compmm_m2228_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_select_15(BITSELECT,7803)@215
    assign i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_select_15_b = i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_join(BITJOIN,7802)@215
    assign i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_select_15_b};

    // leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(MUX,25486)@215
    assign leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_join_q or leftShiftStage0Idx1_uid25485_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_71_c_compmm_m2248_vt_join_q;
            1'b1 : leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25485_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(MUX,25491)@215
    assign leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s or leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25490_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = leftShiftStage0_uid25487_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25490_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x(MUX,25496)@215
    assign leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s or leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25495_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = leftShiftStage1_uid25492_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25495_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28(BITSELECT,9745)@215
    assign i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28_b = leftShiftStage2_uid25497_i_shl_i_i_i_i_i77_i_71_c_compmm_m0_shift_x_q[28:13];

    // redist407_i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28_b_1(DELAY,29535)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist407_i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_join(BITJOIN,9744)@216
    assign i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_join_q = {redist407_i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma(CHAINMULTADD,29095)@210 + 5
    // out q@216
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_66162_c_compmm_m114_out_dest_data_out_144_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_66161_c_compmm_m115_out_dest_data_out_143_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ch[0] <= redist646_sync_together4364_aunroll_x_in_c1_eni5_144_tpl_142_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ch[1] <= redist645_sync_together4364_aunroll_x_in_c1_eni5_143_tpl_142_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250(ADD,8915)@216
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_71_i_c_compmm_m2245_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_71_i_c_compmm_m2247_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_71_i_c_compmm_m2246_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_71_c_compmm_m2249_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_o[33:0];

    // rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x(MUX,20242)@216
    assign rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q or rightShiftStage0Idx1_uid20241_dupName_283_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q;
            1'b1 : rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20241_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x(MUX,20247)@216
    assign rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20246_dupName_283_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20243_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20246_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x(MUX,20252)@216
    assign rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20251_dupName_283_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20248_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20251_dupName_283_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2251_vt_select_20(BITSELECT,11201)@216
    assign i_unnamed_c_compmm_m2251_vt_select_20_b = rightShiftStage2_uid20253_dupName_283_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2251_vt_join(BITJOIN,11200)@216
    assign i_unnamed_c_compmm_m2251_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2251_vt_select_20_b};

    // i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x(BITSELECT,3544)@216
    assign i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x_b = i_unnamed_c_compmm_m2251_vt_join_q[15:0];

    // redist1045_i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x_b_1(DELAY,30173)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1045_i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20262_dupName_284_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20261)@216
    assign rightShiftStage1Idx1Rng8_uid20262_dupName_284_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20264_dupName_284_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20263)@216
    assign rightShiftStage1Idx1_uid20264_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20262_dupName_284_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20257_dupName_284_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20256)@216
    assign rightShiftStage0Idx1Rng4_uid20257_dupName_284_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q[33:4];

    // rightShiftStage0Idx1_uid20259_dupName_284_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20258)@216
    assign rightShiftStage0Idx1_uid20259_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20257_dupName_284_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x(MUX,20260)@216
    assign rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q or rightShiftStage0Idx1_uid20259_dupName_284_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_71_i_c_compmm_m2250_q;
            1'b1 : rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20259_dupName_284_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x(MUX,20265)@216
    assign rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20264_dupName_284_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20261_dupName_284_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20264_dupName_284_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2253_vt_select_21(BITSELECT,11204)@216
    assign i_unnamed_c_compmm_m2253_vt_select_21_b = rightShiftStage1_uid20266_dupName_284_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2253_vt_join(BITJOIN,11203)@216
    assign i_unnamed_c_compmm_m2253_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2253_vt_select_21_b};

    // i_unnamed_c_compmm_m2254_sel_x(BITSELECT,6093)@216
    assign i_unnamed_c_compmm_m2254_sel_x_b = i_unnamed_c_compmm_m2253_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2255_BitSelect_for_a(BITSELECT,28538)@216
    assign i_unnamed_c_compmm_m2255_BitSelect_for_a_b = i_unnamed_c_compmm_m2254_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2255_join(BITJOIN,28539)@216
    assign i_unnamed_c_compmm_m2255_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2255_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2255_vt_select_0(BITSELECT,11209)@216
    assign i_unnamed_c_compmm_m2255_vt_select_0_b = i_unnamed_c_compmm_m2255_join_q[0:0];

    // redist165_i_unnamed_c_compmm_m2255_vt_select_0_b_1(DELAY,29293)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist165_i_unnamed_c_compmm_m2255_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2255_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2255_vt_join(BITJOIN,11208)@217
    assign i_unnamed_c_compmm_m2255_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist165_i_unnamed_c_compmm_m2255_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_71_c_compmm_m2256(ADD,7127)@217
    assign i_add_i_i_i_i_i126_i_71_c_compmm_m2256_a = {1'b0, i_unnamed_c_compmm_m2255_vt_join_q};
    assign i_add_i_i_i_i_i126_i_71_c_compmm_m2256_b = {1'b0, redist1045_i_conv_i_i_i_i97_i_71_c_compmm_m2252_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_71_c_compmm_m2256_o = $unsigned(i_add_i_i_i_i_i126_i_71_c_compmm_m2256_a) + $unsigned(i_add_i_i_i_i_i126_i_71_c_compmm_m2256_b);
    assign i_add_i_i_i_i_i126_i_71_c_compmm_m2256_q = i_add_i_i_i_i_i126_i_71_c_compmm_m2256_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_71_c_compmm_m2256_sel_x(BITSELECT,2141)@217
    assign bgTrunc_i_add_i_i_i_i_i126_i_71_c_compmm_m2256_sel_x_b = i_add_i_i_i_i_i126_i_71_c_compmm_m2256_q[15:0];

    // i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_sel_x(BITSELECT,3674)@217
    assign i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_71_c_compmm_m2256_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_select_15(BITSELECT,7807)@217
    assign i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_select_15_b = i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_join(BITJOIN,7806)@217
    assign i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_select_15_b};

    // leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(MUX,25504)@217
    assign leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_join_q or leftShiftStage0Idx1_uid25503_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_72_c_compmm_m2276_vt_join_q;
            1'b1 : leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25503_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(MUX,25509)@217
    assign leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s or leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25508_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = leftShiftStage0_uid25505_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25508_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x(MUX,25514)@217
    assign leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s or leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25513_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = leftShiftStage1_uid25510_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25513_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28(BITSELECT,9748)@217
    assign i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28_b = leftShiftStage2_uid25515_i_shl_i_i_i_i_i77_i_72_c_compmm_m0_shift_x_q[28:13];

    // redist406_i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28_b_1(DELAY,29534)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist406_i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_join(BITJOIN,9747)@218
    assign i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_join_q = {redist406_i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma(CHAINMULTADD,29096)@212 + 5
    // out q@218
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_66164_c_compmm_m112_out_dest_data_out_146_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_66163_c_compmm_m113_out_dest_data_out_145_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ch[0] <= redist648_sync_together4364_aunroll_x_in_c1_eni5_146_tpl_144_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ch[1] <= redist647_sync_together4364_aunroll_x_in_c1_eni5_145_tpl_144_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278(ADD,8916)@218
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_72_i_c_compmm_m2273_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_72_i_c_compmm_m2275_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_72_i_c_compmm_m2274_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_72_c_compmm_m2277_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_o[33:0];

    // rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x(MUX,20304)@218
    assign rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q or rightShiftStage0Idx1_uid20303_dupName_287_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q;
            1'b1 : rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20303_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x(MUX,20309)@218
    assign rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20308_dupName_287_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20305_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20308_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x(MUX,20314)@218
    assign rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20313_dupName_287_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20310_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20313_dupName_287_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2279_vt_select_20(BITSELECT,11223)@218
    assign i_unnamed_c_compmm_m2279_vt_select_20_b = rightShiftStage2_uid20315_dupName_287_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2279_vt_join(BITJOIN,11222)@218
    assign i_unnamed_c_compmm_m2279_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2279_vt_select_20_b};

    // i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x(BITSELECT,3545)@218
    assign i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x_b = i_unnamed_c_compmm_m2279_vt_join_q[15:0];

    // redist1044_i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x_b_1(DELAY,30172)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1044_i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20324_dupName_288_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20323)@218
    assign rightShiftStage1Idx1Rng8_uid20324_dupName_288_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20326_dupName_288_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20325)@218
    assign rightShiftStage1Idx1_uid20326_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20324_dupName_288_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20319_dupName_288_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20318)@218
    assign rightShiftStage0Idx1Rng4_uid20319_dupName_288_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q[33:4];

    // rightShiftStage0Idx1_uid20321_dupName_288_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20320)@218
    assign rightShiftStage0Idx1_uid20321_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20319_dupName_288_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x(MUX,20322)@218
    assign rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q or rightShiftStage0Idx1_uid20321_dupName_288_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_72_i_c_compmm_m2278_q;
            1'b1 : rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20321_dupName_288_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x(MUX,20327)@218
    assign rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20326_dupName_288_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20323_dupName_288_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20326_dupName_288_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2281_vt_select_21(BITSELECT,11226)@218
    assign i_unnamed_c_compmm_m2281_vt_select_21_b = rightShiftStage1_uid20328_dupName_288_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2281_vt_join(BITJOIN,11225)@218
    assign i_unnamed_c_compmm_m2281_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2281_vt_select_21_b};

    // i_unnamed_c_compmm_m2282_sel_x(BITSELECT,6095)@218
    assign i_unnamed_c_compmm_m2282_sel_x_b = i_unnamed_c_compmm_m2281_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2283_BitSelect_for_a(BITSELECT,28542)@218
    assign i_unnamed_c_compmm_m2283_BitSelect_for_a_b = i_unnamed_c_compmm_m2282_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2283_join(BITJOIN,28543)@218
    assign i_unnamed_c_compmm_m2283_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2283_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2283_vt_select_0(BITSELECT,11231)@218
    assign i_unnamed_c_compmm_m2283_vt_select_0_b = i_unnamed_c_compmm_m2283_join_q[0:0];

    // redist163_i_unnamed_c_compmm_m2283_vt_select_0_b_1(DELAY,29291)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist163_i_unnamed_c_compmm_m2283_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2283_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2283_vt_join(BITJOIN,11230)@219
    assign i_unnamed_c_compmm_m2283_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist163_i_unnamed_c_compmm_m2283_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_72_c_compmm_m2284(ADD,7128)@219
    assign i_add_i_i_i_i_i126_i_72_c_compmm_m2284_a = {1'b0, i_unnamed_c_compmm_m2283_vt_join_q};
    assign i_add_i_i_i_i_i126_i_72_c_compmm_m2284_b = {1'b0, redist1044_i_conv_i_i_i_i97_i_72_c_compmm_m2280_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_72_c_compmm_m2284_o = $unsigned(i_add_i_i_i_i_i126_i_72_c_compmm_m2284_a) + $unsigned(i_add_i_i_i_i_i126_i_72_c_compmm_m2284_b);
    assign i_add_i_i_i_i_i126_i_72_c_compmm_m2284_q = i_add_i_i_i_i_i126_i_72_c_compmm_m2284_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_72_c_compmm_m2284_sel_x(BITSELECT,2142)@219
    assign bgTrunc_i_add_i_i_i_i_i126_i_72_c_compmm_m2284_sel_x_b = i_add_i_i_i_i_i126_i_72_c_compmm_m2284_q[15:0];

    // i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_sel_x(BITSELECT,3675)@219
    assign i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_72_c_compmm_m2284_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_select_15(BITSELECT,7811)@219
    assign i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_select_15_b = i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_join(BITJOIN,7810)@219
    assign i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_select_15_b};

    // leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(MUX,25522)@219
    assign leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_join_q or leftShiftStage0Idx1_uid25521_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_73_c_compmm_m2304_vt_join_q;
            1'b1 : leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25521_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(MUX,25527)@219
    assign leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s or leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25526_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = leftShiftStage0_uid25523_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25526_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x(MUX,25532)@219
    assign leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s or leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25531_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = leftShiftStage1_uid25528_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25531_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28(BITSELECT,9751)@219
    assign i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28_b = leftShiftStage2_uid25533_i_shl_i_i_i_i_i77_i_73_c_compmm_m0_shift_x_q[28:13];

    // redist405_i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28_b_1(DELAY,29533)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist405_i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_join(BITJOIN,9750)@220
    assign i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_join_q = {redist405_i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma(CHAINMULTADD,29097)@214 + 5
    // out q@220
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_66166_c_compmm_m110_out_dest_data_out_148_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_66165_c_compmm_m111_out_dest_data_out_147_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ch[0] <= redist650_sync_together4364_aunroll_x_in_c1_eni5_148_tpl_146_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ch[1] <= redist649_sync_together4364_aunroll_x_in_c1_eni5_147_tpl_146_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306(ADD,8917)@220
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_73_i_c_compmm_m2301_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_73_i_c_compmm_m2303_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_73_i_c_compmm_m2302_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_73_c_compmm_m2305_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_o[33:0];

    // rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x(MUX,20366)@220
    assign rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q or rightShiftStage0Idx1_uid20365_dupName_291_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q;
            1'b1 : rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20365_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x(MUX,20371)@220
    assign rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20370_dupName_291_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20367_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20370_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x(MUX,20376)@220
    assign rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20375_dupName_291_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20372_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20375_dupName_291_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2307_vt_select_20(BITSELECT,11245)@220
    assign i_unnamed_c_compmm_m2307_vt_select_20_b = rightShiftStage2_uid20377_dupName_291_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2307_vt_join(BITJOIN,11244)@220
    assign i_unnamed_c_compmm_m2307_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2307_vt_select_20_b};

    // i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x(BITSELECT,3546)@220
    assign i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x_b = i_unnamed_c_compmm_m2307_vt_join_q[15:0];

    // redist1043_i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x_b_1(DELAY,30171)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1043_i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20386_dupName_292_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20385)@220
    assign rightShiftStage1Idx1Rng8_uid20386_dupName_292_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20388_dupName_292_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20387)@220
    assign rightShiftStage1Idx1_uid20388_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20386_dupName_292_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20381_dupName_292_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20380)@220
    assign rightShiftStage0Idx1Rng4_uid20381_dupName_292_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q[33:4];

    // rightShiftStage0Idx1_uid20383_dupName_292_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20382)@220
    assign rightShiftStage0Idx1_uid20383_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20381_dupName_292_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x(MUX,20384)@220
    assign rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q or rightShiftStage0Idx1_uid20383_dupName_292_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_73_i_c_compmm_m2306_q;
            1'b1 : rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20383_dupName_292_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x(MUX,20389)@220
    assign rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20388_dupName_292_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20385_dupName_292_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20388_dupName_292_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2309_vt_select_21(BITSELECT,11248)@220
    assign i_unnamed_c_compmm_m2309_vt_select_21_b = rightShiftStage1_uid20390_dupName_292_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2309_vt_join(BITJOIN,11247)@220
    assign i_unnamed_c_compmm_m2309_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2309_vt_select_21_b};

    // i_unnamed_c_compmm_m2310_sel_x(BITSELECT,6097)@220
    assign i_unnamed_c_compmm_m2310_sel_x_b = i_unnamed_c_compmm_m2309_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2311_BitSelect_for_a(BITSELECT,28546)@220
    assign i_unnamed_c_compmm_m2311_BitSelect_for_a_b = i_unnamed_c_compmm_m2310_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2311_join(BITJOIN,28547)@220
    assign i_unnamed_c_compmm_m2311_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2311_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2311_vt_select_0(BITSELECT,11253)@220
    assign i_unnamed_c_compmm_m2311_vt_select_0_b = i_unnamed_c_compmm_m2311_join_q[0:0];

    // redist161_i_unnamed_c_compmm_m2311_vt_select_0_b_1(DELAY,29289)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist161_i_unnamed_c_compmm_m2311_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2311_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2311_vt_join(BITJOIN,11252)@221
    assign i_unnamed_c_compmm_m2311_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist161_i_unnamed_c_compmm_m2311_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_73_c_compmm_m2312(ADD,7129)@221
    assign i_add_i_i_i_i_i126_i_73_c_compmm_m2312_a = {1'b0, i_unnamed_c_compmm_m2311_vt_join_q};
    assign i_add_i_i_i_i_i126_i_73_c_compmm_m2312_b = {1'b0, redist1043_i_conv_i_i_i_i97_i_73_c_compmm_m2308_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_73_c_compmm_m2312_o = $unsigned(i_add_i_i_i_i_i126_i_73_c_compmm_m2312_a) + $unsigned(i_add_i_i_i_i_i126_i_73_c_compmm_m2312_b);
    assign i_add_i_i_i_i_i126_i_73_c_compmm_m2312_q = i_add_i_i_i_i_i126_i_73_c_compmm_m2312_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_73_c_compmm_m2312_sel_x(BITSELECT,2143)@221
    assign bgTrunc_i_add_i_i_i_i_i126_i_73_c_compmm_m2312_sel_x_b = i_add_i_i_i_i_i126_i_73_c_compmm_m2312_q[15:0];

    // i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_sel_x(BITSELECT,3676)@221
    assign i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_73_c_compmm_m2312_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_select_15(BITSELECT,7815)@221
    assign i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_select_15_b = i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_join(BITJOIN,7814)@221
    assign i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_select_15_b};

    // leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(MUX,25540)@221
    assign leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_join_q or leftShiftStage0Idx1_uid25539_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_74_c_compmm_m2332_vt_join_q;
            1'b1 : leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25539_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(MUX,25545)@221
    assign leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s or leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25544_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = leftShiftStage0_uid25541_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25544_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x(MUX,25550)@221
    assign leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s or leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25549_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = leftShiftStage1_uid25546_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25549_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28(BITSELECT,9754)@221
    assign i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28_b = leftShiftStage2_uid25551_i_shl_i_i_i_i_i77_i_74_c_compmm_m0_shift_x_q[28:13];

    // redist404_i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28_b_1(DELAY,29532)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist404_i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_join(BITJOIN,9753)@222
    assign i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_join_q = {redist404_i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma(CHAINMULTADD,29098)@216 + 5
    // out q@222
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_66168_c_compmm_m108_out_dest_data_out_150_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_66167_c_compmm_m109_out_dest_data_out_149_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ch[0] <= redist652_sync_together4364_aunroll_x_in_c1_eni5_150_tpl_148_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ch[1] <= redist651_sync_together4364_aunroll_x_in_c1_eni5_149_tpl_148_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334(ADD,8918)@222
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_74_i_c_compmm_m2329_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_74_i_c_compmm_m2331_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_74_i_c_compmm_m2330_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_74_c_compmm_m2333_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_o[33:0];

    // rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x(MUX,20428)@222
    assign rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q or rightShiftStage0Idx1_uid20427_dupName_295_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q;
            1'b1 : rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20427_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x(MUX,20433)@222
    assign rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20432_dupName_295_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20429_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20432_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x(MUX,20438)@222
    assign rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20437_dupName_295_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20434_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20437_dupName_295_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2335_vt_select_20(BITSELECT,11267)@222
    assign i_unnamed_c_compmm_m2335_vt_select_20_b = rightShiftStage2_uid20439_dupName_295_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2335_vt_join(BITJOIN,11266)@222
    assign i_unnamed_c_compmm_m2335_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2335_vt_select_20_b};

    // i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x(BITSELECT,3547)@222
    assign i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x_b = i_unnamed_c_compmm_m2335_vt_join_q[15:0];

    // redist1042_i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x_b_1(DELAY,30170)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1042_i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20448_dupName_296_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20447)@222
    assign rightShiftStage1Idx1Rng8_uid20448_dupName_296_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20450_dupName_296_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20449)@222
    assign rightShiftStage1Idx1_uid20450_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20448_dupName_296_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20443_dupName_296_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20442)@222
    assign rightShiftStage0Idx1Rng4_uid20443_dupName_296_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q[33:4];

    // rightShiftStage0Idx1_uid20445_dupName_296_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20444)@222
    assign rightShiftStage0Idx1_uid20445_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20443_dupName_296_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x(MUX,20446)@222
    assign rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q or rightShiftStage0Idx1_uid20445_dupName_296_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_74_i_c_compmm_m2334_q;
            1'b1 : rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20445_dupName_296_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x(MUX,20451)@222
    assign rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20450_dupName_296_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20447_dupName_296_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20450_dupName_296_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2337_vt_select_21(BITSELECT,11270)@222
    assign i_unnamed_c_compmm_m2337_vt_select_21_b = rightShiftStage1_uid20452_dupName_296_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2337_vt_join(BITJOIN,11269)@222
    assign i_unnamed_c_compmm_m2337_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2337_vt_select_21_b};

    // i_unnamed_c_compmm_m2338_sel_x(BITSELECT,6099)@222
    assign i_unnamed_c_compmm_m2338_sel_x_b = i_unnamed_c_compmm_m2337_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2339_BitSelect_for_a(BITSELECT,28550)@222
    assign i_unnamed_c_compmm_m2339_BitSelect_for_a_b = i_unnamed_c_compmm_m2338_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2339_join(BITJOIN,28551)@222
    assign i_unnamed_c_compmm_m2339_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2339_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2339_vt_select_0(BITSELECT,11275)@222
    assign i_unnamed_c_compmm_m2339_vt_select_0_b = i_unnamed_c_compmm_m2339_join_q[0:0];

    // redist159_i_unnamed_c_compmm_m2339_vt_select_0_b_1(DELAY,29287)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist159_i_unnamed_c_compmm_m2339_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2339_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2339_vt_join(BITJOIN,11274)@223
    assign i_unnamed_c_compmm_m2339_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist159_i_unnamed_c_compmm_m2339_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_74_c_compmm_m2340(ADD,7130)@223
    assign i_add_i_i_i_i_i126_i_74_c_compmm_m2340_a = {1'b0, i_unnamed_c_compmm_m2339_vt_join_q};
    assign i_add_i_i_i_i_i126_i_74_c_compmm_m2340_b = {1'b0, redist1042_i_conv_i_i_i_i97_i_74_c_compmm_m2336_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_74_c_compmm_m2340_o = $unsigned(i_add_i_i_i_i_i126_i_74_c_compmm_m2340_a) + $unsigned(i_add_i_i_i_i_i126_i_74_c_compmm_m2340_b);
    assign i_add_i_i_i_i_i126_i_74_c_compmm_m2340_q = i_add_i_i_i_i_i126_i_74_c_compmm_m2340_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_74_c_compmm_m2340_sel_x(BITSELECT,2144)@223
    assign bgTrunc_i_add_i_i_i_i_i126_i_74_c_compmm_m2340_sel_x_b = i_add_i_i_i_i_i126_i_74_c_compmm_m2340_q[15:0];

    // i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_sel_x(BITSELECT,3677)@223
    assign i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_74_c_compmm_m2340_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_select_15(BITSELECT,7819)@223
    assign i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_select_15_b = i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_join(BITJOIN,7818)@223
    assign i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_select_15_b};

    // leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(MUX,25558)@223
    assign leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_join_q or leftShiftStage0Idx1_uid25557_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_75_c_compmm_m2360_vt_join_q;
            1'b1 : leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25557_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(MUX,25563)@223
    assign leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s or leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25562_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = leftShiftStage0_uid25559_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25562_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x(MUX,25568)@223
    assign leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s or leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25567_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = leftShiftStage1_uid25564_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25567_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28(BITSELECT,9757)@223
    assign i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28_b = leftShiftStage2_uid25569_i_shl_i_i_i_i_i77_i_75_c_compmm_m0_shift_x_q[28:13];

    // redist403_i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28_b_1(DELAY,29531)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist403_i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_join(BITJOIN,9756)@224
    assign i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_join_q = {redist403_i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma(CHAINMULTADD,29099)@218 + 5
    // out q@224
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_66170_c_compmm_m106_out_dest_data_out_152_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_66169_c_compmm_m107_out_dest_data_out_151_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ch[0] <= redist654_sync_together4364_aunroll_x_in_c1_eni5_152_tpl_150_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ch[1] <= redist653_sync_together4364_aunroll_x_in_c1_eni5_151_tpl_150_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362(ADD,8919)@224
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_75_i_c_compmm_m2357_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_75_i_c_compmm_m2359_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_75_i_c_compmm_m2358_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_75_c_compmm_m2361_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_o[33:0];

    // rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x(MUX,20490)@224
    assign rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q or rightShiftStage0Idx1_uid20489_dupName_299_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q;
            1'b1 : rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20489_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x(MUX,20495)@224
    assign rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20494_dupName_299_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20491_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20494_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x(MUX,20500)@224
    assign rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20499_dupName_299_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20496_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20499_dupName_299_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2363_vt_select_20(BITSELECT,11289)@224
    assign i_unnamed_c_compmm_m2363_vt_select_20_b = rightShiftStage2_uid20501_dupName_299_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2363_vt_join(BITJOIN,11288)@224
    assign i_unnamed_c_compmm_m2363_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2363_vt_select_20_b};

    // i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x(BITSELECT,3548)@224
    assign i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x_b = i_unnamed_c_compmm_m2363_vt_join_q[15:0];

    // redist1041_i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x_b_1(DELAY,30169)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1041_i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20510_dupName_300_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20509)@224
    assign rightShiftStage1Idx1Rng8_uid20510_dupName_300_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20512_dupName_300_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20511)@224
    assign rightShiftStage1Idx1_uid20512_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20510_dupName_300_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20505_dupName_300_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20504)@224
    assign rightShiftStage0Idx1Rng4_uid20505_dupName_300_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q[33:4];

    // rightShiftStage0Idx1_uid20507_dupName_300_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20506)@224
    assign rightShiftStage0Idx1_uid20507_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20505_dupName_300_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x(MUX,20508)@224
    assign rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q or rightShiftStage0Idx1_uid20507_dupName_300_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_75_i_c_compmm_m2362_q;
            1'b1 : rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20507_dupName_300_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x(MUX,20513)@224
    assign rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20512_dupName_300_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20509_dupName_300_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20512_dupName_300_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2365_vt_select_21(BITSELECT,11292)@224
    assign i_unnamed_c_compmm_m2365_vt_select_21_b = rightShiftStage1_uid20514_dupName_300_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2365_vt_join(BITJOIN,11291)@224
    assign i_unnamed_c_compmm_m2365_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2365_vt_select_21_b};

    // i_unnamed_c_compmm_m2366_sel_x(BITSELECT,6101)@224
    assign i_unnamed_c_compmm_m2366_sel_x_b = i_unnamed_c_compmm_m2365_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2367_BitSelect_for_a(BITSELECT,28554)@224
    assign i_unnamed_c_compmm_m2367_BitSelect_for_a_b = i_unnamed_c_compmm_m2366_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2367_join(BITJOIN,28555)@224
    assign i_unnamed_c_compmm_m2367_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2367_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2367_vt_select_0(BITSELECT,11297)@224
    assign i_unnamed_c_compmm_m2367_vt_select_0_b = i_unnamed_c_compmm_m2367_join_q[0:0];

    // redist157_i_unnamed_c_compmm_m2367_vt_select_0_b_1(DELAY,29285)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist157_i_unnamed_c_compmm_m2367_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2367_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2367_vt_join(BITJOIN,11296)@225
    assign i_unnamed_c_compmm_m2367_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist157_i_unnamed_c_compmm_m2367_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_75_c_compmm_m2368(ADD,7131)@225
    assign i_add_i_i_i_i_i126_i_75_c_compmm_m2368_a = {1'b0, i_unnamed_c_compmm_m2367_vt_join_q};
    assign i_add_i_i_i_i_i126_i_75_c_compmm_m2368_b = {1'b0, redist1041_i_conv_i_i_i_i97_i_75_c_compmm_m2364_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_75_c_compmm_m2368_o = $unsigned(i_add_i_i_i_i_i126_i_75_c_compmm_m2368_a) + $unsigned(i_add_i_i_i_i_i126_i_75_c_compmm_m2368_b);
    assign i_add_i_i_i_i_i126_i_75_c_compmm_m2368_q = i_add_i_i_i_i_i126_i_75_c_compmm_m2368_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_75_c_compmm_m2368_sel_x(BITSELECT,2145)@225
    assign bgTrunc_i_add_i_i_i_i_i126_i_75_c_compmm_m2368_sel_x_b = i_add_i_i_i_i_i126_i_75_c_compmm_m2368_q[15:0];

    // i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_sel_x(BITSELECT,3678)@225
    assign i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_75_c_compmm_m2368_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_select_15(BITSELECT,7823)@225
    assign i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_select_15_b = i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_join(BITJOIN,7822)@225
    assign i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_select_15_b};

    // leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(MUX,25576)@225
    assign leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_join_q or leftShiftStage0Idx1_uid25575_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_76_c_compmm_m2388_vt_join_q;
            1'b1 : leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25575_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(MUX,25581)@225
    assign leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s or leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25580_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = leftShiftStage0_uid25577_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25580_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x(MUX,25586)@225
    assign leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s or leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25585_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = leftShiftStage1_uid25582_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25585_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28(BITSELECT,9760)@225
    assign i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28_b = leftShiftStage2_uid25587_i_shl_i_i_i_i_i77_i_76_c_compmm_m0_shift_x_q[28:13];

    // redist402_i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28_b_1(DELAY,29530)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist402_i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_join(BITJOIN,9759)@226
    assign i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_join_q = {redist402_i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma(CHAINMULTADD,29100)@220 + 5
    // out q@226
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_66172_c_compmm_m104_out_dest_data_out_154_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_66171_c_compmm_m105_out_dest_data_out_153_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ch[0] <= redist656_sync_together4364_aunroll_x_in_c1_eni5_154_tpl_152_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ch[1] <= redist655_sync_together4364_aunroll_x_in_c1_eni5_153_tpl_152_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390(ADD,8920)@226
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_76_i_c_compmm_m2385_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_76_i_c_compmm_m2387_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_76_i_c_compmm_m2386_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_76_c_compmm_m2389_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_o[33:0];

    // rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x(MUX,20552)@226
    assign rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q or rightShiftStage0Idx1_uid20551_dupName_303_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q;
            1'b1 : rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20551_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x(MUX,20557)@226
    assign rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20556_dupName_303_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20553_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20556_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x(MUX,20562)@226
    assign rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20561_dupName_303_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20558_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20561_dupName_303_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2391_vt_select_20(BITSELECT,11311)@226
    assign i_unnamed_c_compmm_m2391_vt_select_20_b = rightShiftStage2_uid20563_dupName_303_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2391_vt_join(BITJOIN,11310)@226
    assign i_unnamed_c_compmm_m2391_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2391_vt_select_20_b};

    // i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x(BITSELECT,3549)@226
    assign i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x_b = i_unnamed_c_compmm_m2391_vt_join_q[15:0];

    // redist1040_i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x_b_1(DELAY,30168)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1040_i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20572_dupName_304_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20571)@226
    assign rightShiftStage1Idx1Rng8_uid20572_dupName_304_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20574_dupName_304_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20573)@226
    assign rightShiftStage1Idx1_uid20574_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20572_dupName_304_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20567_dupName_304_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20566)@226
    assign rightShiftStage0Idx1Rng4_uid20567_dupName_304_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q[33:4];

    // rightShiftStage0Idx1_uid20569_dupName_304_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20568)@226
    assign rightShiftStage0Idx1_uid20569_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20567_dupName_304_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x(MUX,20570)@226
    assign rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q or rightShiftStage0Idx1_uid20569_dupName_304_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_76_i_c_compmm_m2390_q;
            1'b1 : rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20569_dupName_304_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x(MUX,20575)@226
    assign rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20574_dupName_304_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20571_dupName_304_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20574_dupName_304_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2393_vt_select_21(BITSELECT,11314)@226
    assign i_unnamed_c_compmm_m2393_vt_select_21_b = rightShiftStage1_uid20576_dupName_304_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2393_vt_join(BITJOIN,11313)@226
    assign i_unnamed_c_compmm_m2393_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2393_vt_select_21_b};

    // i_unnamed_c_compmm_m2394_sel_x(BITSELECT,6103)@226
    assign i_unnamed_c_compmm_m2394_sel_x_b = i_unnamed_c_compmm_m2393_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2395_BitSelect_for_a(BITSELECT,28558)@226
    assign i_unnamed_c_compmm_m2395_BitSelect_for_a_b = i_unnamed_c_compmm_m2394_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2395_join(BITJOIN,28559)@226
    assign i_unnamed_c_compmm_m2395_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2395_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2395_vt_select_0(BITSELECT,11319)@226
    assign i_unnamed_c_compmm_m2395_vt_select_0_b = i_unnamed_c_compmm_m2395_join_q[0:0];

    // redist155_i_unnamed_c_compmm_m2395_vt_select_0_b_1(DELAY,29283)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist155_i_unnamed_c_compmm_m2395_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2395_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2395_vt_join(BITJOIN,11318)@227
    assign i_unnamed_c_compmm_m2395_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist155_i_unnamed_c_compmm_m2395_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_76_c_compmm_m2396(ADD,7132)@227
    assign i_add_i_i_i_i_i126_i_76_c_compmm_m2396_a = {1'b0, i_unnamed_c_compmm_m2395_vt_join_q};
    assign i_add_i_i_i_i_i126_i_76_c_compmm_m2396_b = {1'b0, redist1040_i_conv_i_i_i_i97_i_76_c_compmm_m2392_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_76_c_compmm_m2396_o = $unsigned(i_add_i_i_i_i_i126_i_76_c_compmm_m2396_a) + $unsigned(i_add_i_i_i_i_i126_i_76_c_compmm_m2396_b);
    assign i_add_i_i_i_i_i126_i_76_c_compmm_m2396_q = i_add_i_i_i_i_i126_i_76_c_compmm_m2396_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_76_c_compmm_m2396_sel_x(BITSELECT,2146)@227
    assign bgTrunc_i_add_i_i_i_i_i126_i_76_c_compmm_m2396_sel_x_b = i_add_i_i_i_i_i126_i_76_c_compmm_m2396_q[15:0];

    // i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_sel_x(BITSELECT,3679)@227
    assign i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_76_c_compmm_m2396_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_select_15(BITSELECT,7827)@227
    assign i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_select_15_b = i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_join(BITJOIN,7826)@227
    assign i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_select_15_b};

    // leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(MUX,25594)@227
    assign leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_join_q or leftShiftStage0Idx1_uid25593_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_77_c_compmm_m2416_vt_join_q;
            1'b1 : leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25593_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(MUX,25599)@227
    assign leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s or leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25598_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = leftShiftStage0_uid25595_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25598_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x(MUX,25604)@227
    assign leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s or leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25603_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = leftShiftStage1_uid25600_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25603_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28(BITSELECT,9763)@227
    assign i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28_b = leftShiftStage2_uid25605_i_shl_i_i_i_i_i77_i_77_c_compmm_m0_shift_x_q[28:13];

    // redist401_i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28_b_1(DELAY,29529)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist401_i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_join(BITJOIN,9762)@228
    assign i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_join_q = {redist401_i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma(CHAINMULTADD,29101)@222 + 5
    // out q@228
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_66174_c_compmm_m102_out_dest_data_out_156_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_66173_c_compmm_m103_out_dest_data_out_155_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ch[0] <= redist658_sync_together4364_aunroll_x_in_c1_eni5_156_tpl_154_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ch[1] <= redist657_sync_together4364_aunroll_x_in_c1_eni5_155_tpl_154_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418(ADD,8921)@228
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_77_i_c_compmm_m2413_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_77_i_c_compmm_m2415_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_77_i_c_compmm_m2414_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_77_c_compmm_m2417_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_o[33:0];

    // rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x(MUX,20614)@228
    assign rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q or rightShiftStage0Idx1_uid20613_dupName_307_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q;
            1'b1 : rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20613_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x(MUX,20619)@228
    assign rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20618_dupName_307_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20615_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20618_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x(MUX,20624)@228
    assign rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20623_dupName_307_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20620_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20623_dupName_307_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2419_vt_select_20(BITSELECT,11333)@228
    assign i_unnamed_c_compmm_m2419_vt_select_20_b = rightShiftStage2_uid20625_dupName_307_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2419_vt_join(BITJOIN,11332)@228
    assign i_unnamed_c_compmm_m2419_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2419_vt_select_20_b};

    // i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x(BITSELECT,3550)@228
    assign i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x_b = i_unnamed_c_compmm_m2419_vt_join_q[15:0];

    // redist1039_i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x_b_1(DELAY,30167)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1039_i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20634_dupName_308_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20633)@228
    assign rightShiftStage1Idx1Rng8_uid20634_dupName_308_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20636_dupName_308_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20635)@228
    assign rightShiftStage1Idx1_uid20636_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20634_dupName_308_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20629_dupName_308_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20628)@228
    assign rightShiftStage0Idx1Rng4_uid20629_dupName_308_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q[33:4];

    // rightShiftStage0Idx1_uid20631_dupName_308_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20630)@228
    assign rightShiftStage0Idx1_uid20631_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20629_dupName_308_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x(MUX,20632)@228
    assign rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q or rightShiftStage0Idx1_uid20631_dupName_308_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_77_i_c_compmm_m2418_q;
            1'b1 : rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20631_dupName_308_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x(MUX,20637)@228
    assign rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20636_dupName_308_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20633_dupName_308_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20636_dupName_308_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2421_vt_select_21(BITSELECT,11336)@228
    assign i_unnamed_c_compmm_m2421_vt_select_21_b = rightShiftStage1_uid20638_dupName_308_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2421_vt_join(BITJOIN,11335)@228
    assign i_unnamed_c_compmm_m2421_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2421_vt_select_21_b};

    // i_unnamed_c_compmm_m2422_sel_x(BITSELECT,6105)@228
    assign i_unnamed_c_compmm_m2422_sel_x_b = i_unnamed_c_compmm_m2421_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2423_BitSelect_for_a(BITSELECT,28562)@228
    assign i_unnamed_c_compmm_m2423_BitSelect_for_a_b = i_unnamed_c_compmm_m2422_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2423_join(BITJOIN,28563)@228
    assign i_unnamed_c_compmm_m2423_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2423_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2423_vt_select_0(BITSELECT,11341)@228
    assign i_unnamed_c_compmm_m2423_vt_select_0_b = i_unnamed_c_compmm_m2423_join_q[0:0];

    // redist153_i_unnamed_c_compmm_m2423_vt_select_0_b_1(DELAY,29281)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist153_i_unnamed_c_compmm_m2423_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2423_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2423_vt_join(BITJOIN,11340)@229
    assign i_unnamed_c_compmm_m2423_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist153_i_unnamed_c_compmm_m2423_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_77_c_compmm_m2424(ADD,7133)@229
    assign i_add_i_i_i_i_i126_i_77_c_compmm_m2424_a = {1'b0, i_unnamed_c_compmm_m2423_vt_join_q};
    assign i_add_i_i_i_i_i126_i_77_c_compmm_m2424_b = {1'b0, redist1039_i_conv_i_i_i_i97_i_77_c_compmm_m2420_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_77_c_compmm_m2424_o = $unsigned(i_add_i_i_i_i_i126_i_77_c_compmm_m2424_a) + $unsigned(i_add_i_i_i_i_i126_i_77_c_compmm_m2424_b);
    assign i_add_i_i_i_i_i126_i_77_c_compmm_m2424_q = i_add_i_i_i_i_i126_i_77_c_compmm_m2424_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_77_c_compmm_m2424_sel_x(BITSELECT,2147)@229
    assign bgTrunc_i_add_i_i_i_i_i126_i_77_c_compmm_m2424_sel_x_b = i_add_i_i_i_i_i126_i_77_c_compmm_m2424_q[15:0];

    // i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_sel_x(BITSELECT,3680)@229
    assign i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_77_c_compmm_m2424_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_select_15(BITSELECT,7831)@229
    assign i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_select_15_b = i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_join(BITJOIN,7830)@229
    assign i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_select_15_b};

    // leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(MUX,25612)@229
    assign leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_join_q or leftShiftStage0Idx1_uid25611_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_78_c_compmm_m2444_vt_join_q;
            1'b1 : leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25611_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(MUX,25617)@229
    assign leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s or leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25616_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = leftShiftStage0_uid25613_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25616_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x(MUX,25622)@229
    assign leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s or leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25621_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = leftShiftStage1_uid25618_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25621_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28(BITSELECT,9766)@229
    assign i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28_b = leftShiftStage2_uid25623_i_shl_i_i_i_i_i77_i_78_c_compmm_m0_shift_x_q[28:13];

    // redist400_i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28_b_1(DELAY,29528)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist400_i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_join(BITJOIN,9765)@230
    assign i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_join_q = {redist400_i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma(CHAINMULTADD,29102)@224 + 5
    // out q@230
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_66176_c_compmm_m100_out_dest_data_out_158_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_66175_c_compmm_m101_out_dest_data_out_157_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ch[0] <= redist660_sync_together4364_aunroll_x_in_c1_eni5_158_tpl_156_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ch[1] <= redist659_sync_together4364_aunroll_x_in_c1_eni5_157_tpl_156_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446(ADD,8922)@230
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_78_i_c_compmm_m2441_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_78_i_c_compmm_m2443_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_78_i_c_compmm_m2442_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_78_c_compmm_m2445_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_o[33:0];

    // rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x(MUX,20676)@230
    assign rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q or rightShiftStage0Idx1_uid20675_dupName_311_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q;
            1'b1 : rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20675_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x(MUX,20681)@230
    assign rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20680_dupName_311_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20677_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20680_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x(MUX,20686)@230
    assign rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20685_dupName_311_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20682_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20685_dupName_311_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2447_vt_select_20(BITSELECT,11355)@230
    assign i_unnamed_c_compmm_m2447_vt_select_20_b = rightShiftStage2_uid20687_dupName_311_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2447_vt_join(BITJOIN,11354)@230
    assign i_unnamed_c_compmm_m2447_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2447_vt_select_20_b};

    // i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x(BITSELECT,3551)@230
    assign i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x_b = i_unnamed_c_compmm_m2447_vt_join_q[15:0];

    // redist1038_i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x_b_1(DELAY,30166)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1038_i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20696_dupName_312_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20695)@230
    assign rightShiftStage1Idx1Rng8_uid20696_dupName_312_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20698_dupName_312_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20697)@230
    assign rightShiftStage1Idx1_uid20698_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20696_dupName_312_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20691_dupName_312_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20690)@230
    assign rightShiftStage0Idx1Rng4_uid20691_dupName_312_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q[33:4];

    // rightShiftStage0Idx1_uid20693_dupName_312_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20692)@230
    assign rightShiftStage0Idx1_uid20693_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20691_dupName_312_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x(MUX,20694)@230
    assign rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q or rightShiftStage0Idx1_uid20693_dupName_312_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_78_i_c_compmm_m2446_q;
            1'b1 : rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20693_dupName_312_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x(MUX,20699)@230
    assign rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20698_dupName_312_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20695_dupName_312_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20698_dupName_312_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2449_vt_select_21(BITSELECT,11358)@230
    assign i_unnamed_c_compmm_m2449_vt_select_21_b = rightShiftStage1_uid20700_dupName_312_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2449_vt_join(BITJOIN,11357)@230
    assign i_unnamed_c_compmm_m2449_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2449_vt_select_21_b};

    // i_unnamed_c_compmm_m2450_sel_x(BITSELECT,6107)@230
    assign i_unnamed_c_compmm_m2450_sel_x_b = i_unnamed_c_compmm_m2449_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2451_BitSelect_for_a(BITSELECT,28566)@230
    assign i_unnamed_c_compmm_m2451_BitSelect_for_a_b = i_unnamed_c_compmm_m2450_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2451_join(BITJOIN,28567)@230
    assign i_unnamed_c_compmm_m2451_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2451_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2451_vt_select_0(BITSELECT,11363)@230
    assign i_unnamed_c_compmm_m2451_vt_select_0_b = i_unnamed_c_compmm_m2451_join_q[0:0];

    // redist151_i_unnamed_c_compmm_m2451_vt_select_0_b_1(DELAY,29279)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist151_i_unnamed_c_compmm_m2451_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2451_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2451_vt_join(BITJOIN,11362)@231
    assign i_unnamed_c_compmm_m2451_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist151_i_unnamed_c_compmm_m2451_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_78_c_compmm_m2452(ADD,7134)@231
    assign i_add_i_i_i_i_i126_i_78_c_compmm_m2452_a = {1'b0, i_unnamed_c_compmm_m2451_vt_join_q};
    assign i_add_i_i_i_i_i126_i_78_c_compmm_m2452_b = {1'b0, redist1038_i_conv_i_i_i_i97_i_78_c_compmm_m2448_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_78_c_compmm_m2452_o = $unsigned(i_add_i_i_i_i_i126_i_78_c_compmm_m2452_a) + $unsigned(i_add_i_i_i_i_i126_i_78_c_compmm_m2452_b);
    assign i_add_i_i_i_i_i126_i_78_c_compmm_m2452_q = i_add_i_i_i_i_i126_i_78_c_compmm_m2452_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_78_c_compmm_m2452_sel_x(BITSELECT,2148)@231
    assign bgTrunc_i_add_i_i_i_i_i126_i_78_c_compmm_m2452_sel_x_b = i_add_i_i_i_i_i126_i_78_c_compmm_m2452_q[15:0];

    // i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_sel_x(BITSELECT,3681)@231
    assign i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_78_c_compmm_m2452_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_select_15(BITSELECT,7835)@231
    assign i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_select_15_b = i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_join(BITJOIN,7834)@231
    assign i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_select_15_b};

    // leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(MUX,25630)@231
    assign leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_join_q or leftShiftStage0Idx1_uid25629_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_79_c_compmm_m2472_vt_join_q;
            1'b1 : leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25629_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(MUX,25635)@231
    assign leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s or leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25634_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = leftShiftStage0_uid25631_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25634_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x(MUX,25640)@231
    assign leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s or leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25639_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = leftShiftStage1_uid25636_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25639_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28(BITSELECT,9769)@231
    assign i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28_b = leftShiftStage2_uid25641_i_shl_i_i_i_i_i77_i_79_c_compmm_m0_shift_x_q[28:13];

    // redist399_i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28_b_1(DELAY,29527)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist399_i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_join(BITJOIN,9768)@232
    assign i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_join_q = {redist399_i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma(CHAINMULTADD,29103)@226 + 5
    // out q@232
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_66178_c_compmm_m98_out_dest_data_out_160_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_66177_c_compmm_m99_out_dest_data_out_159_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ch[0] <= redist662_sync_together4364_aunroll_x_in_c1_eni5_160_tpl_158_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ch[1] <= redist661_sync_together4364_aunroll_x_in_c1_eni5_159_tpl_158_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474(ADD,8923)@232
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_79_i_c_compmm_m2469_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_79_i_c_compmm_m2471_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_79_i_c_compmm_m2470_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_79_c_compmm_m2473_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_o[33:0];

    // rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x(MUX,20738)@232
    assign rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q or rightShiftStage0Idx1_uid20737_dupName_315_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q;
            1'b1 : rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20737_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x(MUX,20743)@232
    assign rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20742_dupName_315_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20739_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20742_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x(MUX,20748)@232
    assign rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20747_dupName_315_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20744_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20747_dupName_315_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2475_vt_select_20(BITSELECT,11377)@232
    assign i_unnamed_c_compmm_m2475_vt_select_20_b = rightShiftStage2_uid20749_dupName_315_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2475_vt_join(BITJOIN,11376)@232
    assign i_unnamed_c_compmm_m2475_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2475_vt_select_20_b};

    // i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x(BITSELECT,3552)@232
    assign i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x_b = i_unnamed_c_compmm_m2475_vt_join_q[15:0];

    // redist1037_i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x_b_1(DELAY,30165)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1037_i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20758_dupName_316_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20757)@232
    assign rightShiftStage1Idx1Rng8_uid20758_dupName_316_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20760_dupName_316_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20759)@232
    assign rightShiftStage1Idx1_uid20760_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20758_dupName_316_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20753_dupName_316_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20752)@232
    assign rightShiftStage0Idx1Rng4_uid20753_dupName_316_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q[33:4];

    // rightShiftStage0Idx1_uid20755_dupName_316_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20754)@232
    assign rightShiftStage0Idx1_uid20755_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20753_dupName_316_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x(MUX,20756)@232
    assign rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q or rightShiftStage0Idx1_uid20755_dupName_316_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_79_i_c_compmm_m2474_q;
            1'b1 : rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20755_dupName_316_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x(MUX,20761)@232
    assign rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20760_dupName_316_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20757_dupName_316_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20760_dupName_316_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2477_vt_select_21(BITSELECT,11380)@232
    assign i_unnamed_c_compmm_m2477_vt_select_21_b = rightShiftStage1_uid20762_dupName_316_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2477_vt_join(BITJOIN,11379)@232
    assign i_unnamed_c_compmm_m2477_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2477_vt_select_21_b};

    // i_unnamed_c_compmm_m2478_sel_x(BITSELECT,6109)@232
    assign i_unnamed_c_compmm_m2478_sel_x_b = i_unnamed_c_compmm_m2477_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2479_BitSelect_for_a(BITSELECT,28570)@232
    assign i_unnamed_c_compmm_m2479_BitSelect_for_a_b = i_unnamed_c_compmm_m2478_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2479_join(BITJOIN,28571)@232
    assign i_unnamed_c_compmm_m2479_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2479_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2479_vt_select_0(BITSELECT,11385)@232
    assign i_unnamed_c_compmm_m2479_vt_select_0_b = i_unnamed_c_compmm_m2479_join_q[0:0];

    // redist149_i_unnamed_c_compmm_m2479_vt_select_0_b_1(DELAY,29277)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist149_i_unnamed_c_compmm_m2479_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2479_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2479_vt_join(BITJOIN,11384)@233
    assign i_unnamed_c_compmm_m2479_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist149_i_unnamed_c_compmm_m2479_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_79_c_compmm_m2480(ADD,7135)@233
    assign i_add_i_i_i_i_i126_i_79_c_compmm_m2480_a = {1'b0, i_unnamed_c_compmm_m2479_vt_join_q};
    assign i_add_i_i_i_i_i126_i_79_c_compmm_m2480_b = {1'b0, redist1037_i_conv_i_i_i_i97_i_79_c_compmm_m2476_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_79_c_compmm_m2480_o = $unsigned(i_add_i_i_i_i_i126_i_79_c_compmm_m2480_a) + $unsigned(i_add_i_i_i_i_i126_i_79_c_compmm_m2480_b);
    assign i_add_i_i_i_i_i126_i_79_c_compmm_m2480_q = i_add_i_i_i_i_i126_i_79_c_compmm_m2480_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_79_c_compmm_m2480_sel_x(BITSELECT,2149)@233
    assign bgTrunc_i_add_i_i_i_i_i126_i_79_c_compmm_m2480_sel_x_b = i_add_i_i_i_i_i126_i_79_c_compmm_m2480_q[15:0];

    // i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_sel_x(BITSELECT,3683)@233
    assign i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_79_c_compmm_m2480_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_select_15(BITSELECT,7843)@233
    assign i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_select_15_b = i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_join(BITJOIN,7842)@233
    assign i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_select_15_b};

    // leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(MUX,25666)@233
    assign leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_join_q or leftShiftStage0Idx1_uid25665_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_80_c_compmm_m2500_vt_join_q;
            1'b1 : leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25665_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(MUX,25671)@233
    assign leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s or leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25670_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = leftShiftStage0_uid25667_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25670_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x(MUX,25676)@233
    assign leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s or leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25675_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = leftShiftStage1_uid25672_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25675_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28(BITSELECT,9775)@233
    assign i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28_b = leftShiftStage2_uid25677_i_shl_i_i_i_i_i77_i_80_c_compmm_m0_shift_x_q[28:13];

    // redist397_i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28_b_1(DELAY,29525)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist397_i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_join(BITJOIN,9774)@234
    assign i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_join_q = {redist397_i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma(CHAINMULTADD,29105)@228 + 5
    // out q@234
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_66180_c_compmm_m96_out_dest_data_out_162_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_66179_c_compmm_m97_out_dest_data_out_161_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ch[0] <= redist664_sync_together4364_aunroll_x_in_c1_eni5_162_tpl_160_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ch[1] <= redist663_sync_together4364_aunroll_x_in_c1_eni5_161_tpl_160_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502(ADD,8925)@234
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_80_i_c_compmm_m2497_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_80_i_c_compmm_m2499_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_80_i_c_compmm_m2498_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_80_c_compmm_m2501_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_o[33:0];

    // rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x(MUX,20800)@234
    assign rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q or rightShiftStage0Idx1_uid20799_dupName_319_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q;
            1'b1 : rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20799_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x(MUX,20805)@234
    assign rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20804_dupName_319_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20801_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20804_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x(MUX,20810)@234
    assign rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20809_dupName_319_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20806_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20809_dupName_319_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2503_vt_select_20(BITSELECT,11399)@234
    assign i_unnamed_c_compmm_m2503_vt_select_20_b = rightShiftStage2_uid20811_dupName_319_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2503_vt_join(BITJOIN,11398)@234
    assign i_unnamed_c_compmm_m2503_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2503_vt_select_20_b};

    // i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x(BITSELECT,3554)@234
    assign i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x_b = i_unnamed_c_compmm_m2503_vt_join_q[15:0];

    // redist1035_i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x_b_1(DELAY,30163)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1035_i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20820_dupName_320_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20819)@234
    assign rightShiftStage1Idx1Rng8_uid20820_dupName_320_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20822_dupName_320_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20821)@234
    assign rightShiftStage1Idx1_uid20822_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20820_dupName_320_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20815_dupName_320_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20814)@234
    assign rightShiftStage0Idx1Rng4_uid20815_dupName_320_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q[33:4];

    // rightShiftStage0Idx1_uid20817_dupName_320_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20816)@234
    assign rightShiftStage0Idx1_uid20817_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20815_dupName_320_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x(MUX,20818)@234
    assign rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q or rightShiftStage0Idx1_uid20817_dupName_320_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_80_i_c_compmm_m2502_q;
            1'b1 : rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20817_dupName_320_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x(MUX,20823)@234
    assign rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20822_dupName_320_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20819_dupName_320_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20822_dupName_320_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2505_vt_select_21(BITSELECT,11402)@234
    assign i_unnamed_c_compmm_m2505_vt_select_21_b = rightShiftStage1_uid20824_dupName_320_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2505_vt_join(BITJOIN,11401)@234
    assign i_unnamed_c_compmm_m2505_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2505_vt_select_21_b};

    // i_unnamed_c_compmm_m2506_sel_x(BITSELECT,6111)@234
    assign i_unnamed_c_compmm_m2506_sel_x_b = i_unnamed_c_compmm_m2505_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2507_BitSelect_for_a(BITSELECT,28574)@234
    assign i_unnamed_c_compmm_m2507_BitSelect_for_a_b = i_unnamed_c_compmm_m2506_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2507_join(BITJOIN,28575)@234
    assign i_unnamed_c_compmm_m2507_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2507_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2507_vt_select_0(BITSELECT,11407)@234
    assign i_unnamed_c_compmm_m2507_vt_select_0_b = i_unnamed_c_compmm_m2507_join_q[0:0];

    // redist147_i_unnamed_c_compmm_m2507_vt_select_0_b_1(DELAY,29275)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist147_i_unnamed_c_compmm_m2507_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2507_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2507_vt_join(BITJOIN,11406)@235
    assign i_unnamed_c_compmm_m2507_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist147_i_unnamed_c_compmm_m2507_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_80_c_compmm_m2508(ADD,7137)@235
    assign i_add_i_i_i_i_i126_i_80_c_compmm_m2508_a = {1'b0, i_unnamed_c_compmm_m2507_vt_join_q};
    assign i_add_i_i_i_i_i126_i_80_c_compmm_m2508_b = {1'b0, redist1035_i_conv_i_i_i_i97_i_80_c_compmm_m2504_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_80_c_compmm_m2508_o = $unsigned(i_add_i_i_i_i_i126_i_80_c_compmm_m2508_a) + $unsigned(i_add_i_i_i_i_i126_i_80_c_compmm_m2508_b);
    assign i_add_i_i_i_i_i126_i_80_c_compmm_m2508_q = i_add_i_i_i_i_i126_i_80_c_compmm_m2508_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_80_c_compmm_m2508_sel_x(BITSELECT,2151)@235
    assign bgTrunc_i_add_i_i_i_i_i126_i_80_c_compmm_m2508_sel_x_b = i_add_i_i_i_i_i126_i_80_c_compmm_m2508_q[15:0];

    // i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_sel_x(BITSELECT,3684)@235
    assign i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_80_c_compmm_m2508_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_select_15(BITSELECT,7847)@235
    assign i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_select_15_b = i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_join(BITJOIN,7846)@235
    assign i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_select_15_b};

    // leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(MUX,25684)@235
    assign leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_join_q or leftShiftStage0Idx1_uid25683_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_81_c_compmm_m2528_vt_join_q;
            1'b1 : leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25683_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(MUX,25689)@235
    assign leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s or leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25688_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = leftShiftStage0_uid25685_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25688_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x(MUX,25694)@235
    assign leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s or leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25693_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = leftShiftStage1_uid25690_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25693_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28(BITSELECT,9778)@235
    assign i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28_b = leftShiftStage2_uid25695_i_shl_i_i_i_i_i77_i_81_c_compmm_m0_shift_x_q[28:13];

    // redist396_i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28_b_1(DELAY,29524)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist396_i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_join(BITJOIN,9777)@236
    assign i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_join_q = {redist396_i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma(CHAINMULTADD,29106)@230 + 5
    // out q@236
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_66182_c_compmm_m94_out_dest_data_out_164_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_66181_c_compmm_m95_out_dest_data_out_163_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ch[0] <= redist666_sync_together4364_aunroll_x_in_c1_eni5_164_tpl_162_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ch[1] <= redist665_sync_together4364_aunroll_x_in_c1_eni5_163_tpl_162_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530(ADD,8926)@236
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_81_i_c_compmm_m2525_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_81_i_c_compmm_m2527_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_81_i_c_compmm_m2526_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_81_c_compmm_m2529_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_o[33:0];

    // rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x(MUX,20862)@236
    assign rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q or rightShiftStage0Idx1_uid20861_dupName_323_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q;
            1'b1 : rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20861_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x(MUX,20867)@236
    assign rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20866_dupName_323_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20863_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20866_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x(MUX,20872)@236
    assign rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20871_dupName_323_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20868_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20871_dupName_323_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2531_vt_select_20(BITSELECT,11421)@236
    assign i_unnamed_c_compmm_m2531_vt_select_20_b = rightShiftStage2_uid20873_dupName_323_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2531_vt_join(BITJOIN,11420)@236
    assign i_unnamed_c_compmm_m2531_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2531_vt_select_20_b};

    // i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x(BITSELECT,3555)@236
    assign i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x_b = i_unnamed_c_compmm_m2531_vt_join_q[15:0];

    // redist1034_i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x_b_1(DELAY,30162)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1034_i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20882_dupName_324_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20881)@236
    assign rightShiftStage1Idx1Rng8_uid20882_dupName_324_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20884_dupName_324_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20883)@236
    assign rightShiftStage1Idx1_uid20884_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20882_dupName_324_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20877_dupName_324_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20876)@236
    assign rightShiftStage0Idx1Rng4_uid20877_dupName_324_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q[33:4];

    // rightShiftStage0Idx1_uid20879_dupName_324_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20878)@236
    assign rightShiftStage0Idx1_uid20879_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20877_dupName_324_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x(MUX,20880)@236
    assign rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q or rightShiftStage0Idx1_uid20879_dupName_324_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_81_i_c_compmm_m2530_q;
            1'b1 : rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20879_dupName_324_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x(MUX,20885)@236
    assign rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20884_dupName_324_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20881_dupName_324_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20884_dupName_324_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2533_vt_select_21(BITSELECT,11424)@236
    assign i_unnamed_c_compmm_m2533_vt_select_21_b = rightShiftStage1_uid20886_dupName_324_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2533_vt_join(BITJOIN,11423)@236
    assign i_unnamed_c_compmm_m2533_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2533_vt_select_21_b};

    // i_unnamed_c_compmm_m2534_sel_x(BITSELECT,6113)@236
    assign i_unnamed_c_compmm_m2534_sel_x_b = i_unnamed_c_compmm_m2533_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2535_BitSelect_for_a(BITSELECT,28578)@236
    assign i_unnamed_c_compmm_m2535_BitSelect_for_a_b = i_unnamed_c_compmm_m2534_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2535_join(BITJOIN,28579)@236
    assign i_unnamed_c_compmm_m2535_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2535_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2535_vt_select_0(BITSELECT,11429)@236
    assign i_unnamed_c_compmm_m2535_vt_select_0_b = i_unnamed_c_compmm_m2535_join_q[0:0];

    // redist145_i_unnamed_c_compmm_m2535_vt_select_0_b_1(DELAY,29273)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist145_i_unnamed_c_compmm_m2535_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2535_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2535_vt_join(BITJOIN,11428)@237
    assign i_unnamed_c_compmm_m2535_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist145_i_unnamed_c_compmm_m2535_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_81_c_compmm_m2536(ADD,7138)@237
    assign i_add_i_i_i_i_i126_i_81_c_compmm_m2536_a = {1'b0, i_unnamed_c_compmm_m2535_vt_join_q};
    assign i_add_i_i_i_i_i126_i_81_c_compmm_m2536_b = {1'b0, redist1034_i_conv_i_i_i_i97_i_81_c_compmm_m2532_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_81_c_compmm_m2536_o = $unsigned(i_add_i_i_i_i_i126_i_81_c_compmm_m2536_a) + $unsigned(i_add_i_i_i_i_i126_i_81_c_compmm_m2536_b);
    assign i_add_i_i_i_i_i126_i_81_c_compmm_m2536_q = i_add_i_i_i_i_i126_i_81_c_compmm_m2536_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_81_c_compmm_m2536_sel_x(BITSELECT,2152)@237
    assign bgTrunc_i_add_i_i_i_i_i126_i_81_c_compmm_m2536_sel_x_b = i_add_i_i_i_i_i126_i_81_c_compmm_m2536_q[15:0];

    // i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_sel_x(BITSELECT,3685)@237
    assign i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_81_c_compmm_m2536_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_select_15(BITSELECT,7851)@237
    assign i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_select_15_b = i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_join(BITJOIN,7850)@237
    assign i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_select_15_b};

    // leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(MUX,25702)@237
    assign leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_join_q or leftShiftStage0Idx1_uid25701_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_82_c_compmm_m2556_vt_join_q;
            1'b1 : leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25701_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(MUX,25707)@237
    assign leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s or leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25706_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = leftShiftStage0_uid25703_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25706_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x(MUX,25712)@237
    assign leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s or leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25711_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = leftShiftStage1_uid25708_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25711_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28(BITSELECT,9781)@237
    assign i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28_b = leftShiftStage2_uid25713_i_shl_i_i_i_i_i77_i_82_c_compmm_m0_shift_x_q[28:13];

    // redist395_i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28_b_1(DELAY,29523)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist395_i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_join(BITJOIN,9780)@238
    assign i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_join_q = {redist395_i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma(CHAINMULTADD,29107)@232 + 5
    // out q@238
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_66184_c_compmm_m92_out_dest_data_out_166_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_66183_c_compmm_m93_out_dest_data_out_165_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ch[0] <= redist668_sync_together4364_aunroll_x_in_c1_eni5_166_tpl_164_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ch[1] <= redist667_sync_together4364_aunroll_x_in_c1_eni5_165_tpl_164_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558(ADD,8927)@238
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_82_i_c_compmm_m2553_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_82_i_c_compmm_m2555_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_82_i_c_compmm_m2554_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_82_c_compmm_m2557_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_o[33:0];

    // rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x(MUX,20924)@238
    assign rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q or rightShiftStage0Idx1_uid20923_dupName_327_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q;
            1'b1 : rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20923_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x(MUX,20929)@238
    assign rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20928_dupName_327_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20925_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20928_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x(MUX,20934)@238
    assign rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20933_dupName_327_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20930_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20933_dupName_327_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2559_vt_select_20(BITSELECT,11443)@238
    assign i_unnamed_c_compmm_m2559_vt_select_20_b = rightShiftStage2_uid20935_dupName_327_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2559_vt_join(BITJOIN,11442)@238
    assign i_unnamed_c_compmm_m2559_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2559_vt_select_20_b};

    // i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x(BITSELECT,3556)@238
    assign i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x_b = i_unnamed_c_compmm_m2559_vt_join_q[15:0];

    // redist1033_i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x_b_1(DELAY,30161)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1033_i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid20944_dupName_328_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20943)@238
    assign rightShiftStage1Idx1Rng8_uid20944_dupName_328_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid20946_dupName_328_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20945)@238
    assign rightShiftStage1Idx1_uid20946_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid20944_dupName_328_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid20939_dupName_328_i_unnamed_c_compmm_m0_shift_x(BITSELECT,20938)@238
    assign rightShiftStage0Idx1Rng4_uid20939_dupName_328_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q[33:4];

    // rightShiftStage0Idx1_uid20941_dupName_328_i_unnamed_c_compmm_m0_shift_x(BITJOIN,20940)@238
    assign rightShiftStage0Idx1_uid20941_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid20939_dupName_328_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x(MUX,20942)@238
    assign rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q or rightShiftStage0Idx1_uid20941_dupName_328_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_82_i_c_compmm_m2558_q;
            1'b1 : rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20941_dupName_328_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x(MUX,20947)@238
    assign rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20946_dupName_328_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20943_dupName_328_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20946_dupName_328_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2561_vt_select_21(BITSELECT,11446)@238
    assign i_unnamed_c_compmm_m2561_vt_select_21_b = rightShiftStage1_uid20948_dupName_328_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2561_vt_join(BITJOIN,11445)@238
    assign i_unnamed_c_compmm_m2561_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2561_vt_select_21_b};

    // i_unnamed_c_compmm_m2562_sel_x(BITSELECT,6115)@238
    assign i_unnamed_c_compmm_m2562_sel_x_b = i_unnamed_c_compmm_m2561_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2563_BitSelect_for_a(BITSELECT,28582)@238
    assign i_unnamed_c_compmm_m2563_BitSelect_for_a_b = i_unnamed_c_compmm_m2562_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2563_join(BITJOIN,28583)@238
    assign i_unnamed_c_compmm_m2563_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2563_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2563_vt_select_0(BITSELECT,11451)@238
    assign i_unnamed_c_compmm_m2563_vt_select_0_b = i_unnamed_c_compmm_m2563_join_q[0:0];

    // redist143_i_unnamed_c_compmm_m2563_vt_select_0_b_1(DELAY,29271)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist143_i_unnamed_c_compmm_m2563_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2563_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2563_vt_join(BITJOIN,11450)@239
    assign i_unnamed_c_compmm_m2563_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist143_i_unnamed_c_compmm_m2563_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_82_c_compmm_m2564(ADD,7139)@239
    assign i_add_i_i_i_i_i126_i_82_c_compmm_m2564_a = {1'b0, i_unnamed_c_compmm_m2563_vt_join_q};
    assign i_add_i_i_i_i_i126_i_82_c_compmm_m2564_b = {1'b0, redist1033_i_conv_i_i_i_i97_i_82_c_compmm_m2560_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_82_c_compmm_m2564_o = $unsigned(i_add_i_i_i_i_i126_i_82_c_compmm_m2564_a) + $unsigned(i_add_i_i_i_i_i126_i_82_c_compmm_m2564_b);
    assign i_add_i_i_i_i_i126_i_82_c_compmm_m2564_q = i_add_i_i_i_i_i126_i_82_c_compmm_m2564_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_82_c_compmm_m2564_sel_x(BITSELECT,2153)@239
    assign bgTrunc_i_add_i_i_i_i_i126_i_82_c_compmm_m2564_sel_x_b = i_add_i_i_i_i_i126_i_82_c_compmm_m2564_q[15:0];

    // i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_sel_x(BITSELECT,3686)@239
    assign i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_82_c_compmm_m2564_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_select_15(BITSELECT,7855)@239
    assign i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_select_15_b = i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_join(BITJOIN,7854)@239
    assign i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_select_15_b};

    // leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(MUX,25720)@239
    assign leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_join_q or leftShiftStage0Idx1_uid25719_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_83_c_compmm_m2584_vt_join_q;
            1'b1 : leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25719_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(MUX,25725)@239
    assign leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s or leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25724_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = leftShiftStage0_uid25721_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25724_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x(MUX,25730)@239
    assign leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s or leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25729_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = leftShiftStage1_uid25726_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25729_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28(BITSELECT,9784)@239
    assign i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28_b = leftShiftStage2_uid25731_i_shl_i_i_i_i_i77_i_83_c_compmm_m0_shift_x_q[28:13];

    // redist394_i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28_b_1(DELAY,29522)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist394_i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_join(BITJOIN,9783)@240
    assign i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_join_q = {redist394_i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma(CHAINMULTADD,29108)@234 + 5
    // out q@240
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_66186_c_compmm_m90_out_dest_data_out_168_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_66185_c_compmm_m91_out_dest_data_out_167_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ch[0] <= redist670_sync_together4364_aunroll_x_in_c1_eni5_168_tpl_166_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ch[1] <= redist669_sync_together4364_aunroll_x_in_c1_eni5_167_tpl_166_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586(ADD,8928)@240
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_83_i_c_compmm_m2581_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_83_i_c_compmm_m2583_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_83_i_c_compmm_m2582_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_83_c_compmm_m2585_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_o[33:0];

    // rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x(MUX,20986)@240
    assign rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q or rightShiftStage0Idx1_uid20985_dupName_331_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q;
            1'b1 : rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid20985_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x(MUX,20991)@240
    assign rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid20990_dupName_331_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid20987_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid20990_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x(MUX,20996)@240
    assign rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid20995_dupName_331_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid20992_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid20995_dupName_331_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2587_vt_select_20(BITSELECT,11465)@240
    assign i_unnamed_c_compmm_m2587_vt_select_20_b = rightShiftStage2_uid20997_dupName_331_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2587_vt_join(BITJOIN,11464)@240
    assign i_unnamed_c_compmm_m2587_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2587_vt_select_20_b};

    // i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x(BITSELECT,3557)@240
    assign i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x_b = i_unnamed_c_compmm_m2587_vt_join_q[15:0];

    // redist1032_i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x_b_1(DELAY,30160)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1032_i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21006_dupName_332_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21005)@240
    assign rightShiftStage1Idx1Rng8_uid21006_dupName_332_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21008_dupName_332_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21007)@240
    assign rightShiftStage1Idx1_uid21008_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21006_dupName_332_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21001_dupName_332_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21000)@240
    assign rightShiftStage0Idx1Rng4_uid21001_dupName_332_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q[33:4];

    // rightShiftStage0Idx1_uid21003_dupName_332_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21002)@240
    assign rightShiftStage0Idx1_uid21003_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21001_dupName_332_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x(MUX,21004)@240
    assign rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q or rightShiftStage0Idx1_uid21003_dupName_332_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_83_i_c_compmm_m2586_q;
            1'b1 : rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21003_dupName_332_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x(MUX,21009)@240
    assign rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21008_dupName_332_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21005_dupName_332_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21008_dupName_332_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2589_vt_select_21(BITSELECT,11468)@240
    assign i_unnamed_c_compmm_m2589_vt_select_21_b = rightShiftStage1_uid21010_dupName_332_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2589_vt_join(BITJOIN,11467)@240
    assign i_unnamed_c_compmm_m2589_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2589_vt_select_21_b};

    // i_unnamed_c_compmm_m2590_sel_x(BITSELECT,6117)@240
    assign i_unnamed_c_compmm_m2590_sel_x_b = i_unnamed_c_compmm_m2589_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2591_BitSelect_for_a(BITSELECT,28586)@240
    assign i_unnamed_c_compmm_m2591_BitSelect_for_a_b = i_unnamed_c_compmm_m2590_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2591_join(BITJOIN,28587)@240
    assign i_unnamed_c_compmm_m2591_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2591_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2591_vt_select_0(BITSELECT,11473)@240
    assign i_unnamed_c_compmm_m2591_vt_select_0_b = i_unnamed_c_compmm_m2591_join_q[0:0];

    // redist141_i_unnamed_c_compmm_m2591_vt_select_0_b_1(DELAY,29269)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist141_i_unnamed_c_compmm_m2591_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2591_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2591_vt_join(BITJOIN,11472)@241
    assign i_unnamed_c_compmm_m2591_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist141_i_unnamed_c_compmm_m2591_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_83_c_compmm_m2592(ADD,7140)@241
    assign i_add_i_i_i_i_i126_i_83_c_compmm_m2592_a = {1'b0, i_unnamed_c_compmm_m2591_vt_join_q};
    assign i_add_i_i_i_i_i126_i_83_c_compmm_m2592_b = {1'b0, redist1032_i_conv_i_i_i_i97_i_83_c_compmm_m2588_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_83_c_compmm_m2592_o = $unsigned(i_add_i_i_i_i_i126_i_83_c_compmm_m2592_a) + $unsigned(i_add_i_i_i_i_i126_i_83_c_compmm_m2592_b);
    assign i_add_i_i_i_i_i126_i_83_c_compmm_m2592_q = i_add_i_i_i_i_i126_i_83_c_compmm_m2592_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_83_c_compmm_m2592_sel_x(BITSELECT,2154)@241
    assign bgTrunc_i_add_i_i_i_i_i126_i_83_c_compmm_m2592_sel_x_b = i_add_i_i_i_i_i126_i_83_c_compmm_m2592_q[15:0];

    // i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_sel_x(BITSELECT,3687)@241
    assign i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_83_c_compmm_m2592_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_select_15(BITSELECT,7859)@241
    assign i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_select_15_b = i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_join(BITJOIN,7858)@241
    assign i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_select_15_b};

    // leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(MUX,25738)@241
    assign leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_join_q or leftShiftStage0Idx1_uid25737_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_84_c_compmm_m2612_vt_join_q;
            1'b1 : leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25737_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(MUX,25743)@241
    assign leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s or leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25742_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = leftShiftStage0_uid25739_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25742_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x(MUX,25748)@241
    assign leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s or leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25747_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = leftShiftStage1_uid25744_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25747_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28(BITSELECT,9787)@241
    assign i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28_b = leftShiftStage2_uid25749_i_shl_i_i_i_i_i77_i_84_c_compmm_m0_shift_x_q[28:13];

    // redist393_i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28_b_1(DELAY,29521)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist393_i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_join(BITJOIN,9786)@242
    assign i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_join_q = {redist393_i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma(CHAINMULTADD,29109)@236 + 5
    // out q@242
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_66188_c_compmm_m88_out_dest_data_out_170_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_66187_c_compmm_m89_out_dest_data_out_169_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ch[0] <= redist672_sync_together4364_aunroll_x_in_c1_eni5_170_tpl_168_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ch[1] <= redist671_sync_together4364_aunroll_x_in_c1_eni5_169_tpl_168_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614(ADD,8929)@242
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_84_i_c_compmm_m2609_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_84_i_c_compmm_m2611_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_84_i_c_compmm_m2610_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_84_c_compmm_m2613_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_o[33:0];

    // rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x(MUX,21048)@242
    assign rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q or rightShiftStage0Idx1_uid21047_dupName_335_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q;
            1'b1 : rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21047_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x(MUX,21053)@242
    assign rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21052_dupName_335_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21049_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21052_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x(MUX,21058)@242
    assign rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21057_dupName_335_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21054_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21057_dupName_335_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2615_vt_select_20(BITSELECT,11487)@242
    assign i_unnamed_c_compmm_m2615_vt_select_20_b = rightShiftStage2_uid21059_dupName_335_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2615_vt_join(BITJOIN,11486)@242
    assign i_unnamed_c_compmm_m2615_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2615_vt_select_20_b};

    // i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x(BITSELECT,3558)@242
    assign i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x_b = i_unnamed_c_compmm_m2615_vt_join_q[15:0];

    // redist1031_i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x_b_1(DELAY,30159)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1031_i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21068_dupName_336_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21067)@242
    assign rightShiftStage1Idx1Rng8_uid21068_dupName_336_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21070_dupName_336_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21069)@242
    assign rightShiftStage1Idx1_uid21070_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21068_dupName_336_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21063_dupName_336_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21062)@242
    assign rightShiftStage0Idx1Rng4_uid21063_dupName_336_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q[33:4];

    // rightShiftStage0Idx1_uid21065_dupName_336_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21064)@242
    assign rightShiftStage0Idx1_uid21065_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21063_dupName_336_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x(MUX,21066)@242
    assign rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q or rightShiftStage0Idx1_uid21065_dupName_336_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_84_i_c_compmm_m2614_q;
            1'b1 : rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21065_dupName_336_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x(MUX,21071)@242
    assign rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21070_dupName_336_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21067_dupName_336_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21070_dupName_336_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2617_vt_select_21(BITSELECT,11490)@242
    assign i_unnamed_c_compmm_m2617_vt_select_21_b = rightShiftStage1_uid21072_dupName_336_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2617_vt_join(BITJOIN,11489)@242
    assign i_unnamed_c_compmm_m2617_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2617_vt_select_21_b};

    // i_unnamed_c_compmm_m2618_sel_x(BITSELECT,6119)@242
    assign i_unnamed_c_compmm_m2618_sel_x_b = i_unnamed_c_compmm_m2617_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2619_BitSelect_for_a(BITSELECT,28590)@242
    assign i_unnamed_c_compmm_m2619_BitSelect_for_a_b = i_unnamed_c_compmm_m2618_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2619_join(BITJOIN,28591)@242
    assign i_unnamed_c_compmm_m2619_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2619_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2619_vt_select_0(BITSELECT,11495)@242
    assign i_unnamed_c_compmm_m2619_vt_select_0_b = i_unnamed_c_compmm_m2619_join_q[0:0];

    // redist139_i_unnamed_c_compmm_m2619_vt_select_0_b_1(DELAY,29267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist139_i_unnamed_c_compmm_m2619_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2619_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2619_vt_join(BITJOIN,11494)@243
    assign i_unnamed_c_compmm_m2619_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist139_i_unnamed_c_compmm_m2619_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_84_c_compmm_m2620(ADD,7141)@243
    assign i_add_i_i_i_i_i126_i_84_c_compmm_m2620_a = {1'b0, i_unnamed_c_compmm_m2619_vt_join_q};
    assign i_add_i_i_i_i_i126_i_84_c_compmm_m2620_b = {1'b0, redist1031_i_conv_i_i_i_i97_i_84_c_compmm_m2616_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_84_c_compmm_m2620_o = $unsigned(i_add_i_i_i_i_i126_i_84_c_compmm_m2620_a) + $unsigned(i_add_i_i_i_i_i126_i_84_c_compmm_m2620_b);
    assign i_add_i_i_i_i_i126_i_84_c_compmm_m2620_q = i_add_i_i_i_i_i126_i_84_c_compmm_m2620_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_84_c_compmm_m2620_sel_x(BITSELECT,2155)@243
    assign bgTrunc_i_add_i_i_i_i_i126_i_84_c_compmm_m2620_sel_x_b = i_add_i_i_i_i_i126_i_84_c_compmm_m2620_q[15:0];

    // i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_sel_x(BITSELECT,3688)@243
    assign i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_84_c_compmm_m2620_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_select_15(BITSELECT,7863)@243
    assign i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_select_15_b = i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_join(BITJOIN,7862)@243
    assign i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_select_15_b};

    // leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(MUX,25756)@243
    assign leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_join_q or leftShiftStage0Idx1_uid25755_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_85_c_compmm_m2640_vt_join_q;
            1'b1 : leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25755_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(MUX,25761)@243
    assign leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s or leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25760_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = leftShiftStage0_uid25757_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25760_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x(MUX,25766)@243
    assign leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s or leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25765_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = leftShiftStage1_uid25762_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25765_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28(BITSELECT,9790)@243
    assign i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28_b = leftShiftStage2_uid25767_i_shl_i_i_i_i_i77_i_85_c_compmm_m0_shift_x_q[28:13];

    // redist392_i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28_b_1(DELAY,29520)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist392_i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_join(BITJOIN,9789)@244
    assign i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_join_q = {redist392_i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma(CHAINMULTADD,29110)@238 + 5
    // out q@244
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_66190_c_compmm_m86_out_dest_data_out_172_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_66189_c_compmm_m87_out_dest_data_out_171_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ch[0] <= redist674_sync_together4364_aunroll_x_in_c1_eni5_172_tpl_170_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ch[1] <= redist673_sync_together4364_aunroll_x_in_c1_eni5_171_tpl_170_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642(ADD,8930)@244
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_85_i_c_compmm_m2637_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_85_i_c_compmm_m2639_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_85_i_c_compmm_m2638_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_85_c_compmm_m2641_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_o[33:0];

    // rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x(MUX,21110)@244
    assign rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q or rightShiftStage0Idx1_uid21109_dupName_339_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q;
            1'b1 : rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21109_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x(MUX,21115)@244
    assign rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21114_dupName_339_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21111_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21114_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x(MUX,21120)@244
    assign rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21119_dupName_339_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21116_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21119_dupName_339_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2643_vt_select_20(BITSELECT,11512)@244
    assign i_unnamed_c_compmm_m2643_vt_select_20_b = rightShiftStage2_uid21121_dupName_339_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2643_vt_join(BITJOIN,11511)@244
    assign i_unnamed_c_compmm_m2643_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2643_vt_select_20_b};

    // i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x(BITSELECT,3559)@244
    assign i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x_b = i_unnamed_c_compmm_m2643_vt_join_q[15:0];

    // redist1030_i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x_b_1(DELAY,30158)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1030_i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21130_dupName_340_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21129)@244
    assign rightShiftStage1Idx1Rng8_uid21130_dupName_340_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21132_dupName_340_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21131)@244
    assign rightShiftStage1Idx1_uid21132_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21130_dupName_340_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21125_dupName_340_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21124)@244
    assign rightShiftStage0Idx1Rng4_uid21125_dupName_340_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q[33:4];

    // rightShiftStage0Idx1_uid21127_dupName_340_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21126)@244
    assign rightShiftStage0Idx1_uid21127_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21125_dupName_340_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x(MUX,21128)@244
    assign rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q or rightShiftStage0Idx1_uid21127_dupName_340_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_85_i_c_compmm_m2642_q;
            1'b1 : rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21127_dupName_340_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x(MUX,21133)@244
    assign rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21132_dupName_340_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21129_dupName_340_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21132_dupName_340_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2645_vt_select_21(BITSELECT,11515)@244
    assign i_unnamed_c_compmm_m2645_vt_select_21_b = rightShiftStage1_uid21134_dupName_340_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2645_vt_join(BITJOIN,11514)@244
    assign i_unnamed_c_compmm_m2645_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2645_vt_select_21_b};

    // i_unnamed_c_compmm_m2646_sel_x(BITSELECT,6121)@244
    assign i_unnamed_c_compmm_m2646_sel_x_b = i_unnamed_c_compmm_m2645_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2647_BitSelect_for_a(BITSELECT,28594)@244
    assign i_unnamed_c_compmm_m2647_BitSelect_for_a_b = i_unnamed_c_compmm_m2646_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2647_join(BITJOIN,28595)@244
    assign i_unnamed_c_compmm_m2647_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2647_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2647_vt_select_0(BITSELECT,11520)@244
    assign i_unnamed_c_compmm_m2647_vt_select_0_b = i_unnamed_c_compmm_m2647_join_q[0:0];

    // redist137_i_unnamed_c_compmm_m2647_vt_select_0_b_1(DELAY,29265)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist137_i_unnamed_c_compmm_m2647_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2647_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2647_vt_join(BITJOIN,11519)@245
    assign i_unnamed_c_compmm_m2647_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist137_i_unnamed_c_compmm_m2647_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_85_c_compmm_m2648(ADD,7142)@245
    assign i_add_i_i_i_i_i126_i_85_c_compmm_m2648_a = {1'b0, i_unnamed_c_compmm_m2647_vt_join_q};
    assign i_add_i_i_i_i_i126_i_85_c_compmm_m2648_b = {1'b0, redist1030_i_conv_i_i_i_i97_i_85_c_compmm_m2644_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_85_c_compmm_m2648_o = $unsigned(i_add_i_i_i_i_i126_i_85_c_compmm_m2648_a) + $unsigned(i_add_i_i_i_i_i126_i_85_c_compmm_m2648_b);
    assign i_add_i_i_i_i_i126_i_85_c_compmm_m2648_q = i_add_i_i_i_i_i126_i_85_c_compmm_m2648_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_85_c_compmm_m2648_sel_x(BITSELECT,2156)@245
    assign bgTrunc_i_add_i_i_i_i_i126_i_85_c_compmm_m2648_sel_x_b = i_add_i_i_i_i_i126_i_85_c_compmm_m2648_q[15:0];

    // i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_sel_x(BITSELECT,3689)@245
    assign i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_85_c_compmm_m2648_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_select_15(BITSELECT,7867)@245
    assign i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_select_15_b = i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_join(BITJOIN,7866)@245
    assign i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_select_15_b};

    // leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(MUX,25774)@245
    assign leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_join_q or leftShiftStage0Idx1_uid25773_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_86_c_compmm_m2668_vt_join_q;
            1'b1 : leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25773_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(MUX,25779)@245
    assign leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s or leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25778_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = leftShiftStage0_uid25775_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25778_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x(MUX,25784)@245
    assign leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s or leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25783_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = leftShiftStage1_uid25780_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25783_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28(BITSELECT,9793)@245
    assign i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28_b = leftShiftStage2_uid25785_i_shl_i_i_i_i_i77_i_86_c_compmm_m0_shift_x_q[28:13];

    // redist391_i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28_b_1(DELAY,29519)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist391_i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_join(BITJOIN,9792)@246
    assign i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_join_q = {redist391_i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma(CHAINMULTADD,29111)@240 + 5
    // out q@246
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_66192_c_compmm_m84_out_dest_data_out_174_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_66191_c_compmm_m85_out_dest_data_out_173_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ch[0] <= redist676_sync_together4364_aunroll_x_in_c1_eni5_174_tpl_172_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ch[1] <= redist675_sync_together4364_aunroll_x_in_c1_eni5_173_tpl_172_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670(ADD,8931)@246
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_86_i_c_compmm_m2665_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_86_i_c_compmm_m2667_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_86_i_c_compmm_m2666_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_86_c_compmm_m2669_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_o[33:0];

    // rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x(MUX,21172)@246
    assign rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q or rightShiftStage0Idx1_uid21171_dupName_343_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q;
            1'b1 : rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21171_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x(MUX,21177)@246
    assign rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21176_dupName_343_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21173_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21176_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x(MUX,21182)@246
    assign rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21181_dupName_343_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21178_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21181_dupName_343_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2671_vt_select_20(BITSELECT,11539)@246
    assign i_unnamed_c_compmm_m2671_vt_select_20_b = rightShiftStage2_uid21183_dupName_343_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2671_vt_join(BITJOIN,11538)@246
    assign i_unnamed_c_compmm_m2671_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2671_vt_select_20_b};

    // i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x(BITSELECT,3560)@246
    assign i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x_b = i_unnamed_c_compmm_m2671_vt_join_q[15:0];

    // redist1029_i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x_b_1(DELAY,30157)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1029_i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21192_dupName_344_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21191)@246
    assign rightShiftStage1Idx1Rng8_uid21192_dupName_344_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21194_dupName_344_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21193)@246
    assign rightShiftStage1Idx1_uid21194_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21192_dupName_344_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21187_dupName_344_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21186)@246
    assign rightShiftStage0Idx1Rng4_uid21187_dupName_344_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q[33:4];

    // rightShiftStage0Idx1_uid21189_dupName_344_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21188)@246
    assign rightShiftStage0Idx1_uid21189_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21187_dupName_344_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x(MUX,21190)@246
    assign rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q or rightShiftStage0Idx1_uid21189_dupName_344_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_86_i_c_compmm_m2670_q;
            1'b1 : rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21189_dupName_344_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x(MUX,21195)@246
    assign rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21194_dupName_344_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21191_dupName_344_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21194_dupName_344_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2673_vt_select_21(BITSELECT,11542)@246
    assign i_unnamed_c_compmm_m2673_vt_select_21_b = rightShiftStage1_uid21196_dupName_344_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2673_vt_join(BITJOIN,11541)@246
    assign i_unnamed_c_compmm_m2673_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2673_vt_select_21_b};

    // i_unnamed_c_compmm_m2674_sel_x(BITSELECT,6124)@246
    assign i_unnamed_c_compmm_m2674_sel_x_b = i_unnamed_c_compmm_m2673_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2675_BitSelect_for_a(BITSELECT,28600)@246
    assign i_unnamed_c_compmm_m2675_BitSelect_for_a_b = i_unnamed_c_compmm_m2674_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2675_join(BITJOIN,28601)@246
    assign i_unnamed_c_compmm_m2675_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2675_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2675_vt_select_0(BITSELECT,11547)@246
    assign i_unnamed_c_compmm_m2675_vt_select_0_b = i_unnamed_c_compmm_m2675_join_q[0:0];

    // redist135_i_unnamed_c_compmm_m2675_vt_select_0_b_1(DELAY,29263)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist135_i_unnamed_c_compmm_m2675_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2675_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2675_vt_join(BITJOIN,11546)@247
    assign i_unnamed_c_compmm_m2675_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist135_i_unnamed_c_compmm_m2675_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_86_c_compmm_m2676(ADD,7143)@247
    assign i_add_i_i_i_i_i126_i_86_c_compmm_m2676_a = {1'b0, i_unnamed_c_compmm_m2675_vt_join_q};
    assign i_add_i_i_i_i_i126_i_86_c_compmm_m2676_b = {1'b0, redist1029_i_conv_i_i_i_i97_i_86_c_compmm_m2672_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_86_c_compmm_m2676_o = $unsigned(i_add_i_i_i_i_i126_i_86_c_compmm_m2676_a) + $unsigned(i_add_i_i_i_i_i126_i_86_c_compmm_m2676_b);
    assign i_add_i_i_i_i_i126_i_86_c_compmm_m2676_q = i_add_i_i_i_i_i126_i_86_c_compmm_m2676_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_86_c_compmm_m2676_sel_x(BITSELECT,2157)@247
    assign bgTrunc_i_add_i_i_i_i_i126_i_86_c_compmm_m2676_sel_x_b = i_add_i_i_i_i_i126_i_86_c_compmm_m2676_q[15:0];

    // i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_sel_x(BITSELECT,3690)@247
    assign i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_86_c_compmm_m2676_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_select_15(BITSELECT,7871)@247
    assign i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_select_15_b = i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_join(BITJOIN,7870)@247
    assign i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_select_15_b};

    // leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(MUX,25792)@247
    assign leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_join_q or leftShiftStage0Idx1_uid25791_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_87_c_compmm_m2696_vt_join_q;
            1'b1 : leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25791_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(MUX,25797)@247
    assign leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s or leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25796_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = leftShiftStage0_uid25793_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25796_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x(MUX,25802)@247
    assign leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s or leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25801_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = leftShiftStage1_uid25798_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25801_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28(BITSELECT,9796)@247
    assign i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28_b = leftShiftStage2_uid25803_i_shl_i_i_i_i_i77_i_87_c_compmm_m0_shift_x_q[28:13];

    // redist390_i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28_b_1(DELAY,29518)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist390_i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_join(BITJOIN,9795)@248
    assign i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_join_q = {redist390_i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma(CHAINMULTADD,29112)@242 + 5
    // out q@248
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_66194_c_compmm_m82_out_dest_data_out_176_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_66193_c_compmm_m83_out_dest_data_out_175_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ch[0] <= redist678_sync_together4364_aunroll_x_in_c1_eni5_176_tpl_174_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ch[1] <= redist677_sync_together4364_aunroll_x_in_c1_eni5_175_tpl_174_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698(ADD,8932)@248
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_87_i_c_compmm_m2693_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_87_i_c_compmm_m2695_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_87_i_c_compmm_m2694_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_87_c_compmm_m2697_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_o[33:0];

    // rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x(MUX,21234)@248
    assign rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q or rightShiftStage0Idx1_uid21233_dupName_347_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q;
            1'b1 : rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21233_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x(MUX,21239)@248
    assign rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21238_dupName_347_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21235_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21238_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x(MUX,21244)@248
    assign rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21243_dupName_347_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21240_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21243_dupName_347_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2699_vt_select_20(BITSELECT,11564)@248
    assign i_unnamed_c_compmm_m2699_vt_select_20_b = rightShiftStage2_uid21245_dupName_347_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2699_vt_join(BITJOIN,11563)@248
    assign i_unnamed_c_compmm_m2699_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2699_vt_select_20_b};

    // i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x(BITSELECT,3561)@248
    assign i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x_b = i_unnamed_c_compmm_m2699_vt_join_q[15:0];

    // redist1028_i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x_b_1(DELAY,30156)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1028_i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21254_dupName_348_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21253)@248
    assign rightShiftStage1Idx1Rng8_uid21254_dupName_348_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21256_dupName_348_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21255)@248
    assign rightShiftStage1Idx1_uid21256_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21254_dupName_348_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21249_dupName_348_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21248)@248
    assign rightShiftStage0Idx1Rng4_uid21249_dupName_348_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q[33:4];

    // rightShiftStage0Idx1_uid21251_dupName_348_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21250)@248
    assign rightShiftStage0Idx1_uid21251_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21249_dupName_348_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x(MUX,21252)@248
    assign rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q or rightShiftStage0Idx1_uid21251_dupName_348_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_87_i_c_compmm_m2698_q;
            1'b1 : rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21251_dupName_348_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x(MUX,21257)@248
    assign rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21256_dupName_348_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21253_dupName_348_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21256_dupName_348_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2701_vt_select_21(BITSELECT,11567)@248
    assign i_unnamed_c_compmm_m2701_vt_select_21_b = rightShiftStage1_uid21258_dupName_348_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2701_vt_join(BITJOIN,11566)@248
    assign i_unnamed_c_compmm_m2701_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2701_vt_select_21_b};

    // i_unnamed_c_compmm_m2702_sel_x(BITSELECT,6126)@248
    assign i_unnamed_c_compmm_m2702_sel_x_b = i_unnamed_c_compmm_m2701_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2703_BitSelect_for_a(BITSELECT,28604)@248
    assign i_unnamed_c_compmm_m2703_BitSelect_for_a_b = i_unnamed_c_compmm_m2702_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2703_join(BITJOIN,28605)@248
    assign i_unnamed_c_compmm_m2703_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2703_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2703_vt_select_0(BITSELECT,11572)@248
    assign i_unnamed_c_compmm_m2703_vt_select_0_b = i_unnamed_c_compmm_m2703_join_q[0:0];

    // redist133_i_unnamed_c_compmm_m2703_vt_select_0_b_1(DELAY,29261)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist133_i_unnamed_c_compmm_m2703_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2703_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2703_vt_join(BITJOIN,11571)@249
    assign i_unnamed_c_compmm_m2703_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist133_i_unnamed_c_compmm_m2703_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_87_c_compmm_m2704(ADD,7144)@249
    assign i_add_i_i_i_i_i126_i_87_c_compmm_m2704_a = {1'b0, i_unnamed_c_compmm_m2703_vt_join_q};
    assign i_add_i_i_i_i_i126_i_87_c_compmm_m2704_b = {1'b0, redist1028_i_conv_i_i_i_i97_i_87_c_compmm_m2700_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_87_c_compmm_m2704_o = $unsigned(i_add_i_i_i_i_i126_i_87_c_compmm_m2704_a) + $unsigned(i_add_i_i_i_i_i126_i_87_c_compmm_m2704_b);
    assign i_add_i_i_i_i_i126_i_87_c_compmm_m2704_q = i_add_i_i_i_i_i126_i_87_c_compmm_m2704_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_87_c_compmm_m2704_sel_x(BITSELECT,2158)@249
    assign bgTrunc_i_add_i_i_i_i_i126_i_87_c_compmm_m2704_sel_x_b = i_add_i_i_i_i_i126_i_87_c_compmm_m2704_q[15:0];

    // i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_sel_x(BITSELECT,3691)@249
    assign i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_87_c_compmm_m2704_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_select_15(BITSELECT,7875)@249
    assign i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_select_15_b = i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_join(BITJOIN,7874)@249
    assign i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_select_15_b};

    // leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(MUX,25810)@249
    assign leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_join_q or leftShiftStage0Idx1_uid25809_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_88_c_compmm_m2724_vt_join_q;
            1'b1 : leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25809_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(MUX,25815)@249
    assign leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s or leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25814_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = leftShiftStage0_uid25811_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25814_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x(MUX,25820)@249
    assign leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s or leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25819_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = leftShiftStage1_uid25816_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25819_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28(BITSELECT,9799)@249
    assign i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28_b = leftShiftStage2_uid25821_i_shl_i_i_i_i_i77_i_88_c_compmm_m0_shift_x_q[28:13];

    // redist389_i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28_b_1(DELAY,29517)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist389_i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_join(BITJOIN,9798)@250
    assign i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_join_q = {redist389_i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma(CHAINMULTADD,29113)@244 + 5
    // out q@250
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_66196_c_compmm_m80_out_dest_data_out_178_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_66195_c_compmm_m81_out_dest_data_out_177_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ch[0] <= redist680_sync_together4364_aunroll_x_in_c1_eni5_178_tpl_176_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ch[1] <= redist679_sync_together4364_aunroll_x_in_c1_eni5_177_tpl_176_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726(ADD,8933)@250
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_88_i_c_compmm_m2721_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_88_i_c_compmm_m2723_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_88_i_c_compmm_m2722_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_88_c_compmm_m2725_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_o[33:0];

    // rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x(MUX,21296)@250
    assign rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q or rightShiftStage0Idx1_uid21295_dupName_351_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q;
            1'b1 : rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21295_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x(MUX,21301)@250
    assign rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21300_dupName_351_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21297_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21300_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x(MUX,21306)@250
    assign rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21305_dupName_351_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21302_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21305_dupName_351_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2727_vt_select_20(BITSELECT,11586)@250
    assign i_unnamed_c_compmm_m2727_vt_select_20_b = rightShiftStage2_uid21307_dupName_351_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2727_vt_join(BITJOIN,11585)@250
    assign i_unnamed_c_compmm_m2727_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2727_vt_select_20_b};

    // i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x(BITSELECT,3562)@250
    assign i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x_b = i_unnamed_c_compmm_m2727_vt_join_q[15:0];

    // redist1027_i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x_b_1(DELAY,30155)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1027_i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21316_dupName_352_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21315)@250
    assign rightShiftStage1Idx1Rng8_uid21316_dupName_352_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21318_dupName_352_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21317)@250
    assign rightShiftStage1Idx1_uid21318_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21316_dupName_352_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21311_dupName_352_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21310)@250
    assign rightShiftStage0Idx1Rng4_uid21311_dupName_352_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q[33:4];

    // rightShiftStage0Idx1_uid21313_dupName_352_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21312)@250
    assign rightShiftStage0Idx1_uid21313_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21311_dupName_352_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x(MUX,21314)@250
    assign rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q or rightShiftStage0Idx1_uid21313_dupName_352_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_88_i_c_compmm_m2726_q;
            1'b1 : rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21313_dupName_352_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x(MUX,21319)@250
    assign rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21318_dupName_352_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21315_dupName_352_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21318_dupName_352_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2729_vt_select_21(BITSELECT,11589)@250
    assign i_unnamed_c_compmm_m2729_vt_select_21_b = rightShiftStage1_uid21320_dupName_352_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2729_vt_join(BITJOIN,11588)@250
    assign i_unnamed_c_compmm_m2729_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2729_vt_select_21_b};

    // i_unnamed_c_compmm_m2730_sel_x(BITSELECT,6128)@250
    assign i_unnamed_c_compmm_m2730_sel_x_b = i_unnamed_c_compmm_m2729_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2731_BitSelect_for_a(BITSELECT,28608)@250
    assign i_unnamed_c_compmm_m2731_BitSelect_for_a_b = i_unnamed_c_compmm_m2730_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2731_join(BITJOIN,28609)@250
    assign i_unnamed_c_compmm_m2731_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2731_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2731_vt_select_0(BITSELECT,11594)@250
    assign i_unnamed_c_compmm_m2731_vt_select_0_b = i_unnamed_c_compmm_m2731_join_q[0:0];

    // redist131_i_unnamed_c_compmm_m2731_vt_select_0_b_1(DELAY,29259)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist131_i_unnamed_c_compmm_m2731_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2731_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2731_vt_join(BITJOIN,11593)@251
    assign i_unnamed_c_compmm_m2731_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist131_i_unnamed_c_compmm_m2731_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_88_c_compmm_m2732(ADD,7145)@251
    assign i_add_i_i_i_i_i126_i_88_c_compmm_m2732_a = {1'b0, i_unnamed_c_compmm_m2731_vt_join_q};
    assign i_add_i_i_i_i_i126_i_88_c_compmm_m2732_b = {1'b0, redist1027_i_conv_i_i_i_i97_i_88_c_compmm_m2728_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_88_c_compmm_m2732_o = $unsigned(i_add_i_i_i_i_i126_i_88_c_compmm_m2732_a) + $unsigned(i_add_i_i_i_i_i126_i_88_c_compmm_m2732_b);
    assign i_add_i_i_i_i_i126_i_88_c_compmm_m2732_q = i_add_i_i_i_i_i126_i_88_c_compmm_m2732_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_88_c_compmm_m2732_sel_x(BITSELECT,2159)@251
    assign bgTrunc_i_add_i_i_i_i_i126_i_88_c_compmm_m2732_sel_x_b = i_add_i_i_i_i_i126_i_88_c_compmm_m2732_q[15:0];

    // i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_sel_x(BITSELECT,3692)@251
    assign i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_88_c_compmm_m2732_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_select_15(BITSELECT,7879)@251
    assign i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_select_15_b = i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_join(BITJOIN,7878)@251
    assign i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_select_15_b};

    // leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(MUX,25828)@251
    assign leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_join_q or leftShiftStage0Idx1_uid25827_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_89_c_compmm_m2752_vt_join_q;
            1'b1 : leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25827_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(MUX,25833)@251
    assign leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s or leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25832_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = leftShiftStage0_uid25829_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25832_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x(MUX,25838)@251
    assign leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s or leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25837_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = leftShiftStage1_uid25834_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25837_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28(BITSELECT,9802)@251
    assign i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28_b = leftShiftStage2_uid25839_i_shl_i_i_i_i_i77_i_89_c_compmm_m0_shift_x_q[28:13];

    // redist388_i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28_b_1(DELAY,29516)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist388_i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_join(BITJOIN,9801)@252
    assign i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_join_q = {redist388_i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma(CHAINMULTADD,29114)@246 + 5
    // out q@252
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_66198_c_compmm_m78_out_dest_data_out_180_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_66197_c_compmm_m79_out_dest_data_out_179_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ch[0] <= redist682_sync_together4364_aunroll_x_in_c1_eni5_180_tpl_178_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ch[1] <= redist681_sync_together4364_aunroll_x_in_c1_eni5_179_tpl_178_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754(ADD,8934)@252
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_89_i_c_compmm_m2749_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_89_i_c_compmm_m2751_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_89_i_c_compmm_m2750_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_89_c_compmm_m2753_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_o[33:0];

    // rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x(MUX,21358)@252
    assign rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q or rightShiftStage0Idx1_uid21357_dupName_355_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q;
            1'b1 : rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21357_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x(MUX,21363)@252
    assign rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21362_dupName_355_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21359_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21362_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x(MUX,21368)@252
    assign rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21367_dupName_355_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21364_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21367_dupName_355_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2755_vt_select_20(BITSELECT,11608)@252
    assign i_unnamed_c_compmm_m2755_vt_select_20_b = rightShiftStage2_uid21369_dupName_355_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2755_vt_join(BITJOIN,11607)@252
    assign i_unnamed_c_compmm_m2755_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2755_vt_select_20_b};

    // i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x(BITSELECT,3563)@252
    assign i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x_b = i_unnamed_c_compmm_m2755_vt_join_q[15:0];

    // redist1026_i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x_b_1(DELAY,30154)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1026_i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21378_dupName_356_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21377)@252
    assign rightShiftStage1Idx1Rng8_uid21378_dupName_356_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21380_dupName_356_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21379)@252
    assign rightShiftStage1Idx1_uid21380_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21378_dupName_356_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21373_dupName_356_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21372)@252
    assign rightShiftStage0Idx1Rng4_uid21373_dupName_356_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q[33:4];

    // rightShiftStage0Idx1_uid21375_dupName_356_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21374)@252
    assign rightShiftStage0Idx1_uid21375_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21373_dupName_356_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x(MUX,21376)@252
    assign rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q or rightShiftStage0Idx1_uid21375_dupName_356_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_89_i_c_compmm_m2754_q;
            1'b1 : rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21375_dupName_356_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x(MUX,21381)@252
    assign rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21380_dupName_356_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21377_dupName_356_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21380_dupName_356_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2757_vt_select_21(BITSELECT,11611)@252
    assign i_unnamed_c_compmm_m2757_vt_select_21_b = rightShiftStage1_uid21382_dupName_356_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2757_vt_join(BITJOIN,11610)@252
    assign i_unnamed_c_compmm_m2757_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2757_vt_select_21_b};

    // i_unnamed_c_compmm_m2758_sel_x(BITSELECT,6130)@252
    assign i_unnamed_c_compmm_m2758_sel_x_b = i_unnamed_c_compmm_m2757_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2759_BitSelect_for_a(BITSELECT,28612)@252
    assign i_unnamed_c_compmm_m2759_BitSelect_for_a_b = i_unnamed_c_compmm_m2758_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2759_join(BITJOIN,28613)@252
    assign i_unnamed_c_compmm_m2759_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2759_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2759_vt_select_0(BITSELECT,11616)@252
    assign i_unnamed_c_compmm_m2759_vt_select_0_b = i_unnamed_c_compmm_m2759_join_q[0:0];

    // redist129_i_unnamed_c_compmm_m2759_vt_select_0_b_1(DELAY,29257)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist129_i_unnamed_c_compmm_m2759_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2759_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2759_vt_join(BITJOIN,11615)@253
    assign i_unnamed_c_compmm_m2759_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist129_i_unnamed_c_compmm_m2759_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_89_c_compmm_m2760(ADD,7146)@253
    assign i_add_i_i_i_i_i126_i_89_c_compmm_m2760_a = {1'b0, i_unnamed_c_compmm_m2759_vt_join_q};
    assign i_add_i_i_i_i_i126_i_89_c_compmm_m2760_b = {1'b0, redist1026_i_conv_i_i_i_i97_i_89_c_compmm_m2756_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_89_c_compmm_m2760_o = $unsigned(i_add_i_i_i_i_i126_i_89_c_compmm_m2760_a) + $unsigned(i_add_i_i_i_i_i126_i_89_c_compmm_m2760_b);
    assign i_add_i_i_i_i_i126_i_89_c_compmm_m2760_q = i_add_i_i_i_i_i126_i_89_c_compmm_m2760_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_89_c_compmm_m2760_sel_x(BITSELECT,2160)@253
    assign bgTrunc_i_add_i_i_i_i_i126_i_89_c_compmm_m2760_sel_x_b = i_add_i_i_i_i_i126_i_89_c_compmm_m2760_q[15:0];

    // i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_sel_x(BITSELECT,3694)@253
    assign i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_89_c_compmm_m2760_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_select_15(BITSELECT,7887)@253
    assign i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_select_15_b = i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_join(BITJOIN,7886)@253
    assign i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_select_15_b};

    // leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(MUX,25864)@253
    assign leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_join_q or leftShiftStage0Idx1_uid25863_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_90_c_compmm_m2780_vt_join_q;
            1'b1 : leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25863_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(MUX,25869)@253
    assign leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s or leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25868_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = leftShiftStage0_uid25865_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25868_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x(MUX,25874)@253
    assign leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s or leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25873_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = leftShiftStage1_uid25870_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25873_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28(BITSELECT,9808)@253
    assign i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28_b = leftShiftStage2_uid25875_i_shl_i_i_i_i_i77_i_90_c_compmm_m0_shift_x_q[28:13];

    // redist386_i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28_b_1(DELAY,29514)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist386_i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_join(BITJOIN,9807)@254
    assign i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_join_q = {redist386_i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma(CHAINMULTADD,29116)@248 + 5
    // out q@254
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_66200_c_compmm_m76_out_dest_data_out_182_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_66199_c_compmm_m77_out_dest_data_out_181_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ch[0] <= redist684_sync_together4364_aunroll_x_in_c1_eni5_182_tpl_180_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ch[1] <= redist683_sync_together4364_aunroll_x_in_c1_eni5_181_tpl_180_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782(ADD,8936)@254
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_90_i_c_compmm_m2777_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_90_i_c_compmm_m2779_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_90_i_c_compmm_m2778_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_90_c_compmm_m2781_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_o[33:0];

    // rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x(MUX,21420)@254
    assign rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q or rightShiftStage0Idx1_uid21419_dupName_359_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q;
            1'b1 : rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21419_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x(MUX,21425)@254
    assign rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21424_dupName_359_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21421_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21424_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x(MUX,21430)@254
    assign rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21429_dupName_359_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21426_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21429_dupName_359_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2783_vt_select_20(BITSELECT,11633)@254
    assign i_unnamed_c_compmm_m2783_vt_select_20_b = rightShiftStage2_uid21431_dupName_359_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2783_vt_join(BITJOIN,11632)@254
    assign i_unnamed_c_compmm_m2783_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2783_vt_select_20_b};

    // i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x(BITSELECT,3565)@254
    assign i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x_b = i_unnamed_c_compmm_m2783_vt_join_q[15:0];

    // redist1024_i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x_b_1(DELAY,30152)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1024_i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21440_dupName_360_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21439)@254
    assign rightShiftStage1Idx1Rng8_uid21440_dupName_360_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21442_dupName_360_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21441)@254
    assign rightShiftStage1Idx1_uid21442_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21440_dupName_360_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21435_dupName_360_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21434)@254
    assign rightShiftStage0Idx1Rng4_uid21435_dupName_360_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q[33:4];

    // rightShiftStage0Idx1_uid21437_dupName_360_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21436)@254
    assign rightShiftStage0Idx1_uid21437_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21435_dupName_360_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x(MUX,21438)@254
    assign rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q or rightShiftStage0Idx1_uid21437_dupName_360_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_90_i_c_compmm_m2782_q;
            1'b1 : rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21437_dupName_360_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x(MUX,21443)@254
    assign rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21442_dupName_360_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21439_dupName_360_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21442_dupName_360_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2785_vt_select_21(BITSELECT,11636)@254
    assign i_unnamed_c_compmm_m2785_vt_select_21_b = rightShiftStage1_uid21444_dupName_360_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2785_vt_join(BITJOIN,11635)@254
    assign i_unnamed_c_compmm_m2785_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2785_vt_select_21_b};

    // i_unnamed_c_compmm_m2786_sel_x(BITSELECT,6132)@254
    assign i_unnamed_c_compmm_m2786_sel_x_b = i_unnamed_c_compmm_m2785_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2787_BitSelect_for_a(BITSELECT,28616)@254
    assign i_unnamed_c_compmm_m2787_BitSelect_for_a_b = i_unnamed_c_compmm_m2786_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2787_join(BITJOIN,28617)@254
    assign i_unnamed_c_compmm_m2787_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2787_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2787_vt_select_0(BITSELECT,11641)@254
    assign i_unnamed_c_compmm_m2787_vt_select_0_b = i_unnamed_c_compmm_m2787_join_q[0:0];

    // redist127_i_unnamed_c_compmm_m2787_vt_select_0_b_1(DELAY,29255)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist127_i_unnamed_c_compmm_m2787_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2787_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2787_vt_join(BITJOIN,11640)@255
    assign i_unnamed_c_compmm_m2787_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist127_i_unnamed_c_compmm_m2787_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_90_c_compmm_m2788(ADD,7148)@255
    assign i_add_i_i_i_i_i126_i_90_c_compmm_m2788_a = {1'b0, i_unnamed_c_compmm_m2787_vt_join_q};
    assign i_add_i_i_i_i_i126_i_90_c_compmm_m2788_b = {1'b0, redist1024_i_conv_i_i_i_i97_i_90_c_compmm_m2784_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_90_c_compmm_m2788_o = $unsigned(i_add_i_i_i_i_i126_i_90_c_compmm_m2788_a) + $unsigned(i_add_i_i_i_i_i126_i_90_c_compmm_m2788_b);
    assign i_add_i_i_i_i_i126_i_90_c_compmm_m2788_q = i_add_i_i_i_i_i126_i_90_c_compmm_m2788_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_90_c_compmm_m2788_sel_x(BITSELECT,2162)@255
    assign bgTrunc_i_add_i_i_i_i_i126_i_90_c_compmm_m2788_sel_x_b = i_add_i_i_i_i_i126_i_90_c_compmm_m2788_q[15:0];

    // i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_sel_x(BITSELECT,3695)@255
    assign i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_90_c_compmm_m2788_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_select_15(BITSELECT,7891)@255
    assign i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_select_15_b = i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_join(BITJOIN,7890)@255
    assign i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_select_15_b};

    // leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(MUX,25882)@255
    assign leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_join_q or leftShiftStage0Idx1_uid25881_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_91_c_compmm_m2808_vt_join_q;
            1'b1 : leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25881_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(MUX,25887)@255
    assign leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s or leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25886_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = leftShiftStage0_uid25883_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25886_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x(MUX,25892)@255
    assign leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s or leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25891_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = leftShiftStage1_uid25888_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25891_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28(BITSELECT,9811)@255
    assign i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28_b = leftShiftStage2_uid25893_i_shl_i_i_i_i_i77_i_91_c_compmm_m0_shift_x_q[28:13];

    // redist385_i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28_b_1(DELAY,29513)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist385_i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_join(BITJOIN,9810)@256
    assign i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_join_q = {redist385_i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma(CHAINMULTADD,29117)@250 + 5
    // out q@256
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_66202_c_compmm_m74_out_dest_data_out_184_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_66201_c_compmm_m75_out_dest_data_out_183_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ch[0] <= redist686_sync_together4364_aunroll_x_in_c1_eni5_184_tpl_182_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ch[1] <= redist685_sync_together4364_aunroll_x_in_c1_eni5_183_tpl_182_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810(ADD,8937)@256
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_91_i_c_compmm_m2805_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_91_i_c_compmm_m2807_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_91_i_c_compmm_m2806_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_91_c_compmm_m2809_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_o[33:0];

    // rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x(MUX,21482)@256
    assign rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q or rightShiftStage0Idx1_uid21481_dupName_363_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q;
            1'b1 : rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21481_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x(MUX,21487)@256
    assign rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21486_dupName_363_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21483_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21486_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x(MUX,21492)@256
    assign rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21491_dupName_363_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21488_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21491_dupName_363_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2811_vt_select_20(BITSELECT,11660)@256
    assign i_unnamed_c_compmm_m2811_vt_select_20_b = rightShiftStage2_uid21493_dupName_363_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2811_vt_join(BITJOIN,11659)@256
    assign i_unnamed_c_compmm_m2811_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2811_vt_select_20_b};

    // i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x(BITSELECT,3566)@256
    assign i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x_b = i_unnamed_c_compmm_m2811_vt_join_q[15:0];

    // redist1023_i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x_b_1(DELAY,30151)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1023_i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21502_dupName_364_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21501)@256
    assign rightShiftStage1Idx1Rng8_uid21502_dupName_364_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21504_dupName_364_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21503)@256
    assign rightShiftStage1Idx1_uid21504_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21502_dupName_364_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21497_dupName_364_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21496)@256
    assign rightShiftStage0Idx1Rng4_uid21497_dupName_364_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q[33:4];

    // rightShiftStage0Idx1_uid21499_dupName_364_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21498)@256
    assign rightShiftStage0Idx1_uid21499_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21497_dupName_364_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x(MUX,21500)@256
    assign rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q or rightShiftStage0Idx1_uid21499_dupName_364_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_91_i_c_compmm_m2810_q;
            1'b1 : rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21499_dupName_364_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x(MUX,21505)@256
    assign rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21504_dupName_364_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21501_dupName_364_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21504_dupName_364_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2813_vt_select_21(BITSELECT,11663)@256
    assign i_unnamed_c_compmm_m2813_vt_select_21_b = rightShiftStage1_uid21506_dupName_364_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2813_vt_join(BITJOIN,11662)@256
    assign i_unnamed_c_compmm_m2813_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2813_vt_select_21_b};

    // i_unnamed_c_compmm_m2814_sel_x(BITSELECT,6135)@256
    assign i_unnamed_c_compmm_m2814_sel_x_b = i_unnamed_c_compmm_m2813_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2815_BitSelect_for_a(BITSELECT,28622)@256
    assign i_unnamed_c_compmm_m2815_BitSelect_for_a_b = i_unnamed_c_compmm_m2814_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2815_join(BITJOIN,28623)@256
    assign i_unnamed_c_compmm_m2815_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2815_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2815_vt_select_0(BITSELECT,11668)@256
    assign i_unnamed_c_compmm_m2815_vt_select_0_b = i_unnamed_c_compmm_m2815_join_q[0:0];

    // redist125_i_unnamed_c_compmm_m2815_vt_select_0_b_1(DELAY,29253)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist125_i_unnamed_c_compmm_m2815_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2815_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2815_vt_join(BITJOIN,11667)@257
    assign i_unnamed_c_compmm_m2815_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist125_i_unnamed_c_compmm_m2815_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_91_c_compmm_m2816(ADD,7149)@257
    assign i_add_i_i_i_i_i126_i_91_c_compmm_m2816_a = {1'b0, i_unnamed_c_compmm_m2815_vt_join_q};
    assign i_add_i_i_i_i_i126_i_91_c_compmm_m2816_b = {1'b0, redist1023_i_conv_i_i_i_i97_i_91_c_compmm_m2812_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_91_c_compmm_m2816_o = $unsigned(i_add_i_i_i_i_i126_i_91_c_compmm_m2816_a) + $unsigned(i_add_i_i_i_i_i126_i_91_c_compmm_m2816_b);
    assign i_add_i_i_i_i_i126_i_91_c_compmm_m2816_q = i_add_i_i_i_i_i126_i_91_c_compmm_m2816_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_91_c_compmm_m2816_sel_x(BITSELECT,2163)@257
    assign bgTrunc_i_add_i_i_i_i_i126_i_91_c_compmm_m2816_sel_x_b = i_add_i_i_i_i_i126_i_91_c_compmm_m2816_q[15:0];

    // i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_sel_x(BITSELECT,3696)@257
    assign i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_91_c_compmm_m2816_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_select_15(BITSELECT,7895)@257
    assign i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_select_15_b = i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_join(BITJOIN,7894)@257
    assign i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_select_15_b};

    // leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(MUX,25900)@257
    assign leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_join_q or leftShiftStage0Idx1_uid25899_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_92_c_compmm_m2836_vt_join_q;
            1'b1 : leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25899_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(MUX,25905)@257
    assign leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s or leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25904_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = leftShiftStage0_uid25901_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25904_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x(MUX,25910)@257
    assign leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s or leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25909_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = leftShiftStage1_uid25906_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25909_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28(BITSELECT,9814)@257
    assign i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28_b = leftShiftStage2_uid25911_i_shl_i_i_i_i_i77_i_92_c_compmm_m0_shift_x_q[28:13];

    // redist384_i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28_b_1(DELAY,29512)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist384_i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_join(BITJOIN,9813)@258
    assign i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_join_q = {redist384_i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma(CHAINMULTADD,29118)@252 + 5
    // out q@258
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_66204_c_compmm_m72_out_dest_data_out_186_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_66203_c_compmm_m73_out_dest_data_out_185_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ch[0] <= redist688_sync_together4364_aunroll_x_in_c1_eni5_186_tpl_184_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ch[1] <= redist687_sync_together4364_aunroll_x_in_c1_eni5_185_tpl_184_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838(ADD,8938)@258
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_92_i_c_compmm_m2833_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_92_i_c_compmm_m2835_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_92_i_c_compmm_m2834_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_92_c_compmm_m2837_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_o[33:0];

    // rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x(MUX,21544)@258
    assign rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q or rightShiftStage0Idx1_uid21543_dupName_367_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q;
            1'b1 : rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21543_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x(MUX,21549)@258
    assign rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21548_dupName_367_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21545_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21548_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x(MUX,21554)@258
    assign rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21553_dupName_367_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21550_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21553_dupName_367_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2839_vt_select_20(BITSELECT,11685)@258
    assign i_unnamed_c_compmm_m2839_vt_select_20_b = rightShiftStage2_uid21555_dupName_367_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2839_vt_join(BITJOIN,11684)@258
    assign i_unnamed_c_compmm_m2839_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2839_vt_select_20_b};

    // i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x(BITSELECT,3567)@258
    assign i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x_b = i_unnamed_c_compmm_m2839_vt_join_q[15:0];

    // redist1022_i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x_b_1(DELAY,30150)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1022_i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21564_dupName_368_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21563)@258
    assign rightShiftStage1Idx1Rng8_uid21564_dupName_368_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21566_dupName_368_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21565)@258
    assign rightShiftStage1Idx1_uid21566_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21564_dupName_368_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21559_dupName_368_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21558)@258
    assign rightShiftStage0Idx1Rng4_uid21559_dupName_368_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q[33:4];

    // rightShiftStage0Idx1_uid21561_dupName_368_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21560)@258
    assign rightShiftStage0Idx1_uid21561_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21559_dupName_368_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x(MUX,21562)@258
    assign rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q or rightShiftStage0Idx1_uid21561_dupName_368_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_92_i_c_compmm_m2838_q;
            1'b1 : rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21561_dupName_368_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x(MUX,21567)@258
    assign rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21566_dupName_368_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21563_dupName_368_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21566_dupName_368_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2841_vt_select_21(BITSELECT,11688)@258
    assign i_unnamed_c_compmm_m2841_vt_select_21_b = rightShiftStage1_uid21568_dupName_368_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2841_vt_join(BITJOIN,11687)@258
    assign i_unnamed_c_compmm_m2841_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2841_vt_select_21_b};

    // i_unnamed_c_compmm_m2842_sel_x(BITSELECT,6137)@258
    assign i_unnamed_c_compmm_m2842_sel_x_b = i_unnamed_c_compmm_m2841_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2843_BitSelect_for_a(BITSELECT,28626)@258
    assign i_unnamed_c_compmm_m2843_BitSelect_for_a_b = i_unnamed_c_compmm_m2842_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2843_join(BITJOIN,28627)@258
    assign i_unnamed_c_compmm_m2843_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2843_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2843_vt_select_0(BITSELECT,11693)@258
    assign i_unnamed_c_compmm_m2843_vt_select_0_b = i_unnamed_c_compmm_m2843_join_q[0:0];

    // redist123_i_unnamed_c_compmm_m2843_vt_select_0_b_1(DELAY,29251)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist123_i_unnamed_c_compmm_m2843_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2843_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2843_vt_join(BITJOIN,11692)@259
    assign i_unnamed_c_compmm_m2843_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist123_i_unnamed_c_compmm_m2843_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_92_c_compmm_m2844(ADD,7150)@259
    assign i_add_i_i_i_i_i126_i_92_c_compmm_m2844_a = {1'b0, i_unnamed_c_compmm_m2843_vt_join_q};
    assign i_add_i_i_i_i_i126_i_92_c_compmm_m2844_b = {1'b0, redist1022_i_conv_i_i_i_i97_i_92_c_compmm_m2840_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_92_c_compmm_m2844_o = $unsigned(i_add_i_i_i_i_i126_i_92_c_compmm_m2844_a) + $unsigned(i_add_i_i_i_i_i126_i_92_c_compmm_m2844_b);
    assign i_add_i_i_i_i_i126_i_92_c_compmm_m2844_q = i_add_i_i_i_i_i126_i_92_c_compmm_m2844_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_92_c_compmm_m2844_sel_x(BITSELECT,2164)@259
    assign bgTrunc_i_add_i_i_i_i_i126_i_92_c_compmm_m2844_sel_x_b = i_add_i_i_i_i_i126_i_92_c_compmm_m2844_q[15:0];

    // i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_sel_x(BITSELECT,3697)@259
    assign i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_92_c_compmm_m2844_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_select_15(BITSELECT,7899)@259
    assign i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_select_15_b = i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_join(BITJOIN,7898)@259
    assign i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_select_15_b};

    // leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(MUX,25918)@259
    assign leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_join_q or leftShiftStage0Idx1_uid25917_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_93_c_compmm_m2864_vt_join_q;
            1'b1 : leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25917_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(MUX,25923)@259
    assign leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s or leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25922_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = leftShiftStage0_uid25919_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25922_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x(MUX,25928)@259
    assign leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s or leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25927_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = leftShiftStage1_uid25924_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25927_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28(BITSELECT,9817)@259
    assign i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28_b = leftShiftStage2_uid25929_i_shl_i_i_i_i_i77_i_93_c_compmm_m0_shift_x_q[28:13];

    // redist383_i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28_b_1(DELAY,29511)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist383_i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_join(BITJOIN,9816)@260
    assign i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_join_q = {redist383_i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma(CHAINMULTADD,29119)@254 + 5
    // out q@260
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_66206_c_compmm_m70_out_dest_data_out_188_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_66205_c_compmm_m71_out_dest_data_out_187_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ch[0] <= redist690_sync_together4364_aunroll_x_in_c1_eni5_188_tpl_186_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ch[1] <= redist689_sync_together4364_aunroll_x_in_c1_eni5_187_tpl_186_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866(ADD,8939)@260
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_93_i_c_compmm_m2861_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_93_i_c_compmm_m2863_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_93_i_c_compmm_m2862_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_93_c_compmm_m2865_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_o[33:0];

    // rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x(MUX,21606)@260
    assign rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q or rightShiftStage0Idx1_uid21605_dupName_371_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q;
            1'b1 : rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21605_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x(MUX,21611)@260
    assign rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21610_dupName_371_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21607_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21610_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x(MUX,21616)@260
    assign rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21615_dupName_371_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21612_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21615_dupName_371_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2867_vt_select_20(BITSELECT,11707)@260
    assign i_unnamed_c_compmm_m2867_vt_select_20_b = rightShiftStage2_uid21617_dupName_371_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2867_vt_join(BITJOIN,11706)@260
    assign i_unnamed_c_compmm_m2867_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2867_vt_select_20_b};

    // i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x(BITSELECT,3568)@260
    assign i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x_b = i_unnamed_c_compmm_m2867_vt_join_q[15:0];

    // redist1021_i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x_b_1(DELAY,30149)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1021_i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21626_dupName_372_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21625)@260
    assign rightShiftStage1Idx1Rng8_uid21626_dupName_372_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21628_dupName_372_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21627)@260
    assign rightShiftStage1Idx1_uid21628_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21626_dupName_372_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21621_dupName_372_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21620)@260
    assign rightShiftStage0Idx1Rng4_uid21621_dupName_372_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q[33:4];

    // rightShiftStage0Idx1_uid21623_dupName_372_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21622)@260
    assign rightShiftStage0Idx1_uid21623_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21621_dupName_372_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x(MUX,21624)@260
    assign rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q or rightShiftStage0Idx1_uid21623_dupName_372_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_93_i_c_compmm_m2866_q;
            1'b1 : rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21623_dupName_372_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x(MUX,21629)@260
    assign rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21628_dupName_372_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21625_dupName_372_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21628_dupName_372_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2869_vt_select_21(BITSELECT,11710)@260
    assign i_unnamed_c_compmm_m2869_vt_select_21_b = rightShiftStage1_uid21630_dupName_372_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2869_vt_join(BITJOIN,11709)@260
    assign i_unnamed_c_compmm_m2869_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2869_vt_select_21_b};

    // i_unnamed_c_compmm_m2870_sel_x(BITSELECT,6139)@260
    assign i_unnamed_c_compmm_m2870_sel_x_b = i_unnamed_c_compmm_m2869_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2871_BitSelect_for_a(BITSELECT,28630)@260
    assign i_unnamed_c_compmm_m2871_BitSelect_for_a_b = i_unnamed_c_compmm_m2870_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2871_join(BITJOIN,28631)@260
    assign i_unnamed_c_compmm_m2871_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2871_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2871_vt_select_0(BITSELECT,11715)@260
    assign i_unnamed_c_compmm_m2871_vt_select_0_b = i_unnamed_c_compmm_m2871_join_q[0:0];

    // redist121_i_unnamed_c_compmm_m2871_vt_select_0_b_1(DELAY,29249)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist121_i_unnamed_c_compmm_m2871_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2871_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2871_vt_join(BITJOIN,11714)@261
    assign i_unnamed_c_compmm_m2871_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist121_i_unnamed_c_compmm_m2871_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_93_c_compmm_m2872(ADD,7151)@261
    assign i_add_i_i_i_i_i126_i_93_c_compmm_m2872_a = {1'b0, i_unnamed_c_compmm_m2871_vt_join_q};
    assign i_add_i_i_i_i_i126_i_93_c_compmm_m2872_b = {1'b0, redist1021_i_conv_i_i_i_i97_i_93_c_compmm_m2868_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_93_c_compmm_m2872_o = $unsigned(i_add_i_i_i_i_i126_i_93_c_compmm_m2872_a) + $unsigned(i_add_i_i_i_i_i126_i_93_c_compmm_m2872_b);
    assign i_add_i_i_i_i_i126_i_93_c_compmm_m2872_q = i_add_i_i_i_i_i126_i_93_c_compmm_m2872_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_93_c_compmm_m2872_sel_x(BITSELECT,2165)@261
    assign bgTrunc_i_add_i_i_i_i_i126_i_93_c_compmm_m2872_sel_x_b = i_add_i_i_i_i_i126_i_93_c_compmm_m2872_q[15:0];

    // i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_sel_x(BITSELECT,3698)@261
    assign i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_93_c_compmm_m2872_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_select_15(BITSELECT,7903)@261
    assign i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_select_15_b = i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_join(BITJOIN,7902)@261
    assign i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_select_15_b};

    // leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(MUX,25936)@261
    assign leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_join_q or leftShiftStage0Idx1_uid25935_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_94_c_compmm_m2892_vt_join_q;
            1'b1 : leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25935_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(MUX,25941)@261
    assign leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s or leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25940_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = leftShiftStage0_uid25937_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25940_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x(MUX,25946)@261
    assign leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s or leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25945_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = leftShiftStage1_uid25942_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25945_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28(BITSELECT,9820)@261
    assign i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28_b = leftShiftStage2_uid25947_i_shl_i_i_i_i_i77_i_94_c_compmm_m0_shift_x_q[28:13];

    // redist382_i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28_b_1(DELAY,29510)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist382_i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_join(BITJOIN,9819)@262
    assign i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_join_q = {redist382_i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma(CHAINMULTADD,29120)@256 + 5
    // out q@262
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_66208_c_compmm_m68_out_dest_data_out_190_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_66207_c_compmm_m69_out_dest_data_out_189_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ch[0] <= redist692_sync_together4364_aunroll_x_in_c1_eni5_190_tpl_188_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ch[1] <= redist691_sync_together4364_aunroll_x_in_c1_eni5_189_tpl_188_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894(ADD,8940)@262
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_94_i_c_compmm_m2889_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_94_i_c_compmm_m2891_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_94_i_c_compmm_m2890_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_94_c_compmm_m2893_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_o[33:0];

    // rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x(MUX,21668)@262
    assign rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q or rightShiftStage0Idx1_uid21667_dupName_375_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q;
            1'b1 : rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21667_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x(MUX,21673)@262
    assign rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21672_dupName_375_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21669_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21672_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x(MUX,21678)@262
    assign rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21677_dupName_375_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21674_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21677_dupName_375_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2895_vt_select_20(BITSELECT,11729)@262
    assign i_unnamed_c_compmm_m2895_vt_select_20_b = rightShiftStage2_uid21679_dupName_375_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2895_vt_join(BITJOIN,11728)@262
    assign i_unnamed_c_compmm_m2895_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2895_vt_select_20_b};

    // i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x(BITSELECT,3569)@262
    assign i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x_b = i_unnamed_c_compmm_m2895_vt_join_q[15:0];

    // redist1020_i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x_b_1(DELAY,30148)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1020_i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21688_dupName_376_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21687)@262
    assign rightShiftStage1Idx1Rng8_uid21688_dupName_376_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21690_dupName_376_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21689)@262
    assign rightShiftStage1Idx1_uid21690_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21688_dupName_376_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21683_dupName_376_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21682)@262
    assign rightShiftStage0Idx1Rng4_uid21683_dupName_376_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q[33:4];

    // rightShiftStage0Idx1_uid21685_dupName_376_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21684)@262
    assign rightShiftStage0Idx1_uid21685_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21683_dupName_376_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x(MUX,21686)@262
    assign rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q or rightShiftStage0Idx1_uid21685_dupName_376_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_94_i_c_compmm_m2894_q;
            1'b1 : rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21685_dupName_376_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x(MUX,21691)@262
    assign rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21690_dupName_376_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21687_dupName_376_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21690_dupName_376_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2897_vt_select_21(BITSELECT,11732)@262
    assign i_unnamed_c_compmm_m2897_vt_select_21_b = rightShiftStage1_uid21692_dupName_376_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2897_vt_join(BITJOIN,11731)@262
    assign i_unnamed_c_compmm_m2897_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2897_vt_select_21_b};

    // i_unnamed_c_compmm_m2898_sel_x(BITSELECT,6141)@262
    assign i_unnamed_c_compmm_m2898_sel_x_b = i_unnamed_c_compmm_m2897_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2899_BitSelect_for_a(BITSELECT,28634)@262
    assign i_unnamed_c_compmm_m2899_BitSelect_for_a_b = i_unnamed_c_compmm_m2898_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2899_join(BITJOIN,28635)@262
    assign i_unnamed_c_compmm_m2899_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2899_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2899_vt_select_0(BITSELECT,11737)@262
    assign i_unnamed_c_compmm_m2899_vt_select_0_b = i_unnamed_c_compmm_m2899_join_q[0:0];

    // redist119_i_unnamed_c_compmm_m2899_vt_select_0_b_1(DELAY,29247)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist119_i_unnamed_c_compmm_m2899_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2899_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2899_vt_join(BITJOIN,11736)@263
    assign i_unnamed_c_compmm_m2899_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist119_i_unnamed_c_compmm_m2899_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_94_c_compmm_m2900(ADD,7152)@263
    assign i_add_i_i_i_i_i126_i_94_c_compmm_m2900_a = {1'b0, i_unnamed_c_compmm_m2899_vt_join_q};
    assign i_add_i_i_i_i_i126_i_94_c_compmm_m2900_b = {1'b0, redist1020_i_conv_i_i_i_i97_i_94_c_compmm_m2896_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_94_c_compmm_m2900_o = $unsigned(i_add_i_i_i_i_i126_i_94_c_compmm_m2900_a) + $unsigned(i_add_i_i_i_i_i126_i_94_c_compmm_m2900_b);
    assign i_add_i_i_i_i_i126_i_94_c_compmm_m2900_q = i_add_i_i_i_i_i126_i_94_c_compmm_m2900_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_94_c_compmm_m2900_sel_x(BITSELECT,2166)@263
    assign bgTrunc_i_add_i_i_i_i_i126_i_94_c_compmm_m2900_sel_x_b = i_add_i_i_i_i_i126_i_94_c_compmm_m2900_q[15:0];

    // i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_sel_x(BITSELECT,3699)@263
    assign i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_94_c_compmm_m2900_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_select_15(BITSELECT,7907)@263
    assign i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_select_15_b = i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_join(BITJOIN,7906)@263
    assign i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_select_15_b};

    // leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(MUX,25954)@263
    assign leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_join_q or leftShiftStage0Idx1_uid25953_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_95_c_compmm_m2920_vt_join_q;
            1'b1 : leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25953_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(MUX,25959)@263
    assign leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s or leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25958_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = leftShiftStage0_uid25955_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25958_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x(MUX,25964)@263
    assign leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s or leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25963_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = leftShiftStage1_uid25960_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25963_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28(BITSELECT,9823)@263
    assign i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28_b = leftShiftStage2_uid25965_i_shl_i_i_i_i_i77_i_95_c_compmm_m0_shift_x_q[28:13];

    // redist381_i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28_b_1(DELAY,29509)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist381_i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_join(BITJOIN,9822)@264
    assign i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_join_q = {redist381_i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma(CHAINMULTADD,29121)@258 + 5
    // out q@264
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_66210_c_compmm_m66_out_dest_data_out_192_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_66209_c_compmm_m67_out_dest_data_out_191_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ch[0] <= redist694_sync_together4364_aunroll_x_in_c1_eni5_192_tpl_190_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ch[1] <= redist693_sync_together4364_aunroll_x_in_c1_eni5_191_tpl_190_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922(ADD,8941)@264
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_95_i_c_compmm_m2917_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_95_i_c_compmm_m2919_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_95_i_c_compmm_m2918_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_95_c_compmm_m2921_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_o[33:0];

    // rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x(MUX,21730)@264
    assign rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q or rightShiftStage0Idx1_uid21729_dupName_379_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q;
            1'b1 : rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21729_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x(MUX,21735)@264
    assign rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21734_dupName_379_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21731_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21734_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x(MUX,21740)@264
    assign rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21739_dupName_379_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21736_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21739_dupName_379_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2923_vt_select_20(BITSELECT,11757)@264
    assign i_unnamed_c_compmm_m2923_vt_select_20_b = rightShiftStage2_uid21741_dupName_379_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2923_vt_join(BITJOIN,11756)@264
    assign i_unnamed_c_compmm_m2923_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2923_vt_select_20_b};

    // i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x(BITSELECT,3570)@264
    assign i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x_b = i_unnamed_c_compmm_m2923_vt_join_q[15:0];

    // redist1019_i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x_b_1(DELAY,30147)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1019_i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21750_dupName_380_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21749)@264
    assign rightShiftStage1Idx1Rng8_uid21750_dupName_380_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21752_dupName_380_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21751)@264
    assign rightShiftStage1Idx1_uid21752_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21750_dupName_380_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21745_dupName_380_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21744)@264
    assign rightShiftStage0Idx1Rng4_uid21745_dupName_380_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q[33:4];

    // rightShiftStage0Idx1_uid21747_dupName_380_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21746)@264
    assign rightShiftStage0Idx1_uid21747_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21745_dupName_380_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x(MUX,21748)@264
    assign rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q or rightShiftStage0Idx1_uid21747_dupName_380_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_95_i_c_compmm_m2922_q;
            1'b1 : rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21747_dupName_380_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x(MUX,21753)@264
    assign rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21752_dupName_380_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21749_dupName_380_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21752_dupName_380_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2925_vt_select_21(BITSELECT,11760)@264
    assign i_unnamed_c_compmm_m2925_vt_select_21_b = rightShiftStage1_uid21754_dupName_380_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2925_vt_join(BITJOIN,11759)@264
    assign i_unnamed_c_compmm_m2925_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2925_vt_select_21_b};

    // i_unnamed_c_compmm_m2926_sel_x(BITSELECT,6144)@264
    assign i_unnamed_c_compmm_m2926_sel_x_b = i_unnamed_c_compmm_m2925_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2927_BitSelect_for_a(BITSELECT,28638)@264
    assign i_unnamed_c_compmm_m2927_BitSelect_for_a_b = i_unnamed_c_compmm_m2926_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2927_join(BITJOIN,28639)@264
    assign i_unnamed_c_compmm_m2927_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2927_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2927_vt_select_0(BITSELECT,11765)@264
    assign i_unnamed_c_compmm_m2927_vt_select_0_b = i_unnamed_c_compmm_m2927_join_q[0:0];

    // redist117_i_unnamed_c_compmm_m2927_vt_select_0_b_1(DELAY,29245)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist117_i_unnamed_c_compmm_m2927_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2927_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2927_vt_join(BITJOIN,11764)@265
    assign i_unnamed_c_compmm_m2927_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist117_i_unnamed_c_compmm_m2927_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_95_c_compmm_m2928(ADD,7153)@265
    assign i_add_i_i_i_i_i126_i_95_c_compmm_m2928_a = {1'b0, i_unnamed_c_compmm_m2927_vt_join_q};
    assign i_add_i_i_i_i_i126_i_95_c_compmm_m2928_b = {1'b0, redist1019_i_conv_i_i_i_i97_i_95_c_compmm_m2924_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_95_c_compmm_m2928_o = $unsigned(i_add_i_i_i_i_i126_i_95_c_compmm_m2928_a) + $unsigned(i_add_i_i_i_i_i126_i_95_c_compmm_m2928_b);
    assign i_add_i_i_i_i_i126_i_95_c_compmm_m2928_q = i_add_i_i_i_i_i126_i_95_c_compmm_m2928_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_95_c_compmm_m2928_sel_x(BITSELECT,2167)@265
    assign bgTrunc_i_add_i_i_i_i_i126_i_95_c_compmm_m2928_sel_x_b = i_add_i_i_i_i_i126_i_95_c_compmm_m2928_q[15:0];

    // i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_sel_x(BITSELECT,3700)@265
    assign i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_95_c_compmm_m2928_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_select_15(BITSELECT,7911)@265
    assign i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_select_15_b = i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_join(BITJOIN,7910)@265
    assign i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_select_15_b};

    // leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(MUX,25972)@265
    assign leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_join_q or leftShiftStage0Idx1_uid25971_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_96_c_compmm_m2949_vt_join_q;
            1'b1 : leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25971_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(MUX,25977)@265
    assign leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s or leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25976_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = leftShiftStage0_uid25973_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25976_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x(MUX,25982)@265
    assign leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s or leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25981_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = leftShiftStage1_uid25978_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25981_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28(BITSELECT,9826)@265
    assign i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28_b = leftShiftStage2_uid25983_i_shl_i_i_i_i_i77_i_96_c_compmm_m0_shift_x_q[28:13];

    // redist380_i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28_b_1(DELAY,29508)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist380_i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_join(BITJOIN,9825)@266
    assign i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_join_q = {redist380_i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma(CHAINMULTADD,29122)@260 + 5
    // out q@266
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_1_c_compmm_m_fpgaunique_67212_c_compmm_m64_out_dest_data_out_194_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_0_c_compmm_m_fpgaunique_67211_c_compmm_m65_out_dest_data_out_193_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ch[0] <= redist696_sync_together4364_aunroll_x_in_c1_eni5_194_tpl_192_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ch[1] <= redist695_sync_together4364_aunroll_x_in_c1_eni5_193_tpl_192_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951(ADD,8942)@266
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_96_i_c_compmm_m2946_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_96_i_c_compmm_m2948_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_96_i_c_compmm_m2947_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_96_c_compmm_m2950_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_o[33:0];

    // rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x(MUX,21792)@266
    assign rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q or rightShiftStage0Idx1_uid21791_dupName_383_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q;
            1'b1 : rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21791_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x(MUX,21797)@266
    assign rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21796_dupName_383_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21793_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21796_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x(MUX,21802)@266
    assign rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21801_dupName_383_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21798_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21801_dupName_383_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2952_vt_select_20(BITSELECT,11784)@266
    assign i_unnamed_c_compmm_m2952_vt_select_20_b = rightShiftStage2_uid21803_dupName_383_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2952_vt_join(BITJOIN,11783)@266
    assign i_unnamed_c_compmm_m2952_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2952_vt_select_20_b};

    // i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x(BITSELECT,3571)@266
    assign i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x_b = i_unnamed_c_compmm_m2952_vt_join_q[15:0];

    // redist1018_i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x_b_1(DELAY,30146)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1018_i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21812_dupName_384_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21811)@266
    assign rightShiftStage1Idx1Rng8_uid21812_dupName_384_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21814_dupName_384_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21813)@266
    assign rightShiftStage1Idx1_uid21814_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21812_dupName_384_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21807_dupName_384_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21806)@266
    assign rightShiftStage0Idx1Rng4_uid21807_dupName_384_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q[33:4];

    // rightShiftStage0Idx1_uid21809_dupName_384_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21808)@266
    assign rightShiftStage0Idx1_uid21809_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21807_dupName_384_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x(MUX,21810)@266
    assign rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q or rightShiftStage0Idx1_uid21809_dupName_384_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_96_i_c_compmm_m2951_q;
            1'b1 : rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21809_dupName_384_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x(MUX,21815)@266
    assign rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21814_dupName_384_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21811_dupName_384_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21814_dupName_384_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2954_vt_select_21(BITSELECT,11787)@266
    assign i_unnamed_c_compmm_m2954_vt_select_21_b = rightShiftStage1_uid21816_dupName_384_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2954_vt_join(BITJOIN,11786)@266
    assign i_unnamed_c_compmm_m2954_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2954_vt_select_21_b};

    // i_unnamed_c_compmm_m2955_sel_x(BITSELECT,6146)@266
    assign i_unnamed_c_compmm_m2955_sel_x_b = i_unnamed_c_compmm_m2954_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2956_BitSelect_for_a(BITSELECT,28644)@266
    assign i_unnamed_c_compmm_m2956_BitSelect_for_a_b = i_unnamed_c_compmm_m2955_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2956_join(BITJOIN,28645)@266
    assign i_unnamed_c_compmm_m2956_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2956_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2956_vt_select_0(BITSELECT,11792)@266
    assign i_unnamed_c_compmm_m2956_vt_select_0_b = i_unnamed_c_compmm_m2956_join_q[0:0];

    // redist114_i_unnamed_c_compmm_m2956_vt_select_0_b_1(DELAY,29242)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist114_i_unnamed_c_compmm_m2956_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2956_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2956_vt_join(BITJOIN,11791)@267
    assign i_unnamed_c_compmm_m2956_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist114_i_unnamed_c_compmm_m2956_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_96_c_compmm_m2957(ADD,7154)@267
    assign i_add_i_i_i_i_i126_i_96_c_compmm_m2957_a = {1'b0, i_unnamed_c_compmm_m2956_vt_join_q};
    assign i_add_i_i_i_i_i126_i_96_c_compmm_m2957_b = {1'b0, redist1018_i_conv_i_i_i_i97_i_96_c_compmm_m2953_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_96_c_compmm_m2957_o = $unsigned(i_add_i_i_i_i_i126_i_96_c_compmm_m2957_a) + $unsigned(i_add_i_i_i_i_i126_i_96_c_compmm_m2957_b);
    assign i_add_i_i_i_i_i126_i_96_c_compmm_m2957_q = i_add_i_i_i_i_i126_i_96_c_compmm_m2957_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_96_c_compmm_m2957_sel_x(BITSELECT,2168)@267
    assign bgTrunc_i_add_i_i_i_i_i126_i_96_c_compmm_m2957_sel_x_b = i_add_i_i_i_i_i126_i_96_c_compmm_m2957_q[15:0];

    // i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_sel_x(BITSELECT,3701)@267
    assign i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_96_c_compmm_m2957_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_select_15(BITSELECT,7915)@267
    assign i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_select_15_b = i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_join(BITJOIN,7914)@267
    assign i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_select_15_b};

    // leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(MUX,25990)@267
    assign leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_join_q or leftShiftStage0Idx1_uid25989_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_97_c_compmm_m2977_vt_join_q;
            1'b1 : leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid25989_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(MUX,25995)@267
    assign leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s or leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid25994_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = leftShiftStage0_uid25991_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid25994_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x(MUX,26000)@267
    assign leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s or leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid25999_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = leftShiftStage1_uid25996_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid25999_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28(BITSELECT,9829)@267
    assign i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28_b = leftShiftStage2_uid26001_i_shl_i_i_i_i_i77_i_97_c_compmm_m0_shift_x_q[28:13];

    // redist379_i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28_b_1(DELAY,29507)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist379_i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_join(BITJOIN,9828)@268
    assign i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_join_q = {redist379_i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma(CHAINMULTADD,29123)@262 + 5
    // out q@268
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_3_c_compmm_m_fpgaunique_67214_c_compmm_m62_out_dest_data_out_196_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_2_c_compmm_m_fpgaunique_67213_c_compmm_m63_out_dest_data_out_195_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ch[0] <= redist698_sync_together4364_aunroll_x_in_c1_eni5_196_tpl_194_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ch[1] <= redist697_sync_together4364_aunroll_x_in_c1_eni5_195_tpl_194_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979(ADD,8943)@268
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_97_i_c_compmm_m2974_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_97_i_c_compmm_m2976_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_97_i_c_compmm_m2975_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_97_c_compmm_m2978_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_o[33:0];

    // rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x(MUX,21854)@268
    assign rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q or rightShiftStage0Idx1_uid21853_dupName_387_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q;
            1'b1 : rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21853_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x(MUX,21859)@268
    assign rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21858_dupName_387_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21855_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21858_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x(MUX,21864)@268
    assign rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21863_dupName_387_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21860_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21863_dupName_387_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2980_vt_select_20(BITSELECT,11806)@268
    assign i_unnamed_c_compmm_m2980_vt_select_20_b = rightShiftStage2_uid21865_dupName_387_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m2980_vt_join(BITJOIN,11805)@268
    assign i_unnamed_c_compmm_m2980_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m2980_vt_select_20_b};

    // i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x(BITSELECT,3572)@268
    assign i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x_b = i_unnamed_c_compmm_m2980_vt_join_q[15:0];

    // redist1017_i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x_b_1(DELAY,30145)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1017_i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21874_dupName_388_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21873)@268
    assign rightShiftStage1Idx1Rng8_uid21874_dupName_388_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21876_dupName_388_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21875)@268
    assign rightShiftStage1Idx1_uid21876_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21874_dupName_388_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21869_dupName_388_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21868)@268
    assign rightShiftStage0Idx1Rng4_uid21869_dupName_388_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q[33:4];

    // rightShiftStage0Idx1_uid21871_dupName_388_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21870)@268
    assign rightShiftStage0Idx1_uid21871_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21869_dupName_388_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x(MUX,21872)@268
    assign rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q or rightShiftStage0Idx1_uid21871_dupName_388_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_97_i_c_compmm_m2979_q;
            1'b1 : rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21871_dupName_388_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x(MUX,21877)@268
    assign rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21876_dupName_388_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21873_dupName_388_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21876_dupName_388_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m2982_vt_select_21(BITSELECT,11809)@268
    assign i_unnamed_c_compmm_m2982_vt_select_21_b = rightShiftStage1_uid21878_dupName_388_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m2982_vt_join(BITJOIN,11808)@268
    assign i_unnamed_c_compmm_m2982_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m2982_vt_select_21_b};

    // i_unnamed_c_compmm_m2983_sel_x(BITSELECT,6148)@268
    assign i_unnamed_c_compmm_m2983_sel_x_b = i_unnamed_c_compmm_m2982_vt_join_q[15:0];

    // i_unnamed_c_compmm_m2984_BitSelect_for_a(BITSELECT,28648)@268
    assign i_unnamed_c_compmm_m2984_BitSelect_for_a_b = i_unnamed_c_compmm_m2983_sel_x_b[0:0];

    // i_unnamed_c_compmm_m2984_join(BITJOIN,28649)@268
    assign i_unnamed_c_compmm_m2984_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m2984_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m2984_vt_select_0(BITSELECT,11814)@268
    assign i_unnamed_c_compmm_m2984_vt_select_0_b = i_unnamed_c_compmm_m2984_join_q[0:0];

    // redist112_i_unnamed_c_compmm_m2984_vt_select_0_b_1(DELAY,29240)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist112_i_unnamed_c_compmm_m2984_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m2984_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m2984_vt_join(BITJOIN,11813)@269
    assign i_unnamed_c_compmm_m2984_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist112_i_unnamed_c_compmm_m2984_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_97_c_compmm_m2985(ADD,7155)@269
    assign i_add_i_i_i_i_i126_i_97_c_compmm_m2985_a = {1'b0, i_unnamed_c_compmm_m2984_vt_join_q};
    assign i_add_i_i_i_i_i126_i_97_c_compmm_m2985_b = {1'b0, redist1017_i_conv_i_i_i_i97_i_97_c_compmm_m2981_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_97_c_compmm_m2985_o = $unsigned(i_add_i_i_i_i_i126_i_97_c_compmm_m2985_a) + $unsigned(i_add_i_i_i_i_i126_i_97_c_compmm_m2985_b);
    assign i_add_i_i_i_i_i126_i_97_c_compmm_m2985_q = i_add_i_i_i_i_i126_i_97_c_compmm_m2985_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_97_c_compmm_m2985_sel_x(BITSELECT,2169)@269
    assign bgTrunc_i_add_i_i_i_i_i126_i_97_c_compmm_m2985_sel_x_b = i_add_i_i_i_i_i126_i_97_c_compmm_m2985_q[15:0];

    // i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_sel_x(BITSELECT,3702)@269
    assign i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_97_c_compmm_m2985_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_select_15(BITSELECT,7919)@269
    assign i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_select_15_b = i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_join(BITJOIN,7918)@269
    assign i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_select_15_b};

    // leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(MUX,26008)@269
    assign leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_join_q or leftShiftStage0Idx1_uid26007_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_98_c_compmm_m3005_vt_join_q;
            1'b1 : leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26007_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(MUX,26013)@269
    assign leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s or leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26012_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = leftShiftStage0_uid26009_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26012_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x(MUX,26018)@269
    assign leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s or leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26017_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = leftShiftStage1_uid26014_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26017_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28(BITSELECT,9832)@269
    assign i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28_b = leftShiftStage2_uid26019_i_shl_i_i_i_i_i77_i_98_c_compmm_m0_shift_x_q[28:13];

    // redist378_i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28_b_1(DELAY,29506)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist378_i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_join(BITJOIN,9831)@270
    assign i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_join_q = {redist378_i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma(CHAINMULTADD,29124)@264 + 5
    // out q@270
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_5_c_compmm_m_fpgaunique_67216_c_compmm_m60_out_dest_data_out_198_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_4_c_compmm_m_fpgaunique_67215_c_compmm_m61_out_dest_data_out_197_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ch[0] <= redist700_sync_together4364_aunroll_x_in_c1_eni5_198_tpl_196_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ch[1] <= redist699_sync_together4364_aunroll_x_in_c1_eni5_197_tpl_196_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007(ADD,8944)@270
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_98_i_c_compmm_m3002_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_98_i_c_compmm_m3004_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_98_i_c_compmm_m3003_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_98_c_compmm_m3006_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_o[33:0];

    // rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x(MUX,21916)@270
    assign rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q or rightShiftStage0Idx1_uid21915_dupName_391_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q;
            1'b1 : rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21915_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x(MUX,21921)@270
    assign rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21920_dupName_391_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21917_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21920_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x(MUX,21926)@270
    assign rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21925_dupName_391_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21922_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21925_dupName_391_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3008_vt_select_20(BITSELECT,11828)@270
    assign i_unnamed_c_compmm_m3008_vt_select_20_b = rightShiftStage2_uid21927_dupName_391_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3008_vt_join(BITJOIN,11827)@270
    assign i_unnamed_c_compmm_m3008_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3008_vt_select_20_b};

    // i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x(BITSELECT,3573)@270
    assign i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x_b = i_unnamed_c_compmm_m3008_vt_join_q[15:0];

    // redist1016_i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x_b_1(DELAY,30144)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1016_i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21936_dupName_392_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21935)@270
    assign rightShiftStage1Idx1Rng8_uid21936_dupName_392_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid21938_dupName_392_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21937)@270
    assign rightShiftStage1Idx1_uid21938_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21936_dupName_392_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21931_dupName_392_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21930)@270
    assign rightShiftStage0Idx1Rng4_uid21931_dupName_392_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q[33:4];

    // rightShiftStage0Idx1_uid21933_dupName_392_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21932)@270
    assign rightShiftStage0Idx1_uid21933_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21931_dupName_392_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x(MUX,21934)@270
    assign rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q or rightShiftStage0Idx1_uid21933_dupName_392_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_98_i_c_compmm_m3007_q;
            1'b1 : rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21933_dupName_392_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x(MUX,21939)@270
    assign rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21938_dupName_392_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21935_dupName_392_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21938_dupName_392_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3010_vt_select_21(BITSELECT,11831)@270
    assign i_unnamed_c_compmm_m3010_vt_select_21_b = rightShiftStage1_uid21940_dupName_392_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3010_vt_join(BITJOIN,11830)@270
    assign i_unnamed_c_compmm_m3010_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3010_vt_select_21_b};

    // i_unnamed_c_compmm_m3011_sel_x(BITSELECT,6150)@270
    assign i_unnamed_c_compmm_m3011_sel_x_b = i_unnamed_c_compmm_m3010_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3012_BitSelect_for_a(BITSELECT,28652)@270
    assign i_unnamed_c_compmm_m3012_BitSelect_for_a_b = i_unnamed_c_compmm_m3011_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3012_join(BITJOIN,28653)@270
    assign i_unnamed_c_compmm_m3012_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3012_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3012_vt_select_0(BITSELECT,11836)@270
    assign i_unnamed_c_compmm_m3012_vt_select_0_b = i_unnamed_c_compmm_m3012_join_q[0:0];

    // redist110_i_unnamed_c_compmm_m3012_vt_select_0_b_1(DELAY,29238)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist110_i_unnamed_c_compmm_m3012_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3012_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3012_vt_join(BITJOIN,11835)@271
    assign i_unnamed_c_compmm_m3012_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist110_i_unnamed_c_compmm_m3012_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_98_c_compmm_m3013(ADD,7156)@271
    assign i_add_i_i_i_i_i126_i_98_c_compmm_m3013_a = {1'b0, i_unnamed_c_compmm_m3012_vt_join_q};
    assign i_add_i_i_i_i_i126_i_98_c_compmm_m3013_b = {1'b0, redist1016_i_conv_i_i_i_i97_i_98_c_compmm_m3009_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_98_c_compmm_m3013_o = $unsigned(i_add_i_i_i_i_i126_i_98_c_compmm_m3013_a) + $unsigned(i_add_i_i_i_i_i126_i_98_c_compmm_m3013_b);
    assign i_add_i_i_i_i_i126_i_98_c_compmm_m3013_q = i_add_i_i_i_i_i126_i_98_c_compmm_m3013_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_98_c_compmm_m3013_sel_x(BITSELECT,2170)@271
    assign bgTrunc_i_add_i_i_i_i_i126_i_98_c_compmm_m3013_sel_x_b = i_add_i_i_i_i_i126_i_98_c_compmm_m3013_q[15:0];

    // i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_sel_x(BITSELECT,3703)@271
    assign i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_98_c_compmm_m3013_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_select_15(BITSELECT,7923)@271
    assign i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_select_15_b = i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_join(BITJOIN,7922)@271
    assign i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_select_15_b};

    // leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(MUX,26026)@271
    assign leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_join_q or leftShiftStage0Idx1_uid26025_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_99_c_compmm_m3033_vt_join_q;
            1'b1 : leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid26025_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(MUX,26031)@271
    assign leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s or leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid26030_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = leftShiftStage0_uid26027_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid26030_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x(MUX,26036)@271
    assign leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s or leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid26035_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = leftShiftStage1_uid26032_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid26035_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28(BITSELECT,9835)@271
    assign i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28_b = leftShiftStage2_uid26037_i_shl_i_i_i_i_i77_i_99_c_compmm_m0_shift_x_q[28:13];

    // redist377_i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28_b_1(DELAY,29505)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist377_i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_join(BITJOIN,9834)@272
    assign i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_join_q = {redist377_i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma(CHAINMULTADD,29125)@266 + 5
    // out q@272
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_7_c_compmm_m_fpgaunique_67218_c_compmm_m58_out_dest_data_out_200_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_6_c_compmm_m_fpgaunique_67217_c_compmm_m59_out_dest_data_out_199_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ch[0] <= redist702_sync_together4364_aunroll_x_in_c1_eni5_200_tpl_198_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ch[1] <= redist701_sync_together4364_aunroll_x_in_c1_eni5_199_tpl_198_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035(ADD,8945)@272
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_99_i_c_compmm_m3030_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_99_i_c_compmm_m3032_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_99_i_c_compmm_m3031_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_99_c_compmm_m3034_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_o[33:0];

    // rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x(MUX,21978)@272
    assign rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q or rightShiftStage0Idx1_uid21977_dupName_395_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q;
            1'b1 : rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21977_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x(MUX,21983)@272
    assign rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid21982_dupName_395_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21979_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid21982_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x(MUX,21988)@272
    assign rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid21987_dupName_395_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid21984_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid21987_dupName_395_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3036_vt_select_20(BITSELECT,11850)@272
    assign i_unnamed_c_compmm_m3036_vt_select_20_b = rightShiftStage2_uid21989_dupName_395_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3036_vt_join(BITJOIN,11849)@272
    assign i_unnamed_c_compmm_m3036_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3036_vt_select_20_b};

    // i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x(BITSELECT,3574)@272
    assign i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x_b = i_unnamed_c_compmm_m3036_vt_join_q[15:0];

    // redist1015_i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x_b_1(DELAY,30143)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1015_i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid21998_dupName_396_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21997)@272
    assign rightShiftStage1Idx1Rng8_uid21998_dupName_396_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22000_dupName_396_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21999)@272
    assign rightShiftStage1Idx1_uid22000_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid21998_dupName_396_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid21993_dupName_396_i_unnamed_c_compmm_m0_shift_x(BITSELECT,21992)@272
    assign rightShiftStage0Idx1Rng4_uid21993_dupName_396_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q[33:4];

    // rightShiftStage0Idx1_uid21995_dupName_396_i_unnamed_c_compmm_m0_shift_x(BITJOIN,21994)@272
    assign rightShiftStage0Idx1_uid21995_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid21993_dupName_396_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x(MUX,21996)@272
    assign rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q or rightShiftStage0Idx1_uid21995_dupName_396_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_99_i_c_compmm_m3035_q;
            1'b1 : rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid21995_dupName_396_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x(MUX,22001)@272
    assign rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22000_dupName_396_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid21997_dupName_396_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22000_dupName_396_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3038_vt_select_21(BITSELECT,11853)@272
    assign i_unnamed_c_compmm_m3038_vt_select_21_b = rightShiftStage1_uid22002_dupName_396_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3038_vt_join(BITJOIN,11852)@272
    assign i_unnamed_c_compmm_m3038_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3038_vt_select_21_b};

    // i_unnamed_c_compmm_m3039_sel_x(BITSELECT,6152)@272
    assign i_unnamed_c_compmm_m3039_sel_x_b = i_unnamed_c_compmm_m3038_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3040_BitSelect_for_a(BITSELECT,28656)@272
    assign i_unnamed_c_compmm_m3040_BitSelect_for_a_b = i_unnamed_c_compmm_m3039_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3040_join(BITJOIN,28657)@272
    assign i_unnamed_c_compmm_m3040_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3040_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3040_vt_select_0(BITSELECT,11858)@272
    assign i_unnamed_c_compmm_m3040_vt_select_0_b = i_unnamed_c_compmm_m3040_join_q[0:0];

    // redist108_i_unnamed_c_compmm_m3040_vt_select_0_b_1(DELAY,29236)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist108_i_unnamed_c_compmm_m3040_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3040_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3040_vt_join(BITJOIN,11857)@273
    assign i_unnamed_c_compmm_m3040_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist108_i_unnamed_c_compmm_m3040_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_99_c_compmm_m3041(ADD,7157)@273
    assign i_add_i_i_i_i_i126_i_99_c_compmm_m3041_a = {1'b0, i_unnamed_c_compmm_m3040_vt_join_q};
    assign i_add_i_i_i_i_i126_i_99_c_compmm_m3041_b = {1'b0, redist1015_i_conv_i_i_i_i97_i_99_c_compmm_m3037_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_99_c_compmm_m3041_o = $unsigned(i_add_i_i_i_i_i126_i_99_c_compmm_m3041_a) + $unsigned(i_add_i_i_i_i_i126_i_99_c_compmm_m3041_b);
    assign i_add_i_i_i_i_i126_i_99_c_compmm_m3041_q = i_add_i_i_i_i_i126_i_99_c_compmm_m3041_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_99_c_compmm_m3041_sel_x(BITSELECT,2171)@273
    assign bgTrunc_i_add_i_i_i_i_i126_i_99_c_compmm_m3041_sel_x_b = i_add_i_i_i_i_i126_i_99_c_compmm_m3041_q[15:0];

    // i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_sel_x(BITSELECT,3578)@273
    assign i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_99_c_compmm_m3041_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_select_15(BITSELECT,7423)@273
    assign i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_select_15_b = i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_join(BITJOIN,7422)@273
    assign i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_select_15_b};

    // leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(MUX,23776)@273
    assign leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_join_q or leftShiftStage0Idx1_uid23775_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_join_q;
            1'b1 : leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23775_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(MUX,23781)@273
    assign leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s or leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23780_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = leftShiftStage0_uid23777_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23780_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x(MUX,23786)@273
    assign leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s or leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23785_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = leftShiftStage1_uid23782_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23785_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28(BITSELECT,9460)@273
    assign i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28_b = leftShiftStage2_uid23787_i_shl_i_i_i_i_i77_i_100_c_compmm_m0_shift_x_q[28:13];

    // redist502_i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28_b_1(DELAY,29630)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist502_i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_join(BITJOIN,9459)@274
    assign i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_join_q = {redist502_i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma(CHAINMULTADD,29000)@268 + 5
    // out q@274
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_9_c_compmm_m_fpgaunique_67220_c_compmm_m56_out_dest_data_out_202_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_8_c_compmm_m_fpgaunique_67219_c_compmm_m57_out_dest_data_out_201_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ch[0] <= redist704_sync_together4364_aunroll_x_in_c1_eni5_202_tpl_200_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ch[1] <= redist703_sync_together4364_aunroll_x_in_c1_eni5_201_tpl_200_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063(ADD,8820)@274
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_100_i_c_compmm_m3058_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_100_i_c_compmm_m3060_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_100_i_c_compmm_m3059_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_100_c_compmm_m3062_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_o[33:0];

    // rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x(MUX,22040)@274
    assign rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q or rightShiftStage0Idx1_uid22039_dupName_399_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q;
            1'b1 : rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22039_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x(MUX,22045)@274
    assign rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22044_dupName_399_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22041_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22044_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x(MUX,22050)@274
    assign rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22049_dupName_399_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22046_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22049_dupName_399_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3064_vt_select_20(BITSELECT,11875)@274
    assign i_unnamed_c_compmm_m3064_vt_select_20_b = rightShiftStage2_uid22051_dupName_399_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3064_vt_join(BITJOIN,11874)@274
    assign i_unnamed_c_compmm_m3064_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3064_vt_select_20_b};

    // i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x(BITSELECT,3449)@274
    assign i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x_b = i_unnamed_c_compmm_m3064_vt_join_q[15:0];

    // redist1140_i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x_b_1(DELAY,30268)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1140_i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22060_dupName_400_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22059)@274
    assign rightShiftStage1Idx1Rng8_uid22060_dupName_400_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22062_dupName_400_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22061)@274
    assign rightShiftStage1Idx1_uid22062_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22060_dupName_400_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22055_dupName_400_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22054)@274
    assign rightShiftStage0Idx1Rng4_uid22055_dupName_400_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q[33:4];

    // rightShiftStage0Idx1_uid22057_dupName_400_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22056)@274
    assign rightShiftStage0Idx1_uid22057_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22055_dupName_400_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x(MUX,22058)@274
    assign rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q or rightShiftStage0Idx1_uid22057_dupName_400_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_100_i_c_compmm_m3063_q;
            1'b1 : rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22057_dupName_400_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x(MUX,22063)@274
    assign rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22062_dupName_400_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22059_dupName_400_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22062_dupName_400_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3066_vt_select_21(BITSELECT,11878)@274
    assign i_unnamed_c_compmm_m3066_vt_select_21_b = rightShiftStage1_uid22064_dupName_400_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3066_vt_join(BITJOIN,11877)@274
    assign i_unnamed_c_compmm_m3066_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3066_vt_select_21_b};

    // i_unnamed_c_compmm_m3067_sel_x(BITSELECT,6154)@274
    assign i_unnamed_c_compmm_m3067_sel_x_b = i_unnamed_c_compmm_m3066_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3068_BitSelect_for_a(BITSELECT,28660)@274
    assign i_unnamed_c_compmm_m3068_BitSelect_for_a_b = i_unnamed_c_compmm_m3067_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3068_join(BITJOIN,28661)@274
    assign i_unnamed_c_compmm_m3068_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3068_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3068_vt_select_0(BITSELECT,11883)@274
    assign i_unnamed_c_compmm_m3068_vt_select_0_b = i_unnamed_c_compmm_m3068_join_q[0:0];

    // redist106_i_unnamed_c_compmm_m3068_vt_select_0_b_1(DELAY,29234)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist106_i_unnamed_c_compmm_m3068_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3068_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3068_vt_join(BITJOIN,11882)@275
    assign i_unnamed_c_compmm_m3068_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist106_i_unnamed_c_compmm_m3068_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_100_c_compmm_m3069(ADD,7032)@275
    assign i_add_i_i_i_i_i126_i_100_c_compmm_m3069_a = {1'b0, i_unnamed_c_compmm_m3068_vt_join_q};
    assign i_add_i_i_i_i_i126_i_100_c_compmm_m3069_b = {1'b0, redist1140_i_conv_i_i_i_i97_i_100_c_compmm_m3065_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_100_c_compmm_m3069_o = $unsigned(i_add_i_i_i_i_i126_i_100_c_compmm_m3069_a) + $unsigned(i_add_i_i_i_i_i126_i_100_c_compmm_m3069_b);
    assign i_add_i_i_i_i_i126_i_100_c_compmm_m3069_q = i_add_i_i_i_i_i126_i_100_c_compmm_m3069_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_100_c_compmm_m3069_sel_x(BITSELECT,2046)@275
    assign bgTrunc_i_add_i_i_i_i_i126_i_100_c_compmm_m3069_sel_x_b = i_add_i_i_i_i_i126_i_100_c_compmm_m3069_q[15:0];

    // i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_sel_x(BITSELECT,3579)@275
    assign i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_100_c_compmm_m3069_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_select_15(BITSELECT,7427)@275
    assign i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_select_15_b = i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_join(BITJOIN,7426)@275
    assign i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_select_15_b};

    // leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(MUX,23794)@275
    assign leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_join_q or leftShiftStage0Idx1_uid23793_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_101_c_compmm_m3089_vt_join_q;
            1'b1 : leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23793_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(MUX,23799)@275
    assign leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s or leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23798_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = leftShiftStage0_uid23795_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23798_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x(MUX,23804)@275
    assign leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s or leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23803_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = leftShiftStage1_uid23800_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23803_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28(BITSELECT,9463)@275
    assign i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28_b = leftShiftStage2_uid23805_i_shl_i_i_i_i_i77_i_101_c_compmm_m0_shift_x_q[28:13];

    // redist501_i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28_b_1(DELAY,29629)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist501_i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_join(BITJOIN,9462)@276
    assign i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_join_q = {redist501_i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma(CHAINMULTADD,29001)@270 + 5
    // out q@276
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_11_c_compmm_m_fpgaunique_67222_c_compmm_m54_out_dest_data_out_204_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_10_c_compmm_m_fpgaunique_67221_c_compmm_m55_out_dest_data_out_203_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ch[0] <= redist706_sync_together4364_aunroll_x_in_c1_eni5_204_tpl_202_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ch[1] <= redist705_sync_together4364_aunroll_x_in_c1_eni5_203_tpl_202_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091(ADD,8821)@276
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_101_i_c_compmm_m3086_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_101_i_c_compmm_m3088_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_101_i_c_compmm_m3087_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_101_c_compmm_m3090_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_o[33:0];

    // rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x(MUX,22102)@276
    assign rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q or rightShiftStage0Idx1_uid22101_dupName_403_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q;
            1'b1 : rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22101_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x(MUX,22107)@276
    assign rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22106_dupName_403_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22103_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22106_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x(MUX,22112)@276
    assign rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22111_dupName_403_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22108_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22111_dupName_403_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3092_vt_select_20(BITSELECT,11902)@276
    assign i_unnamed_c_compmm_m3092_vt_select_20_b = rightShiftStage2_uid22113_dupName_403_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3092_vt_join(BITJOIN,11901)@276
    assign i_unnamed_c_compmm_m3092_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3092_vt_select_20_b};

    // i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x(BITSELECT,3450)@276
    assign i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x_b = i_unnamed_c_compmm_m3092_vt_join_q[15:0];

    // redist1139_i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x_b_1(DELAY,30267)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1139_i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22122_dupName_404_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22121)@276
    assign rightShiftStage1Idx1Rng8_uid22122_dupName_404_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22124_dupName_404_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22123)@276
    assign rightShiftStage1Idx1_uid22124_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22122_dupName_404_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22117_dupName_404_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22116)@276
    assign rightShiftStage0Idx1Rng4_uid22117_dupName_404_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q[33:4];

    // rightShiftStage0Idx1_uid22119_dupName_404_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22118)@276
    assign rightShiftStage0Idx1_uid22119_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22117_dupName_404_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x(MUX,22120)@276
    assign rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q or rightShiftStage0Idx1_uid22119_dupName_404_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_101_i_c_compmm_m3091_q;
            1'b1 : rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22119_dupName_404_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x(MUX,22125)@276
    assign rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22124_dupName_404_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22121_dupName_404_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22124_dupName_404_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3094_vt_select_21(BITSELECT,11905)@276
    assign i_unnamed_c_compmm_m3094_vt_select_21_b = rightShiftStage1_uid22126_dupName_404_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3094_vt_join(BITJOIN,11904)@276
    assign i_unnamed_c_compmm_m3094_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3094_vt_select_21_b};

    // i_unnamed_c_compmm_m3095_sel_x(BITSELECT,6157)@276
    assign i_unnamed_c_compmm_m3095_sel_x_b = i_unnamed_c_compmm_m3094_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3096_BitSelect_for_a(BITSELECT,28666)@276
    assign i_unnamed_c_compmm_m3096_BitSelect_for_a_b = i_unnamed_c_compmm_m3095_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3096_join(BITJOIN,28667)@276
    assign i_unnamed_c_compmm_m3096_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3096_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3096_vt_select_0(BITSELECT,11910)@276
    assign i_unnamed_c_compmm_m3096_vt_select_0_b = i_unnamed_c_compmm_m3096_join_q[0:0];

    // redist104_i_unnamed_c_compmm_m3096_vt_select_0_b_1(DELAY,29232)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist104_i_unnamed_c_compmm_m3096_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3096_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3096_vt_join(BITJOIN,11909)@277
    assign i_unnamed_c_compmm_m3096_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist104_i_unnamed_c_compmm_m3096_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_101_c_compmm_m3097(ADD,7033)@277
    assign i_add_i_i_i_i_i126_i_101_c_compmm_m3097_a = {1'b0, i_unnamed_c_compmm_m3096_vt_join_q};
    assign i_add_i_i_i_i_i126_i_101_c_compmm_m3097_b = {1'b0, redist1139_i_conv_i_i_i_i97_i_101_c_compmm_m3093_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_101_c_compmm_m3097_o = $unsigned(i_add_i_i_i_i_i126_i_101_c_compmm_m3097_a) + $unsigned(i_add_i_i_i_i_i126_i_101_c_compmm_m3097_b);
    assign i_add_i_i_i_i_i126_i_101_c_compmm_m3097_q = i_add_i_i_i_i_i126_i_101_c_compmm_m3097_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_101_c_compmm_m3097_sel_x(BITSELECT,2047)@277
    assign bgTrunc_i_add_i_i_i_i_i126_i_101_c_compmm_m3097_sel_x_b = i_add_i_i_i_i_i126_i_101_c_compmm_m3097_q[15:0];

    // i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_sel_x(BITSELECT,3580)@277
    assign i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_101_c_compmm_m3097_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_select_15(BITSELECT,7431)@277
    assign i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_select_15_b = i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_join(BITJOIN,7430)@277
    assign i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_select_15_b};

    // leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(MUX,23812)@277
    assign leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_join_q or leftShiftStage0Idx1_uid23811_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_102_c_compmm_m3117_vt_join_q;
            1'b1 : leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23811_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(MUX,23817)@277
    assign leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s or leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23816_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = leftShiftStage0_uid23813_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23816_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x(MUX,23822)@277
    assign leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s or leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23821_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = leftShiftStage1_uid23818_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23821_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28(BITSELECT,9466)@277
    assign i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28_b = leftShiftStage2_uid23823_i_shl_i_i_i_i_i77_i_102_c_compmm_m0_shift_x_q[28:13];

    // redist500_i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28_b_1(DELAY,29628)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist500_i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_join(BITJOIN,9465)@278
    assign i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_join_q = {redist500_i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma(CHAINMULTADD,29002)@272 + 5
    // out q@278
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_13_c_compmm_m_fpgaunique_67224_c_compmm_m52_out_dest_data_out_206_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_12_c_compmm_m_fpgaunique_67223_c_compmm_m53_out_dest_data_out_205_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ch[0] <= redist708_sync_together4364_aunroll_x_in_c1_eni5_206_tpl_204_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ch[1] <= redist707_sync_together4364_aunroll_x_in_c1_eni5_205_tpl_204_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119(ADD,8822)@278
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_102_i_c_compmm_m3114_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_102_i_c_compmm_m3116_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_102_i_c_compmm_m3115_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_102_c_compmm_m3118_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_o[33:0];

    // rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x(MUX,22164)@278
    assign rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q or rightShiftStage0Idx1_uid22163_dupName_407_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q;
            1'b1 : rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22163_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x(MUX,22169)@278
    assign rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22168_dupName_407_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22165_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22168_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x(MUX,22174)@278
    assign rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22173_dupName_407_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22170_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22173_dupName_407_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3120_vt_select_20(BITSELECT,11927)@278
    assign i_unnamed_c_compmm_m3120_vt_select_20_b = rightShiftStage2_uid22175_dupName_407_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3120_vt_join(BITJOIN,11926)@278
    assign i_unnamed_c_compmm_m3120_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3120_vt_select_20_b};

    // i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x(BITSELECT,3451)@278
    assign i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x_b = i_unnamed_c_compmm_m3120_vt_join_q[15:0];

    // redist1138_i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x_b_1(DELAY,30266)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1138_i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22184_dupName_408_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22183)@278
    assign rightShiftStage1Idx1Rng8_uid22184_dupName_408_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22186_dupName_408_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22185)@278
    assign rightShiftStage1Idx1_uid22186_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22184_dupName_408_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22179_dupName_408_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22178)@278
    assign rightShiftStage0Idx1Rng4_uid22179_dupName_408_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q[33:4];

    // rightShiftStage0Idx1_uid22181_dupName_408_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22180)@278
    assign rightShiftStage0Idx1_uid22181_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22179_dupName_408_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x(MUX,22182)@278
    assign rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q or rightShiftStage0Idx1_uid22181_dupName_408_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_102_i_c_compmm_m3119_q;
            1'b1 : rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22181_dupName_408_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x(MUX,22187)@278
    assign rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22186_dupName_408_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22183_dupName_408_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22186_dupName_408_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3122_vt_select_21(BITSELECT,11930)@278
    assign i_unnamed_c_compmm_m3122_vt_select_21_b = rightShiftStage1_uid22188_dupName_408_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3122_vt_join(BITJOIN,11929)@278
    assign i_unnamed_c_compmm_m3122_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3122_vt_select_21_b};

    // i_unnamed_c_compmm_m3123_sel_x(BITSELECT,6159)@278
    assign i_unnamed_c_compmm_m3123_sel_x_b = i_unnamed_c_compmm_m3122_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3124_BitSelect_for_a(BITSELECT,28670)@278
    assign i_unnamed_c_compmm_m3124_BitSelect_for_a_b = i_unnamed_c_compmm_m3123_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3124_join(BITJOIN,28671)@278
    assign i_unnamed_c_compmm_m3124_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3124_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3124_vt_select_0(BITSELECT,11935)@278
    assign i_unnamed_c_compmm_m3124_vt_select_0_b = i_unnamed_c_compmm_m3124_join_q[0:0];

    // redist102_i_unnamed_c_compmm_m3124_vt_select_0_b_1(DELAY,29230)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist102_i_unnamed_c_compmm_m3124_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3124_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3124_vt_join(BITJOIN,11934)@279
    assign i_unnamed_c_compmm_m3124_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist102_i_unnamed_c_compmm_m3124_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_102_c_compmm_m3125(ADD,7034)@279
    assign i_add_i_i_i_i_i126_i_102_c_compmm_m3125_a = {1'b0, i_unnamed_c_compmm_m3124_vt_join_q};
    assign i_add_i_i_i_i_i126_i_102_c_compmm_m3125_b = {1'b0, redist1138_i_conv_i_i_i_i97_i_102_c_compmm_m3121_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_102_c_compmm_m3125_o = $unsigned(i_add_i_i_i_i_i126_i_102_c_compmm_m3125_a) + $unsigned(i_add_i_i_i_i_i126_i_102_c_compmm_m3125_b);
    assign i_add_i_i_i_i_i126_i_102_c_compmm_m3125_q = i_add_i_i_i_i_i126_i_102_c_compmm_m3125_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_102_c_compmm_m3125_sel_x(BITSELECT,2048)@279
    assign bgTrunc_i_add_i_i_i_i_i126_i_102_c_compmm_m3125_sel_x_b = i_add_i_i_i_i_i126_i_102_c_compmm_m3125_q[15:0];

    // i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_sel_x(BITSELECT,3581)@279
    assign i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_102_c_compmm_m3125_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_select_15(BITSELECT,7435)@279
    assign i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_select_15_b = i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_join(BITJOIN,7434)@279
    assign i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_select_15_b};

    // leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(MUX,23830)@279
    assign leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_join_q or leftShiftStage0Idx1_uid23829_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_103_c_compmm_m3145_vt_join_q;
            1'b1 : leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23829_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(MUX,23835)@279
    assign leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s or leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23834_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = leftShiftStage0_uid23831_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23834_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x(MUX,23840)@279
    assign leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s or leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23839_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = leftShiftStage1_uid23836_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23839_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28(BITSELECT,9469)@279
    assign i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28_b = leftShiftStage2_uid23841_i_shl_i_i_i_i_i77_i_103_c_compmm_m0_shift_x_q[28:13];

    // redist499_i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28_b_1(DELAY,29627)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist499_i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_join(BITJOIN,9468)@280
    assign i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_join_q = {redist499_i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma(CHAINMULTADD,29003)@274 + 5
    // out q@280
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_15_c_compmm_m_fpgaunique_67226_c_compmm_m50_out_dest_data_out_208_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_14_c_compmm_m_fpgaunique_67225_c_compmm_m51_out_dest_data_out_207_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ch[0] <= redist710_sync_together4364_aunroll_x_in_c1_eni5_208_tpl_206_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ch[1] <= redist709_sync_together4364_aunroll_x_in_c1_eni5_207_tpl_206_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147(ADD,8823)@280
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_103_i_c_compmm_m3142_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_103_i_c_compmm_m3144_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_103_i_c_compmm_m3143_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_103_c_compmm_m3146_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_o[33:0];

    // rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x(MUX,22226)@280
    assign rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q or rightShiftStage0Idx1_uid22225_dupName_411_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q;
            1'b1 : rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22225_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x(MUX,22231)@280
    assign rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22230_dupName_411_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22227_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22230_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x(MUX,22236)@280
    assign rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22235_dupName_411_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22232_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22235_dupName_411_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3148_vt_select_20(BITSELECT,11949)@280
    assign i_unnamed_c_compmm_m3148_vt_select_20_b = rightShiftStage2_uid22237_dupName_411_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3148_vt_join(BITJOIN,11948)@280
    assign i_unnamed_c_compmm_m3148_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3148_vt_select_20_b};

    // i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x(BITSELECT,3452)@280
    assign i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x_b = i_unnamed_c_compmm_m3148_vt_join_q[15:0];

    // redist1137_i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x_b_1(DELAY,30265)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1137_i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22246_dupName_412_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22245)@280
    assign rightShiftStage1Idx1Rng8_uid22246_dupName_412_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22248_dupName_412_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22247)@280
    assign rightShiftStage1Idx1_uid22248_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22246_dupName_412_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22241_dupName_412_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22240)@280
    assign rightShiftStage0Idx1Rng4_uid22241_dupName_412_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q[33:4];

    // rightShiftStage0Idx1_uid22243_dupName_412_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22242)@280
    assign rightShiftStage0Idx1_uid22243_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22241_dupName_412_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x(MUX,22244)@280
    assign rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q or rightShiftStage0Idx1_uid22243_dupName_412_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_103_i_c_compmm_m3147_q;
            1'b1 : rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22243_dupName_412_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x(MUX,22249)@280
    assign rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22248_dupName_412_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22245_dupName_412_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22248_dupName_412_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3150_vt_select_21(BITSELECT,11952)@280
    assign i_unnamed_c_compmm_m3150_vt_select_21_b = rightShiftStage1_uid22250_dupName_412_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3150_vt_join(BITJOIN,11951)@280
    assign i_unnamed_c_compmm_m3150_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3150_vt_select_21_b};

    // i_unnamed_c_compmm_m3151_sel_x(BITSELECT,6161)@280
    assign i_unnamed_c_compmm_m3151_sel_x_b = i_unnamed_c_compmm_m3150_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3152_BitSelect_for_a(BITSELECT,28674)@280
    assign i_unnamed_c_compmm_m3152_BitSelect_for_a_b = i_unnamed_c_compmm_m3151_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3152_join(BITJOIN,28675)@280
    assign i_unnamed_c_compmm_m3152_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3152_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3152_vt_select_0(BITSELECT,11957)@280
    assign i_unnamed_c_compmm_m3152_vt_select_0_b = i_unnamed_c_compmm_m3152_join_q[0:0];

    // redist100_i_unnamed_c_compmm_m3152_vt_select_0_b_1(DELAY,29228)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist100_i_unnamed_c_compmm_m3152_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3152_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3152_vt_join(BITJOIN,11956)@281
    assign i_unnamed_c_compmm_m3152_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist100_i_unnamed_c_compmm_m3152_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_103_c_compmm_m3153(ADD,7035)@281
    assign i_add_i_i_i_i_i126_i_103_c_compmm_m3153_a = {1'b0, i_unnamed_c_compmm_m3152_vt_join_q};
    assign i_add_i_i_i_i_i126_i_103_c_compmm_m3153_b = {1'b0, redist1137_i_conv_i_i_i_i97_i_103_c_compmm_m3149_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_103_c_compmm_m3153_o = $unsigned(i_add_i_i_i_i_i126_i_103_c_compmm_m3153_a) + $unsigned(i_add_i_i_i_i_i126_i_103_c_compmm_m3153_b);
    assign i_add_i_i_i_i_i126_i_103_c_compmm_m3153_q = i_add_i_i_i_i_i126_i_103_c_compmm_m3153_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_103_c_compmm_m3153_sel_x(BITSELECT,2049)@281
    assign bgTrunc_i_add_i_i_i_i_i126_i_103_c_compmm_m3153_sel_x_b = i_add_i_i_i_i_i126_i_103_c_compmm_m3153_q[15:0];

    // i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_sel_x(BITSELECT,3582)@281
    assign i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_103_c_compmm_m3153_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_select_15(BITSELECT,7439)@281
    assign i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_select_15_b = i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_join(BITJOIN,7438)@281
    assign i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_select_15_b};

    // leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(MUX,23848)@281
    assign leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_join_q or leftShiftStage0Idx1_uid23847_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_104_c_compmm_m3173_vt_join_q;
            1'b1 : leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23847_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(MUX,23853)@281
    assign leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s or leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23852_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = leftShiftStage0_uid23849_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23852_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x(MUX,23858)@281
    assign leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s or leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23857_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = leftShiftStage1_uid23854_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23857_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28(BITSELECT,9472)@281
    assign i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28_b = leftShiftStage2_uid23859_i_shl_i_i_i_i_i77_i_104_c_compmm_m0_shift_x_q[28:13];

    // redist498_i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28_b_1(DELAY,29626)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist498_i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_join(BITJOIN,9471)@282
    assign i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_join_q = {redist498_i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma(CHAINMULTADD,29004)@276 + 5
    // out q@282
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_17_c_compmm_m_fpgaunique_67228_c_compmm_m48_out_dest_data_out_210_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_16_c_compmm_m_fpgaunique_67227_c_compmm_m49_out_dest_data_out_209_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ch[0] <= redist712_sync_together4364_aunroll_x_in_c1_eni5_210_tpl_208_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ch[1] <= redist711_sync_together4364_aunroll_x_in_c1_eni5_209_tpl_208_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175(ADD,8824)@282
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_104_i_c_compmm_m3170_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_104_i_c_compmm_m3172_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_104_i_c_compmm_m3171_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_104_c_compmm_m3174_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_o[33:0];

    // rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x(MUX,22288)@282
    assign rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q or rightShiftStage0Idx1_uid22287_dupName_415_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q;
            1'b1 : rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22287_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x(MUX,22293)@282
    assign rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22292_dupName_415_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22289_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22292_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x(MUX,22298)@282
    assign rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22297_dupName_415_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22294_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22297_dupName_415_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3176_vt_select_20(BITSELECT,11971)@282
    assign i_unnamed_c_compmm_m3176_vt_select_20_b = rightShiftStage2_uid22299_dupName_415_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3176_vt_join(BITJOIN,11970)@282
    assign i_unnamed_c_compmm_m3176_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3176_vt_select_20_b};

    // i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x(BITSELECT,3453)@282
    assign i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x_b = i_unnamed_c_compmm_m3176_vt_join_q[15:0];

    // redist1136_i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x_b_1(DELAY,30264)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1136_i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22308_dupName_416_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22307)@282
    assign rightShiftStage1Idx1Rng8_uid22308_dupName_416_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22310_dupName_416_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22309)@282
    assign rightShiftStage1Idx1_uid22310_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22308_dupName_416_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22303_dupName_416_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22302)@282
    assign rightShiftStage0Idx1Rng4_uid22303_dupName_416_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q[33:4];

    // rightShiftStage0Idx1_uid22305_dupName_416_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22304)@282
    assign rightShiftStage0Idx1_uid22305_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22303_dupName_416_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x(MUX,22306)@282
    assign rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q or rightShiftStage0Idx1_uid22305_dupName_416_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_104_i_c_compmm_m3175_q;
            1'b1 : rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22305_dupName_416_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x(MUX,22311)@282
    assign rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22310_dupName_416_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22307_dupName_416_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22310_dupName_416_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3178_vt_select_21(BITSELECT,11974)@282
    assign i_unnamed_c_compmm_m3178_vt_select_21_b = rightShiftStage1_uid22312_dupName_416_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3178_vt_join(BITJOIN,11973)@282
    assign i_unnamed_c_compmm_m3178_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3178_vt_select_21_b};

    // i_unnamed_c_compmm_m3179_sel_x(BITSELECT,6163)@282
    assign i_unnamed_c_compmm_m3179_sel_x_b = i_unnamed_c_compmm_m3178_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3180_BitSelect_for_a(BITSELECT,28678)@282
    assign i_unnamed_c_compmm_m3180_BitSelect_for_a_b = i_unnamed_c_compmm_m3179_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3180_join(BITJOIN,28679)@282
    assign i_unnamed_c_compmm_m3180_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3180_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3180_vt_select_0(BITSELECT,11982)@282
    assign i_unnamed_c_compmm_m3180_vt_select_0_b = i_unnamed_c_compmm_m3180_join_q[0:0];

    // redist98_i_unnamed_c_compmm_m3180_vt_select_0_b_1(DELAY,29226)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist98_i_unnamed_c_compmm_m3180_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3180_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3180_vt_join(BITJOIN,11981)@283
    assign i_unnamed_c_compmm_m3180_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist98_i_unnamed_c_compmm_m3180_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_104_c_compmm_m3181(ADD,7036)@283
    assign i_add_i_i_i_i_i126_i_104_c_compmm_m3181_a = {1'b0, i_unnamed_c_compmm_m3180_vt_join_q};
    assign i_add_i_i_i_i_i126_i_104_c_compmm_m3181_b = {1'b0, redist1136_i_conv_i_i_i_i97_i_104_c_compmm_m3177_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_104_c_compmm_m3181_o = $unsigned(i_add_i_i_i_i_i126_i_104_c_compmm_m3181_a) + $unsigned(i_add_i_i_i_i_i126_i_104_c_compmm_m3181_b);
    assign i_add_i_i_i_i_i126_i_104_c_compmm_m3181_q = i_add_i_i_i_i_i126_i_104_c_compmm_m3181_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_104_c_compmm_m3181_sel_x(BITSELECT,2050)@283
    assign bgTrunc_i_add_i_i_i_i_i126_i_104_c_compmm_m3181_sel_x_b = i_add_i_i_i_i_i126_i_104_c_compmm_m3181_q[15:0];

    // i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_sel_x(BITSELECT,3583)@283
    assign i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_104_c_compmm_m3181_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_select_15(BITSELECT,7443)@283
    assign i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_select_15_b = i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_join(BITJOIN,7442)@283
    assign i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_select_15_b};

    // leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(MUX,23866)@283
    assign leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_join_q or leftShiftStage0Idx1_uid23865_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_105_c_compmm_m3201_vt_join_q;
            1'b1 : leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23865_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(MUX,23871)@283
    assign leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s or leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23870_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = leftShiftStage0_uid23867_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23870_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x(MUX,23876)@283
    assign leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s or leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23875_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = leftShiftStage1_uid23872_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23875_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28(BITSELECT,9475)@283
    assign i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28_b = leftShiftStage2_uid23877_i_shl_i_i_i_i_i77_i_105_c_compmm_m0_shift_x_q[28:13];

    // redist497_i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28_b_1(DELAY,29625)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist497_i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_join(BITJOIN,9474)@284
    assign i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_join_q = {redist497_i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma(CHAINMULTADD,29005)@278 + 5
    // out q@284
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_19_c_compmm_m_fpgaunique_67230_c_compmm_m46_out_dest_data_out_212_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_18_c_compmm_m_fpgaunique_67229_c_compmm_m47_out_dest_data_out_211_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ch[0] <= redist714_sync_together4364_aunroll_x_in_c1_eni5_212_tpl_210_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ch[1] <= redist713_sync_together4364_aunroll_x_in_c1_eni5_211_tpl_210_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203(ADD,8825)@284
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_105_i_c_compmm_m3198_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_105_i_c_compmm_m3200_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_105_i_c_compmm_m3199_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_105_c_compmm_m3202_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_o[33:0];

    // rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x(MUX,22350)@284
    assign rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q or rightShiftStage0Idx1_uid22349_dupName_419_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q;
            1'b1 : rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22349_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x(MUX,22355)@284
    assign rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22354_dupName_419_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22351_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22354_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x(MUX,22360)@284
    assign rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22359_dupName_419_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22356_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22359_dupName_419_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3204_vt_select_20(BITSELECT,11999)@284
    assign i_unnamed_c_compmm_m3204_vt_select_20_b = rightShiftStage2_uid22361_dupName_419_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3204_vt_join(BITJOIN,11998)@284
    assign i_unnamed_c_compmm_m3204_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3204_vt_select_20_b};

    // i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x(BITSELECT,3454)@284
    assign i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x_b = i_unnamed_c_compmm_m3204_vt_join_q[15:0];

    // redist1135_i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x_b_1(DELAY,30263)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1135_i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22370_dupName_420_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22369)@284
    assign rightShiftStage1Idx1Rng8_uid22370_dupName_420_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22372_dupName_420_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22371)@284
    assign rightShiftStage1Idx1_uid22372_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22370_dupName_420_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22365_dupName_420_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22364)@284
    assign rightShiftStage0Idx1Rng4_uid22365_dupName_420_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q[33:4];

    // rightShiftStage0Idx1_uid22367_dupName_420_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22366)@284
    assign rightShiftStage0Idx1_uid22367_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22365_dupName_420_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x(MUX,22368)@284
    assign rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q or rightShiftStage0Idx1_uid22367_dupName_420_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_105_i_c_compmm_m3203_q;
            1'b1 : rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22367_dupName_420_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x(MUX,22373)@284
    assign rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22372_dupName_420_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22369_dupName_420_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22372_dupName_420_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3206_vt_select_21(BITSELECT,12002)@284
    assign i_unnamed_c_compmm_m3206_vt_select_21_b = rightShiftStage1_uid22374_dupName_420_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3206_vt_join(BITJOIN,12001)@284
    assign i_unnamed_c_compmm_m3206_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3206_vt_select_21_b};

    // i_unnamed_c_compmm_m3207_sel_x(BITSELECT,6166)@284
    assign i_unnamed_c_compmm_m3207_sel_x_b = i_unnamed_c_compmm_m3206_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3208_BitSelect_for_a(BITSELECT,28682)@284
    assign i_unnamed_c_compmm_m3208_BitSelect_for_a_b = i_unnamed_c_compmm_m3207_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3208_join(BITJOIN,28683)@284
    assign i_unnamed_c_compmm_m3208_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3208_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3208_vt_select_0(BITSELECT,12007)@284
    assign i_unnamed_c_compmm_m3208_vt_select_0_b = i_unnamed_c_compmm_m3208_join_q[0:0];

    // redist96_i_unnamed_c_compmm_m3208_vt_select_0_b_1(DELAY,29224)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist96_i_unnamed_c_compmm_m3208_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3208_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3208_vt_join(BITJOIN,12006)@285
    assign i_unnamed_c_compmm_m3208_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist96_i_unnamed_c_compmm_m3208_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_105_c_compmm_m3209(ADD,7037)@285
    assign i_add_i_i_i_i_i126_i_105_c_compmm_m3209_a = {1'b0, i_unnamed_c_compmm_m3208_vt_join_q};
    assign i_add_i_i_i_i_i126_i_105_c_compmm_m3209_b = {1'b0, redist1135_i_conv_i_i_i_i97_i_105_c_compmm_m3205_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_105_c_compmm_m3209_o = $unsigned(i_add_i_i_i_i_i126_i_105_c_compmm_m3209_a) + $unsigned(i_add_i_i_i_i_i126_i_105_c_compmm_m3209_b);
    assign i_add_i_i_i_i_i126_i_105_c_compmm_m3209_q = i_add_i_i_i_i_i126_i_105_c_compmm_m3209_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_105_c_compmm_m3209_sel_x(BITSELECT,2051)@285
    assign bgTrunc_i_add_i_i_i_i_i126_i_105_c_compmm_m3209_sel_x_b = i_add_i_i_i_i_i126_i_105_c_compmm_m3209_q[15:0];

    // i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_sel_x(BITSELECT,3584)@285
    assign i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_105_c_compmm_m3209_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_select_15(BITSELECT,7447)@285
    assign i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_select_15_b = i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_join(BITJOIN,7446)@285
    assign i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_select_15_b};

    // leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(MUX,23884)@285
    assign leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_join_q or leftShiftStage0Idx1_uid23883_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_106_c_compmm_m3229_vt_join_q;
            1'b1 : leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23883_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(MUX,23889)@285
    assign leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s or leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23888_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = leftShiftStage0_uid23885_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23888_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x(MUX,23894)@285
    assign leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s or leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23893_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = leftShiftStage1_uid23890_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23893_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28(BITSELECT,9478)@285
    assign i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28_b = leftShiftStage2_uid23895_i_shl_i_i_i_i_i77_i_106_c_compmm_m0_shift_x_q[28:13];

    // redist496_i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28_b_1(DELAY,29624)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist496_i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_join(BITJOIN,9477)@286
    assign i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_join_q = {redist496_i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma(CHAINMULTADD,29006)@280 + 5
    // out q@286
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_21_c_compmm_m_fpgaunique_67232_c_compmm_m44_out_dest_data_out_214_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_20_c_compmm_m_fpgaunique_67231_c_compmm_m45_out_dest_data_out_213_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ch[0] <= redist716_sync_together4364_aunroll_x_in_c1_eni5_214_tpl_212_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ch[1] <= redist715_sync_together4364_aunroll_x_in_c1_eni5_213_tpl_212_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231(ADD,8826)@286
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_106_i_c_compmm_m3226_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_106_i_c_compmm_m3228_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_106_i_c_compmm_m3227_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_106_c_compmm_m3230_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_o[33:0];

    // rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x(MUX,22412)@286
    assign rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q or rightShiftStage0Idx1_uid22411_dupName_423_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q;
            1'b1 : rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22411_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x(MUX,22417)@286
    assign rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22416_dupName_423_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22413_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22416_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x(MUX,22422)@286
    assign rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22421_dupName_423_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22418_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22421_dupName_423_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3232_vt_select_20(BITSELECT,12026)@286
    assign i_unnamed_c_compmm_m3232_vt_select_20_b = rightShiftStage2_uid22423_dupName_423_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3232_vt_join(BITJOIN,12025)@286
    assign i_unnamed_c_compmm_m3232_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3232_vt_select_20_b};

    // i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x(BITSELECT,3455)@286
    assign i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x_b = i_unnamed_c_compmm_m3232_vt_join_q[15:0];

    // redist1134_i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x_b_1(DELAY,30262)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1134_i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22432_dupName_424_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22431)@286
    assign rightShiftStage1Idx1Rng8_uid22432_dupName_424_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22434_dupName_424_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22433)@286
    assign rightShiftStage1Idx1_uid22434_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22432_dupName_424_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22427_dupName_424_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22426)@286
    assign rightShiftStage0Idx1Rng4_uid22427_dupName_424_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q[33:4];

    // rightShiftStage0Idx1_uid22429_dupName_424_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22428)@286
    assign rightShiftStage0Idx1_uid22429_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22427_dupName_424_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x(MUX,22430)@286
    assign rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q or rightShiftStage0Idx1_uid22429_dupName_424_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_106_i_c_compmm_m3231_q;
            1'b1 : rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22429_dupName_424_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x(MUX,22435)@286
    assign rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22434_dupName_424_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22431_dupName_424_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22434_dupName_424_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3234_vt_select_21(BITSELECT,12029)@286
    assign i_unnamed_c_compmm_m3234_vt_select_21_b = rightShiftStage1_uid22436_dupName_424_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3234_vt_join(BITJOIN,12028)@286
    assign i_unnamed_c_compmm_m3234_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3234_vt_select_21_b};

    // i_unnamed_c_compmm_m3235_sel_x(BITSELECT,6168)@286
    assign i_unnamed_c_compmm_m3235_sel_x_b = i_unnamed_c_compmm_m3234_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3236_BitSelect_for_a(BITSELECT,28688)@286
    assign i_unnamed_c_compmm_m3236_BitSelect_for_a_b = i_unnamed_c_compmm_m3235_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3236_join(BITJOIN,28689)@286
    assign i_unnamed_c_compmm_m3236_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3236_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3236_vt_select_0(BITSELECT,12034)@286
    assign i_unnamed_c_compmm_m3236_vt_select_0_b = i_unnamed_c_compmm_m3236_join_q[0:0];

    // redist93_i_unnamed_c_compmm_m3236_vt_select_0_b_1(DELAY,29221)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist93_i_unnamed_c_compmm_m3236_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3236_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3236_vt_join(BITJOIN,12033)@287
    assign i_unnamed_c_compmm_m3236_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist93_i_unnamed_c_compmm_m3236_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_106_c_compmm_m3237(ADD,7038)@287
    assign i_add_i_i_i_i_i126_i_106_c_compmm_m3237_a = {1'b0, i_unnamed_c_compmm_m3236_vt_join_q};
    assign i_add_i_i_i_i_i126_i_106_c_compmm_m3237_b = {1'b0, redist1134_i_conv_i_i_i_i97_i_106_c_compmm_m3233_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_106_c_compmm_m3237_o = $unsigned(i_add_i_i_i_i_i126_i_106_c_compmm_m3237_a) + $unsigned(i_add_i_i_i_i_i126_i_106_c_compmm_m3237_b);
    assign i_add_i_i_i_i_i126_i_106_c_compmm_m3237_q = i_add_i_i_i_i_i126_i_106_c_compmm_m3237_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_106_c_compmm_m3237_sel_x(BITSELECT,2052)@287
    assign bgTrunc_i_add_i_i_i_i_i126_i_106_c_compmm_m3237_sel_x_b = i_add_i_i_i_i_i126_i_106_c_compmm_m3237_q[15:0];

    // i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_sel_x(BITSELECT,3585)@287
    assign i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_106_c_compmm_m3237_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_select_15(BITSELECT,7451)@287
    assign i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_select_15_b = i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_join(BITJOIN,7450)@287
    assign i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_select_15_b};

    // leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(MUX,23902)@287
    assign leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_join_q or leftShiftStage0Idx1_uid23901_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_107_c_compmm_m3257_vt_join_q;
            1'b1 : leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23901_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(MUX,23907)@287
    assign leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s or leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23906_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = leftShiftStage0_uid23903_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23906_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x(MUX,23912)@287
    assign leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s or leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23911_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = leftShiftStage1_uid23908_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23911_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28(BITSELECT,9481)@287
    assign i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28_b = leftShiftStage2_uid23913_i_shl_i_i_i_i_i77_i_107_c_compmm_m0_shift_x_q[28:13];

    // redist495_i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28_b_1(DELAY,29623)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist495_i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_join(BITJOIN,9480)@288
    assign i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_join_q = {redist495_i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma(CHAINMULTADD,29007)@282 + 5
    // out q@288
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_23_c_compmm_m_fpgaunique_67234_c_compmm_m42_out_dest_data_out_216_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_22_c_compmm_m_fpgaunique_67233_c_compmm_m43_out_dest_data_out_215_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ch[0] <= redist718_sync_together4364_aunroll_x_in_c1_eni5_216_tpl_214_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ch[1] <= redist717_sync_together4364_aunroll_x_in_c1_eni5_215_tpl_214_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259(ADD,8827)@288
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_107_i_c_compmm_m3254_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_107_i_c_compmm_m3256_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_107_i_c_compmm_m3255_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_107_c_compmm_m3258_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_o[33:0];

    // rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x(MUX,22474)@288
    assign rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q or rightShiftStage0Idx1_uid22473_dupName_427_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q;
            1'b1 : rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22473_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x(MUX,22479)@288
    assign rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22478_dupName_427_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22475_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22478_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x(MUX,22484)@288
    assign rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22483_dupName_427_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22480_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22483_dupName_427_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3260_vt_select_20(BITSELECT,12048)@288
    assign i_unnamed_c_compmm_m3260_vt_select_20_b = rightShiftStage2_uid22485_dupName_427_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3260_vt_join(BITJOIN,12047)@288
    assign i_unnamed_c_compmm_m3260_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3260_vt_select_20_b};

    // i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x(BITSELECT,3456)@288
    assign i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x_b = i_unnamed_c_compmm_m3260_vt_join_q[15:0];

    // redist1133_i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x_b_1(DELAY,30261)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1133_i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22494_dupName_428_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22493)@288
    assign rightShiftStage1Idx1Rng8_uid22494_dupName_428_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22496_dupName_428_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22495)@288
    assign rightShiftStage1Idx1_uid22496_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22494_dupName_428_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22489_dupName_428_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22488)@288
    assign rightShiftStage0Idx1Rng4_uid22489_dupName_428_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q[33:4];

    // rightShiftStage0Idx1_uid22491_dupName_428_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22490)@288
    assign rightShiftStage0Idx1_uid22491_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22489_dupName_428_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x(MUX,22492)@288
    assign rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q or rightShiftStage0Idx1_uid22491_dupName_428_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_107_i_c_compmm_m3259_q;
            1'b1 : rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22491_dupName_428_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x(MUX,22497)@288
    assign rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22496_dupName_428_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22493_dupName_428_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22496_dupName_428_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3262_vt_select_21(BITSELECT,12051)@288
    assign i_unnamed_c_compmm_m3262_vt_select_21_b = rightShiftStage1_uid22498_dupName_428_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3262_vt_join(BITJOIN,12050)@288
    assign i_unnamed_c_compmm_m3262_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3262_vt_select_21_b};

    // i_unnamed_c_compmm_m3263_sel_x(BITSELECT,6170)@288
    assign i_unnamed_c_compmm_m3263_sel_x_b = i_unnamed_c_compmm_m3262_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3264_BitSelect_for_a(BITSELECT,28692)@288
    assign i_unnamed_c_compmm_m3264_BitSelect_for_a_b = i_unnamed_c_compmm_m3263_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3264_join(BITJOIN,28693)@288
    assign i_unnamed_c_compmm_m3264_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3264_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3264_vt_select_0(BITSELECT,12056)@288
    assign i_unnamed_c_compmm_m3264_vt_select_0_b = i_unnamed_c_compmm_m3264_join_q[0:0];

    // redist91_i_unnamed_c_compmm_m3264_vt_select_0_b_1(DELAY,29219)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist91_i_unnamed_c_compmm_m3264_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3264_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3264_vt_join(BITJOIN,12055)@289
    assign i_unnamed_c_compmm_m3264_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist91_i_unnamed_c_compmm_m3264_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_107_c_compmm_m3265(ADD,7039)@289
    assign i_add_i_i_i_i_i126_i_107_c_compmm_m3265_a = {1'b0, i_unnamed_c_compmm_m3264_vt_join_q};
    assign i_add_i_i_i_i_i126_i_107_c_compmm_m3265_b = {1'b0, redist1133_i_conv_i_i_i_i97_i_107_c_compmm_m3261_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_107_c_compmm_m3265_o = $unsigned(i_add_i_i_i_i_i126_i_107_c_compmm_m3265_a) + $unsigned(i_add_i_i_i_i_i126_i_107_c_compmm_m3265_b);
    assign i_add_i_i_i_i_i126_i_107_c_compmm_m3265_q = i_add_i_i_i_i_i126_i_107_c_compmm_m3265_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_107_c_compmm_m3265_sel_x(BITSELECT,2053)@289
    assign bgTrunc_i_add_i_i_i_i_i126_i_107_c_compmm_m3265_sel_x_b = i_add_i_i_i_i_i126_i_107_c_compmm_m3265_q[15:0];

    // i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_sel_x(BITSELECT,3586)@289
    assign i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_107_c_compmm_m3265_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_select_15(BITSELECT,7455)@289
    assign i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_select_15_b = i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_join(BITJOIN,7454)@289
    assign i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_select_15_b};

    // leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(MUX,23920)@289
    assign leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_join_q or leftShiftStage0Idx1_uid23919_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_108_c_compmm_m3285_vt_join_q;
            1'b1 : leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23919_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(MUX,23925)@289
    assign leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s or leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23924_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = leftShiftStage0_uid23921_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23924_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x(MUX,23930)@289
    assign leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s or leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23929_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = leftShiftStage1_uid23926_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23929_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28(BITSELECT,9484)@289
    assign i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28_b = leftShiftStage2_uid23931_i_shl_i_i_i_i_i77_i_108_c_compmm_m0_shift_x_q[28:13];

    // redist494_i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28_b_1(DELAY,29622)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist494_i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_join(BITJOIN,9483)@290
    assign i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_join_q = {redist494_i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma(CHAINMULTADD,29008)@284 + 5
    // out q@290
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_25_c_compmm_m_fpgaunique_67236_c_compmm_m40_out_dest_data_out_218_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_24_c_compmm_m_fpgaunique_67235_c_compmm_m41_out_dest_data_out_217_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ch[0] <= redist720_sync_together4364_aunroll_x_in_c1_eni5_218_tpl_216_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ch[1] <= redist719_sync_together4364_aunroll_x_in_c1_eni5_217_tpl_216_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287(ADD,8828)@290
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_108_i_c_compmm_m3282_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_108_i_c_compmm_m3284_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_108_i_c_compmm_m3283_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_108_c_compmm_m3286_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_o[33:0];

    // rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x(MUX,22536)@290
    assign rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q or rightShiftStage0Idx1_uid22535_dupName_431_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q;
            1'b1 : rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22535_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x(MUX,22541)@290
    assign rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22540_dupName_431_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22537_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22540_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x(MUX,22546)@290
    assign rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22545_dupName_431_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22542_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22545_dupName_431_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3288_vt_select_20(BITSELECT,12070)@290
    assign i_unnamed_c_compmm_m3288_vt_select_20_b = rightShiftStage2_uid22547_dupName_431_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3288_vt_join(BITJOIN,12069)@290
    assign i_unnamed_c_compmm_m3288_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3288_vt_select_20_b};

    // i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x(BITSELECT,3457)@290
    assign i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x_b = i_unnamed_c_compmm_m3288_vt_join_q[15:0];

    // redist1132_i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x_b_1(DELAY,30260)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1132_i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22556_dupName_432_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22555)@290
    assign rightShiftStage1Idx1Rng8_uid22556_dupName_432_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22558_dupName_432_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22557)@290
    assign rightShiftStage1Idx1_uid22558_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22556_dupName_432_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22551_dupName_432_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22550)@290
    assign rightShiftStage0Idx1Rng4_uid22551_dupName_432_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q[33:4];

    // rightShiftStage0Idx1_uid22553_dupName_432_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22552)@290
    assign rightShiftStage0Idx1_uid22553_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22551_dupName_432_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x(MUX,22554)@290
    assign rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q or rightShiftStage0Idx1_uid22553_dupName_432_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_108_i_c_compmm_m3287_q;
            1'b1 : rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22553_dupName_432_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x(MUX,22559)@290
    assign rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22558_dupName_432_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22555_dupName_432_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22558_dupName_432_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3290_vt_select_21(BITSELECT,12073)@290
    assign i_unnamed_c_compmm_m3290_vt_select_21_b = rightShiftStage1_uid22560_dupName_432_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3290_vt_join(BITJOIN,12072)@290
    assign i_unnamed_c_compmm_m3290_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3290_vt_select_21_b};

    // i_unnamed_c_compmm_m3291_sel_x(BITSELECT,6172)@290
    assign i_unnamed_c_compmm_m3291_sel_x_b = i_unnamed_c_compmm_m3290_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3292_BitSelect_for_a(BITSELECT,28696)@290
    assign i_unnamed_c_compmm_m3292_BitSelect_for_a_b = i_unnamed_c_compmm_m3291_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3292_join(BITJOIN,28697)@290
    assign i_unnamed_c_compmm_m3292_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3292_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3292_vt_select_0(BITSELECT,12078)@290
    assign i_unnamed_c_compmm_m3292_vt_select_0_b = i_unnamed_c_compmm_m3292_join_q[0:0];

    // redist89_i_unnamed_c_compmm_m3292_vt_select_0_b_1(DELAY,29217)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist89_i_unnamed_c_compmm_m3292_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3292_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3292_vt_join(BITJOIN,12077)@291
    assign i_unnamed_c_compmm_m3292_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist89_i_unnamed_c_compmm_m3292_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_108_c_compmm_m3293(ADD,7040)@291
    assign i_add_i_i_i_i_i126_i_108_c_compmm_m3293_a = {1'b0, i_unnamed_c_compmm_m3292_vt_join_q};
    assign i_add_i_i_i_i_i126_i_108_c_compmm_m3293_b = {1'b0, redist1132_i_conv_i_i_i_i97_i_108_c_compmm_m3289_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_108_c_compmm_m3293_o = $unsigned(i_add_i_i_i_i_i126_i_108_c_compmm_m3293_a) + $unsigned(i_add_i_i_i_i_i126_i_108_c_compmm_m3293_b);
    assign i_add_i_i_i_i_i126_i_108_c_compmm_m3293_q = i_add_i_i_i_i_i126_i_108_c_compmm_m3293_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_108_c_compmm_m3293_sel_x(BITSELECT,2054)@291
    assign bgTrunc_i_add_i_i_i_i_i126_i_108_c_compmm_m3293_sel_x_b = i_add_i_i_i_i_i126_i_108_c_compmm_m3293_q[15:0];

    // i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_sel_x(BITSELECT,3587)@291
    assign i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_108_c_compmm_m3293_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_select_15(BITSELECT,7459)@291
    assign i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_select_15_b = i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_join(BITJOIN,7458)@291
    assign i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_select_15_b};

    // leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(MUX,23938)@291
    assign leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_join_q or leftShiftStage0Idx1_uid23937_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_109_c_compmm_m3313_vt_join_q;
            1'b1 : leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23937_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(MUX,23943)@291
    assign leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s or leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23942_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = leftShiftStage0_uid23939_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23942_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x(MUX,23948)@291
    assign leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s or leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23947_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = leftShiftStage1_uid23944_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23947_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28(BITSELECT,9487)@291
    assign i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28_b = leftShiftStage2_uid23949_i_shl_i_i_i_i_i77_i_109_c_compmm_m0_shift_x_q[28:13];

    // redist493_i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28_b_1(DELAY,29621)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist493_i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_join(BITJOIN,9486)@292
    assign i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_join_q = {redist493_i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma(CHAINMULTADD,29009)@286 + 5
    // out q@292
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_27_c_compmm_m_fpgaunique_67238_c_compmm_m38_out_dest_data_out_220_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_26_c_compmm_m_fpgaunique_67237_c_compmm_m39_out_dest_data_out_219_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ch[0] <= redist722_sync_together4364_aunroll_x_in_c1_eni5_220_tpl_218_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ch[1] <= redist721_sync_together4364_aunroll_x_in_c1_eni5_219_tpl_218_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315(ADD,8829)@292
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_109_i_c_compmm_m3310_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_109_i_c_compmm_m3312_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_109_i_c_compmm_m3311_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_109_c_compmm_m3314_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_o[33:0];

    // rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x(MUX,22598)@292
    assign rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q or rightShiftStage0Idx1_uid22597_dupName_435_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q;
            1'b1 : rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22597_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x(MUX,22603)@292
    assign rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22602_dupName_435_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22599_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22602_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x(MUX,22608)@292
    assign rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22607_dupName_435_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22604_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22607_dupName_435_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3316_vt_select_20(BITSELECT,12092)@292
    assign i_unnamed_c_compmm_m3316_vt_select_20_b = rightShiftStage2_uid22609_dupName_435_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3316_vt_join(BITJOIN,12091)@292
    assign i_unnamed_c_compmm_m3316_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3316_vt_select_20_b};

    // i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x(BITSELECT,3458)@292
    assign i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x_b = i_unnamed_c_compmm_m3316_vt_join_q[15:0];

    // redist1131_i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x_b_1(DELAY,30259)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1131_i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22618_dupName_436_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22617)@292
    assign rightShiftStage1Idx1Rng8_uid22618_dupName_436_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22620_dupName_436_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22619)@292
    assign rightShiftStage1Idx1_uid22620_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22618_dupName_436_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22613_dupName_436_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22612)@292
    assign rightShiftStage0Idx1Rng4_uid22613_dupName_436_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q[33:4];

    // rightShiftStage0Idx1_uid22615_dupName_436_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22614)@292
    assign rightShiftStage0Idx1_uid22615_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22613_dupName_436_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x(MUX,22616)@292
    assign rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q or rightShiftStage0Idx1_uid22615_dupName_436_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_109_i_c_compmm_m3315_q;
            1'b1 : rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22615_dupName_436_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x(MUX,22621)@292
    assign rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22620_dupName_436_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22617_dupName_436_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22620_dupName_436_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3318_vt_select_21(BITSELECT,12095)@292
    assign i_unnamed_c_compmm_m3318_vt_select_21_b = rightShiftStage1_uid22622_dupName_436_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3318_vt_join(BITJOIN,12094)@292
    assign i_unnamed_c_compmm_m3318_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3318_vt_select_21_b};

    // i_unnamed_c_compmm_m3319_sel_x(BITSELECT,6174)@292
    assign i_unnamed_c_compmm_m3319_sel_x_b = i_unnamed_c_compmm_m3318_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3320_BitSelect_for_a(BITSELECT,28700)@292
    assign i_unnamed_c_compmm_m3320_BitSelect_for_a_b = i_unnamed_c_compmm_m3319_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3320_join(BITJOIN,28701)@292
    assign i_unnamed_c_compmm_m3320_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3320_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3320_vt_select_0(BITSELECT,12100)@292
    assign i_unnamed_c_compmm_m3320_vt_select_0_b = i_unnamed_c_compmm_m3320_join_q[0:0];

    // redist87_i_unnamed_c_compmm_m3320_vt_select_0_b_1(DELAY,29215)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist87_i_unnamed_c_compmm_m3320_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3320_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3320_vt_join(BITJOIN,12099)@293
    assign i_unnamed_c_compmm_m3320_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist87_i_unnamed_c_compmm_m3320_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_109_c_compmm_m3321(ADD,7041)@293
    assign i_add_i_i_i_i_i126_i_109_c_compmm_m3321_a = {1'b0, i_unnamed_c_compmm_m3320_vt_join_q};
    assign i_add_i_i_i_i_i126_i_109_c_compmm_m3321_b = {1'b0, redist1131_i_conv_i_i_i_i97_i_109_c_compmm_m3317_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_109_c_compmm_m3321_o = $unsigned(i_add_i_i_i_i_i126_i_109_c_compmm_m3321_a) + $unsigned(i_add_i_i_i_i_i126_i_109_c_compmm_m3321_b);
    assign i_add_i_i_i_i_i126_i_109_c_compmm_m3321_q = i_add_i_i_i_i_i126_i_109_c_compmm_m3321_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_109_c_compmm_m3321_sel_x(BITSELECT,2055)@293
    assign bgTrunc_i_add_i_i_i_i_i126_i_109_c_compmm_m3321_sel_x_b = i_add_i_i_i_i_i126_i_109_c_compmm_m3321_q[15:0];

    // i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_sel_x(BITSELECT,3589)@293
    assign i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_109_c_compmm_m3321_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_select_15(BITSELECT,7467)@293
    assign i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_select_15_b = i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_join(BITJOIN,7466)@293
    assign i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_select_15_b};

    // leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(MUX,23974)@293
    assign leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_join_q or leftShiftStage0Idx1_uid23973_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_110_c_compmm_m3341_vt_join_q;
            1'b1 : leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23973_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(MUX,23979)@293
    assign leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s or leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23978_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = leftShiftStage0_uid23975_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23978_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x(MUX,23984)@293
    assign leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s or leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid23983_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = leftShiftStage1_uid23980_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid23983_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28(BITSELECT,9493)@293
    assign i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28_b = leftShiftStage2_uid23985_i_shl_i_i_i_i_i77_i_110_c_compmm_m0_shift_x_q[28:13];

    // redist491_i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28_b_1(DELAY,29619)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist491_i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_join(BITJOIN,9492)@294
    assign i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_join_q = {redist491_i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma(CHAINMULTADD,29011)@288 + 5
    // out q@294
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_29_c_compmm_m_fpgaunique_67240_c_compmm_m36_out_dest_data_out_222_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_28_c_compmm_m_fpgaunique_67239_c_compmm_m37_out_dest_data_out_221_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ch[0] <= redist724_sync_together4364_aunroll_x_in_c1_eni5_222_tpl_220_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ch[1] <= redist723_sync_together4364_aunroll_x_in_c1_eni5_221_tpl_220_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343(ADD,8831)@294
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_110_i_c_compmm_m3338_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_110_i_c_compmm_m3340_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_110_i_c_compmm_m3339_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_110_c_compmm_m3342_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_o[33:0];

    // rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x(MUX,22660)@294
    assign rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q or rightShiftStage0Idx1_uid22659_dupName_439_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q;
            1'b1 : rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22659_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x(MUX,22665)@294
    assign rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22664_dupName_439_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22661_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22664_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x(MUX,22670)@294
    assign rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22669_dupName_439_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22666_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22669_dupName_439_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3344_vt_select_20(BITSELECT,12117)@294
    assign i_unnamed_c_compmm_m3344_vt_select_20_b = rightShiftStage2_uid22671_dupName_439_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3344_vt_join(BITJOIN,12116)@294
    assign i_unnamed_c_compmm_m3344_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3344_vt_select_20_b};

    // i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x(BITSELECT,3460)@294
    assign i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x_b = i_unnamed_c_compmm_m3344_vt_join_q[15:0];

    // redist1129_i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x_b_1(DELAY,30257)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1129_i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22680_dupName_440_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22679)@294
    assign rightShiftStage1Idx1Rng8_uid22680_dupName_440_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22682_dupName_440_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22681)@294
    assign rightShiftStage1Idx1_uid22682_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22680_dupName_440_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22675_dupName_440_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22674)@294
    assign rightShiftStage0Idx1Rng4_uid22675_dupName_440_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q[33:4];

    // rightShiftStage0Idx1_uid22677_dupName_440_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22676)@294
    assign rightShiftStage0Idx1_uid22677_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22675_dupName_440_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x(MUX,22678)@294
    assign rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q or rightShiftStage0Idx1_uid22677_dupName_440_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_110_i_c_compmm_m3343_q;
            1'b1 : rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22677_dupName_440_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x(MUX,22683)@294
    assign rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22682_dupName_440_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22679_dupName_440_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22682_dupName_440_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3346_vt_select_21(BITSELECT,12120)@294
    assign i_unnamed_c_compmm_m3346_vt_select_21_b = rightShiftStage1_uid22684_dupName_440_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3346_vt_join(BITJOIN,12119)@294
    assign i_unnamed_c_compmm_m3346_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3346_vt_select_21_b};

    // i_unnamed_c_compmm_m3347_sel_x(BITSELECT,6176)@294
    assign i_unnamed_c_compmm_m3347_sel_x_b = i_unnamed_c_compmm_m3346_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3348_BitSelect_for_a(BITSELECT,28704)@294
    assign i_unnamed_c_compmm_m3348_BitSelect_for_a_b = i_unnamed_c_compmm_m3347_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3348_join(BITJOIN,28705)@294
    assign i_unnamed_c_compmm_m3348_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3348_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3348_vt_select_0(BITSELECT,12125)@294
    assign i_unnamed_c_compmm_m3348_vt_select_0_b = i_unnamed_c_compmm_m3348_join_q[0:0];

    // redist85_i_unnamed_c_compmm_m3348_vt_select_0_b_1(DELAY,29213)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist85_i_unnamed_c_compmm_m3348_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3348_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3348_vt_join(BITJOIN,12124)@295
    assign i_unnamed_c_compmm_m3348_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist85_i_unnamed_c_compmm_m3348_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_110_c_compmm_m3349(ADD,7043)@295
    assign i_add_i_i_i_i_i126_i_110_c_compmm_m3349_a = {1'b0, i_unnamed_c_compmm_m3348_vt_join_q};
    assign i_add_i_i_i_i_i126_i_110_c_compmm_m3349_b = {1'b0, redist1129_i_conv_i_i_i_i97_i_110_c_compmm_m3345_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_110_c_compmm_m3349_o = $unsigned(i_add_i_i_i_i_i126_i_110_c_compmm_m3349_a) + $unsigned(i_add_i_i_i_i_i126_i_110_c_compmm_m3349_b);
    assign i_add_i_i_i_i_i126_i_110_c_compmm_m3349_q = i_add_i_i_i_i_i126_i_110_c_compmm_m3349_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_110_c_compmm_m3349_sel_x(BITSELECT,2057)@295
    assign bgTrunc_i_add_i_i_i_i_i126_i_110_c_compmm_m3349_sel_x_b = i_add_i_i_i_i_i126_i_110_c_compmm_m3349_q[15:0];

    // i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_sel_x(BITSELECT,3590)@295
    assign i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_110_c_compmm_m3349_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_select_15(BITSELECT,7471)@295
    assign i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_select_15_b = i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_join(BITJOIN,7470)@295
    assign i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_select_15_b};

    // leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(MUX,23992)@295
    assign leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_join_q or leftShiftStage0Idx1_uid23991_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_111_c_compmm_m3369_vt_join_q;
            1'b1 : leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid23991_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(MUX,23997)@295
    assign leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s or leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid23996_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = leftShiftStage0_uid23993_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid23996_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x(MUX,24002)@295
    assign leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s or leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24001_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = leftShiftStage1_uid23998_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24001_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28(BITSELECT,9496)@295
    assign i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28_b = leftShiftStage2_uid24003_i_shl_i_i_i_i_i77_i_111_c_compmm_m0_shift_x_q[28:13];

    // redist490_i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28_b_1(DELAY,29618)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist490_i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_join(BITJOIN,9495)@296
    assign i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_join_q = {redist490_i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma(CHAINMULTADD,29012)@290 + 5
    // out q@296
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_31_c_compmm_m_fpgaunique_67242_c_compmm_m34_out_dest_data_out_224_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_30_c_compmm_m_fpgaunique_67241_c_compmm_m35_out_dest_data_out_223_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ch[0] <= redist726_sync_together4364_aunroll_x_in_c1_eni5_224_tpl_222_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ch[1] <= redist725_sync_together4364_aunroll_x_in_c1_eni5_223_tpl_222_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371(ADD,8832)@296
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_111_i_c_compmm_m3366_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_111_i_c_compmm_m3368_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_111_i_c_compmm_m3367_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_111_c_compmm_m3370_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_o[33:0];

    // rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x(MUX,22722)@296
    assign rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q or rightShiftStage0Idx1_uid22721_dupName_443_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q;
            1'b1 : rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22721_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x(MUX,22727)@296
    assign rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22726_dupName_443_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22723_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22726_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x(MUX,22732)@296
    assign rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22731_dupName_443_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22728_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22731_dupName_443_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3372_vt_select_20(BITSELECT,12144)@296
    assign i_unnamed_c_compmm_m3372_vt_select_20_b = rightShiftStage2_uid22733_dupName_443_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3372_vt_join(BITJOIN,12143)@296
    assign i_unnamed_c_compmm_m3372_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3372_vt_select_20_b};

    // i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x(BITSELECT,3461)@296
    assign i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x_b = i_unnamed_c_compmm_m3372_vt_join_q[15:0];

    // redist1128_i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x_b_1(DELAY,30256)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1128_i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22742_dupName_444_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22741)@296
    assign rightShiftStage1Idx1Rng8_uid22742_dupName_444_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22744_dupName_444_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22743)@296
    assign rightShiftStage1Idx1_uid22744_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22742_dupName_444_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22737_dupName_444_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22736)@296
    assign rightShiftStage0Idx1Rng4_uid22737_dupName_444_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q[33:4];

    // rightShiftStage0Idx1_uid22739_dupName_444_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22738)@296
    assign rightShiftStage0Idx1_uid22739_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22737_dupName_444_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x(MUX,22740)@296
    assign rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q or rightShiftStage0Idx1_uid22739_dupName_444_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_111_i_c_compmm_m3371_q;
            1'b1 : rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22739_dupName_444_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x(MUX,22745)@296
    assign rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22744_dupName_444_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22741_dupName_444_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22744_dupName_444_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3374_vt_select_21(BITSELECT,12147)@296
    assign i_unnamed_c_compmm_m3374_vt_select_21_b = rightShiftStage1_uid22746_dupName_444_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3374_vt_join(BITJOIN,12146)@296
    assign i_unnamed_c_compmm_m3374_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3374_vt_select_21_b};

    // i_unnamed_c_compmm_m3375_sel_x(BITSELECT,6179)@296
    assign i_unnamed_c_compmm_m3375_sel_x_b = i_unnamed_c_compmm_m3374_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3376_BitSelect_for_a(BITSELECT,28710)@296
    assign i_unnamed_c_compmm_m3376_BitSelect_for_a_b = i_unnamed_c_compmm_m3375_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3376_join(BITJOIN,28711)@296
    assign i_unnamed_c_compmm_m3376_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3376_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3376_vt_select_0(BITSELECT,12152)@296
    assign i_unnamed_c_compmm_m3376_vt_select_0_b = i_unnamed_c_compmm_m3376_join_q[0:0];

    // redist83_i_unnamed_c_compmm_m3376_vt_select_0_b_1(DELAY,29211)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist83_i_unnamed_c_compmm_m3376_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3376_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3376_vt_join(BITJOIN,12151)@297
    assign i_unnamed_c_compmm_m3376_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist83_i_unnamed_c_compmm_m3376_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_111_c_compmm_m3377(ADD,7044)@297
    assign i_add_i_i_i_i_i126_i_111_c_compmm_m3377_a = {1'b0, i_unnamed_c_compmm_m3376_vt_join_q};
    assign i_add_i_i_i_i_i126_i_111_c_compmm_m3377_b = {1'b0, redist1128_i_conv_i_i_i_i97_i_111_c_compmm_m3373_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_111_c_compmm_m3377_o = $unsigned(i_add_i_i_i_i_i126_i_111_c_compmm_m3377_a) + $unsigned(i_add_i_i_i_i_i126_i_111_c_compmm_m3377_b);
    assign i_add_i_i_i_i_i126_i_111_c_compmm_m3377_q = i_add_i_i_i_i_i126_i_111_c_compmm_m3377_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_111_c_compmm_m3377_sel_x(BITSELECT,2058)@297
    assign bgTrunc_i_add_i_i_i_i_i126_i_111_c_compmm_m3377_sel_x_b = i_add_i_i_i_i_i126_i_111_c_compmm_m3377_q[15:0];

    // i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_sel_x(BITSELECT,3591)@297
    assign i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_111_c_compmm_m3377_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_select_15(BITSELECT,7475)@297
    assign i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_select_15_b = i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_join(BITJOIN,7474)@297
    assign i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_select_15_b};

    // leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(MUX,24010)@297
    assign leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_join_q or leftShiftStage0Idx1_uid24009_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_112_c_compmm_m3397_vt_join_q;
            1'b1 : leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24009_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(MUX,24015)@297
    assign leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s or leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24014_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = leftShiftStage0_uid24011_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24014_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x(MUX,24020)@297
    assign leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s or leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24019_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = leftShiftStage1_uid24016_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24019_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28(BITSELECT,9499)@297
    assign i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28_b = leftShiftStage2_uid24021_i_shl_i_i_i_i_i77_i_112_c_compmm_m0_shift_x_q[28:13];

    // redist489_i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28_b_1(DELAY,29617)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist489_i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_join(BITJOIN,9498)@298
    assign i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_join_q = {redist489_i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma(CHAINMULTADD,29013)@292 + 5
    // out q@298
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_33_c_compmm_m_fpgaunique_67244_c_compmm_m32_out_dest_data_out_226_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_32_c_compmm_m_fpgaunique_67243_c_compmm_m33_out_dest_data_out_225_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ch[0] <= redist728_sync_together4364_aunroll_x_in_c1_eni5_226_tpl_224_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ch[1] <= redist727_sync_together4364_aunroll_x_in_c1_eni5_225_tpl_224_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399(ADD,8833)@298
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_112_i_c_compmm_m3394_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_112_i_c_compmm_m3396_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_112_i_c_compmm_m3395_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_112_c_compmm_m3398_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_o[33:0];

    // rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x(MUX,22784)@298
    assign rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q or rightShiftStage0Idx1_uid22783_dupName_447_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q;
            1'b1 : rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22783_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x(MUX,22789)@298
    assign rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22788_dupName_447_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22785_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22788_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x(MUX,22794)@298
    assign rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22793_dupName_447_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22790_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22793_dupName_447_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3400_vt_select_20(BITSELECT,12169)@298
    assign i_unnamed_c_compmm_m3400_vt_select_20_b = rightShiftStage2_uid22795_dupName_447_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3400_vt_join(BITJOIN,12168)@298
    assign i_unnamed_c_compmm_m3400_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3400_vt_select_20_b};

    // i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x(BITSELECT,3462)@298
    assign i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x_b = i_unnamed_c_compmm_m3400_vt_join_q[15:0];

    // redist1127_i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x_b_1(DELAY,30255)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1127_i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22804_dupName_448_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22803)@298
    assign rightShiftStage1Idx1Rng8_uid22804_dupName_448_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22806_dupName_448_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22805)@298
    assign rightShiftStage1Idx1_uid22806_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22804_dupName_448_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22799_dupName_448_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22798)@298
    assign rightShiftStage0Idx1Rng4_uid22799_dupName_448_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q[33:4];

    // rightShiftStage0Idx1_uid22801_dupName_448_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22800)@298
    assign rightShiftStage0Idx1_uid22801_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22799_dupName_448_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x(MUX,22802)@298
    assign rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q or rightShiftStage0Idx1_uid22801_dupName_448_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_112_i_c_compmm_m3399_q;
            1'b1 : rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22801_dupName_448_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x(MUX,22807)@298
    assign rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22806_dupName_448_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22803_dupName_448_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22806_dupName_448_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3402_vt_select_21(BITSELECT,12172)@298
    assign i_unnamed_c_compmm_m3402_vt_select_21_b = rightShiftStage1_uid22808_dupName_448_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3402_vt_join(BITJOIN,12171)@298
    assign i_unnamed_c_compmm_m3402_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3402_vt_select_21_b};

    // i_unnamed_c_compmm_m3403_sel_x(BITSELECT,6181)@298
    assign i_unnamed_c_compmm_m3403_sel_x_b = i_unnamed_c_compmm_m3402_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3404_BitSelect_for_a(BITSELECT,28714)@298
    assign i_unnamed_c_compmm_m3404_BitSelect_for_a_b = i_unnamed_c_compmm_m3403_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3404_join(BITJOIN,28715)@298
    assign i_unnamed_c_compmm_m3404_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3404_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3404_vt_select_0(BITSELECT,12177)@298
    assign i_unnamed_c_compmm_m3404_vt_select_0_b = i_unnamed_c_compmm_m3404_join_q[0:0];

    // redist80_i_unnamed_c_compmm_m3404_vt_select_0_b_1(DELAY,29208)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist80_i_unnamed_c_compmm_m3404_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3404_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3404_vt_join(BITJOIN,12176)@299
    assign i_unnamed_c_compmm_m3404_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist80_i_unnamed_c_compmm_m3404_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_112_c_compmm_m3405(ADD,7045)@299
    assign i_add_i_i_i_i_i126_i_112_c_compmm_m3405_a = {1'b0, i_unnamed_c_compmm_m3404_vt_join_q};
    assign i_add_i_i_i_i_i126_i_112_c_compmm_m3405_b = {1'b0, redist1127_i_conv_i_i_i_i97_i_112_c_compmm_m3401_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_112_c_compmm_m3405_o = $unsigned(i_add_i_i_i_i_i126_i_112_c_compmm_m3405_a) + $unsigned(i_add_i_i_i_i_i126_i_112_c_compmm_m3405_b);
    assign i_add_i_i_i_i_i126_i_112_c_compmm_m3405_q = i_add_i_i_i_i_i126_i_112_c_compmm_m3405_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_112_c_compmm_m3405_sel_x(BITSELECT,2059)@299
    assign bgTrunc_i_add_i_i_i_i_i126_i_112_c_compmm_m3405_sel_x_b = i_add_i_i_i_i_i126_i_112_c_compmm_m3405_q[15:0];

    // i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_sel_x(BITSELECT,3592)@299
    assign i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_112_c_compmm_m3405_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_select_15(BITSELECT,7479)@299
    assign i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_select_15_b = i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_join(BITJOIN,7478)@299
    assign i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_select_15_b};

    // leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(MUX,24028)@299
    assign leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_join_q or leftShiftStage0Idx1_uid24027_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_113_c_compmm_m3425_vt_join_q;
            1'b1 : leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24027_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(MUX,24033)@299
    assign leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s or leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24032_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = leftShiftStage0_uid24029_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24032_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x(MUX,24038)@299
    assign leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s or leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24037_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = leftShiftStage1_uid24034_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24037_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28(BITSELECT,9502)@299
    assign i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28_b = leftShiftStage2_uid24039_i_shl_i_i_i_i_i77_i_113_c_compmm_m0_shift_x_q[28:13];

    // redist488_i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28_b_1(DELAY,29616)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist488_i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_join(BITJOIN,9501)@300
    assign i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_join_q = {redist488_i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma(CHAINMULTADD,29014)@294 + 5
    // out q@300
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_35_c_compmm_m_fpgaunique_67246_c_compmm_m30_out_dest_data_out_228_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_34_c_compmm_m_fpgaunique_67245_c_compmm_m31_out_dest_data_out_227_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ch[0] <= redist730_sync_together4364_aunroll_x_in_c1_eni5_228_tpl_226_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ch[1] <= redist729_sync_together4364_aunroll_x_in_c1_eni5_227_tpl_226_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427(ADD,8834)@300
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_113_i_c_compmm_m3422_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_113_i_c_compmm_m3424_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_113_i_c_compmm_m3423_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_113_c_compmm_m3426_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_o[33:0];

    // rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x(MUX,22846)@300
    assign rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q or rightShiftStage0Idx1_uid22845_dupName_451_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q;
            1'b1 : rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22845_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x(MUX,22851)@300
    assign rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22850_dupName_451_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22847_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22850_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x(MUX,22856)@300
    assign rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22855_dupName_451_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22852_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22855_dupName_451_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3428_vt_select_20(BITSELECT,12191)@300
    assign i_unnamed_c_compmm_m3428_vt_select_20_b = rightShiftStage2_uid22857_dupName_451_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3428_vt_join(BITJOIN,12190)@300
    assign i_unnamed_c_compmm_m3428_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3428_vt_select_20_b};

    // i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x(BITSELECT,3463)@300
    assign i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x_b = i_unnamed_c_compmm_m3428_vt_join_q[15:0];

    // redist1126_i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x_b_1(DELAY,30254)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1126_i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22866_dupName_452_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22865)@300
    assign rightShiftStage1Idx1Rng8_uid22866_dupName_452_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22868_dupName_452_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22867)@300
    assign rightShiftStage1Idx1_uid22868_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22866_dupName_452_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22861_dupName_452_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22860)@300
    assign rightShiftStage0Idx1Rng4_uid22861_dupName_452_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q[33:4];

    // rightShiftStage0Idx1_uid22863_dupName_452_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22862)@300
    assign rightShiftStage0Idx1_uid22863_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22861_dupName_452_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x(MUX,22864)@300
    assign rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q or rightShiftStage0Idx1_uid22863_dupName_452_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_113_i_c_compmm_m3427_q;
            1'b1 : rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22863_dupName_452_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x(MUX,22869)@300
    assign rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22868_dupName_452_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22865_dupName_452_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22868_dupName_452_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3430_vt_select_21(BITSELECT,12194)@300
    assign i_unnamed_c_compmm_m3430_vt_select_21_b = rightShiftStage1_uid22870_dupName_452_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3430_vt_join(BITJOIN,12193)@300
    assign i_unnamed_c_compmm_m3430_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3430_vt_select_21_b};

    // i_unnamed_c_compmm_m3431_sel_x(BITSELECT,6183)@300
    assign i_unnamed_c_compmm_m3431_sel_x_b = i_unnamed_c_compmm_m3430_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3432_BitSelect_for_a(BITSELECT,28718)@300
    assign i_unnamed_c_compmm_m3432_BitSelect_for_a_b = i_unnamed_c_compmm_m3431_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3432_join(BITJOIN,28719)@300
    assign i_unnamed_c_compmm_m3432_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3432_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3432_vt_select_0(BITSELECT,12199)@300
    assign i_unnamed_c_compmm_m3432_vt_select_0_b = i_unnamed_c_compmm_m3432_join_q[0:0];

    // redist78_i_unnamed_c_compmm_m3432_vt_select_0_b_1(DELAY,29206)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist78_i_unnamed_c_compmm_m3432_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3432_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3432_vt_join(BITJOIN,12198)@301
    assign i_unnamed_c_compmm_m3432_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist78_i_unnamed_c_compmm_m3432_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_113_c_compmm_m3433(ADD,7046)@301
    assign i_add_i_i_i_i_i126_i_113_c_compmm_m3433_a = {1'b0, i_unnamed_c_compmm_m3432_vt_join_q};
    assign i_add_i_i_i_i_i126_i_113_c_compmm_m3433_b = {1'b0, redist1126_i_conv_i_i_i_i97_i_113_c_compmm_m3429_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_113_c_compmm_m3433_o = $unsigned(i_add_i_i_i_i_i126_i_113_c_compmm_m3433_a) + $unsigned(i_add_i_i_i_i_i126_i_113_c_compmm_m3433_b);
    assign i_add_i_i_i_i_i126_i_113_c_compmm_m3433_q = i_add_i_i_i_i_i126_i_113_c_compmm_m3433_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_113_c_compmm_m3433_sel_x(BITSELECT,2060)@301
    assign bgTrunc_i_add_i_i_i_i_i126_i_113_c_compmm_m3433_sel_x_b = i_add_i_i_i_i_i126_i_113_c_compmm_m3433_q[15:0];

    // i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_sel_x(BITSELECT,3593)@301
    assign i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_113_c_compmm_m3433_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_select_15(BITSELECT,7483)@301
    assign i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_select_15_b = i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_join(BITJOIN,7482)@301
    assign i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_select_15_b};

    // leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(MUX,24046)@301
    assign leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_join_q or leftShiftStage0Idx1_uid24045_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_114_c_compmm_m3453_vt_join_q;
            1'b1 : leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24045_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(MUX,24051)@301
    assign leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s or leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24050_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = leftShiftStage0_uid24047_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24050_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x(MUX,24056)@301
    assign leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s or leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24055_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = leftShiftStage1_uid24052_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24055_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28(BITSELECT,9505)@301
    assign i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28_b = leftShiftStage2_uid24057_i_shl_i_i_i_i_i77_i_114_c_compmm_m0_shift_x_q[28:13];

    // redist487_i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28_b_1(DELAY,29615)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist487_i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_join(BITJOIN,9504)@302
    assign i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_join_q = {redist487_i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma(CHAINMULTADD,29015)@296 + 5
    // out q@302
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_37_c_compmm_m_fpgaunique_67248_c_compmm_m28_out_dest_data_out_230_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_36_c_compmm_m_fpgaunique_67247_c_compmm_m29_out_dest_data_out_229_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ch[0] <= redist732_sync_together4364_aunroll_x_in_c1_eni5_230_tpl_228_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ch[1] <= redist731_sync_together4364_aunroll_x_in_c1_eni5_229_tpl_228_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455(ADD,8835)@302
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_114_i_c_compmm_m3450_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_114_i_c_compmm_m3452_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_114_i_c_compmm_m3451_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_114_c_compmm_m3454_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_o[33:0];

    // rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x(MUX,22908)@302
    assign rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q or rightShiftStage0Idx1_uid22907_dupName_455_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q;
            1'b1 : rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22907_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x(MUX,22913)@302
    assign rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22912_dupName_455_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22909_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22912_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x(MUX,22918)@302
    assign rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22917_dupName_455_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22914_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22917_dupName_455_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3456_vt_select_20(BITSELECT,12213)@302
    assign i_unnamed_c_compmm_m3456_vt_select_20_b = rightShiftStage2_uid22919_dupName_455_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3456_vt_join(BITJOIN,12212)@302
    assign i_unnamed_c_compmm_m3456_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3456_vt_select_20_b};

    // i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x(BITSELECT,3464)@302
    assign i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x_b = i_unnamed_c_compmm_m3456_vt_join_q[15:0];

    // redist1125_i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x_b_1(DELAY,30253)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1125_i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22928_dupName_456_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22927)@302
    assign rightShiftStage1Idx1Rng8_uid22928_dupName_456_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22930_dupName_456_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22929)@302
    assign rightShiftStage1Idx1_uid22930_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22928_dupName_456_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22923_dupName_456_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22922)@302
    assign rightShiftStage0Idx1Rng4_uid22923_dupName_456_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q[33:4];

    // rightShiftStage0Idx1_uid22925_dupName_456_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22924)@302
    assign rightShiftStage0Idx1_uid22925_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22923_dupName_456_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x(MUX,22926)@302
    assign rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q or rightShiftStage0Idx1_uid22925_dupName_456_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_114_i_c_compmm_m3455_q;
            1'b1 : rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22925_dupName_456_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x(MUX,22931)@302
    assign rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22930_dupName_456_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22927_dupName_456_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22930_dupName_456_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3458_vt_select_21(BITSELECT,12216)@302
    assign i_unnamed_c_compmm_m3458_vt_select_21_b = rightShiftStage1_uid22932_dupName_456_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3458_vt_join(BITJOIN,12215)@302
    assign i_unnamed_c_compmm_m3458_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3458_vt_select_21_b};

    // i_unnamed_c_compmm_m3459_sel_x(BITSELECT,6185)@302
    assign i_unnamed_c_compmm_m3459_sel_x_b = i_unnamed_c_compmm_m3458_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3460_BitSelect_for_a(BITSELECT,28722)@302
    assign i_unnamed_c_compmm_m3460_BitSelect_for_a_b = i_unnamed_c_compmm_m3459_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3460_join(BITJOIN,28723)@302
    assign i_unnamed_c_compmm_m3460_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3460_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3460_vt_select_0(BITSELECT,12224)@302
    assign i_unnamed_c_compmm_m3460_vt_select_0_b = i_unnamed_c_compmm_m3460_join_q[0:0];

    // redist76_i_unnamed_c_compmm_m3460_vt_select_0_b_1(DELAY,29204)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist76_i_unnamed_c_compmm_m3460_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3460_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3460_vt_join(BITJOIN,12223)@303
    assign i_unnamed_c_compmm_m3460_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist76_i_unnamed_c_compmm_m3460_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_114_c_compmm_m3461(ADD,7047)@303
    assign i_add_i_i_i_i_i126_i_114_c_compmm_m3461_a = {1'b0, i_unnamed_c_compmm_m3460_vt_join_q};
    assign i_add_i_i_i_i_i126_i_114_c_compmm_m3461_b = {1'b0, redist1125_i_conv_i_i_i_i97_i_114_c_compmm_m3457_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_114_c_compmm_m3461_o = $unsigned(i_add_i_i_i_i_i126_i_114_c_compmm_m3461_a) + $unsigned(i_add_i_i_i_i_i126_i_114_c_compmm_m3461_b);
    assign i_add_i_i_i_i_i126_i_114_c_compmm_m3461_q = i_add_i_i_i_i_i126_i_114_c_compmm_m3461_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_114_c_compmm_m3461_sel_x(BITSELECT,2061)@303
    assign bgTrunc_i_add_i_i_i_i_i126_i_114_c_compmm_m3461_sel_x_b = i_add_i_i_i_i_i126_i_114_c_compmm_m3461_q[15:0];

    // i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_sel_x(BITSELECT,3594)@303
    assign i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_114_c_compmm_m3461_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_select_15(BITSELECT,7487)@303
    assign i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_select_15_b = i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_join(BITJOIN,7486)@303
    assign i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_select_15_b};

    // leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(MUX,24064)@303
    assign leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_join_q or leftShiftStage0Idx1_uid24063_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_115_c_compmm_m3481_vt_join_q;
            1'b1 : leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24063_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(MUX,24069)@303
    assign leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s or leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24068_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = leftShiftStage0_uid24065_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24068_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x(MUX,24074)@303
    assign leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s or leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24073_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = leftShiftStage1_uid24070_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24073_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28(BITSELECT,9508)@303
    assign i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28_b = leftShiftStage2_uid24075_i_shl_i_i_i_i_i77_i_115_c_compmm_m0_shift_x_q[28:13];

    // redist486_i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28_b_1(DELAY,29614)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist486_i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_join(BITJOIN,9507)@304
    assign i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_join_q = {redist486_i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma(CHAINMULTADD,29016)@298 + 5
    // out q@304
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_39_c_compmm_m_fpgaunique_67250_c_compmm_m26_out_dest_data_out_232_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_38_c_compmm_m_fpgaunique_67249_c_compmm_m27_out_dest_data_out_231_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ch[0] <= redist734_sync_together4364_aunroll_x_in_c1_eni5_232_tpl_230_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ch[1] <= redist733_sync_together4364_aunroll_x_in_c1_eni5_231_tpl_230_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483(ADD,8836)@304
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_115_i_c_compmm_m3478_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_115_i_c_compmm_m3480_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_115_i_c_compmm_m3479_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_115_c_compmm_m3482_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_o[33:0];

    // rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x(MUX,22970)@304
    assign rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q or rightShiftStage0Idx1_uid22969_dupName_459_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q;
            1'b1 : rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22969_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x(MUX,22975)@304
    assign rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22974_dupName_459_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22971_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22974_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x(MUX,22980)@304
    assign rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid22979_dupName_459_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid22976_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid22979_dupName_459_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3484_vt_select_20(BITSELECT,12241)@304
    assign i_unnamed_c_compmm_m3484_vt_select_20_b = rightShiftStage2_uid22981_dupName_459_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3484_vt_join(BITJOIN,12240)@304
    assign i_unnamed_c_compmm_m3484_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3484_vt_select_20_b};

    // i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x(BITSELECT,3465)@304
    assign i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x_b = i_unnamed_c_compmm_m3484_vt_join_q[15:0];

    // redist1124_i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x_b_1(DELAY,30252)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1124_i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid22990_dupName_460_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22989)@304
    assign rightShiftStage1Idx1Rng8_uid22990_dupName_460_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid22992_dupName_460_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22991)@304
    assign rightShiftStage1Idx1_uid22992_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid22990_dupName_460_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid22985_dupName_460_i_unnamed_c_compmm_m0_shift_x(BITSELECT,22984)@304
    assign rightShiftStage0Idx1Rng4_uid22985_dupName_460_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q[33:4];

    // rightShiftStage0Idx1_uid22987_dupName_460_i_unnamed_c_compmm_m0_shift_x(BITJOIN,22986)@304
    assign rightShiftStage0Idx1_uid22987_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid22985_dupName_460_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x(MUX,22988)@304
    assign rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q or rightShiftStage0Idx1_uid22987_dupName_460_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_115_i_c_compmm_m3483_q;
            1'b1 : rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid22987_dupName_460_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x(MUX,22993)@304
    assign rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid22992_dupName_460_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid22989_dupName_460_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid22992_dupName_460_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3486_vt_select_21(BITSELECT,12244)@304
    assign i_unnamed_c_compmm_m3486_vt_select_21_b = rightShiftStage1_uid22994_dupName_460_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3486_vt_join(BITJOIN,12243)@304
    assign i_unnamed_c_compmm_m3486_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3486_vt_select_21_b};

    // i_unnamed_c_compmm_m3487_sel_x(BITSELECT,6188)@304
    assign i_unnamed_c_compmm_m3487_sel_x_b = i_unnamed_c_compmm_m3486_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3488_BitSelect_for_a(BITSELECT,28726)@304
    assign i_unnamed_c_compmm_m3488_BitSelect_for_a_b = i_unnamed_c_compmm_m3487_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3488_join(BITJOIN,28727)@304
    assign i_unnamed_c_compmm_m3488_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3488_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3488_vt_select_0(BITSELECT,12249)@304
    assign i_unnamed_c_compmm_m3488_vt_select_0_b = i_unnamed_c_compmm_m3488_join_q[0:0];

    // redist74_i_unnamed_c_compmm_m3488_vt_select_0_b_1(DELAY,29202)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist74_i_unnamed_c_compmm_m3488_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3488_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3488_vt_join(BITJOIN,12248)@305
    assign i_unnamed_c_compmm_m3488_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist74_i_unnamed_c_compmm_m3488_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_115_c_compmm_m3489(ADD,7048)@305
    assign i_add_i_i_i_i_i126_i_115_c_compmm_m3489_a = {1'b0, i_unnamed_c_compmm_m3488_vt_join_q};
    assign i_add_i_i_i_i_i126_i_115_c_compmm_m3489_b = {1'b0, redist1124_i_conv_i_i_i_i97_i_115_c_compmm_m3485_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_115_c_compmm_m3489_o = $unsigned(i_add_i_i_i_i_i126_i_115_c_compmm_m3489_a) + $unsigned(i_add_i_i_i_i_i126_i_115_c_compmm_m3489_b);
    assign i_add_i_i_i_i_i126_i_115_c_compmm_m3489_q = i_add_i_i_i_i_i126_i_115_c_compmm_m3489_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_115_c_compmm_m3489_sel_x(BITSELECT,2062)@305
    assign bgTrunc_i_add_i_i_i_i_i126_i_115_c_compmm_m3489_sel_x_b = i_add_i_i_i_i_i126_i_115_c_compmm_m3489_q[15:0];

    // i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_sel_x(BITSELECT,3595)@305
    assign i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_115_c_compmm_m3489_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_select_15(BITSELECT,7491)@305
    assign i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_select_15_b = i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_join(BITJOIN,7490)@305
    assign i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_select_15_b};

    // leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(MUX,24082)@305
    assign leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_join_q or leftShiftStage0Idx1_uid24081_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_116_c_compmm_m3509_vt_join_q;
            1'b1 : leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24081_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(MUX,24087)@305
    assign leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s or leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24086_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = leftShiftStage0_uid24083_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24086_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x(MUX,24092)@305
    assign leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s or leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24091_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = leftShiftStage1_uid24088_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24091_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28(BITSELECT,9511)@305
    assign i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28_b = leftShiftStage2_uid24093_i_shl_i_i_i_i_i77_i_116_c_compmm_m0_shift_x_q[28:13];

    // redist485_i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28_b_1(DELAY,29613)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist485_i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_join(BITJOIN,9510)@306
    assign i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_join_q = {redist485_i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma(CHAINMULTADD,29017)@300 + 5
    // out q@306
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_41_c_compmm_m_fpgaunique_67252_c_compmm_m24_out_dest_data_out_234_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_40_c_compmm_m_fpgaunique_67251_c_compmm_m25_out_dest_data_out_233_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ch[0] <= redist736_sync_together4364_aunroll_x_in_c1_eni5_234_tpl_232_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ch[1] <= redist735_sync_together4364_aunroll_x_in_c1_eni5_233_tpl_232_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511(ADD,8837)@306
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_116_i_c_compmm_m3506_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_116_i_c_compmm_m3508_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_116_i_c_compmm_m3507_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_116_c_compmm_m3510_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_o[33:0];

    // rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x(MUX,23032)@306
    assign rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q or rightShiftStage0Idx1_uid23031_dupName_463_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q;
            1'b1 : rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23031_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x(MUX,23037)@306
    assign rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23036_dupName_463_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23033_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23036_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x(MUX,23042)@306
    assign rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23041_dupName_463_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23038_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23041_dupName_463_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3512_vt_select_20(BITSELECT,12268)@306
    assign i_unnamed_c_compmm_m3512_vt_select_20_b = rightShiftStage2_uid23043_dupName_463_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3512_vt_join(BITJOIN,12267)@306
    assign i_unnamed_c_compmm_m3512_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3512_vt_select_20_b};

    // i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x(BITSELECT,3466)@306
    assign i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x_b = i_unnamed_c_compmm_m3512_vt_join_q[15:0];

    // redist1123_i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x_b_1(DELAY,30251)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1123_i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23052_dupName_464_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23051)@306
    assign rightShiftStage1Idx1Rng8_uid23052_dupName_464_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23054_dupName_464_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23053)@306
    assign rightShiftStage1Idx1_uid23054_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23052_dupName_464_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23047_dupName_464_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23046)@306
    assign rightShiftStage0Idx1Rng4_uid23047_dupName_464_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q[33:4];

    // rightShiftStage0Idx1_uid23049_dupName_464_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23048)@306
    assign rightShiftStage0Idx1_uid23049_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23047_dupName_464_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x(MUX,23050)@306
    assign rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q or rightShiftStage0Idx1_uid23049_dupName_464_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_116_i_c_compmm_m3511_q;
            1'b1 : rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23049_dupName_464_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x(MUX,23055)@306
    assign rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23054_dupName_464_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23051_dupName_464_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23054_dupName_464_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3514_vt_select_21(BITSELECT,12271)@306
    assign i_unnamed_c_compmm_m3514_vt_select_21_b = rightShiftStage1_uid23056_dupName_464_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3514_vt_join(BITJOIN,12270)@306
    assign i_unnamed_c_compmm_m3514_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3514_vt_select_21_b};

    // i_unnamed_c_compmm_m3515_sel_x(BITSELECT,6190)@306
    assign i_unnamed_c_compmm_m3515_sel_x_b = i_unnamed_c_compmm_m3514_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3516_BitSelect_for_a(BITSELECT,28732)@306
    assign i_unnamed_c_compmm_m3516_BitSelect_for_a_b = i_unnamed_c_compmm_m3515_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3516_join(BITJOIN,28733)@306
    assign i_unnamed_c_compmm_m3516_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3516_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3516_vt_select_0(BITSELECT,12276)@306
    assign i_unnamed_c_compmm_m3516_vt_select_0_b = i_unnamed_c_compmm_m3516_join_q[0:0];

    // redist71_i_unnamed_c_compmm_m3516_vt_select_0_b_1(DELAY,29199)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist71_i_unnamed_c_compmm_m3516_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3516_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3516_vt_join(BITJOIN,12275)@307
    assign i_unnamed_c_compmm_m3516_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist71_i_unnamed_c_compmm_m3516_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_116_c_compmm_m3517(ADD,7049)@307
    assign i_add_i_i_i_i_i126_i_116_c_compmm_m3517_a = {1'b0, i_unnamed_c_compmm_m3516_vt_join_q};
    assign i_add_i_i_i_i_i126_i_116_c_compmm_m3517_b = {1'b0, redist1123_i_conv_i_i_i_i97_i_116_c_compmm_m3513_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_116_c_compmm_m3517_o = $unsigned(i_add_i_i_i_i_i126_i_116_c_compmm_m3517_a) + $unsigned(i_add_i_i_i_i_i126_i_116_c_compmm_m3517_b);
    assign i_add_i_i_i_i_i126_i_116_c_compmm_m3517_q = i_add_i_i_i_i_i126_i_116_c_compmm_m3517_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_116_c_compmm_m3517_sel_x(BITSELECT,2063)@307
    assign bgTrunc_i_add_i_i_i_i_i126_i_116_c_compmm_m3517_sel_x_b = i_add_i_i_i_i_i126_i_116_c_compmm_m3517_q[15:0];

    // i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_sel_x(BITSELECT,3596)@307
    assign i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_116_c_compmm_m3517_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_select_15(BITSELECT,7495)@307
    assign i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_select_15_b = i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_join(BITJOIN,7494)@307
    assign i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_select_15_b};

    // leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(MUX,24100)@307
    assign leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_join_q or leftShiftStage0Idx1_uid24099_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_117_c_compmm_m3537_vt_join_q;
            1'b1 : leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24099_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(MUX,24105)@307
    assign leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s or leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24104_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = leftShiftStage0_uid24101_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24104_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x(MUX,24110)@307
    assign leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s or leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24109_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = leftShiftStage1_uid24106_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24109_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28(BITSELECT,9514)@307
    assign i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28_b = leftShiftStage2_uid24111_i_shl_i_i_i_i_i77_i_117_c_compmm_m0_shift_x_q[28:13];

    // redist484_i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28_b_1(DELAY,29612)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist484_i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_join(BITJOIN,9513)@308
    assign i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_join_q = {redist484_i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma(CHAINMULTADD,29018)@302 + 5
    // out q@308
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_43_c_compmm_m_fpgaunique_67254_c_compmm_m22_out_dest_data_out_236_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_42_c_compmm_m_fpgaunique_67253_c_compmm_m23_out_dest_data_out_235_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ch[0] <= redist738_sync_together4364_aunroll_x_in_c1_eni5_236_tpl_234_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ch[1] <= redist737_sync_together4364_aunroll_x_in_c1_eni5_235_tpl_234_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539(ADD,8838)@308
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_117_i_c_compmm_m3534_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_117_i_c_compmm_m3536_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_117_i_c_compmm_m3535_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_117_c_compmm_m3538_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_o[33:0];

    // rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x(MUX,23094)@308
    assign rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q or rightShiftStage0Idx1_uid23093_dupName_467_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q;
            1'b1 : rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23093_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x(MUX,23099)@308
    assign rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23098_dupName_467_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23095_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23098_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x(MUX,23104)@308
    assign rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23103_dupName_467_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23100_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23103_dupName_467_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3540_vt_select_20(BITSELECT,12290)@308
    assign i_unnamed_c_compmm_m3540_vt_select_20_b = rightShiftStage2_uid23105_dupName_467_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3540_vt_join(BITJOIN,12289)@308
    assign i_unnamed_c_compmm_m3540_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3540_vt_select_20_b};

    // i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x(BITSELECT,3467)@308
    assign i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x_b = i_unnamed_c_compmm_m3540_vt_join_q[15:0];

    // redist1122_i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x_b_1(DELAY,30250)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1122_i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23114_dupName_468_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23113)@308
    assign rightShiftStage1Idx1Rng8_uid23114_dupName_468_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23116_dupName_468_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23115)@308
    assign rightShiftStage1Idx1_uid23116_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23114_dupName_468_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23109_dupName_468_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23108)@308
    assign rightShiftStage0Idx1Rng4_uid23109_dupName_468_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q[33:4];

    // rightShiftStage0Idx1_uid23111_dupName_468_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23110)@308
    assign rightShiftStage0Idx1_uid23111_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23109_dupName_468_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x(MUX,23112)@308
    assign rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q or rightShiftStage0Idx1_uid23111_dupName_468_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_117_i_c_compmm_m3539_q;
            1'b1 : rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23111_dupName_468_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x(MUX,23117)@308
    assign rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23116_dupName_468_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23113_dupName_468_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23116_dupName_468_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3542_vt_select_21(BITSELECT,12293)@308
    assign i_unnamed_c_compmm_m3542_vt_select_21_b = rightShiftStage1_uid23118_dupName_468_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3542_vt_join(BITJOIN,12292)@308
    assign i_unnamed_c_compmm_m3542_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3542_vt_select_21_b};

    // i_unnamed_c_compmm_m3543_sel_x(BITSELECT,6192)@308
    assign i_unnamed_c_compmm_m3543_sel_x_b = i_unnamed_c_compmm_m3542_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3544_BitSelect_for_a(BITSELECT,28736)@308
    assign i_unnamed_c_compmm_m3544_BitSelect_for_a_b = i_unnamed_c_compmm_m3543_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3544_join(BITJOIN,28737)@308
    assign i_unnamed_c_compmm_m3544_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3544_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3544_vt_select_0(BITSELECT,12298)@308
    assign i_unnamed_c_compmm_m3544_vt_select_0_b = i_unnamed_c_compmm_m3544_join_q[0:0];

    // redist69_i_unnamed_c_compmm_m3544_vt_select_0_b_1(DELAY,29197)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist69_i_unnamed_c_compmm_m3544_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3544_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3544_vt_join(BITJOIN,12297)@309
    assign i_unnamed_c_compmm_m3544_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist69_i_unnamed_c_compmm_m3544_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_117_c_compmm_m3545(ADD,7050)@309
    assign i_add_i_i_i_i_i126_i_117_c_compmm_m3545_a = {1'b0, i_unnamed_c_compmm_m3544_vt_join_q};
    assign i_add_i_i_i_i_i126_i_117_c_compmm_m3545_b = {1'b0, redist1122_i_conv_i_i_i_i97_i_117_c_compmm_m3541_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_117_c_compmm_m3545_o = $unsigned(i_add_i_i_i_i_i126_i_117_c_compmm_m3545_a) + $unsigned(i_add_i_i_i_i_i126_i_117_c_compmm_m3545_b);
    assign i_add_i_i_i_i_i126_i_117_c_compmm_m3545_q = i_add_i_i_i_i_i126_i_117_c_compmm_m3545_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_117_c_compmm_m3545_sel_x(BITSELECT,2064)@309
    assign bgTrunc_i_add_i_i_i_i_i126_i_117_c_compmm_m3545_sel_x_b = i_add_i_i_i_i_i126_i_117_c_compmm_m3545_q[15:0];

    // i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_sel_x(BITSELECT,3597)@309
    assign i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_117_c_compmm_m3545_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_select_15(BITSELECT,7499)@309
    assign i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_select_15_b = i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_join(BITJOIN,7498)@309
    assign i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_select_15_b};

    // leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(MUX,24118)@309
    assign leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_join_q or leftShiftStage0Idx1_uid24117_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_118_c_compmm_m3565_vt_join_q;
            1'b1 : leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24117_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(MUX,24123)@309
    assign leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s or leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24122_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = leftShiftStage0_uid24119_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24122_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x(MUX,24128)@309
    assign leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s or leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24127_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = leftShiftStage1_uid24124_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24127_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28(BITSELECT,9517)@309
    assign i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28_b = leftShiftStage2_uid24129_i_shl_i_i_i_i_i77_i_118_c_compmm_m0_shift_x_q[28:13];

    // redist483_i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28_b_1(DELAY,29611)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist483_i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_join(BITJOIN,9516)@310
    assign i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_join_q = {redist483_i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma(CHAINMULTADD,29019)@304 + 5
    // out q@310
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_45_c_compmm_m_fpgaunique_67256_c_compmm_m20_out_dest_data_out_238_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_44_c_compmm_m_fpgaunique_67255_c_compmm_m21_out_dest_data_out_237_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ch[0] <= redist740_sync_together4364_aunroll_x_in_c1_eni5_238_tpl_236_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ch[1] <= redist739_sync_together4364_aunroll_x_in_c1_eni5_237_tpl_236_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567(ADD,8839)@310
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_118_i_c_compmm_m3562_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_118_i_c_compmm_m3564_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_118_i_c_compmm_m3563_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_118_c_compmm_m3566_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_o[33:0];

    // rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x(MUX,23156)@310
    assign rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q or rightShiftStage0Idx1_uid23155_dupName_471_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q;
            1'b1 : rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23155_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x(MUX,23161)@310
    assign rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23160_dupName_471_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23157_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23160_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x(MUX,23166)@310
    assign rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23165_dupName_471_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23162_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23165_dupName_471_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3568_vt_select_20(BITSELECT,12312)@310
    assign i_unnamed_c_compmm_m3568_vt_select_20_b = rightShiftStage2_uid23167_dupName_471_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3568_vt_join(BITJOIN,12311)@310
    assign i_unnamed_c_compmm_m3568_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3568_vt_select_20_b};

    // i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x(BITSELECT,3468)@310
    assign i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x_b = i_unnamed_c_compmm_m3568_vt_join_q[15:0];

    // redist1121_i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x_b_1(DELAY,30249)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1121_i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23176_dupName_472_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23175)@310
    assign rightShiftStage1Idx1Rng8_uid23176_dupName_472_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23178_dupName_472_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23177)@310
    assign rightShiftStage1Idx1_uid23178_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23176_dupName_472_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23171_dupName_472_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23170)@310
    assign rightShiftStage0Idx1Rng4_uid23171_dupName_472_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q[33:4];

    // rightShiftStage0Idx1_uid23173_dupName_472_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23172)@310
    assign rightShiftStage0Idx1_uid23173_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23171_dupName_472_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x(MUX,23174)@310
    assign rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q or rightShiftStage0Idx1_uid23173_dupName_472_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_118_i_c_compmm_m3567_q;
            1'b1 : rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23173_dupName_472_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x(MUX,23179)@310
    assign rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23178_dupName_472_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23175_dupName_472_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23178_dupName_472_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3570_vt_select_21(BITSELECT,12315)@310
    assign i_unnamed_c_compmm_m3570_vt_select_21_b = rightShiftStage1_uid23180_dupName_472_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3570_vt_join(BITJOIN,12314)@310
    assign i_unnamed_c_compmm_m3570_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3570_vt_select_21_b};

    // i_unnamed_c_compmm_m3571_sel_x(BITSELECT,6194)@310
    assign i_unnamed_c_compmm_m3571_sel_x_b = i_unnamed_c_compmm_m3570_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3572_BitSelect_for_a(BITSELECT,28740)@310
    assign i_unnamed_c_compmm_m3572_BitSelect_for_a_b = i_unnamed_c_compmm_m3571_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3572_join(BITJOIN,28741)@310
    assign i_unnamed_c_compmm_m3572_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3572_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3572_vt_select_0(BITSELECT,12320)@310
    assign i_unnamed_c_compmm_m3572_vt_select_0_b = i_unnamed_c_compmm_m3572_join_q[0:0];

    // redist67_i_unnamed_c_compmm_m3572_vt_select_0_b_1(DELAY,29195)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist67_i_unnamed_c_compmm_m3572_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3572_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3572_vt_join(BITJOIN,12319)@311
    assign i_unnamed_c_compmm_m3572_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist67_i_unnamed_c_compmm_m3572_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_118_c_compmm_m3573(ADD,7051)@311
    assign i_add_i_i_i_i_i126_i_118_c_compmm_m3573_a = {1'b0, i_unnamed_c_compmm_m3572_vt_join_q};
    assign i_add_i_i_i_i_i126_i_118_c_compmm_m3573_b = {1'b0, redist1121_i_conv_i_i_i_i97_i_118_c_compmm_m3569_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_118_c_compmm_m3573_o = $unsigned(i_add_i_i_i_i_i126_i_118_c_compmm_m3573_a) + $unsigned(i_add_i_i_i_i_i126_i_118_c_compmm_m3573_b);
    assign i_add_i_i_i_i_i126_i_118_c_compmm_m3573_q = i_add_i_i_i_i_i126_i_118_c_compmm_m3573_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_118_c_compmm_m3573_sel_x(BITSELECT,2065)@311
    assign bgTrunc_i_add_i_i_i_i_i126_i_118_c_compmm_m3573_sel_x_b = i_add_i_i_i_i_i126_i_118_c_compmm_m3573_q[15:0];

    // i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_sel_x(BITSELECT,3598)@311
    assign i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_118_c_compmm_m3573_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_select_15(BITSELECT,7503)@311
    assign i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_select_15_b = i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_join(BITJOIN,7502)@311
    assign i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_select_15_b};

    // leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(MUX,24136)@311
    assign leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_join_q or leftShiftStage0Idx1_uid24135_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_119_c_compmm_m3593_vt_join_q;
            1'b1 : leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24135_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(MUX,24141)@311
    assign leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s or leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24140_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = leftShiftStage0_uid24137_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24140_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x(MUX,24146)@311
    assign leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s or leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24145_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = leftShiftStage1_uid24142_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24145_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28(BITSELECT,9520)@311
    assign i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28_b = leftShiftStage2_uid24147_i_shl_i_i_i_i_i77_i_119_c_compmm_m0_shift_x_q[28:13];

    // redist482_i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28_b_1(DELAY,29610)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist482_i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_join(BITJOIN,9519)@312
    assign i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_join_q = {redist482_i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma(CHAINMULTADD,29020)@306 + 5
    // out q@312
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_47_c_compmm_m_fpgaunique_67258_c_compmm_m18_out_dest_data_out_240_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_46_c_compmm_m_fpgaunique_67257_c_compmm_m19_out_dest_data_out_239_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ch[0] <= redist742_sync_together4364_aunroll_x_in_c1_eni5_240_tpl_238_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ch[1] <= redist741_sync_together4364_aunroll_x_in_c1_eni5_239_tpl_238_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595(ADD,8840)@312
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_119_i_c_compmm_m3590_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_119_i_c_compmm_m3592_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_119_i_c_compmm_m3591_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_119_c_compmm_m3594_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_o[33:0];

    // rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x(MUX,23218)@312
    assign rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q or rightShiftStage0Idx1_uid23217_dupName_475_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q;
            1'b1 : rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23217_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x(MUX,23223)@312
    assign rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23222_dupName_475_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23219_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23222_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x(MUX,23228)@312
    assign rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23227_dupName_475_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23224_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23227_dupName_475_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3596_vt_select_20(BITSELECT,12334)@312
    assign i_unnamed_c_compmm_m3596_vt_select_20_b = rightShiftStage2_uid23229_dupName_475_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3596_vt_join(BITJOIN,12333)@312
    assign i_unnamed_c_compmm_m3596_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3596_vt_select_20_b};

    // i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x(BITSELECT,3469)@312
    assign i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x_b = i_unnamed_c_compmm_m3596_vt_join_q[15:0];

    // redist1120_i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x_b_1(DELAY,30248)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1120_i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23238_dupName_476_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23237)@312
    assign rightShiftStage1Idx1Rng8_uid23238_dupName_476_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23240_dupName_476_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23239)@312
    assign rightShiftStage1Idx1_uid23240_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23238_dupName_476_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23233_dupName_476_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23232)@312
    assign rightShiftStage0Idx1Rng4_uid23233_dupName_476_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q[33:4];

    // rightShiftStage0Idx1_uid23235_dupName_476_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23234)@312
    assign rightShiftStage0Idx1_uid23235_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23233_dupName_476_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x(MUX,23236)@312
    assign rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q or rightShiftStage0Idx1_uid23235_dupName_476_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_119_i_c_compmm_m3595_q;
            1'b1 : rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23235_dupName_476_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x(MUX,23241)@312
    assign rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23240_dupName_476_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23237_dupName_476_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23240_dupName_476_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3598_vt_select_21(BITSELECT,12337)@312
    assign i_unnamed_c_compmm_m3598_vt_select_21_b = rightShiftStage1_uid23242_dupName_476_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3598_vt_join(BITJOIN,12336)@312
    assign i_unnamed_c_compmm_m3598_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3598_vt_select_21_b};

    // i_unnamed_c_compmm_m3599_sel_x(BITSELECT,6196)@312
    assign i_unnamed_c_compmm_m3599_sel_x_b = i_unnamed_c_compmm_m3598_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3600_BitSelect_for_a(BITSELECT,28744)@312
    assign i_unnamed_c_compmm_m3600_BitSelect_for_a_b = i_unnamed_c_compmm_m3599_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3600_join(BITJOIN,28745)@312
    assign i_unnamed_c_compmm_m3600_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3600_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3600_vt_select_0(BITSELECT,12342)@312
    assign i_unnamed_c_compmm_m3600_vt_select_0_b = i_unnamed_c_compmm_m3600_join_q[0:0];

    // redist65_i_unnamed_c_compmm_m3600_vt_select_0_b_1(DELAY,29193)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist65_i_unnamed_c_compmm_m3600_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3600_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3600_vt_join(BITJOIN,12341)@313
    assign i_unnamed_c_compmm_m3600_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist65_i_unnamed_c_compmm_m3600_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_119_c_compmm_m3601(ADD,7052)@313
    assign i_add_i_i_i_i_i126_i_119_c_compmm_m3601_a = {1'b0, i_unnamed_c_compmm_m3600_vt_join_q};
    assign i_add_i_i_i_i_i126_i_119_c_compmm_m3601_b = {1'b0, redist1120_i_conv_i_i_i_i97_i_119_c_compmm_m3597_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_119_c_compmm_m3601_o = $unsigned(i_add_i_i_i_i_i126_i_119_c_compmm_m3601_a) + $unsigned(i_add_i_i_i_i_i126_i_119_c_compmm_m3601_b);
    assign i_add_i_i_i_i_i126_i_119_c_compmm_m3601_q = i_add_i_i_i_i_i126_i_119_c_compmm_m3601_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_119_c_compmm_m3601_sel_x(BITSELECT,2066)@313
    assign bgTrunc_i_add_i_i_i_i_i126_i_119_c_compmm_m3601_sel_x_b = i_add_i_i_i_i_i126_i_119_c_compmm_m3601_q[15:0];

    // i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_sel_x(BITSELECT,3600)@313
    assign i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_119_c_compmm_m3601_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_select_15(BITSELECT,7511)@313
    assign i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_select_15_b = i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_join(BITJOIN,7510)@313
    assign i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_select_15_b};

    // leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(MUX,24172)@313
    assign leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_join_q or leftShiftStage0Idx1_uid24171_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_120_c_compmm_m3621_vt_join_q;
            1'b1 : leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24171_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(MUX,24177)@313
    assign leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s or leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24176_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = leftShiftStage0_uid24173_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24176_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x(MUX,24182)@313
    assign leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s or leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24181_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = leftShiftStage1_uid24178_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24181_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28(BITSELECT,9526)@313
    assign i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28_b = leftShiftStage2_uid24183_i_shl_i_i_i_i_i77_i_120_c_compmm_m0_shift_x_q[28:13];

    // redist480_i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28_b_1(DELAY,29608)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist480_i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_join(BITJOIN,9525)@314
    assign i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_join_q = {redist480_i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma(CHAINMULTADD,29022)@308 + 5
    // out q@314
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_49_c_compmm_m_fpgaunique_67260_c_compmm_m16_out_dest_data_out_242_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_48_c_compmm_m_fpgaunique_67259_c_compmm_m17_out_dest_data_out_241_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ch[0] <= redist744_sync_together4364_aunroll_x_in_c1_eni5_242_tpl_240_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ch[1] <= redist743_sync_together4364_aunroll_x_in_c1_eni5_241_tpl_240_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623(ADD,8842)@314
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_120_i_c_compmm_m3618_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_120_i_c_compmm_m3620_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_120_i_c_compmm_m3619_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_120_c_compmm_m3622_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_o[33:0];

    // rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x(MUX,23280)@314
    assign rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q or rightShiftStage0Idx1_uid23279_dupName_479_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q;
            1'b1 : rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23279_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x(MUX,23285)@314
    assign rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23284_dupName_479_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23281_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23284_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x(MUX,23290)@314
    assign rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23289_dupName_479_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23286_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23289_dupName_479_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3624_vt_select_20(BITSELECT,12359)@314
    assign i_unnamed_c_compmm_m3624_vt_select_20_b = rightShiftStage2_uid23291_dupName_479_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3624_vt_join(BITJOIN,12358)@314
    assign i_unnamed_c_compmm_m3624_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3624_vt_select_20_b};

    // i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x(BITSELECT,3471)@314
    assign i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x_b = i_unnamed_c_compmm_m3624_vt_join_q[15:0];

    // redist1118_i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x_b_1(DELAY,30246)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1118_i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23300_dupName_480_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23299)@314
    assign rightShiftStage1Idx1Rng8_uid23300_dupName_480_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23302_dupName_480_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23301)@314
    assign rightShiftStage1Idx1_uid23302_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23300_dupName_480_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23295_dupName_480_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23294)@314
    assign rightShiftStage0Idx1Rng4_uid23295_dupName_480_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q[33:4];

    // rightShiftStage0Idx1_uid23297_dupName_480_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23296)@314
    assign rightShiftStage0Idx1_uid23297_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23295_dupName_480_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x(MUX,23298)@314
    assign rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q or rightShiftStage0Idx1_uid23297_dupName_480_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_120_i_c_compmm_m3623_q;
            1'b1 : rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23297_dupName_480_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x(MUX,23303)@314
    assign rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23302_dupName_480_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23299_dupName_480_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23302_dupName_480_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3626_vt_select_21(BITSELECT,12362)@314
    assign i_unnamed_c_compmm_m3626_vt_select_21_b = rightShiftStage1_uid23304_dupName_480_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3626_vt_join(BITJOIN,12361)@314
    assign i_unnamed_c_compmm_m3626_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3626_vt_select_21_b};

    // i_unnamed_c_compmm_m3627_sel_x(BITSELECT,6198)@314
    assign i_unnamed_c_compmm_m3627_sel_x_b = i_unnamed_c_compmm_m3626_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3628_BitSelect_for_a(BITSELECT,28748)@314
    assign i_unnamed_c_compmm_m3628_BitSelect_for_a_b = i_unnamed_c_compmm_m3627_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3628_join(BITJOIN,28749)@314
    assign i_unnamed_c_compmm_m3628_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3628_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3628_vt_select_0(BITSELECT,12367)@314
    assign i_unnamed_c_compmm_m3628_vt_select_0_b = i_unnamed_c_compmm_m3628_join_q[0:0];

    // redist63_i_unnamed_c_compmm_m3628_vt_select_0_b_1(DELAY,29191)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist63_i_unnamed_c_compmm_m3628_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3628_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3628_vt_join(BITJOIN,12366)@315
    assign i_unnamed_c_compmm_m3628_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist63_i_unnamed_c_compmm_m3628_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_120_c_compmm_m3629(ADD,7054)@315
    assign i_add_i_i_i_i_i126_i_120_c_compmm_m3629_a = {1'b0, i_unnamed_c_compmm_m3628_vt_join_q};
    assign i_add_i_i_i_i_i126_i_120_c_compmm_m3629_b = {1'b0, redist1118_i_conv_i_i_i_i97_i_120_c_compmm_m3625_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_120_c_compmm_m3629_o = $unsigned(i_add_i_i_i_i_i126_i_120_c_compmm_m3629_a) + $unsigned(i_add_i_i_i_i_i126_i_120_c_compmm_m3629_b);
    assign i_add_i_i_i_i_i126_i_120_c_compmm_m3629_q = i_add_i_i_i_i_i126_i_120_c_compmm_m3629_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_120_c_compmm_m3629_sel_x(BITSELECT,2068)@315
    assign bgTrunc_i_add_i_i_i_i_i126_i_120_c_compmm_m3629_sel_x_b = i_add_i_i_i_i_i126_i_120_c_compmm_m3629_q[15:0];

    // i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_sel_x(BITSELECT,3601)@315
    assign i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_120_c_compmm_m3629_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_select_15(BITSELECT,7515)@315
    assign i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_select_15_b = i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_join(BITJOIN,7514)@315
    assign i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_select_15_b};

    // leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(MUX,24190)@315
    assign leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_join_q or leftShiftStage0Idx1_uid24189_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_121_c_compmm_m3649_vt_join_q;
            1'b1 : leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24189_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(MUX,24195)@315
    assign leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s or leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24194_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = leftShiftStage0_uid24191_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24194_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x(MUX,24200)@315
    assign leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s or leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24199_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = leftShiftStage1_uid24196_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24199_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28(BITSELECT,9529)@315
    assign i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28_b = leftShiftStage2_uid24201_i_shl_i_i_i_i_i77_i_121_c_compmm_m0_shift_x_q[28:13];

    // redist479_i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28_b_1(DELAY,29607)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist479_i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_join(BITJOIN,9528)@316
    assign i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_join_q = {redist479_i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma(CHAINMULTADD,29023)@310 + 5
    // out q@316
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_51_c_compmm_m_fpgaunique_67262_c_compmm_m14_out_dest_data_out_244_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_50_c_compmm_m_fpgaunique_67261_c_compmm_m15_out_dest_data_out_243_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ch[0] <= redist746_sync_together4364_aunroll_x_in_c1_eni5_244_tpl_242_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ch[1] <= redist745_sync_together4364_aunroll_x_in_c1_eni5_243_tpl_242_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651(ADD,8843)@316
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_121_i_c_compmm_m3646_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_121_i_c_compmm_m3648_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_121_i_c_compmm_m3647_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_121_c_compmm_m3650_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_o[33:0];

    // rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x(MUX,23342)@316
    assign rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q or rightShiftStage0Idx1_uid23341_dupName_483_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q;
            1'b1 : rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23341_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x(MUX,23347)@316
    assign rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23346_dupName_483_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23343_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23346_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x(MUX,23352)@316
    assign rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23351_dupName_483_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23348_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23351_dupName_483_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3652_vt_select_20(BITSELECT,12386)@316
    assign i_unnamed_c_compmm_m3652_vt_select_20_b = rightShiftStage2_uid23353_dupName_483_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3652_vt_join(BITJOIN,12385)@316
    assign i_unnamed_c_compmm_m3652_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3652_vt_select_20_b};

    // i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x(BITSELECT,3472)@316
    assign i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x_b = i_unnamed_c_compmm_m3652_vt_join_q[15:0];

    // redist1117_i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x_b_1(DELAY,30245)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1117_i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23362_dupName_484_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23361)@316
    assign rightShiftStage1Idx1Rng8_uid23362_dupName_484_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23364_dupName_484_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23363)@316
    assign rightShiftStage1Idx1_uid23364_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23362_dupName_484_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23357_dupName_484_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23356)@316
    assign rightShiftStage0Idx1Rng4_uid23357_dupName_484_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q[33:4];

    // rightShiftStage0Idx1_uid23359_dupName_484_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23358)@316
    assign rightShiftStage0Idx1_uid23359_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23357_dupName_484_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x(MUX,23360)@316
    assign rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q or rightShiftStage0Idx1_uid23359_dupName_484_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_121_i_c_compmm_m3651_q;
            1'b1 : rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23359_dupName_484_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x(MUX,23365)@316
    assign rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23364_dupName_484_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23361_dupName_484_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23364_dupName_484_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3654_vt_select_21(BITSELECT,12389)@316
    assign i_unnamed_c_compmm_m3654_vt_select_21_b = rightShiftStage1_uid23366_dupName_484_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3654_vt_join(BITJOIN,12388)@316
    assign i_unnamed_c_compmm_m3654_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3654_vt_select_21_b};

    // i_unnamed_c_compmm_m3655_sel_x(BITSELECT,6201)@316
    assign i_unnamed_c_compmm_m3655_sel_x_b = i_unnamed_c_compmm_m3654_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3656_BitSelect_for_a(BITSELECT,28754)@316
    assign i_unnamed_c_compmm_m3656_BitSelect_for_a_b = i_unnamed_c_compmm_m3655_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3656_join(BITJOIN,28755)@316
    assign i_unnamed_c_compmm_m3656_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3656_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3656_vt_select_0(BITSELECT,12394)@316
    assign i_unnamed_c_compmm_m3656_vt_select_0_b = i_unnamed_c_compmm_m3656_join_q[0:0];

    // redist61_i_unnamed_c_compmm_m3656_vt_select_0_b_1(DELAY,29189)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist61_i_unnamed_c_compmm_m3656_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3656_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3656_vt_join(BITJOIN,12393)@317
    assign i_unnamed_c_compmm_m3656_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist61_i_unnamed_c_compmm_m3656_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_121_c_compmm_m3657(ADD,7055)@317
    assign i_add_i_i_i_i_i126_i_121_c_compmm_m3657_a = {1'b0, i_unnamed_c_compmm_m3656_vt_join_q};
    assign i_add_i_i_i_i_i126_i_121_c_compmm_m3657_b = {1'b0, redist1117_i_conv_i_i_i_i97_i_121_c_compmm_m3653_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_121_c_compmm_m3657_o = $unsigned(i_add_i_i_i_i_i126_i_121_c_compmm_m3657_a) + $unsigned(i_add_i_i_i_i_i126_i_121_c_compmm_m3657_b);
    assign i_add_i_i_i_i_i126_i_121_c_compmm_m3657_q = i_add_i_i_i_i_i126_i_121_c_compmm_m3657_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_121_c_compmm_m3657_sel_x(BITSELECT,2069)@317
    assign bgTrunc_i_add_i_i_i_i_i126_i_121_c_compmm_m3657_sel_x_b = i_add_i_i_i_i_i126_i_121_c_compmm_m3657_q[15:0];

    // i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_sel_x(BITSELECT,3602)@317
    assign i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_121_c_compmm_m3657_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_select_15(BITSELECT,7519)@317
    assign i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_select_15_b = i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_join(BITJOIN,7518)@317
    assign i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_select_15_b};

    // leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(MUX,24208)@317
    assign leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_join_q or leftShiftStage0Idx1_uid24207_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_122_c_compmm_m3677_vt_join_q;
            1'b1 : leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24207_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(MUX,24213)@317
    assign leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s or leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24212_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = leftShiftStage0_uid24209_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24212_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x(MUX,24218)@317
    assign leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s or leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24217_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = leftShiftStage1_uid24214_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24217_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28(BITSELECT,9532)@317
    assign i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28_b = leftShiftStage2_uid24219_i_shl_i_i_i_i_i77_i_122_c_compmm_m0_shift_x_q[28:13];

    // redist478_i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28_b_1(DELAY,29606)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist478_i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_join(BITJOIN,9531)@318
    assign i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_join_q = {redist478_i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma(CHAINMULTADD,29024)@312 + 5
    // out q@318
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_53_c_compmm_m_fpgaunique_67264_c_compmm_m12_out_dest_data_out_246_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_52_c_compmm_m_fpgaunique_67263_c_compmm_m13_out_dest_data_out_245_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ch[0] <= redist748_sync_together4364_aunroll_x_in_c1_eni5_246_tpl_244_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ch[1] <= redist747_sync_together4364_aunroll_x_in_c1_eni5_245_tpl_244_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679(ADD,8844)@318
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_122_i_c_compmm_m3674_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_122_i_c_compmm_m3676_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_122_i_c_compmm_m3675_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_122_c_compmm_m3678_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_o[33:0];

    // rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x(MUX,23404)@318
    assign rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q or rightShiftStage0Idx1_uid23403_dupName_487_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q;
            1'b1 : rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23403_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x(MUX,23409)@318
    assign rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23408_dupName_487_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23405_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23408_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x(MUX,23414)@318
    assign rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23413_dupName_487_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23410_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23413_dupName_487_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3680_vt_select_20(BITSELECT,12411)@318
    assign i_unnamed_c_compmm_m3680_vt_select_20_b = rightShiftStage2_uid23415_dupName_487_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3680_vt_join(BITJOIN,12410)@318
    assign i_unnamed_c_compmm_m3680_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3680_vt_select_20_b};

    // i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x(BITSELECT,3473)@318
    assign i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x_b = i_unnamed_c_compmm_m3680_vt_join_q[15:0];

    // redist1116_i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x_b_1(DELAY,30244)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1116_i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23424_dupName_488_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23423)@318
    assign rightShiftStage1Idx1Rng8_uid23424_dupName_488_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23426_dupName_488_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23425)@318
    assign rightShiftStage1Idx1_uid23426_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23424_dupName_488_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23419_dupName_488_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23418)@318
    assign rightShiftStage0Idx1Rng4_uid23419_dupName_488_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q[33:4];

    // rightShiftStage0Idx1_uid23421_dupName_488_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23420)@318
    assign rightShiftStage0Idx1_uid23421_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23419_dupName_488_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x(MUX,23422)@318
    assign rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q or rightShiftStage0Idx1_uid23421_dupName_488_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_122_i_c_compmm_m3679_q;
            1'b1 : rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23421_dupName_488_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x(MUX,23427)@318
    assign rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23426_dupName_488_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23423_dupName_488_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23426_dupName_488_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3682_vt_select_21(BITSELECT,12414)@318
    assign i_unnamed_c_compmm_m3682_vt_select_21_b = rightShiftStage1_uid23428_dupName_488_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3682_vt_join(BITJOIN,12413)@318
    assign i_unnamed_c_compmm_m3682_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3682_vt_select_21_b};

    // i_unnamed_c_compmm_m3683_sel_x(BITSELECT,6203)@318
    assign i_unnamed_c_compmm_m3683_sel_x_b = i_unnamed_c_compmm_m3682_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3684_BitSelect_for_a(BITSELECT,28758)@318
    assign i_unnamed_c_compmm_m3684_BitSelect_for_a_b = i_unnamed_c_compmm_m3683_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3684_join(BITJOIN,28759)@318
    assign i_unnamed_c_compmm_m3684_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3684_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3684_vt_select_0(BITSELECT,12419)@318
    assign i_unnamed_c_compmm_m3684_vt_select_0_b = i_unnamed_c_compmm_m3684_join_q[0:0];

    // redist58_i_unnamed_c_compmm_m3684_vt_select_0_b_1(DELAY,29186)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist58_i_unnamed_c_compmm_m3684_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3684_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3684_vt_join(BITJOIN,12418)@319
    assign i_unnamed_c_compmm_m3684_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist58_i_unnamed_c_compmm_m3684_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_122_c_compmm_m3685(ADD,7056)@319
    assign i_add_i_i_i_i_i126_i_122_c_compmm_m3685_a = {1'b0, i_unnamed_c_compmm_m3684_vt_join_q};
    assign i_add_i_i_i_i_i126_i_122_c_compmm_m3685_b = {1'b0, redist1116_i_conv_i_i_i_i97_i_122_c_compmm_m3681_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_122_c_compmm_m3685_o = $unsigned(i_add_i_i_i_i_i126_i_122_c_compmm_m3685_a) + $unsigned(i_add_i_i_i_i_i126_i_122_c_compmm_m3685_b);
    assign i_add_i_i_i_i_i126_i_122_c_compmm_m3685_q = i_add_i_i_i_i_i126_i_122_c_compmm_m3685_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_122_c_compmm_m3685_sel_x(BITSELECT,2070)@319
    assign bgTrunc_i_add_i_i_i_i_i126_i_122_c_compmm_m3685_sel_x_b = i_add_i_i_i_i_i126_i_122_c_compmm_m3685_q[15:0];

    // i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_sel_x(BITSELECT,3603)@319
    assign i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_122_c_compmm_m3685_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_select_15(BITSELECT,7523)@319
    assign i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_select_15_b = i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_join(BITJOIN,7522)@319
    assign i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_select_15_b};

    // leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(MUX,24226)@319
    assign leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_join_q or leftShiftStage0Idx1_uid24225_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_123_c_compmm_m3705_vt_join_q;
            1'b1 : leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24225_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(MUX,24231)@319
    assign leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s or leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24230_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = leftShiftStage0_uid24227_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24230_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x(MUX,24236)@319
    assign leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s or leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24235_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = leftShiftStage1_uid24232_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24235_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28(BITSELECT,9535)@319
    assign i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28_b = leftShiftStage2_uid24237_i_shl_i_i_i_i_i77_i_123_c_compmm_m0_shift_x_q[28:13];

    // redist477_i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28_b_1(DELAY,29605)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist477_i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_join(BITJOIN,9534)@320
    assign i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_join_q = {redist477_i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma(CHAINMULTADD,29025)@314 + 5
    // out q@320
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_55_c_compmm_m_fpgaunique_67266_c_compmm_m10_out_dest_data_out_248_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_54_c_compmm_m_fpgaunique_67265_c_compmm_m11_out_dest_data_out_247_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ch[0] <= redist750_sync_together4364_aunroll_x_in_c1_eni5_248_tpl_246_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ch[1] <= redist749_sync_together4364_aunroll_x_in_c1_eni5_247_tpl_246_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707(ADD,8845)@320
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_123_i_c_compmm_m3702_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_123_i_c_compmm_m3704_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_123_i_c_compmm_m3703_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_123_c_compmm_m3706_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_o[33:0];

    // rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x(MUX,23466)@320
    assign rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q or rightShiftStage0Idx1_uid23465_dupName_491_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q;
            1'b1 : rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23465_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x(MUX,23471)@320
    assign rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23470_dupName_491_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23467_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23470_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x(MUX,23476)@320
    assign rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23475_dupName_491_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23472_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23475_dupName_491_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3708_vt_select_20(BITSELECT,12433)@320
    assign i_unnamed_c_compmm_m3708_vt_select_20_b = rightShiftStage2_uid23477_dupName_491_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3708_vt_join(BITJOIN,12432)@320
    assign i_unnamed_c_compmm_m3708_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3708_vt_select_20_b};

    // i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x(BITSELECT,3474)@320
    assign i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x_b = i_unnamed_c_compmm_m3708_vt_join_q[15:0];

    // redist1115_i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x_b_1(DELAY,30243)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1115_i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23486_dupName_492_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23485)@320
    assign rightShiftStage1Idx1Rng8_uid23486_dupName_492_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23488_dupName_492_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23487)@320
    assign rightShiftStage1Idx1_uid23488_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23486_dupName_492_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23481_dupName_492_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23480)@320
    assign rightShiftStage0Idx1Rng4_uid23481_dupName_492_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q[33:4];

    // rightShiftStage0Idx1_uid23483_dupName_492_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23482)@320
    assign rightShiftStage0Idx1_uid23483_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23481_dupName_492_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x(MUX,23484)@320
    assign rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q or rightShiftStage0Idx1_uid23483_dupName_492_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_123_i_c_compmm_m3707_q;
            1'b1 : rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23483_dupName_492_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x(MUX,23489)@320
    assign rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23488_dupName_492_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23485_dupName_492_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23488_dupName_492_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3710_vt_select_21(BITSELECT,12436)@320
    assign i_unnamed_c_compmm_m3710_vt_select_21_b = rightShiftStage1_uid23490_dupName_492_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3710_vt_join(BITJOIN,12435)@320
    assign i_unnamed_c_compmm_m3710_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3710_vt_select_21_b};

    // i_unnamed_c_compmm_m3711_sel_x(BITSELECT,6205)@320
    assign i_unnamed_c_compmm_m3711_sel_x_b = i_unnamed_c_compmm_m3710_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3712_BitSelect_for_a(BITSELECT,28762)@320
    assign i_unnamed_c_compmm_m3712_BitSelect_for_a_b = i_unnamed_c_compmm_m3711_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3712_join(BITJOIN,28763)@320
    assign i_unnamed_c_compmm_m3712_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3712_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3712_vt_select_0(BITSELECT,12441)@320
    assign i_unnamed_c_compmm_m3712_vt_select_0_b = i_unnamed_c_compmm_m3712_join_q[0:0];

    // redist56_i_unnamed_c_compmm_m3712_vt_select_0_b_1(DELAY,29184)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist56_i_unnamed_c_compmm_m3712_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3712_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3712_vt_join(BITJOIN,12440)@321
    assign i_unnamed_c_compmm_m3712_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist56_i_unnamed_c_compmm_m3712_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_123_c_compmm_m3713(ADD,7057)@321
    assign i_add_i_i_i_i_i126_i_123_c_compmm_m3713_a = {1'b0, i_unnamed_c_compmm_m3712_vt_join_q};
    assign i_add_i_i_i_i_i126_i_123_c_compmm_m3713_b = {1'b0, redist1115_i_conv_i_i_i_i97_i_123_c_compmm_m3709_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_123_c_compmm_m3713_o = $unsigned(i_add_i_i_i_i_i126_i_123_c_compmm_m3713_a) + $unsigned(i_add_i_i_i_i_i126_i_123_c_compmm_m3713_b);
    assign i_add_i_i_i_i_i126_i_123_c_compmm_m3713_q = i_add_i_i_i_i_i126_i_123_c_compmm_m3713_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_123_c_compmm_m3713_sel_x(BITSELECT,2071)@321
    assign bgTrunc_i_add_i_i_i_i_i126_i_123_c_compmm_m3713_sel_x_b = i_add_i_i_i_i_i126_i_123_c_compmm_m3713_q[15:0];

    // i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_sel_x(BITSELECT,3604)@321
    assign i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_123_c_compmm_m3713_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_select_15(BITSELECT,7527)@321
    assign i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_select_15_b = i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_join(BITJOIN,7526)@321
    assign i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_select_15_b};

    // leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(MUX,24244)@321
    assign leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_join_q or leftShiftStage0Idx1_uid24243_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_124_c_compmm_m3733_vt_join_q;
            1'b1 : leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24243_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(MUX,24249)@321
    assign leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s or leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24248_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = leftShiftStage0_uid24245_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24248_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x(MUX,24254)@321
    assign leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s or leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24253_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = leftShiftStage1_uid24250_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24253_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28(BITSELECT,9538)@321
    assign i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28_b = leftShiftStage2_uid24255_i_shl_i_i_i_i_i77_i_124_c_compmm_m0_shift_x_q[28:13];

    // redist476_i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28_b_1(DELAY,29604)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist476_i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_join(BITJOIN,9537)@322
    assign i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_join_q = {redist476_i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma(CHAINMULTADD,29026)@316 + 5
    // out q@322
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_57_c_compmm_m_fpgaunique_67268_c_compmm_m8_out_dest_data_out_250_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_56_c_compmm_m_fpgaunique_67267_c_compmm_m9_out_dest_data_out_249_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ch[0] <= redist752_sync_together4364_aunroll_x_in_c1_eni5_250_tpl_248_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ch[1] <= redist751_sync_together4364_aunroll_x_in_c1_eni5_249_tpl_248_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735(ADD,8846)@322
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_124_i_c_compmm_m3730_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_124_i_c_compmm_m3732_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_124_i_c_compmm_m3731_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_124_c_compmm_m3734_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_o[33:0];

    // rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x(MUX,23528)@322
    assign rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q or rightShiftStage0Idx1_uid23527_dupName_495_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q;
            1'b1 : rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23527_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x(MUX,23533)@322
    assign rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23532_dupName_495_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23529_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23532_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x(MUX,23538)@322
    assign rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23537_dupName_495_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23534_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23537_dupName_495_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3736_vt_select_20(BITSELECT,12455)@322
    assign i_unnamed_c_compmm_m3736_vt_select_20_b = rightShiftStage2_uid23539_dupName_495_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3736_vt_join(BITJOIN,12454)@322
    assign i_unnamed_c_compmm_m3736_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3736_vt_select_20_b};

    // i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x(BITSELECT,3475)@322
    assign i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x_b = i_unnamed_c_compmm_m3736_vt_join_q[15:0];

    // redist1114_i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x_b_1(DELAY,30242)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1114_i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23548_dupName_496_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23547)@322
    assign rightShiftStage1Idx1Rng8_uid23548_dupName_496_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23550_dupName_496_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23549)@322
    assign rightShiftStage1Idx1_uid23550_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23548_dupName_496_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23543_dupName_496_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23542)@322
    assign rightShiftStage0Idx1Rng4_uid23543_dupName_496_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q[33:4];

    // rightShiftStage0Idx1_uid23545_dupName_496_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23544)@322
    assign rightShiftStage0Idx1_uid23545_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23543_dupName_496_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x(MUX,23546)@322
    assign rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q or rightShiftStage0Idx1_uid23545_dupName_496_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_124_i_c_compmm_m3735_q;
            1'b1 : rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23545_dupName_496_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x(MUX,23551)@322
    assign rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23550_dupName_496_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23547_dupName_496_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23550_dupName_496_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3738_vt_select_21(BITSELECT,12458)@322
    assign i_unnamed_c_compmm_m3738_vt_select_21_b = rightShiftStage1_uid23552_dupName_496_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3738_vt_join(BITJOIN,12457)@322
    assign i_unnamed_c_compmm_m3738_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3738_vt_select_21_b};

    // i_unnamed_c_compmm_m3739_sel_x(BITSELECT,6207)@322
    assign i_unnamed_c_compmm_m3739_sel_x_b = i_unnamed_c_compmm_m3738_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3740_BitSelect_for_a(BITSELECT,28766)@322
    assign i_unnamed_c_compmm_m3740_BitSelect_for_a_b = i_unnamed_c_compmm_m3739_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3740_join(BITJOIN,28767)@322
    assign i_unnamed_c_compmm_m3740_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3740_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3740_vt_select_0(BITSELECT,12466)@322
    assign i_unnamed_c_compmm_m3740_vt_select_0_b = i_unnamed_c_compmm_m3740_join_q[0:0];

    // redist54_i_unnamed_c_compmm_m3740_vt_select_0_b_1(DELAY,29182)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist54_i_unnamed_c_compmm_m3740_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3740_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3740_vt_join(BITJOIN,12465)@323
    assign i_unnamed_c_compmm_m3740_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist54_i_unnamed_c_compmm_m3740_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_124_c_compmm_m3741(ADD,7058)@323
    assign i_add_i_i_i_i_i126_i_124_c_compmm_m3741_a = {1'b0, i_unnamed_c_compmm_m3740_vt_join_q};
    assign i_add_i_i_i_i_i126_i_124_c_compmm_m3741_b = {1'b0, redist1114_i_conv_i_i_i_i97_i_124_c_compmm_m3737_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_124_c_compmm_m3741_o = $unsigned(i_add_i_i_i_i_i126_i_124_c_compmm_m3741_a) + $unsigned(i_add_i_i_i_i_i126_i_124_c_compmm_m3741_b);
    assign i_add_i_i_i_i_i126_i_124_c_compmm_m3741_q = i_add_i_i_i_i_i126_i_124_c_compmm_m3741_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_124_c_compmm_m3741_sel_x(BITSELECT,2072)@323
    assign bgTrunc_i_add_i_i_i_i_i126_i_124_c_compmm_m3741_sel_x_b = i_add_i_i_i_i_i126_i_124_c_compmm_m3741_q[15:0];

    // i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_sel_x(BITSELECT,3605)@323
    assign i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_124_c_compmm_m3741_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_select_15(BITSELECT,7531)@323
    assign i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_select_15_b = i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_join(BITJOIN,7530)@323
    assign i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_select_15_b};

    // leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(MUX,24262)@323
    assign leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_join_q or leftShiftStage0Idx1_uid24261_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_125_c_compmm_m3761_vt_join_q;
            1'b1 : leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24261_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(MUX,24267)@323
    assign leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s or leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24266_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = leftShiftStage0_uid24263_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24266_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x(MUX,24272)@323
    assign leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s or leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24271_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = leftShiftStage1_uid24268_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24271_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28(BITSELECT,9541)@323
    assign i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28_b = leftShiftStage2_uid24273_i_shl_i_i_i_i_i77_i_125_c_compmm_m0_shift_x_q[28:13];

    // redist475_i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28_b_1(DELAY,29603)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist475_i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_join(BITJOIN,9540)@324
    assign i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_join_q = {redist475_i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma(CHAINMULTADD,29027)@318 + 5
    // out q@324
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_59_c_compmm_m_fpgaunique_67270_c_compmm_m6_out_dest_data_out_252_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_58_c_compmm_m_fpgaunique_67269_c_compmm_m7_out_dest_data_out_251_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ch[0] <= redist754_sync_together4364_aunroll_x_in_c1_eni5_252_tpl_250_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ch[1] <= redist753_sync_together4364_aunroll_x_in_c1_eni5_251_tpl_250_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763(ADD,8847)@324
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_125_i_c_compmm_m3758_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_125_i_c_compmm_m3760_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_125_i_c_compmm_m3759_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_125_c_compmm_m3762_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_o[33:0];

    // rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x(MUX,23590)@324
    assign rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q or rightShiftStage0Idx1_uid23589_dupName_499_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q;
            1'b1 : rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23589_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x(MUX,23595)@324
    assign rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23594_dupName_499_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23591_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23594_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x(MUX,23600)@324
    assign rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23599_dupName_499_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23596_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23599_dupName_499_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3764_vt_select_20(BITSELECT,12483)@324
    assign i_unnamed_c_compmm_m3764_vt_select_20_b = rightShiftStage2_uid23601_dupName_499_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3764_vt_join(BITJOIN,12482)@324
    assign i_unnamed_c_compmm_m3764_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3764_vt_select_20_b};

    // i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x(BITSELECT,3476)@324
    assign i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x_b = i_unnamed_c_compmm_m3764_vt_join_q[15:0];

    // redist1113_i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x_b_1(DELAY,30241)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1113_i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23610_dupName_500_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23609)@324
    assign rightShiftStage1Idx1Rng8_uid23610_dupName_500_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23612_dupName_500_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23611)@324
    assign rightShiftStage1Idx1_uid23612_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23610_dupName_500_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23605_dupName_500_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23604)@324
    assign rightShiftStage0Idx1Rng4_uid23605_dupName_500_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q[33:4];

    // rightShiftStage0Idx1_uid23607_dupName_500_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23606)@324
    assign rightShiftStage0Idx1_uid23607_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23605_dupName_500_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x(MUX,23608)@324
    assign rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q or rightShiftStage0Idx1_uid23607_dupName_500_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_125_i_c_compmm_m3763_q;
            1'b1 : rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23607_dupName_500_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x(MUX,23613)@324
    assign rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23612_dupName_500_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23609_dupName_500_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23612_dupName_500_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3766_vt_select_21(BITSELECT,12486)@324
    assign i_unnamed_c_compmm_m3766_vt_select_21_b = rightShiftStage1_uid23614_dupName_500_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3766_vt_join(BITJOIN,12485)@324
    assign i_unnamed_c_compmm_m3766_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3766_vt_select_21_b};

    // i_unnamed_c_compmm_m3767_sel_x(BITSELECT,6210)@324
    assign i_unnamed_c_compmm_m3767_sel_x_b = i_unnamed_c_compmm_m3766_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3768_BitSelect_for_a(BITSELECT,28770)@324
    assign i_unnamed_c_compmm_m3768_BitSelect_for_a_b = i_unnamed_c_compmm_m3767_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3768_join(BITJOIN,28771)@324
    assign i_unnamed_c_compmm_m3768_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3768_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3768_vt_select_0(BITSELECT,12491)@324
    assign i_unnamed_c_compmm_m3768_vt_select_0_b = i_unnamed_c_compmm_m3768_join_q[0:0];

    // redist52_i_unnamed_c_compmm_m3768_vt_select_0_b_1(DELAY,29180)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist52_i_unnamed_c_compmm_m3768_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3768_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3768_vt_join(BITJOIN,12490)@325
    assign i_unnamed_c_compmm_m3768_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist52_i_unnamed_c_compmm_m3768_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_125_c_compmm_m3769(ADD,7059)@325
    assign i_add_i_i_i_i_i126_i_125_c_compmm_m3769_a = {1'b0, i_unnamed_c_compmm_m3768_vt_join_q};
    assign i_add_i_i_i_i_i126_i_125_c_compmm_m3769_b = {1'b0, redist1113_i_conv_i_i_i_i97_i_125_c_compmm_m3765_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_125_c_compmm_m3769_o = $unsigned(i_add_i_i_i_i_i126_i_125_c_compmm_m3769_a) + $unsigned(i_add_i_i_i_i_i126_i_125_c_compmm_m3769_b);
    assign i_add_i_i_i_i_i126_i_125_c_compmm_m3769_q = i_add_i_i_i_i_i126_i_125_c_compmm_m3769_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_125_c_compmm_m3769_sel_x(BITSELECT,2073)@325
    assign bgTrunc_i_add_i_i_i_i_i126_i_125_c_compmm_m3769_sel_x_b = i_add_i_i_i_i_i126_i_125_c_compmm_m3769_q[15:0];

    // i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_sel_x(BITSELECT,3606)@325
    assign i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_125_c_compmm_m3769_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_select_15(BITSELECT,7535)@325
    assign i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_select_15_b = i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_join(BITJOIN,7534)@325
    assign i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_select_15_b};

    // leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(MUX,24280)@325
    assign leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_join_q or leftShiftStage0Idx1_uid24279_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_126_c_compmm_m3789_vt_join_q;
            1'b1 : leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24279_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(MUX,24285)@325
    assign leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s or leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24284_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = leftShiftStage0_uid24281_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24284_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x(MUX,24290)@325
    assign leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s or leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24289_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = leftShiftStage1_uid24286_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24289_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28(BITSELECT,9544)@325
    assign i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28_b = leftShiftStage2_uid24291_i_shl_i_i_i_i_i77_i_126_c_compmm_m0_shift_x_q[28:13];

    // redist474_i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28_b_1(DELAY,29602)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist474_i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_join(BITJOIN,9543)@326
    assign i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_join_q = {redist474_i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma(CHAINMULTADD,29028)@320 + 5
    // out q@326
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_61_c_compmm_m_fpgaunique_67272_c_compmm_m4_out_dest_data_out_254_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_60_c_compmm_m_fpgaunique_67271_c_compmm_m5_out_dest_data_out_253_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ch[0] <= redist756_sync_together4364_aunroll_x_in_c1_eni5_254_tpl_252_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ch[1] <= redist755_sync_together4364_aunroll_x_in_c1_eni5_253_tpl_252_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791(ADD,8848)@326
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_126_i_c_compmm_m3786_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_126_i_c_compmm_m3788_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_126_i_c_compmm_m3787_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_126_c_compmm_m3790_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_o[33:0];

    // rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x(MUX,23652)@326
    assign rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q or rightShiftStage0Idx1_uid23651_dupName_503_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q;
            1'b1 : rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23651_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x(MUX,23657)@326
    assign rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23656_dupName_503_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23653_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23656_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x(MUX,23662)@326
    assign rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23661_dupName_503_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23658_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23661_dupName_503_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3792_vt_select_20(BITSELECT,12510)@326
    assign i_unnamed_c_compmm_m3792_vt_select_20_b = rightShiftStage2_uid23663_dupName_503_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3792_vt_join(BITJOIN,12509)@326
    assign i_unnamed_c_compmm_m3792_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3792_vt_select_20_b};

    // i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x(BITSELECT,3477)@326
    assign i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x_b = i_unnamed_c_compmm_m3792_vt_join_q[15:0];

    // redist1112_i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x_b_1(DELAY,30240)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1112_i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23672_dupName_504_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23671)@326
    assign rightShiftStage1Idx1Rng8_uid23672_dupName_504_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23674_dupName_504_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23673)@326
    assign rightShiftStage1Idx1_uid23674_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23672_dupName_504_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23667_dupName_504_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23666)@326
    assign rightShiftStage0Idx1Rng4_uid23667_dupName_504_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q[33:4];

    // rightShiftStage0Idx1_uid23669_dupName_504_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23668)@326
    assign rightShiftStage0Idx1_uid23669_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23667_dupName_504_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x(MUX,23670)@326
    assign rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q or rightShiftStage0Idx1_uid23669_dupName_504_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_126_i_c_compmm_m3791_q;
            1'b1 : rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23669_dupName_504_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x(MUX,23675)@326
    assign rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23674_dupName_504_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23671_dupName_504_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23674_dupName_504_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3794_vt_select_21(BITSELECT,12513)@326
    assign i_unnamed_c_compmm_m3794_vt_select_21_b = rightShiftStage1_uid23676_dupName_504_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3794_vt_join(BITJOIN,12512)@326
    assign i_unnamed_c_compmm_m3794_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3794_vt_select_21_b};

    // i_unnamed_c_compmm_m3795_sel_x(BITSELECT,6212)@326
    assign i_unnamed_c_compmm_m3795_sel_x_b = i_unnamed_c_compmm_m3794_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3796_BitSelect_for_a(BITSELECT,28776)@326
    assign i_unnamed_c_compmm_m3796_BitSelect_for_a_b = i_unnamed_c_compmm_m3795_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3796_join(BITJOIN,28777)@326
    assign i_unnamed_c_compmm_m3796_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3796_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3796_vt_select_0(BITSELECT,12518)@326
    assign i_unnamed_c_compmm_m3796_vt_select_0_b = i_unnamed_c_compmm_m3796_join_q[0:0];

    // redist49_i_unnamed_c_compmm_m3796_vt_select_0_b_1(DELAY,29177)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist49_i_unnamed_c_compmm_m3796_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3796_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3796_vt_join(BITJOIN,12517)@327
    assign i_unnamed_c_compmm_m3796_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist49_i_unnamed_c_compmm_m3796_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_126_c_compmm_m3797(ADD,7060)@327
    assign i_add_i_i_i_i_i126_i_126_c_compmm_m3797_a = {1'b0, i_unnamed_c_compmm_m3796_vt_join_q};
    assign i_add_i_i_i_i_i126_i_126_c_compmm_m3797_b = {1'b0, redist1112_i_conv_i_i_i_i97_i_126_c_compmm_m3793_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_126_c_compmm_m3797_o = $unsigned(i_add_i_i_i_i_i126_i_126_c_compmm_m3797_a) + $unsigned(i_add_i_i_i_i_i126_i_126_c_compmm_m3797_b);
    assign i_add_i_i_i_i_i126_i_126_c_compmm_m3797_q = i_add_i_i_i_i_i126_i_126_c_compmm_m3797_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_126_c_compmm_m3797_sel_x(BITSELECT,2074)@327
    assign bgTrunc_i_add_i_i_i_i_i126_i_126_c_compmm_m3797_sel_x_b = i_add_i_i_i_i_i126_i_126_c_compmm_m3797_q[15:0];

    // i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_sel_x(BITSELECT,3607)@327
    assign i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_sel_x_b = {13'b0000000000000, bgTrunc_i_add_i_i_i_i_i126_i_126_c_compmm_m3797_sel_x_b[15:0]};

    // i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_select_15(BITSELECT,7539)@327
    assign i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_select_15_b = i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_sel_x_b[15:0];

    // i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_join(BITJOIN,7538)@327
    assign i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_select_15_b};

    // leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(MUX,24298)@327
    assign leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s or i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_join_q or leftShiftStage0Idx1_uid24297_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = i_conv_i_i_i_i_i75_i244_127_c_compmm_m3817_vt_join_q;
            1'b1 : leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = leftShiftStage0Idx1_uid24297_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
            default : leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(MUX,24303)@327
    assign leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s or leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q or leftShiftStage1Idx1_uid24302_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = leftShiftStage0_uid24299_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = leftShiftStage1Idx1_uid24302_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
            default : leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x(MUX,24308)@327
    assign leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s = VCC_q;
    always @(leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s or leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q or leftShiftStage2Idx1_uid24307_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q)
    begin
        unique case (leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_s)
            1'b0 : leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = leftShiftStage1_uid24304_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
            1'b1 : leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = leftShiftStage2Idx1_uid24307_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q;
            default : leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q = 29'b0;
        endcase
    end

    // i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28(BITSELECT,9547)@327
    assign i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28_b = leftShiftStage2_uid24309_i_shl_i_i_i_i_i77_i_127_c_compmm_m0_shift_x_q[28:13];

    // redist473_i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28_b_1(DELAY,29601)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist473_i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28_b_1_q <= $unsigned(i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28_b);
        end
    end

    // i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_join(BITJOIN,9546)@328
    assign i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_join_q = {redist473_i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_select_28_b_1_q, i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q};

    // i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma(CHAINMULTADD,29029)@322 + 5
    // out q@328
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_reset = ~ (resetn);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena0 = 1'b1;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena1 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena0;
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena2 = i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena0;
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ah[0] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_63_c_compmm_m_fpgaunique_67274_c_compmm_m2_out_dest_data_out_256_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ah[1] <= i_llvm_fpga_ffwd_dest_i16_memcoalesce_extrvalue_62_c_compmm_m_fpgaunique_67273_c_compmm_m3_out_dest_data_out_255_0;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ch[0] <= redist758_sync_together4364_aunroll_x_in_c1_eni5_256_tpl_254_outputreg0_q;
            i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ch[1] <= redist757_sync_together4364_aunroll_x_in_c1_eni5_255_tpl_254_outputreg0_q;
        end
    end

    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_a0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ah[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_c0 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ch[0]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_a1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ah[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_c1 = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ch[1]);
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_sna = $unsigned(VCC_q);
    tennm_mac #(
        .operation_mode("m18x18_sumof2"),
        .clear_type("none"),
        .use_chainadder("false"),
        .ay_scan_in_clken("0"),
        .ay_scan_in_width(16),
        .by_clken("0"),
        .by_width(16),
        .ax_clken("0"),
        .bx_clken("0"),
        .ax_width(16),
        .bx_width(16),
        .signed_may("true"),
        .signed_mby("true"),
        .signed_max("true"),
        .signed_mbx("true"),
        .input_pipeline_clken("2"),
        .second_pipeline_clken("2"),
        .output_clken("1"),
        .result_a_width(33)
    ) i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_DSP0 (
        .clk(clock),
        .ena({ i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena2, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena1, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_ena0 }),
        .clr({ 1'b0, 1'b0 }),
        .sub(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_sna[0]),
        .negate(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_sna[0]),
        .ay(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_a1),
        .by(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_a0),
        .ax(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_c1),
        .bx(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_c0),
        .resulta(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_s0),
        .accumulate(),
        .loadconst(),
        .az(),
        .coefsela(),
        .bz(),
        .coefselb(),
        .cx(),
        .cy(),
        .dx(),
        .dy(),
        .scanin(),
        .scanout(),
        .chainin(),
        .chainout(),
        .disable_scanin(),
        .disable_chainout(),
        .resultb(),
        .dfxlfsrena(),
        .dfxmisrena()
    );
    dspba_delay_ver #( .width(33), .depth(1), .reset_kind("NONE"), .phase(0), .modulus(1), .reset_high(1'b0) )
    i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_delay ( .xin(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_s0), .xout(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_qq), .clk(clock), .aclr(resetn), .ena(1'b1) );
    assign i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_q = $unsigned(i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_qq[32:0]);

    // i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819(ADD,8849)@328
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_a = $unsigned({{1{i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_q[32]}}, i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i160_i_127_i_c_compmm_m3814_i_llvm_fpga_int_sub_i33_i32_i32_sub_i_i_i_127_i_c_compmm_m3816_i_llvm_fpga_int_mul_i32_i16_i16_mul_i_i150_i_127_i_c_compmm_m3815_merged_cma_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_b = $unsigned({{5{i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_join_q[28]}}, i_shl_i_i_i_i_i77_i_127_c_compmm_m3818_vt_join_q});
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_o = $unsigned($signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_a) + $signed(i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_b));
    assign i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_o[33:0];

    // rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x(MUX,23714)@328
    assign rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q or rightShiftStage0Idx1_uid23713_dupName_507_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q;
            1'b1 : rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23713_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x(MUX,23719)@328
    assign rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23718_dupName_507_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23715_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23718_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x(MUX,23724)@328
    assign rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage2Idx1_uid23723_dupName_507_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1_uid23720_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage2Idx1_uid23723_dupName_507_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3820_vt_select_20(BITSELECT,12532)@328
    assign i_unnamed_c_compmm_m3820_vt_select_20_b = rightShiftStage2_uid23725_dupName_507_i_unnamed_c_compmm_m0_shift_x_q[20:0];

    // i_unnamed_c_compmm_m3820_vt_join(BITJOIN,12531)@328
    assign i_unnamed_c_compmm_m3820_vt_join_q = {i_conv_i_i_i_i_i75_i244_100_c_compmm_m3061_vt_const_28_q, i_unnamed_c_compmm_m3820_vt_select_20_b};

    // i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x(BITSELECT,3478)@328
    assign i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x_b = i_unnamed_c_compmm_m3820_vt_join_q[15:0];

    // redist1111_i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x_b_1(DELAY,30239)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist1111_i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x_b_1_q <= $unsigned(i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x_b);
        end
    end

    // rightShiftStage1Idx1Rng8_uid23734_dupName_508_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23733)@328
    assign rightShiftStage1Idx1Rng8_uid23734_dupName_508_i_unnamed_c_compmm_m0_shift_x_b = rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_q[33:8];

    // rightShiftStage1Idx1_uid23736_dupName_508_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23735)@328
    assign rightShiftStage1Idx1_uid23736_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage1Idx1Pad8_uid15861_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage1Idx1Rng8_uid23734_dupName_508_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0Idx1Rng4_uid23729_dupName_508_i_unnamed_c_compmm_m0_shift_x(BITSELECT,23728)@328
    assign rightShiftStage0Idx1Rng4_uid23729_dupName_508_i_unnamed_c_compmm_m0_shift_x_b = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q[33:4];

    // rightShiftStage0Idx1_uid23731_dupName_508_i_unnamed_c_compmm_m0_shift_x(BITJOIN,23730)@328
    assign rightShiftStage0Idx1_uid23731_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = {rightShiftStage0Idx1Pad4_uid15856_dupName_0_i_unnamed_c_compmm_m0_shift_x_q, rightShiftStage0Idx1Rng4_uid23729_dupName_508_i_unnamed_c_compmm_m0_shift_x_b};

    // rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x(MUX,23732)@328
    assign rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_s or i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q or rightShiftStage0Idx1_uid23731_dupName_508_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = i_llvm_fpga_int_add_i34_i33_i29_add_i_i_i90_i_127_i_c_compmm_m3819_q;
            1'b1 : rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0Idx1_uid23731_dupName_508_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x(MUX,23737)@328
    assign rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_s = VCC_q;
    always @(rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_s or rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_q or rightShiftStage1Idx1_uid23736_dupName_508_i_unnamed_c_compmm_m0_shift_x_q)
    begin
        unique case (rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_s)
            1'b0 : rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage0_uid23733_dupName_508_i_unnamed_c_compmm_m0_shift_x_q;
            1'b1 : rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = rightShiftStage1Idx1_uid23736_dupName_508_i_unnamed_c_compmm_m0_shift_x_q;
            default : rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_q = 34'b0;
        endcase
    end

    // i_unnamed_c_compmm_m3822_vt_select_21(BITSELECT,12535)@328
    assign i_unnamed_c_compmm_m3822_vt_select_21_b = rightShiftStage1_uid23738_dupName_508_i_unnamed_c_compmm_m0_shift_x_q[21:0];

    // i_unnamed_c_compmm_m3822_vt_join(BITJOIN,12534)@328
    assign i_unnamed_c_compmm_m3822_vt_join_q = {i_unnamed_c_compmm_m1007_vt_const_33_q, i_unnamed_c_compmm_m3822_vt_select_21_b};

    // i_unnamed_c_compmm_m3823_sel_x(BITSELECT,6214)@328
    assign i_unnamed_c_compmm_m3823_sel_x_b = i_unnamed_c_compmm_m3822_vt_join_q[15:0];

    // i_unnamed_c_compmm_m3824_BitSelect_for_a(BITSELECT,28780)@328
    assign i_unnamed_c_compmm_m3824_BitSelect_for_a_b = i_unnamed_c_compmm_m3823_sel_x_b[0:0];

    // i_unnamed_c_compmm_m3824_join(BITJOIN,28781)@328
    assign i_unnamed_c_compmm_m3824_join_q = {GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, GND_q, i_unnamed_c_compmm_m3824_BitSelect_for_a_b};

    // i_unnamed_c_compmm_m3824_vt_select_0(BITSELECT,12540)@328
    assign i_unnamed_c_compmm_m3824_vt_select_0_b = i_unnamed_c_compmm_m3824_join_q[0:0];

    // redist47_i_unnamed_c_compmm_m3824_vt_select_0_b_1(DELAY,29175)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist47_i_unnamed_c_compmm_m3824_vt_select_0_b_1_q <= $unsigned(i_unnamed_c_compmm_m3824_vt_select_0_b);
        end
    end

    // i_unnamed_c_compmm_m3824_vt_join(BITJOIN,12539)@329
    assign i_unnamed_c_compmm_m3824_vt_join_q = {i_unnamed_c_compmm_m1009_vt_const_15_q, redist47_i_unnamed_c_compmm_m3824_vt_select_0_b_1_q};

    // i_add_i_i_i_i_i126_i_127_c_compmm_m3825(ADD,7061)@329
    assign i_add_i_i_i_i_i126_i_127_c_compmm_m3825_a = {1'b0, i_unnamed_c_compmm_m3824_vt_join_q};
    assign i_add_i_i_i_i_i126_i_127_c_compmm_m3825_b = {1'b0, redist1111_i_conv_i_i_i_i97_i_127_c_compmm_m3821_sel_x_b_1_q};
    assign i_add_i_i_i_i_i126_i_127_c_compmm_m3825_o = $unsigned(i_add_i_i_i_i_i126_i_127_c_compmm_m3825_a) + $unsigned(i_add_i_i_i_i_i126_i_127_c_compmm_m3825_b);
    assign i_add_i_i_i_i_i126_i_127_c_compmm_m3825_q = i_add_i_i_i_i_i126_i_127_c_compmm_m3825_o[16:0];

    // bgTrunc_i_add_i_i_i_i_i126_i_127_c_compmm_m3825_sel_x(BITSELECT,2075)@329
    assign bgTrunc_i_add_i_i_i_i_i126_i_127_c_compmm_m3825_sel_x_b = i_add_i_i_i_i_i126_i_127_c_compmm_m3825_q[15:0];

    // redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_offset(CONSTANT,31793)
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_offset_q = $unsigned(9'b100000000);

    // redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt(ADD,31794)
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_a = {1'b0, redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_q};
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_b = {1'b0, redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_offset_q};
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_o <= $unsigned(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_a) + $unsigned(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_b);
        end
    end
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_q = redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_o[9:0];

    // redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_inputreg0(DELAY,31789)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_inputreg0_q <= $unsigned(in_c1_eni5_257_tpl);
        end
    end

    // redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr(COUNTER,31792)
    // low=0, high=511, step=1, init=0
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_i <= $unsigned(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_i) + $unsigned(9'd1);
        end
    end
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_q = redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_i[8:0];

    // redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem(DUALMEM,31791)
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_ia = $unsigned(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_inputreg0_q);
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_aa = redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_wraddr_q;
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_ab = redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_rdcnt_q[8:0];
    altera_syncram #(
        .ram_block_type("M20K"),
        .operation_mode("DUAL_PORT"),
        .width_a(64),
        .widthad_a(9),
        .numwords_a(512),
        .width_b(64),
        .widthad_b(9),
        .numwords_b(512),
        .lpm_type("altera_syncram"),
        .width_byteena_a(1),
        .address_reg_b("CLOCK0"),
        .indata_reg_b("CLOCK0"),
        .rdcontrol_reg_b("CLOCK0"),
        .byteena_reg_b("CLOCK0"),
        .outdata_reg_b("CLOCK0"),
        .outdata_sclr_b("NONE"),
        .clock_enable_input_a("NORMAL"),
        .clock_enable_input_b("NORMAL"),
        .clock_enable_output_b("NORMAL"),
        .read_during_write_mode_mixed_ports("DONT_CARE"),
        .power_up_uninitialized("TRUE"),
        .intended_device_family("Agilex")
    ) redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_dmem (
        .clocken0(1'b1),
        .clock0(clock),
        .address_a(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_aa),
        .data_a(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_ia),
        .wren_a(VCC_q[0]),
        .address_b(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_ab),
        .q_b(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_iq),
        .wren_b(),
        .rden_a(),
        .rden_b(),
        .data_b(),
        .clock1(),
        .clocken1(),
        .clocken2(),
        .clocken3(),
        .aclr0(),
        .aclr1(),
        .addressstall_a(),
        .addressstall_b(),
        .byteena_a(),
        .byteena_b(),
        .eccencbypass(),
        .eccencparity(),
        .sclr(),
        .address2_a(),
        .address2_b(),
        .q_a(),
        .eccstatus()
    );
    assign redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_q = redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_iq[63:0];

    // redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_outputreg0(DELAY,31790)
    always @ (posedge clock)
    begin
        if (0)
        begin
        end
        else
        begin
            redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_outputreg0_q <= $unsigned(redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_mem_q);
        end
    end

    // GND(CONSTANT,0)
    assign GND_q = $unsigned(1'b0);

    // sync_out_aunroll_x(GPOUT,6260)@329
    assign out_c1_exi2926_0_tpl = GND_q;
    assign out_c1_exi2926_1_tpl = redist759_sync_together4364_aunroll_x_in_c1_eni5_257_tpl_261_outputreg0_q;
    assign out_c1_exi2926_2_tpl = bgTrunc_i_add_i_i_i_i_i126_i_127_c_compmm_m3825_sel_x_b;
    assign out_c1_exi2926_3_tpl = bgTrunc_i_add_i_i_i_i_i_i_127_c_compmm_m3841_sel_x_b;
    assign out_o_valid = redist1_valid_fanout_reg0_q_7_q;
    assign out_unnamed_c_compMM_m4 = GND_q;

endmodule
